gimble: enable FRS on C1

BUG=b:225941782
BRANCH=none
TEST=Build and verify by EE

Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I220a1c42e436e59d4bdb4fb7a083500ff69ae794
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3514890
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>

Author: ScottChao-Wistron

board/gimble/board.h

@@ -74,6 +74,7 @@
 #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
 #define CONFIG_USBC_PPC_NX20P3483
 
+#define CONFIG_USB_PD_FRS
 #define CONFIG_USB_PD_FRS_PPC
 
 /* measure and check these values on gimble */

board/gimble/gpio.inc

@@ -69,7 +69,7 @@ GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
 GPIO(POWER_LED_GATE,		         PIN(B, 6), GPIO_OUT_LOW)	/* Power LED: White */
 GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
 GPIO(USB_C0_TCPC_RST_ODL,            PIN(A, 7), GPIO_ODR_LOW)
-GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_INPUT)
 GPIO(USB_C1_RT_RST_R_ODL,            PIN(0, 2), GPIO_ODR_HIGH)
 GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
 

board/gimble/usbc_config.c

@@ -57,7 +57,8 @@ const struct tcpc_config_t tcpc_config[] = {
 		.drv = &ps8xxx_tcpm_drv,
 		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
 			 TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V |
-			 TCPC_FLAGS_CONTROL_VCONN,
+			 TCPC_FLAGS_CONTROL_VCONN |
+			 TCPC_FLAGS_CONTROL_FRS,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);