Moved _memory.pyx, _memory.pxd to dpctl.memory submodule

Now to access memory objects one does

import dpctl
import dpctl.memory

Author: oleksandr-pavlyk

dpctl/__init__.py

@@ -47,7 +47,6 @@
 __author__ = "Intel Corp."
 
 from ._sycl_core import *
-from ._memory import MemoryUSMShared, MemoryUSMDevice, MemoryUSMHost
 from ._version import get_versions
 
 

dpctl/_sycl_core.pyx

@@ -30,7 +30,7 @@ from __future__ import print_function
 from enum import Enum, auto
 import logging
 from ._backend cimport *
-from ._memory cimport _Memory
+from .memory._memory cimport _Memory
 from libc.stdlib cimport malloc, free
 
 

dpctl/memory/__init__.pxd

@@ -0,0 +1,30 @@
+##===------------- __init__.pxd - dpctl module --------*- Cython -*-------===##
+##
+##                      Data Parallel Control (dpCtl)
+##
+## Copyright 2020 Intel Corporation
+##
+## Licensed under the Apache License, Version 2.0 (the "License");
+## you may not use this file except in compliance with the License.
+## You may obtain a copy of the License at
+##
+##    http://www.apache.org/licenses/LICENSE-2.0
+##
+## Unless required by applicable law or agreed to in writing, software
+## distributed under the License is distributed on an "AS IS" BASIS,
+## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+## See the License for the specific language governing permissions and
+## limitations under the License.
+##
+##===----------------------------------------------------------------------===##
+##
+## \file
+## This file declares the extension types and functions for the Cython API
+## implemented in sycl_core.pyx.
+##
+##===----------------------------------------------------------------------===##
+
+# distutils: language = c++
+# cython: language_level=3
+
+from ._memory cimport *

dpctl/memory/__init__.py

@@ -0,0 +1,41 @@
+##===---------- memory/__init__.py - dpctl module -------*- Python -*------===##
+##
+##                      Data Parallel Control (dpCtl)
+##
+## Copyright 2020 Intel Corporation
+##
+## Licensed under the Apache License, Version 2.0 (the "License");
+## you may not use this file except in compliance with the License.
+## You may obtain a copy of the License at
+##
+##    http://www.apache.org/licenses/LICENSE-2.0
+##
+## Unless required by applicable law or agreed to in writing, software
+## distributed under the License is distributed on an "AS IS" BASIS,
+## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+## See the License for the specific language governing permissions and
+## limitations under the License.
+##
+##===----------------------------------------------------------------------===##
+##
+## \file
+## This top-level dpctl module.
+##
+##===----------------------------------------------------------------------===##
+"""
+    Data Parallel Control Memory
+
+    `dpctl.memory` provides Python objects for untyped USM memory 
+    container of bytes for each kind of USM pointers: shared pointers,
+    device pointers and host pointers.
+
+    Shared and host pointers are accessible from both host and a device,
+    while device pointers are only accessible from device.
+
+    Python objects corresponding to shared and host pointers implement 
+    Python simple buffer protocol. It is therefore possible to use these
+    objects to maniputalate USM memory using NumPy or `bytearray`, 
+    `memoryview`, or `array.array` classes.
+    
+"""
+from ._memory import MemoryUSMShared, MemoryUSMDevice, MemoryUSMHost

dpctl/_memory.pxd dpctl/memory/_memory.pxddpctl/_memory.pxd renamed to dpctl/memory/_memory.pxd

@@ -21,8 +21,8 @@
 # distutils: language = c++
 # cython: language_level=3
 
-from ._backend cimport DPPLSyclUSMRef
-from ._sycl_core cimport SyclQueue, SyclDevice, SyclContext
+from .._backend cimport DPPLSyclUSMRef
+from .._sycl_core cimport SyclQueue, SyclDevice, SyclContext
 
 
 cdef class _Memory:

dpctl/_memory.pyx dpctl/memory/_memory.pyxdpctl/_memory.pyx renamed to dpctl/memory/_memory.pyx

@@ -30,8 +30,8 @@
 
 import dpctl
 from dpctl._backend cimport *
-from ._sycl_core cimport SyclContext, SyclQueue, SyclDevice
-from ._sycl_core cimport get_current_queue
+from .._sycl_core cimport SyclContext, SyclQueue, SyclDevice
+from .._sycl_core cimport get_current_queue
 
 from cpython cimport Py_buffer
 from cpython.bytes cimport PyBytes_AS_STRING, PyBytes_FromStringAndSize

dpctl/tests/test_sycl_kernel_submit.py

@@ -25,7 +25,7 @@
 import ctypes
 import dpctl
 import unittest
-import dpctl._memory as dpctl_mem
+import dpctl.memory as dpctl_mem
 import numpy as np
 
 

dpctl/tests/test_sycl_queue_memcpy.py

@@ -23,13 +23,14 @@
 ##===----------------------------------------------------------------------===##
 
 import dpctl
+import dpctl.memory
 import unittest
 
 
 class TestQueueMemcpy(unittest.TestCase):
     def _create_memory(self):
         nbytes = 1024
-        mobj = dpctl.MemoryUSMShared(nbytes)
+        mobj = dpctl.memory.MemoryUSMShared(nbytes)
         return mobj
 
     @unittest.skipUnless(
@@ -60,7 +61,9 @@ def test_memcpy_type_error(self):
             q.memcpy(None, mobj, 3)
 
         self.assertEqual(type(cm.exception), TypeError)
-        self.assertEqual(str(cm.exception), "Parameter `dest` should have type _Memory.")
+        self.assertEqual(
+            str(cm.exception), "Parameter `dest` should have type _Memory."
+        )
 
         with self.assertRaises(TypeError) as cm:
             q.memcpy(mobj, None, 3)

dpctl/tests/test_sycl_usm.py

@@ -24,8 +24,7 @@
 
 import unittest
 import dpctl
-from dpctl import MemoryUSMShared, MemoryUSMHost, MemoryUSMDevice
-import dpctl._memory
+from dpctl.memory import MemoryUSMShared, MemoryUSMHost, MemoryUSMDevice
 import numpy as np
 
 

setup.py

@@ -115,9 +115,7 @@ def extensions():
         runtime_library_dirs = []
 
     extension_args = {
-        "depends": [
-            dppl_sycl_interface_include,
-        ],
+        "depends": [dppl_sycl_interface_include,],
         "include_dirs": [np.get_include(), dppl_sycl_interface_include],
         "extra_compile_args": eca + get_other_cxxflags(),
         "extra_link_args": ela,
@@ -130,16 +128,12 @@ def extensions():
     extensions = [
         Extension(
             "dpctl._sycl_core",
-            [
-                os.path.join("dpctl", "_sycl_core.pyx"),
-            ],
+            [os.path.join("dpctl", "_sycl_core.pyx"),],
             **extension_args
         ),
         Extension(
-            "dpctl._memory",
-            [
-                os.path.join("dpctl", "_memory.pyx"),
-            ],
+            "dpctl.memory._memory",
+            [os.path.join("dpctl", "memory", "_memory.pyx"),],
             **extension_args
         ),
     ]