CPU to CPU error-handling communication #118
Description
Hello,
As someone who is new to the topic of PCIe and driver development in general, I have some questions about how error-handling is performed between two CPUs that are setup for NTB. Based on my limited understanding, it seems that the switch sends some sort of error message to the CPU, which will then instruct the host running this driver, to perform some error handling operation.
Since this driver supports NTB operation, I would assume that there is some feature that supports error reporting to multiple hosts, so that all hosts that are linked through NTB would also receive the error reports. In this case, does the driver support some type of CPU to CPU communication? If so, would anyone be able to point me to which part of the code is responsible for this? Any insight regarding this topic would be greatly appreciated.