Added NoNullRangeWarning

JimLewis · JimLewis · commit 00c7d7d35ce1 · 2025-03-06T07:16:26.000-08:00
diff --git a/VendorScripts_ActiveHDL.tcl b/VendorScripts_ActiveHDL.tcl
@@ -253,6 +253,12 @@ proc vendor_analyze_verilog {LibraryName File_Relative_Path args} {
   cd $MY_START_DIR
 }
 
+# -------------------------------------------------
+proc NoNullRangeWarning  {} {
+  return "-nowarn COMP96_0119"
+}
+
+
 # -------------------------------------------------
 # End Previous Simulation
 #
diff --git a/VendorScripts_VSimSA.tcl b/VendorScripts_VSimSA.tcl
@@ -164,6 +164,11 @@ proc vendor_analyze_verilog {LibraryName FileName args} {
         vlog {*}$AnalyzeOptions
 }
 
+# -------------------------------------------------
+proc NoNullRangeWarning  {} {
+  return "-nowarn COMP96_0119"
+}
+
 # -------------------------------------------------
 # End Previous Simulation
 #

Original file line number	Diff line number	Diff line change
`@@ -253,6 +253,12 @@ proc vendor_analyze_verilog {LibraryName File_Relative_Path args} {`
`253`	`253`	`cd $MY_START_DIR`
`254`	`254`	`}`
`255`	`255`
	`256`	`+# -------------------------------------------------`
	`257`	`+proc NoNullRangeWarning {} {`
	`258`	`+ return "-nowarn COMP96_0119"`
	`259`	`+}`
	`260`	`+`
	`261`	`+`
`256`	`262`	`# -------------------------------------------------`
`257`	`263`	`# End Previous Simulation`
`258`	`264`	`#`
Original file line number	Diff line number	Diff line change
`@@ -164,6 +164,11 @@ proc vendor_analyze_verilog {LibraryName FileName args} {`
`164`	`164`	`vlog {*}$AnalyzeOptions`
`165`	`165`	`}`
`166`	`166`
	`167`	`+# -------------------------------------------------`
	`168`	`+proc NoNullRangeWarning {} {`
	`169`	`+ return "-nowarn COMP96_0119"`
	`170`	`+}`
	`171`	`+`
`167`	`172`	`# -------------------------------------------------`
`168`	`173`	`# End Previous Simulation`
`169`	`174`	`#`