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‎libcpu/arm/cortex-a/mmu.h‎

Lines changed: 72 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -41,45 +41,45 @@
4141
* bit[31:20]: Section Bass Address
4242
*/
4343

44-
#define DESC_SEC (0x2) /* for section type */
44+
#define DESC_SEC (0x2) /* for section type */
4545

4646
/* memory types and attributes(TEX C B) */
47-
#define MEMWBWA ((1<<12)|(3<<2)) /* write back, write allocate */
48-
#define MEMWB (3<<2) /* write back, no write allocate */
49-
#define MEMWT (2<<2) /* write through, no write allocate */
50-
#define SHAREDEVICE (1<<2) /* shared device */
51-
#define STRONGORDER (0<<2) /* strong ordered */
47+
#define MEMWBWA ((1 << 12) | (3 << 2)) /* write back, write allocate */
48+
#define MEMWB (3 << 2) /* write back, no write allocate */
49+
#define MEMWT (2 << 2) /* write through, no write allocate */
50+
#define SHAREDEVICE (1 << 2) /* shared device */
51+
#define STRONGORDER (0 << 2) /* strong ordered */
5252

53-
#define XN (1<<4)
53+
#define XN (1 << 4)
5454

5555
/* memory access permissions(AP APX) */
5656
#ifdef RT_USING_SMART
57-
#define AP_RW (1<<10) /* supervisor=RW, user=No */
58-
#define AP_RO ((1<<10) | (1 << 15)) /* supervisor=RO, user=No */
57+
#define AP_RW (1 << 10) /* supervisor=RW, user=No */
58+
#define AP_RO ((1 << 10) | (1 << 15)) /* supervisor=RO, user=No */
5959
#else
60-
#define AP_RW (3<<10) /* supervisor=RW, user=RW */
61-
#define AP_RO (2<<10) /* supervisor=RW, user=RO */
60+
#define AP_RW (3 << 10) /* supervisor=RW, user=RW */
61+
#define AP_RO (2 << 10) /* supervisor=RW, user=RO */
6262
#endif
6363

64-
#define SHARED (1 << 16)
64+
#define SHARED (1 << 16)
6565

6666
/* DACR, Domain n access permission */
67-
#define DOMAIN_FAULT (0x0) /* 0b00: No access */
68-
#define DOMAIN_CHK (0x1) /* 0b01: Client */
69-
#define DOMAIN_NOTCHK (0x3) /* 0b11: No check */
67+
#define DOMAIN_FAULT (0x0) /* 0b00: No access */
68+
#define DOMAIN_CHK (0x1) /* 0b01: Client */
69+
#define DOMAIN_NOTCHK (0x3) /* 0b11: No check */
7070

7171
/* Domain */
72-
#define DOMAIN0 (0x0<<5)
73-
#define DOMAIN1 (0x1<<5)
72+
#define DOMAIN0 (0x0 << 5)
73+
#define DOMAIN1 (0x1 << 5)
7474

7575
/* DACR */
76-
#define DOMAIN0_ATTR (DOMAIN_CHK<<0) /* domain0 use client mode */
77-
#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) /* domain1 use no access mode */
76+
#define DOMAIN0_ATTR (DOMAIN_CHK << 0) /* domain0 use client mode */
77+
#define DOMAIN1_ATTR (DOMAIN_FAULT << 2) /* domain1 use no access mode */
7878

7979
/* Memory types */
80-
#define DEVICE_MEM (SHARED|AP_RW|DOMAIN0|SHAREDEVICE|DESC_SEC|XN)
81-
#define NORMAL_MEM (SHARED|AP_RW|DOMAIN0|MEMWBWA|DESC_SEC)
82-
#define STRONG_ORDER_MEM (SHARED|AP_RO|XN|DESC_SEC)
80+
#define DEVICE_MEM (SHARED | AP_RW | DOMAIN0 | SHAREDEVICE | DESC_SEC | XN)
81+
#define NORMAL_MEM (SHARED | AP_RW | DOMAIN0 | MEMWBWA | DESC_SEC)
82+
#define STRONG_ORDER_MEM (SHARED | AP_RO | XN | DESC_SEC)
8383

8484
struct mem_desc
8585
{
@@ -110,27 +110,27 @@ struct mem_desc
110110
* bit[11]: nG
111111
* bit[31:12]: Small Page Base Address
112112
*/
113-
#define MMU_MAP_MTBL_XN (1<<0)
114-
#define MMU_MAP_MTBL_A (1<<1)
115-
#define MMU_MAP_MTBL_B (1<<2)
116-
#define MMU_MAP_MTBL_C (1<<3)
117-
#define MMU_MAP_MTBL_AP01(x) (x<<4)
118-
#define MMU_MAP_MTBL_TEX(x) (x<<6)
119-
#define MMU_MAP_MTBL_AP2(x) (x<<9)
120-
#define MMU_MAP_MTBL_SHARE (1<<10)
121-
#define MMU_MAP_MTBL_NG(x) (x<<11)
122-
123-
#define MMU_MAP_K_ROCB ((MMU_MAP_MTBL_NG(0))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(1)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE))
124-
#define MMU_MAP_K_RO ((MMU_MAP_MTBL_NG(0))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(1)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE))
125-
#define MMU_MAP_K_RWCB ((MMU_MAP_MTBL_NG(0))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE))
126-
#define MMU_MAP_K_RW ((MMU_MAP_MTBL_NG(0))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_SHARE))
127-
#define MMU_MAP_K_DEVICE ((MMU_MAP_MTBL_NG(0))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_SHARE))
128-
#define MMU_MAP_U_ROCB ((MMU_MAP_MTBL_NG(1))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(2)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE))
129-
#define MMU_MAP_U_RO ((MMU_MAP_MTBL_NG(1))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(2)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE))
130-
#define MMU_MAP_U_RWCB ((MMU_MAP_MTBL_NG(1))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE))
131-
#define MMU_MAP_U_RW ((MMU_MAP_MTBL_NG(1))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_SHARE))
132-
#define MMU_MAP_U_DEVICE ((MMU_MAP_MTBL_NG(1))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_SHARE))
133-
#define MMU_MAP_TRACE(attr) (attr)
113+
#define MMU_MAP_MTBL_XN (1 << 0)
114+
#define MMU_MAP_MTBL_A (1 << 1)
115+
#define MMU_MAP_MTBL_B (1 << 2)
116+
#define MMU_MAP_MTBL_C (1 << 3)
117+
#define MMU_MAP_MTBL_AP01(x) (x << 4)
118+
#define MMU_MAP_MTBL_TEX(x) (x << 6)
119+
#define MMU_MAP_MTBL_AP2(x) (x << 9)
120+
#define MMU_MAP_MTBL_SHARE (1 << 10)
121+
#define MMU_MAP_MTBL_NG(x) (x << 11)
122+
123+
#define MMU_MAP_K_ROCB ((MMU_MAP_MTBL_NG(0)) | (MMU_MAP_MTBL_A | MMU_MAP_MTBL_AP2(1) | MMU_MAP_MTBL_AP01(1) | MMU_MAP_MTBL_TEX(0) | MMU_MAP_MTBL_B | MMU_MAP_MTBL_C | MMU_MAP_MTBL_SHARE))
124+
#define MMU_MAP_K_RO ((MMU_MAP_MTBL_NG(0)) | (MMU_MAP_MTBL_A | MMU_MAP_MTBL_AP2(1) | MMU_MAP_MTBL_AP01(1) | MMU_MAP_MTBL_TEX(0) | MMU_MAP_MTBL_C | MMU_MAP_MTBL_SHARE))
125+
#define MMU_MAP_K_RWCB ((MMU_MAP_MTBL_NG(0)) | (MMU_MAP_MTBL_A | MMU_MAP_MTBL_AP2(0) | MMU_MAP_MTBL_AP01(1) | MMU_MAP_MTBL_TEX(0) | MMU_MAP_MTBL_B | MMU_MAP_MTBL_C | MMU_MAP_MTBL_SHARE))
126+
#define MMU_MAP_K_RW ((MMU_MAP_MTBL_NG(0)) | (MMU_MAP_MTBL_A | MMU_MAP_MTBL_AP2(0) | MMU_MAP_MTBL_AP01(1) | MMU_MAP_MTBL_TEX(0) | MMU_MAP_MTBL_SHARE))
127+
#define MMU_MAP_K_DEVICE ((MMU_MAP_MTBL_NG(0)) | (MMU_MAP_MTBL_A | MMU_MAP_MTBL_AP2(0) | MMU_MAP_MTBL_AP01(1) | MMU_MAP_MTBL_TEX(0) | MMU_MAP_MTBL_B | MMU_MAP_MTBL_SHARE))
128+
#define MMU_MAP_U_ROCB ((MMU_MAP_MTBL_NG(1)) | (MMU_MAP_MTBL_A | MMU_MAP_MTBL_AP2(0) | MMU_MAP_MTBL_AP01(2) | MMU_MAP_MTBL_TEX(0) | MMU_MAP_MTBL_B | MMU_MAP_MTBL_C | MMU_MAP_MTBL_SHARE))
129+
#define MMU_MAP_U_RO ((MMU_MAP_MTBL_NG(1)) | (MMU_MAP_MTBL_A | MMU_MAP_MTBL_AP2(0) | MMU_MAP_MTBL_AP01(2) | MMU_MAP_MTBL_TEX(0) | MMU_MAP_MTBL_C | MMU_MAP_MTBL_SHARE))
130+
#define MMU_MAP_U_RWCB ((MMU_MAP_MTBL_NG(1)) | (MMU_MAP_MTBL_A | MMU_MAP_MTBL_AP2(0) | MMU_MAP_MTBL_AP01(3) | MMU_MAP_MTBL_TEX(0) | MMU_MAP_MTBL_B | MMU_MAP_MTBL_C | MMU_MAP_MTBL_SHARE))
131+
#define MMU_MAP_U_RW ((MMU_MAP_MTBL_NG(1)) | (MMU_MAP_MTBL_A | MMU_MAP_MTBL_AP2(0) | MMU_MAP_MTBL_AP01(3) | MMU_MAP_MTBL_TEX(0) | MMU_MAP_MTBL_SHARE))
132+
#define MMU_MAP_U_DEVICE ((MMU_MAP_MTBL_NG(1)) | (MMU_MAP_MTBL_A | MMU_MAP_MTBL_AP2(0) | MMU_MAP_MTBL_AP01(3) | MMU_MAP_MTBL_TEX(0) | MMU_MAP_MTBL_B | MMU_MAP_MTBL_SHARE))
133+
#define MMU_MAP_TRACE(attr) (attr)
134134

135135
#define ARCH_SECTION_SHIFT 20
136136
#define ARCH_SECTION_SIZE (1 << ARCH_SECTION_SHIFT)
@@ -142,7 +142,7 @@ struct mem_desc
142142
#define ARCH_PAGE_TBL_SIZE (1 << ARCH_PAGE_TBL_SHIFT)
143143
#define ARCH_PAGE_TBL_MASK (ARCH_PAGE_TBL_SIZE - 1)
144144

145-
#define ARCH_MMU_USED_MASK 3
145+
#define ARCH_MMU_USED_MASK 3
146146

147147
#define ARCH_TYPE_SUPERSECTION (1 << 18)
148148

@@ -198,24 +198,24 @@ rt_inline size_t rt_hw_mmu_attr_rm_perm(size_t attr, rt_base_t prot)
198198
switch (prot)
199199
{
200200
/* remove write permission for user */
201-
case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_USER:
202-
if ((attr & AP_APX_MASK) == AP_APX_URW_KRW)
203-
attr &= ~MMU_MAP_MTBL_AP01(0x1);
204-
break;
205-
case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_KERNEL:
206-
switch (attr & AP_APX_MASK)
207-
{
208-
case MMU_MAP_MTBL_AP01(0):
209-
break;
210-
case MMU_MAP_MTBL_AP01(3):
211-
attr = (attr & AP_APX_MASK) | AP_APX_URO_KRO;
212-
default:
213-
attr |= MMU_MAP_MTBL_AP2(0x1);
214-
break;
215-
}
201+
case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_USER:
202+
if ((attr & AP_APX_MASK) == AP_APX_URW_KRW)
203+
attr &= ~MMU_MAP_MTBL_AP01(0x1);
204+
break;
205+
case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_KERNEL:
206+
switch (attr & AP_APX_MASK)
207+
{
208+
case MMU_MAP_MTBL_AP01(0):
216209
break;
210+
case MMU_MAP_MTBL_AP01(3):
211+
attr = (attr & AP_APX_MASK) | AP_APX_URO_KRO;
217212
default:
218-
RT_ASSERT(0);
213+
attr |= MMU_MAP_MTBL_AP2(0x1);
214+
break;
215+
}
216+
break;
217+
default:
218+
RT_ASSERT(0);
219219
}
220220
return attr;
221221
}
@@ -232,13 +232,13 @@ rt_inline size_t rt_hw_mmu_attr_add_perm(size_t attr, rt_base_t prot)
232232
switch (prot)
233233
{
234234
/* add write permission for user */
235-
case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_USER:
236-
case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_KERNEL:
237-
attr |= MMU_MAP_MTBL_AP01(0x3);
238-
attr &= ~MMU_MAP_MTBL_AP2(0x1);
239-
break;
240-
default:
241-
RT_ASSERT(0);
235+
case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_USER:
236+
case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_KERNEL:
237+
attr |= MMU_MAP_MTBL_AP01(0x3);
238+
attr &= ~MMU_MAP_MTBL_AP2(0x1);
239+
break;
240+
default:
241+
RT_ASSERT(0);
242242
}
243243
return attr;
244244
}
@@ -256,11 +256,11 @@ rt_inline rt_bool_t rt_hw_mmu_attr_test_perm(size_t attr, rt_base_t prot)
256256
switch (prot)
257257
{
258258
/* test write permission for user */
259-
case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_USER:
260-
rc = (AP_APX_MASK & attr) == (AP_APX_URW_KRW);
261-
break;
262-
default:
263-
RT_ASSERT(0);
259+
case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_USER:
260+
rc = (AP_APX_MASK & attr) == (AP_APX_URW_KRW);
261+
break;
262+
default:
263+
RT_ASSERT(0);
264264
}
265265
return rc;
266266
}

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