diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index 84f272d066f..959b28b122f 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -338,6 +338,7 @@ "Infineon/psoc6-cy8cproto-062S3-4343W", "Infineon/psoc6-evaluationkit-062S2", "Infineon/xmc7200-kit_xmc7200_evk", + "Infineon/xmc7100d-f144k4160aa", "fujitsu/mb9x/mb9bf500r", "fujitsu/mb9x/mb9bf506r", "fujitsu/mb9x/mb9bf618s", diff --git a/bsp/Infineon/libraries/HAL_Drivers/SConscript b/bsp/Infineon/libraries/HAL_Drivers/SConscript index 67987d27deb..2b7bb6f2e72 100644 --- a/bsp/Infineon/libraries/HAL_Drivers/SConscript +++ b/bsp/Infineon/libraries/HAL_Drivers/SConscript @@ -23,7 +23,7 @@ if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): src += ['drv_soft_i2c.c'] if GetDepend(['RT_USING_I2C']): - if GetDepend('BSP_USING_HW_I2C3') or GetDepend('BSP_USING_HW_I2C4') or GetDepend('BSP_USING_HW_I2C6'): + if GetDepend('BSP_USING_HW_I2C1') or GetDepend('BSP_USING_HW_I2C3') or GetDepend('BSP_USING_HW_I2C4') or GetDepend('BSP_USING_HW_I2C6'): src += ['drv_i2c.c'] if GetDepend(['BSP_USING_SDIO1']): diff --git a/bsp/Infineon/libraries/HAL_Drivers/drv_i2c.c b/bsp/Infineon/libraries/HAL_Drivers/drv_i2c.c index 4c27665df58..f6408191f01 100644 --- a/bsp/Infineon/libraries/HAL_Drivers/drv_i2c.c +++ b/bsp/Infineon/libraries/HAL_Drivers/drv_i2c.c @@ -6,14 +6,24 @@ * Change Logs: * Date Author Notes * 2022-07-08 Rbb666 first implementation. + * 2025-04-21 Hydevcode adapt xmc7100d */ #include "board.h" #if defined(RT_USING_I2C) -#if defined(BSP_USING_HW_I2C2) || defined(BSP_USING_HW_I2C3) || defined(BSP_USING_HW_I2C4)|| defined(BSP_USING_HW_I2C6) +#if defined(BSP_USING_HW_I2C1) || defined(BSP_USING_HW_I2C2) || defined(BSP_USING_HW_I2C3) || defined(BSP_USING_HW_I2C4)|| defined(BSP_USING_HW_I2C6) #include +#ifndef I2C1_CONFIG +#define I2C1_CONFIG \ + { \ + .name = "i2c1", \ + .scl_pin = BSP_I2C1_SCL_PIN, \ + .sda_pin = BSP_I2C1_SDA_PIN, \ + } +#endif /* I2C1_CONFIG */ + #ifndef I2C2_CONFIG #define I2C2_CONFIG \ { \ @@ -53,6 +63,9 @@ enum { +#ifdef BSP_USING_HW_I2C1 + I2C1_INDEX, +#endif #ifdef BSP_USING_HW_I2C2 I2C2_INDEX, #endif @@ -84,6 +97,10 @@ struct ifx_i2c static struct ifx_i2c_config i2c_config[] = { +#ifdef BSP_USING_HW_I2C1 + I2C1_CONFIG, +#endif + #ifdef BSP_USING_HW_I2C2 I2C2_CONFIG, #endif diff --git a/bsp/Infineon/libraries/HAL_Drivers/drv_uart.c b/bsp/Infineon/libraries/HAL_Drivers/drv_uart.c index 593439740f4..0b43792bf16 100644 --- a/bsp/Infineon/libraries/HAL_Drivers/drv_uart.c +++ b/bsp/Infineon/libraries/HAL_Drivers/drv_uart.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2022-06-29 Rbb666 first version + * 2025-04-21 hydevcode modify xmc7100d uart */ #include @@ -228,9 +229,10 @@ static rt_err_t ifx_control(struct rt_serial_device *serial, int cmd, void *arg) /* Enable the interrupt */ #if defined(SOC_SERIES_IFX_XMC) + NVIC_DisableIRQ(UART_NvicMuxN_IRQn); NVIC_EnableIRQ(UART_NvicMuxN_IRQn); #else - NVIC_EnableIRQ(uart->config->intrSrc); + NVIC_EnableIRQ(uart->config->UART_SCB_IRQ_cfg->intrSrc); #endif break; } diff --git a/bsp/Infineon/libraries/HAL_Drivers/drv_uart.h b/bsp/Infineon/libraries/HAL_Drivers/drv_uart.h index 6afec51cc04..c9a82b96537 100644 --- a/bsp/Infineon/libraries/HAL_Drivers/drv_uart.h +++ b/bsp/Infineon/libraries/HAL_Drivers/drv_uart.h @@ -21,16 +21,10 @@ struct ifx_uart_config { cyhal_uart_t *uart_obj; - const char *name; rt_uint32_t tx_pin; rt_uint32_t rx_pin; CySCB_Type *usart_x; -#if defined(SOC_SERIES_IFX_XMC) - rt_uint32_t intrSrc; -#else - IRQn_Type intrSrc; -#endif cy_israddress userIsr; cy_stc_sysint_t *UART_SCB_IRQ_cfg; }; diff --git a/bsp/Infineon/libraries/HAL_Drivers/uart_config.h b/bsp/Infineon/libraries/HAL_Drivers/uart_config.h index e0165c858f6..cef7c74b9ba 100644 --- a/bsp/Infineon/libraries/HAL_Drivers/uart_config.h +++ b/bsp/Infineon/libraries/HAL_Drivers/uart_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2022-07-08 Rbb666 first version + * 2025-04-21 Hydevcode adapt xmc7100d */ #ifndef __UART_CONFIG_H__ @@ -45,7 +46,11 @@ extern "C" /* UART0 device driver structure */ cy_stc_sysint_t UART0_SCB_IRQ_cfg = { +#if defined(SOC_SERIES_IFX_XMC) + .intrSrc = ((UART_NvicMuxN_IRQn << 16) | (cy_en_intr_t)scb_0_interrupt_IRQn), +#else .intrSrc = (IRQn_Type)scb_0_interrupt_IRQn, +#endif .intrPriority = (7u), }; #endif @@ -53,7 +58,11 @@ extern "C" /* UART1 device driver structure */ cy_stc_sysint_t UART1_SCB_IRQ_cfg = { +#if defined(SOC_SERIES_IFX_XMC) + .intrSrc = ((UART_NvicMuxN_IRQn << 16) | (cy_en_intr_t)scb_1_interrupt_IRQn), +#else .intrSrc = (IRQn_Type)scb_1_interrupt_IRQn, +#endif .intrPriority = (7u), }; #endif @@ -61,7 +70,11 @@ extern "C" /* UART2 device driver structure */ cy_stc_sysint_t UART2_SCB_IRQ_cfg = { +#if defined(SOC_SERIES_IFX_XMC) + .intrSrc = ((UART_NvicMuxN_IRQn << 16) | (cy_en_intr_t)scb_2_interrupt_IRQn), +#else .intrSrc = (IRQn_Type)scb_2_interrupt_IRQn, +#endif .intrPriority = (7u), }; #endif @@ -81,7 +94,11 @@ extern "C" /* UART4 device driver structure */ cy_stc_sysint_t UART4_SCB_IRQ_cfg = { +#if defined(SOC_SERIES_IFX_XMC) + .intrSrc = ((UART_NvicMuxN_IRQn << 16) |(cy_en_intr_t)scb_4_interrupt_IRQn), +#else .intrSrc = (IRQn_Type)scb_4_interrupt_IRQn, +#endif .intrPriority = (7u), }; #endif @@ -89,7 +106,11 @@ extern "C" /* UART5 device driver structure */ cy_stc_sysint_t UART5_SCB_IRQ_cfg = { +#if defined(SOC_SERIES_IFX_XMC) + .intrSrc = ((UART_NvicMuxN_IRQn << 16) |(cy_en_intr_t)scb_5_interrupt_IRQn), +#else .intrSrc = (IRQn_Type)scb_5_interrupt_IRQn, +#endif .intrPriority = (7u), }; #endif @@ -97,7 +118,11 @@ extern "C" /* UART6 device driver structure */ cy_stc_sysint_t UART6_SCB_IRQ_cfg = { +#if defined(SOC_SERIES_IFX_XMC) + .intrSrc = ((UART_NvicMuxN_IRQn << 16) |(cy_en_intr_t)scb_6_interrupt_IRQn), +#else .intrSrc = (IRQn_Type)scb_6_interrupt_IRQn, +#endif .intrPriority = (7u), }; #endif @@ -110,7 +135,6 @@ extern "C" .tx_pin = P0_3, \ .rx_pin = P0_2, \ .usart_x = SCB0, \ - .intrSrc = scb_0_interrupt_IRQn, \ .userIsr = uart_isr_callback(uart0), \ .UART_SCB_IRQ_cfg = &UART0_SCB_IRQ_cfg, \ } @@ -126,7 +150,6 @@ extern "C" .tx_pin = P10_1, \ .rx_pin = P10_0, \ .usart_x = SCB1, \ - .intrSrc = scb_1_interrupt_IRQn, \ .userIsr = uart_isr_callback(uart1), \ .UART_SCB_IRQ_cfg = &UART1_SCB_IRQ_cfg, \ } @@ -136,14 +159,13 @@ extern "C" #if defined(BSP_USING_UART2) #ifndef UART2_CONFIG -#if defined(SOC_CY8C6244LQI_S4D92) +#if defined(SOC_XMC7100D_F144K4160AA) #define UART2_CONFIG \ { \ .name = "uart2", \ - .tx_pin = P3_1, \ - .rx_pin = P3_0, \ + .tx_pin = P19_1, \ + .rx_pin = P19_0, \ .usart_x = SCB2, \ - .intrSrc = scb_2_interrupt_IRQn, \ .userIsr = uart_isr_callback(uart2), \ .UART_SCB_IRQ_cfg = &UART2_SCB_IRQ_cfg, \ } @@ -154,7 +176,6 @@ extern "C" .tx_pin = P9_1, \ .rx_pin = P9_0, \ .usart_x = SCB2, \ - .intrSrc = scb_2_interrupt_IRQn, \ .userIsr = uart_isr_callback(uart2), \ .UART_SCB_IRQ_cfg = &UART2_SCB_IRQ_cfg, \ } @@ -172,7 +193,6 @@ extern "C" .tx_pin = P13_1, \ .rx_pin = P13_0, \ .usart_x = SCB3, \ - .intrSrc = scb_3_interrupt_IRQn, \ .userIsr = uart_isr_callback(uart3), \ .UART_SCB_IRQ_cfg = &UART3_SCB_IRQ_cfg, \ } @@ -183,7 +203,6 @@ extern "C" .tx_pin = P6_1, \ .rx_pin = P6_0, \ .usart_x = SCB3, \ - .intrSrc = scb_3_interrupt_IRQn, \ .userIsr = uart_isr_callback(uart3), \ .UART_SCB_IRQ_cfg = &UART3_SCB_IRQ_cfg, \ } @@ -194,16 +213,27 @@ extern "C" #if defined(BSP_USING_UART4) #ifndef UART4_CONFIG +#if defined(SOC_XMC7100D_F144K4160AA) +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .tx_pin = P10_1, \ + .rx_pin = P10_0, \ + .usart_x = SCB4, \ + .userIsr = uart_isr_callback(uart4), \ + .UART_SCB_IRQ_cfg = &UART4_SCB_IRQ_cfg, \ + } +#else #define UART4_CONFIG \ { \ .name = "uart4", \ .tx_pin = P7_1, \ .rx_pin = P7_0, \ .usart_x = SCB4, \ - .intrSrc = scb_4_interrupt_IRQn, \ .userIsr = uart_isr_callback(uart4), \ .UART_SCB_IRQ_cfg = &UART4_SCB_IRQ_cfg, \ } +#endif void uart4_isr_callback(void); #endif /* UART4_CONFIG */ #endif /* BSP_USING_UART4 */ @@ -216,7 +246,6 @@ extern "C" .tx_pin = P5_1, \ .rx_pin = P5_0, \ .usart_x = SCB5, \ - .intrSrc = scb_5_interrupt_IRQn, \ .userIsr = uart_isr_callback(uart5), \ .UART_SCB_IRQ_cfg = &UART5_SCB_IRQ_cfg, \ } @@ -232,7 +261,6 @@ extern "C" .tx_pin = P6_5, \ .rx_pin = P6_4, \ .usart_x = SCB6, \ - .intrSrc = scb_6_interrupt_IRQn, \ .userIsr = uart_isr_callback(uart6), \ .UART_SCB_IRQ_cfg = &UART6_SCB_IRQ_cfg, \ } diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/.ci/attachconfig/ci.attachconfig.yml b/bsp/Infineon/xmc7100d-f144k4160aa/.ci/attachconfig/ci.attachconfig.yml new file mode 100644 index 00000000000..da7fa27476c --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/.ci/attachconfig/ci.attachconfig.yml @@ -0,0 +1,9 @@ +scons.args: &scons + scons_arg: + - '--strict' +# ------ Drivers CI ------ +Drivers.I2C: + <<: *scons + kconfig: + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_HW_I2C1=y diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/.config b/bsp/Infineon/xmc7100d-f144k4160aa/.config new file mode 100644 index 00000000000..dac8c318bd1 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/.config @@ -0,0 +1,1390 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options + +# CONFIG_RT_UTEST_TC_USING_KLIBC is not set +# end of klibc options + +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_HOOKLIST=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart4" +CONFIG_RT_VER_NUM=0x50201 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_CACHE=y +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M7=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +CONFIG_PKG_USING_INFINEON_CAT1CM0P=y +CONFIG_PKG_INFINEON_CAT1CM0P_PATH="/packages/peripherals/hal-sdk/Infineon/Infineon_cat1cm0p" +CONFIG_PKG_USING_INFINEON_CAT1CM0P_LATEST_VERSION=y +CONFIG_PKG_INFINEON_CAT1CM0P_VER="latest" +CONFIG_PKG_USING_INFINEON_CMSIS=y +CONFIG_PKG_INFINEON_CMSIS_PATH="/packages/peripherals/hal-sdk/Infineon/Infineon_cmsis" +CONFIG_PKG_USING_INFINEON_CMSIS_LATEST_VERSION=y +CONFIG_PKG_INFINEON_CMSIS_VER="latest" +CONFIG_PKG_USING_INFINEON_CORE_LIB=y +CONFIG_PKG_INFINEON_CORE_LIB_PATH="/packages/peripherals/hal-sdk/Infineon/Infineon_core-lib" +CONFIG_PKG_USING_INFINEON_CORE_LIB_LATEST_VERSION=y +CONFIG_PKG_INFINEON_CORE_LIB_VER="latest" +CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1=y +CONFIG_PKG_INFINEON_MTB_HAL_CAT1_PATH="/packages/peripherals/hal-sdk/Infineon/Infineon_mtb-hal-cat1" +CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1_LATEST_VERSION=y +CONFIG_PKG_INFINEON_MTB_HAL_CAT1_VER="latest" +CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1=y +CONFIG_PKG_INFINEON_MTB_PDL_CAT1_PATH="/packages/peripherals/hal-sdk/Infineon/Infineon_mtb-pdl-cat1" +CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1_LATEST_VERSION=y +CONFIG_PKG_INFINEON_MTB_PDL_CAT1_VER="latest" +CONFIG_PKG_USING_INFINEON_RETARGET_IO=y +CONFIG_PKG_INFINEON_RETARGET_IO_PATH="/packages/peripherals/hal-sdk/Infineon/Infineon_retarget-io" +CONFIG_PKG_USING_INFINEON_RETARGET_IO_LATEST_VERSION=y +CONFIG_PKG_INFINEON_RETARGET_IO_VER="latest" +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_FAMILY_IFX=y +CONFIG_SOC_SERIES_IFX_XMC=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_XMC7100D_F144K4160AA=y + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_USB_TO_USART=y +# end of Onboard Peripheral Drivers + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART2=y +CONFIG_BSP_USING_UART4=y +CONFIG_UART_CPU_IRQ_Number=3 +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_ETH is not set +# end of On-chip Peripheral Drivers +# end of Hardware Drivers Config diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/.gitignore b/bsp/Infineon/xmc7100d-f144k4160aa/.gitignore new file mode 100644 index 00000000000..7221bde019d --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/Kconfig b/bsp/Infineon/xmc7100d-f144k4160aa/Kconfig new file mode 100644 index 00000000000..73238d3a13b --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/README.md b/bsp/Infineon/xmc7100d-f144k4160aa/README.md new file mode 100644 index 00000000000..8510d79422a --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/README.md @@ -0,0 +1,132 @@ +# Infineon XMC7100D-F144K4160AA 说明 + +## 简介 + +本文档为 `RT-Thread` 为 ` XMC7100D-F144K4160AA`开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 `RT-Thread` 驱动更多板载资源。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **片上外设** | **支持情况** | **备注** | +| :----------: | :----------: | :------: | +| USB 转串口 | 支持 | UART4 | +| GPIO | 支持 | — | +| UART | 支持 | UART2,UART4 | +| I2C | 支持 | I2C1 | + +## 快速上手 + +本 BSP 是以 `GCC` 和 `Jlink` 为开发环境（编译器：GCC），接下来介绍如何将系统运行起来。 + +### 使用 Vscode 开发 + +#### 硬件连接 + +将开发板的swd接口与jlink相连,注意jlink版本建议V8.18以上 + +#### 编译下载 + +1、下载软件包：在ENV环境下输入`pkgs --update`命令，将所需要的HAL库软件包下载下来，文件会存放在`Packages`目录下。 + +2、编译工程：在ENV环境下输入`SCons -j4`或者 `SCons -j16` 命令，j后面的数字取决于cpu线程数，然后ENV会自动编译生成可烧写elf文件 + +3、下载此工程： + +Vscode下载拓展Cortex-Debug，然后在.vscode下新建launch.json文件,并添加以下内容 + +``` + +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Launch XMC7100D CM7 (JLink)", + "type": "cortex-debug", + "request": "launch", + "cwd": "${workspaceFolder}", + "executable": "${workspaceRoot}/rt-thread.elf", + "servertype": "jlink", + "device": "XMC7100-4160_CM7_0_tm", + "interface": "swd", + "serialNumber": "", + "preLaunchCommands": [ + // Program via the hex file to get complete coverage + "exec-file rt-thread.hex" + ], + "overrideRestartCommands": [ + "starti" + ], + // svdFile is optional, it can be very large. + "svdFile": "${workspaceRoot}/libs/cat1c4m.svd", + "breakAfterReset": true, + "runToEntryPoint": "main", // Specifies application entry point name where program will halt + "showDevDebugOutput": "none", + "presentation": { + "hidden": false, + "group": "CM7" + }, + "serverpath": "C:/Program Files/SEGGER/JLink_V820/JLinkGDBServerCL.exe" + }, + // When using 'attach', make sure your program is running on the board and that your + // executable matches the image in the chip exactly, or else strange things can happen + // with breakpoints, variables, etc. + { + "name": "Attach XMC7100D CM7 (JLink)", + "type": "cortex-debug", + "request": "attach", + "cwd": "${workspaceFolder}", + "executable": "${workspaceRoot}/rt-thread.elf", + "servertype": "jlink", + "device": "XMC7100-4160_CM7_0_tm", + "interface": "swd", + "serialNumber": "", + "overrideRestartCommands": [ + "starti" + ], + // svdFile is optional, it can be very large. + "svdFile": "${workspaceRoot}/libs/cat1c4m.svd", + "breakAfterReset": true, + "runToEntryPoint": "main", // Specifies application entry point name for restart/reset + "showDevDebugOutput": "none", + "presentation": { + "hidden": false, + "group": "CM7" + }, + "serverpath": "C:/Program Files/SEGGER/JLink_V820/JLinkGDBServerCL.exe" + } + ] +} + +``` + +随后点击运行按钮即可自动下载程序到开发板 + +## 运行结果 + +下载程序成功之后，点击全速运行。然后打开终端工具串口助手，选择波特率为 115200。复位设备后，LED 将会闪烁，而且在终端上可以看到 `RT-Thread` 的输出信息： + +注：推荐使用串口调试助手如：`MobaXterm` + +```c + \ | / +- RT - Thread Operating System + / | \ 5.2.1 build Apr 21 2025 20:49:36 + 2006 - 2024 Copyright by RT-Thread team +msh > +``` + +## 联系人 + +维护人: + +- [LZerro](https://github.com/LZerro) +- [Hydevcode](https://github.com/hydevcode) \ No newline at end of file diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/SConscript b/bsp/Infineon/xmc7100d-f144k4160aa/SConscript new file mode 100644 index 00000000000..20f7689c53c --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/SConstruct b/bsp/Infineon/xmc7100d-f144k4160aa/SConstruct new file mode 100644 index 00000000000..332a1f967ef --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/SConstruct @@ -0,0 +1,59 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +libraries_path_prefix = SDK_ROOT + +if os.path.exists(SDK_ROOT + '/packages'): + libraries_path_prefix = SDK_ROOT + '/packages' +else: + print("Error: Packages for HAL_Driver does not exist, pull it in ENV using `pkg --update`.") + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +IFX_library = 'Packages' +rtconfig.BSP_LIBRARY_TYPE = IFX_library + +# include drivers +objs.extend(SConscript(os.path.join('../libraries', 'HAL_Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/applications/SConscript b/bsp/Infineon/xmc7100d-f144k4160aa/applications/SConscript new file mode 100644 index 00000000000..034056eca76 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/applications/SConscript @@ -0,0 +1,16 @@ +import rtconfig +from building import * +import os + +cwd = GetCurrentDir() +path = [cwd] +src = Glob('*.c') + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = path) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/applications/main.c b/bsp/Infineon/xmc7100d-f144k4160aa/applications/main.c new file mode 100644 index 00000000000..9ace23db528 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/applications/main.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-04-15 Hydevcode first version + */ +#include +#include + +#include "drv_gpio.h" + +#define LED_PIN GET_PIN(10, 3) + +int main(void) +{ + rt_kprintf("\nHello RT-Thread!\n"); + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + while (1) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(1000); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(1000); + } +} \ No newline at end of file diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/board/Kconfig b/bsp/Infineon/xmc7100d-f144k4160aa/board/Kconfig new file mode 100644 index 00000000000..5e624f01927 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/board/Kconfig @@ -0,0 +1,65 @@ +menu "Hardware Drivers Config" + +config SOC_XMC7100D_F144K4160AA + bool + select SOC_SERIES_IFX_XMC + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + + config BSP_USING_USB_TO_USART + bool "Enable USB TO USART (uart4)" + select BSP_USING_GPIO + select BSP_USING_UART + select BSP_USING_UART4 + default y +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART2 + bool "Enable UART2" + default n + config BSP_USING_UART4 + bool "Enable UART4" + default y + config UART_CPU_IRQ_Number + int "UART connect CPU Interrupt Number (0-7)" + range 0 7 + default 3 + endif + menuconfig BSP_USING_I2C + bool "Enable HW I2C" + default n + select RT_USING_I2C + if BSP_USING_I2C + menuconfig BSP_USING_HW_I2C1 + bool "Enable BSP_USING_HW_I2C1" + default n + if BSP_USING_HW_I2C1 + config BSP_I2C1_SCL_PIN + int "BSP_I2C1_SCL_PIN number(18,2)" + range 0 999 + default 146 + config BSP_I2C1_SDA_PIN + int "BSP_I2C1_SDA_PIN number(18,1)" + range 0 999 + default 145 + endif + endif + +endmenu + +endmenu diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/board/SConscript b/bsp/Infineon/xmc7100d-f144k4160aa/board/SConscript new file mode 100644 index 00000000000..d4626d83e4c --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/board/SConscript @@ -0,0 +1,61 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +objs = [] +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +''') + +path = [cwd] +path += [cwd + '/ports'] + +startup_path_prefix = SDK_LIB +Tool_path = None +index = 'Infineon_mtb-pdl-cat1-latest' + +for filename in os.listdir(startup_path_prefix): + if index in filename: + Tool_path = os.path.join(startup_path_prefix, filename) + +if rtconfig.PLATFORM in ['gcc']: + src += [Tool_path + + '/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_ext.S'] +elif rtconfig.PLATFORM in ['armclang']: + src += [Tool_path + + '/drivers/source/TOOLCHAIN_ARM/cy_syslib_ext.s'] +# CPPDEFINES = [] +CPPDEFINES = ['XMC7100D_F144K4160', + 'COMPONENT_APP_KIT_XMC71_EVK_LITE_V2', + 'COMPONENT_CAT1', + 'COMPONENT_CAT1C', + 'COMPONENT_CAT1C4M', + 'COMPONENT_CM7', + 'COMPONENT_CM7_0', + 'COMPONENT_Debug' + 'COMPONENT_GCC_ARM', + 'COMPONENT_MW_CAT1CM0P', + 'COMPONENT_MW_CMSIS', + 'COMPONENT_MW_CORE_LIB', + 'COMPONENT_MW_CORE_MAKE', + 'COMPONENT_MW_MTB_HAL_CAT1', + 'COMPONENT_MW_MTB_PDL_CAT1', + 'COMPONENT_MW_RECIPE_MAKE_CAT1C', + 'COMPONENT_MW_RETARGET_IO', + 'COMPONENT_SOFTFP', + 'COMPONENT_XMC7x_CM0P_SLEEP', + 'CORE_NAME_CM7_0=1', + 'CY_APPNAME_mtb_example_hal_hello_world', + 'CY_SUPPORTS_DEVICE_VALIDATION', + 'CY_TARGET_BOARD=APP_KIT_XMC71_EVK_LITE_V2', + 'CY_USING_HAL', + 'DEBUG', + 'TARGET_APP_KIT_XMC71_EVK_LITE_V2'] +group = DefineGroup('Drivers', src, depend=[''], CPPPATH=path, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/board/board.c b/bsp/Infineon/xmc7100d-f144k4160aa/board/board.c new file mode 100644 index 00000000000..6e4dd05f9ed --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/board/board.c @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-06-29 Rbb666 first version + */ + +#include "board.h" + +void cy_bsp_all_init(void) +{ + cy_rslt_t result; + + /* Initialize the device and board peripherals */ + result = cybsp_init(); + + /* Board init failed. Stop program execution */ + if (result != CY_RSLT_SUCCESS) + { + CY_ASSERT(0); + } +} diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/board/board.h b/bsp/Infineon/xmc7100d-f144k4160aa/board/board.h new file mode 100644 index 00000000000..0e105e05f2a --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/board/board.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-06-29 Rbb666 first version + * 2022-07-26 Rbb666 Add Flash Config + * 2022-04-21 Hydevcode modify Flash Config + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "drv_common.h" +#include "drv_gpio.h" + +#include "cy_result.h" +#include "cybsp_types.h" +#include "cyhal.h" +#include "cybsp.h" + +#ifdef BSP_USING_USBD + #include "cy_usb_dev.h" + #include "cy_usb_dev_hid.h" + #include "cycfg_usbdev.h" +#endif + +/*SRAM CONFIG*/ +#define IFX_SRAM_SIZE (768) +#define IFX_SRAM_END (0x28000000 + IFX_SRAM_SIZE * 1024) + +#ifdef __ARMCC_VERSION + extern int Image$$RW_IRAM1$$ZI$$Limit; + #define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) + #define HEAP_END IFX_SRAM_END +#elif __ICCARM__ + #pragma section="HEAP" + #define HEAP_BEGIN (__segment_end("HEAP")) +#else + extern unsigned int __end__; + extern unsigned int __HeapLimit; + #define HEAP_BEGIN (void*)&__end__ + #define HEAP_END (void*)&__HeapLimit +#endif + +void cy_bsp_all_init(void); + +#endif + diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/board/linker_scripts/link.ld b/bsp/Infineon/xmc7100d-f144k4160aa/board/linker_scripts/link.ld new file mode 100644 index 00000000000..73fa51a0bcd --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/board/linker_scripts/link.ld @@ -0,0 +1,472 @@ +/***************************************************************************//** +* /file xmc7100_x4160_cm7.ld +* /version 1.0.0 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* /note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* /note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* /copyright +* Copyright 2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +GROUP(-lgcc -lc -lnosys ) +SEARCH_DIR(.) +GROUP(libgcc.a libc.a libm.a libnosys.a) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM7 SRAM */ +STACK_SIZE = 0x1000; +RAMVECTORS_ALIGNMENT = 128; + +sram_start_reserve = 0; + +sram_total_size = 0x000C0000; /* 768K: SRAM0 + SRAM1 */ +sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing) */ +sram_used_by_boot = 0x0; /* Used during boot by Cypress firmware (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations) */ + +cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */ +cm7_0_sram_reserve = 0x000BC000; /* 752K : cm7_0 sram size */ + +code_flash_total_size = 0x00410000; /* 4160K: total flash size */ +cm0plus_code_flash_reserve = 0x00080000; /* 512K : cm0 flash size */ +cm7_0_code_flash_reserve = 0x00390000; /* 3648K: cm7_0 flash size */ + +code_flash_base_address = 0x10000000; +sram_base_address = 0x28000000; + +/* SRAM reservations */ +_base_SRAM_CM7_0 = sram_base_address + cm0plus_sram_reserve; +_size_SRAM_CM7_0 = cm7_0_sram_reserve; + +/* Code flash reservations */ +_base_CODE_FLASH_CM0P = code_flash_base_address; +_size_CODE_FLASH_CM0P = cm0plus_code_flash_reserve; +_base_CODE_FLASH_CM7_0 = code_flash_base_address + cm0plus_code_flash_reserve; +_size_CODE_FLASH_CM7_0 = cm7_0_code_flash_reserve; + +/* Fixed Addresses */ +_base_WORK_FLASH = 0x14000000; +_size_WORK_FLASH = 0x00040000; /* 256K Work flash */ +_base_CM7_0_ITCM = 0x00000000; +_size_CM7_0_ITCM = 0x00004000; +_base_CM7_0_DTCM = 0x20000000; +_size_CM7_0_DTCM = 0x00004000; + +/* For the non-dual cm7 device, _CORE_CM7_0_ should be defined and _CORE_CM7_1_ should not be defined */ +_base_SRAM = _base_SRAM_CM7_0; +_size_SRAM = _size_SRAM_CM7_0; +_base_CODE_FLASH = _base_CODE_FLASH_CM7_0; +_size_CODE_FLASH = _size_CODE_FLASH_CM7_0; +_base_SFLASH_USER_DATA = 0x17000800; +_size_SFLASH_USER_DATA = 0x00000800; +_base_SFLASH_NAR = 0x17001A00; +_size_SFLASH_NAR = 0x00000200; +_base_SFLASH_PUB_KEY = 0x17006400; +_size_SFLASH_PUB_KEY = 0x00000C00; +_base_SFLASH_APP_PROT = 0x17007600; +_size_SFLASH_APP_PROT = 0x00000200; +_base_SFLASH_TOC2 = 0x17007C00; +_size_SFLASH_TOC2 = 0x00000200; +_base_XIP = 0x60000000; +_size_XIP = 0x08000000; +_base_EFUSE = 0x90700000; +_size_EFUSE = 0x00100000; +_base_ITCM = _base_CM7_0_ITCM; +_size_ITCM = _size_CM7_0_ITCM; +_base_DTCM = _base_CM7_0_DTCM; +_size_DTCM = _size_CM7_0_DTCM; + + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM7_0/CM7_1 core. */ + ram (rxw) : ORIGIN = _base_SRAM, LENGTH = _size_SRAM /* SRAM */ + flash_cm0p (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P /* CODE flash CM0+ */ + flash (rx) : ORIGIN = _base_CODE_FLASH, LENGTH = _size_CODE_FLASH /* CODE flash CM7_0/1 */ + + /* This is a 256K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + */ + em_eeprom (rw) : ORIGIN = _base_WORK_FLASH, LENGTH = _size_WORK_FLASH /* WORK flash */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = _base_SFLASH_USER_DATA, LENGTH = _size_SFLASH_USER_DATA /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = _base_SFLASH_NAR, LENGTH = _size_SFLASH_NAR /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = _base_SFLASH_PUB_KEY, LENGTH = _size_SFLASH_PUB_KEY /* Supervisory flash: Public Key */ + sflash_app_prot (rx) : ORIGIN = _base_SFLASH_APP_PROT, LENGTH = _size_SFLASH_APP_PROT + sflash_toc_2 (rx) : ORIGIN = _base_SFLASH_TOC2, LENGTH = _size_SFLASH_TOC2 /* Supervisory flash: Table of Content # 2 */ + xip (rx) : ORIGIN = _base_XIP, LENGTH = _size_XIP /* XIP: 128 MB */ + efuse (rx) : ORIGIN = _base_EFUSE, LENGTH = _size_EFUSE /* 1MB */ + itcm (rx) : ORIGIN = _base_ITCM, LENGTH = _size_ITCM /* ITCM */ + dtcm (rx) : ORIGIN = _base_DTCM, LENGTH = _base_DTCM /* DTCM */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +SECTIONS +{ + /* Cortex-M0+ application flash image area. Comment this section if you don't want to include CM0+ image */ + .cy_cm0p_image ORIGIN(flash_cm0p): + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > flash_cm0p + + /* Check if .cy_m0p_image size exceeds cm0plus_code_flash_reserve */ + ASSERT(__cy_m0p_code_end < ORIGIN(flash), "CM0+ flash image overflows with CM7, increase CM7 base address ") + + /* Cortex-M7 application flash area */ + .text ORIGIN(flash) : + { + /* Cortex-M7 flash vector table */ + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + .rtt_const_tables : + { + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG ((__data_end__ - __data_start__)/4) /* Size */ + + /* Copy code to ITCM */ + LONG (__zero_table_end__) /* From */ + LONG (__itcm_start__) /* To */ + LONG ((__itcm_end__ - __itcm_start__)/4) /* Size */ + + /* Copy data to DTCM */ + LONG (__itcm_flash_end__) /* From */ + LONG (__dtcm_start__) /* To */ + LONG ((__dtcm_end__ - __dtcm_start__)/4) /* Size */ + + __copy_table_end__ = .; + } > flash + + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG ((__bss_end__ - __bss_start__)/4) + __zero_table_end__ = .; + } > flash + + /* itcm */ + .cy_itcm ORIGIN(itcm): + { + __itcm_start__ = .; + KEEP(*(.cy_itcm)) + __itcm_end__ = .; + } > itcm AT>flash + + __itcm_flash_end__ = __zero_table_end__ + (__itcm_end__ - __itcm_start__); + + /* dtcm */ + .cy_dtcm ORIGIN(dtcm): + { + __dtcm_start__ = .; + KEEP(*(.cy_dtcm)) + __dtcm_end__ = .; + } > dtcm AT>flash + + __etext = __itcm_flash_end__ + (__dtcm_end__ - __dtcm_start__) ; + + + .ramVectors (NOLOAD) : + { + . = ALIGN(RAMVECTORS_ALIGNMENT); + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : + { + . = ALIGN(4); + __data_start__ = .; + + *(vtable) + + KEEP(*(.data.cybsp_sysclk_pm_callback.1)) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(32); + + KEEP(*(cy_sharedmem*)) + . = ALIGN(4); + + __data_end__ = .; + } > ram AT>flash + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse +} + + +/*============================================================ + * Symbols for use by application + *============================================================ + */ + +__ecc_init_sram_start_address = ORIGIN(ram); +__ecc_init_sram_end_address = ORIGIN(ram) + LENGTH(ram); + +/* EOF */ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/board/linker_scripts/link.sct b/bsp/Infineon/xmc7100d-f144k4160aa/board/linker_scripts/link.sct new file mode 100644 index 00000000000..29fa0e57970 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/board/linker_scripts/link.sct @@ -0,0 +1,149 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m7 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file xmc7100_x4160_cm7.sct +;* \version 1.0 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM7 core in 'xxx_cm7.sct', +; where 'xx' is the device group; for example, 'xmc7200d_x8384_cm7.sct'. + + +; RAM +#define SRAM_TOTAL_SIZE 0x000C0000 /* 768K: SRAM0 + SRAM1 */ + +; FLASH +#define CODE_FLASH_TOTAL_SIZE 0x00410000 /* 4160K: TOTAL FLASH SIZE */ + +#define SRAM_START_RESERVE 0 +#define SRAM_PRIVATE_FOR_SROM 0x800 /* 2K Private SRAM for SROM (e.g. API processing). Reserved at the beginning */ +#define STACK_SIZE 0x1000 +#define RAMVECTORS_ALIGNMENT 128 + +; RAM +#define SRAM_BASE_ADDRESS 0x28000000 /* SRAM START */ +#define CM0PLUS_SRAM_RESERVE 0x00004000 /* 16K : cm0 sram size */ +#define CM7_0_SRAM_RESERVE 0x000BC000 /* 752K: cm7_0 sram size */ + +; FLASH +#define CODE_FLASH_BASE_ADDRESS 0x10000000 /* FLASH START */ +#define CM0PLUS_CODE_FLASH_RESERVE 0x00080000 /* 512K : cm0 flash size */ +#define CM7_0_CODE_FLASH_RESERVE 0x00390000 /* 3648K: cm7_0 flash size */ + +; SRAM reservations +#define BASE_SRAM_CM0P SRAM_BASE_ADDRESS + SRAM_START_RESERVE + SRAM_PRIVATE_FOR_SROM +#define SIZE_SRAM_CM0P CM0PLUS_SRAM_RESERVE - SRAM_START_RESERVE - SRAM_PRIVATE_FOR_SROM +#define BASE_SRAM_CM7_0 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE +#define SIZE_SRAM_CM7_0 CM7_0_SRAM_RESERVE + +; Code flash reservations +#define BASE_CODE_FLASH_CM0P CODE_FLASH_BASE_ADDRESS +#define SIZE_CODE_FLASH_CM0P CM0PLUS_CODE_FLASH_RESERVE +#define BASE_CODE_FLASH_CM7_0 CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE +#define SIZE_CODE_FLASH_CM7_0 CM7_0_CODE_FLASH_RESERVE + +#define BASE_SRAM BASE_SRAM_CM7_0 +#define SIZE_SRAM SIZE_SRAM_CM7_0 +#define BASE_CODE_FLASH BASE_CODE_FLASH_CM7_0 +#define SIZE_CODE_FLASH SIZE_CODE_FLASH_CM7_0 + + +; Cortex-M0+ application flash image area +LR_IROM BASE_CODE_FLASH_CM0P SIZE_CODE_FLASH_CM0P +{ + .cy_m0p_image +0 + { + * (.cy_m0p_image) + } +} + + +; Cortex-M7 application flash area +LR_IROM1 BASE_CODE_FLASH SIZE_CODE_FLASH +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS BASE_SRAM UNINIT + { + * (.bss.noinit.RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (+RW, +ZI) + } + + RW_RAM_SHARED_DATA +0 ALIGN 32 + { + * (.cy_sharedmem) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + * (.bss.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY BASE_SRAM+SIZE_SRAM-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM1), 8) + { + } + + ; Stack region growing down + ARM_LIB_STACK (BASE_SRAM+SIZE_SRAM) EMPTY -STACK_SIZE + { + } +} diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/SConscript b/bsp/Infineon/xmc7100d-f144k4160aa/libs/SConscript new file mode 100644 index 00000000000..0d2b9b11b2d --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/SConscript @@ -0,0 +1,27 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = [] +group = [] +CPPPATH = [] + +if rtconfig.PLATFORM in ['iccarm']: + print("\nThe current project does not support IAR build\n") + Return('group') +elif rtconfig.PLATFORM in ['gcc', 'armclang']: + src += Glob(cwd + '/TARGET_APP_KIT_XMC71_EVK_LITE_V2/*.c') + src += Glob(cwd + '/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/*.c') + + CPPPATH = [ cwd + '/TARGET_APP_KIT_XMC71_EVK_LITE_V2', + cwd + '/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource'] + if rtconfig.PLATFORM in ['gcc']: + src += [cwd + '/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/system_cm7.c'] + src += [cwd + '/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/startup_cm7.c'] + elif rtconfig.PLATFORM in ['armclang']: + src += [cwd + '/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/system_cm7.c'] + src += [cwd + '/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/startup_cm7.c'] + +group = DefineGroup('libs', src, depend = [''], CPPPATH = CPPPATH) +Return('group') diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/.cyignore b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/.cyignore new file mode 100644 index 00000000000..d8f8d46921a --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/.cyignore @@ -0,0 +1 @@ +docs diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_ARM/linker.sct b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_ARM/linker.sct new file mode 100644 index 00000000000..d7aa9469a6c --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_ARM/linker.sct @@ -0,0 +1,115 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file xmc7100_x4160_cm0plus.sct +;* \version 1.0 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM7 core in 'xxx_cm7.sct', +; where 'xx' is the device group; for example, 'xmc7200d_x8384_cm7.sct'. + +#define SRAM_START_RESERVE 0 +#define SRAM_PRIVATE_FOR_SROM 0x800 /* 2K Private SRAM for SROM (e.g. API processing). Reserved at the beginning */ +#define STACK_SIZE 0x1000 +#define RAMVECTORS_ALIGNMENT 128 + +; SRAM reservations +#define SRAM_BASE_ADDRESS 0x28000000 /* SRAM START */ +#define CM0PLUS_SRAM_RESERVE 0x00004000 /* 16K : cm0 sram size */ +#define BASE_SRAM_CM0P SRAM_BASE_ADDRESS + SRAM_START_RESERVE + SRAM_PRIVATE_FOR_SROM +#define SIZE_SRAM_CM0P CM0PLUS_SRAM_RESERVE - SRAM_START_RESERVE - SRAM_PRIVATE_FOR_SROM +#define SRAM_CM0P_START BASE_SRAM_CM0P +#define SRAM_CM0P_SIZE SIZE_SRAM_CM0P + +; Code flash reservations +#define CODE_FLASH_BASE_ADDRESS 0x10000000 /* FLASH START */ +#define CM0PLUS_CODE_FLASH_RESERVE 0x00080000 /* 512K: cm0 flash size */ +#define BASE_CODE_FLASH_CM0P CODE_FLASH_BASE_ADDRESS +#define SIZE_CODE_FLASH_CM0P CM0PLUS_CODE_FLASH_RESERVE +#define CODE_FLASH_CM0P_START BASE_CODE_FLASH_CM0P +#define CODE_FLASH_CM0P_SIZE SIZE_CODE_FLASH_CM0P + +; Cortex-M0+ application flash area +LR_IROM1 CODE_FLASH_CM0P_START CODE_FLASH_CM0P_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS SRAM_CM0P_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + * (.bss.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY SRAM_CM0P_START+SRAM_CM0P_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM1), 8) + { + } + + ; Stack region growing down + ARM_LIB_STACK (SRAM_CM0P_START+SRAM_CM0P_SIZE) EMPTY -STACK_SIZE + { + } +} diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_ARM/linker_d.sct b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_ARM/linker_d.sct new file mode 100644 index 00000000000..d85d6109c80 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_ARM/linker_d.sct @@ -0,0 +1,115 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file xmc7100d_x4160_cm0plus.sct +;* \version 1.0 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM7 core in 'xxx_cm7.sct', +; where 'xx' is the device group; for example, 'xmc7200d_x8384_cm7.sct'. + +#define SRAM_START_RESERVE 0 +#define SRAM_PRIVATE_FOR_SROM 0x800 /* 2K Private SRAM for SROM (e.g. API processing). Reserved at the beginning */ +#define STACK_SIZE 0x1000 +#define RAMVECTORS_ALIGNMENT 128 + +; SRAM reservations +#define SRAM_BASE_ADDRESS 0x28000000 /* SRAM START */ +#define CM0PLUS_SRAM_RESERVE 0x00004000 /* 16K : cm0 sram size */ +#define BASE_SRAM_CM0P SRAM_BASE_ADDRESS + SRAM_START_RESERVE + SRAM_PRIVATE_FOR_SROM +#define SIZE_SRAM_CM0P CM0PLUS_SRAM_RESERVE - SRAM_START_RESERVE - SRAM_PRIVATE_FOR_SROM +#define SRAM_CM0P_START BASE_SRAM_CM0P +#define SRAM_CM0P_SIZE SIZE_SRAM_CM0P + +; Code flash reservations +#define CODE_FLASH_BASE_ADDRESS 0x10000000 /* FLASH START */ +#define CM0PLUS_CODE_FLASH_RESERVE 0x00080000 /* 512K: cm0 flash size */ +#define BASE_CODE_FLASH_CM0P CODE_FLASH_BASE_ADDRESS +#define SIZE_CODE_FLASH_CM0P CM0PLUS_CODE_FLASH_RESERVE +#define CODE_FLASH_CM0P_START BASE_CODE_FLASH_CM0P +#define CODE_FLASH_CM0P_SIZE SIZE_CODE_FLASH_CM0P + +; Cortex-M0+ application flash area +LR_IROM1 CODE_FLASH_CM0P_START CODE_FLASH_CM0P_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS SRAM_CM0P_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + * (.bss.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY SRAM_CM0P_START+SRAM_CM0P_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM1), 8) + { + } + + ; Stack region growing down + ARM_LIB_STACK (SRAM_CM0P_START+SRAM_CM0P_SIZE) EMPTY -STACK_SIZE + { + } +} diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_cm0plus.s b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_cm0plus.s new file mode 100644 index 00000000000..55722ca345a --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_cm0plus.s @@ -0,0 +1,213 @@ +;/**************************************************************************//** +; * @file startup_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device +; * @version V1.0.1 +; * @date 23. July 2019 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2019 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +CPUSS_RAM0_CTL0 EQU 0x40201300 +CPUSS_RAM1_CTL0 EQU 0x40201380 +CPUSS_RAM2_CTL0 EQU 0x402013a0 + + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Default_Intr_Handler ; CPU User Interrupt #0 + DCD Default_Intr_Handler ; CPU User Interrupt #1 + DCD CM0P_CpuIntr2_Handler ; CPU User Interrupt #2 + DCD CM0P_CpuIntr3_Handler ; CPU User Interrupt #3 + DCD CM0P_CpuIntr4_Handler ; CPU User Interrupt #4 + DCD CM0P_CpuIntr5_Handler ; CPU User Interrupt #5 + DCD CM0P_CpuIntr6_Handler ; CPU User Interrupt #6 + DCD CM0P_CpuIntr7_Handler ; CPU User Interrupt #7 + DCD Default_Intr_Handler ; Internal SW Interrupt #0 + DCD Default_Intr_Handler ; Internal SW Interrupt #1 + DCD Default_Intr_Handler ; Internal SW Interrupt #2 + DCD Default_Intr_Handler ; Internal SW Interrupt #3 + DCD Default_Intr_Handler ; Internal SW Interrupt #4 + DCD Default_Intr_Handler ; Internal SW Interrupt #5 + DCD Default_Intr_Handler ; Internal SW Interrupt #6 + DCD Default_Intr_Handler ; Internal SW Interrupt #7 + +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT CyMain + + ; Disable global interrupts + CPSID I + + ; CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7 core + ; Set CPUSS->RAMx_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC has not been initialized yet + ; Generic code can be used, even if RAMx_CTL0 (x > 0) registers are not implemented in a device + ; or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC SRAM + MOVS r0, #1 + LSLS r0, r0, #19 + LDR r1, =CPUSS_RAM0_CTL0 + LDR r2, [r1] + ORRS r2, r0 + STR r2, [r1] + LDR r1, =CPUSS_RAM1_CTL0 + LDR r2, [r1] + ORRS r2, r0 + STR r2, [r1] + LDR r1, =CPUSS_RAM2_CTL0 + LDR r2, [r1] + ORRS r2, r0 + STR r2, [r1] + + ; Initialize ECC of startup stack (needed for local variables in C startup code) by processing 8 bytes per loop iteration, + ; because the ECC initialization feature uses this generic granularity that will cover any memory (SRAM/TCM) in any TVII device + ; Prerequisite: Stack Pointer (SP) has not been modified (from the vector table init value) by above code (otherwise code must be adapted) + LDR r3, =|Image$$ARM_LIB_STACK$$ZI$$Base| + LDR r1, =|Image$$ARM_LIB_STACK$$ZI$$Length| + ADD r1, r1, r3 ; r1 = stack top + MOV r0, r1 + LDR r3, =0x100 + SUBS r0, r0, r3 ; r0 = stack offset + + MOVS r2, #0 ; clear value + MOVS r3, #0 ; clear value +loopstackclean + STM r0!, {r2, r3} + CMP r0, r1 + BNE loopstackclean + + LDR R0, =SystemInit + BLX R0 + LDR R0, =CyMain + BX R0 + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT CM0P_CpuIntr2_Handler [WEAK] + EXPORT CM0P_CpuIntr3_Handler [WEAK] + EXPORT CM0P_CpuIntr4_Handler [WEAK] + EXPORT CM0P_CpuIntr5_Handler [WEAK] + EXPORT CM0P_CpuIntr6_Handler [WEAK] + EXPORT CM0P_CpuIntr7_Handler [WEAK] + +CM0P_CpuIntr2_Handler +CM0P_CpuIntr3_Handler +CM0P_CpuIntr4_Handler +CM0P_CpuIntr5_Handler +CM0P_CpuIntr6_Handler +CM0P_CpuIntr7_Handler + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP + +; The default macro is not used for HardFault_Handler +; because this results in a poor debug illusion. +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Default_Intr_Handler + + + ALIGN + + + END + diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker.ld b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker.ld new file mode 100644 index 00000000000..3d44590e4df --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker.ld @@ -0,0 +1,367 @@ +/***************************************************************************//** +* \file xmc7100_x4160_cm0plus.ld +* \version 1.0.0 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +GROUP(-lgcc -lc -lnosys ) +SEARCH_DIR(.) +GROUP(libgcc.a libc.a libm.a libnosys.a) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM7 SRAM */ +STACK_SIZE = 0x1000; +RAMVECTORS_ALIGNMENT = 128; + +sram_start_reserve = 0; +sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing). Reserved at the beginning */ + +cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */ +cm0plus_code_flash_reserve = 0x00080000; /* 512K: cm0 flash size */ + +sram_base_address = 0x28000000; +code_flash_base_address = 0x10000000; + +_base_SRAM_CM0P = sram_base_address + sram_start_reserve + sram_private_for_srom; +_size_SRAM_CM0P = cm0plus_sram_reserve - sram_start_reserve - sram_private_for_srom; +_base_CODE_FLASH_CM0P = code_flash_base_address; +_size_CODE_FLASH_CM0P = cm0plus_code_flash_reserve; + +/* Fixed Addesses */ +_base_WORK_FLASH = 0x14000000; +_size_WORK_FLASH = 0x00040000; /* 256K Work flash */ +_base_SFLASH_USER_DATA = 0x17000800; +_size_SFLASH_USER_DATA = 0x00000800; +_base_SFLASH_NAR = 0x17001A00; +_size_SFLASH_NAR = 0x00000200; +_base_SFLASH_PUB_KEY = 0x17006400; +_size_SFLASH_PUB_KEY = 0x00000C00; +_base_SFLASH_APP_PROT = 0x17007600; +_size_SFLASH_APP_PROT = 0x00000200; +_base_SFLASH_TOC2 = 0x17007C00; +_size_SFLASH_TOC2 = 0x00000200; +_base_XIP = 0x60000000; +_size_XIP = 0x08000000; +_base_EFUSE = 0x90700000; +_size_EFUSE = 0x00100000; + + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM33 core. + */ + cm0_ram (rxw) : ORIGIN = _base_SRAM_CM0P, LENGTH = _size_SRAM_CM0P + cm0_flash (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P + + /* This is a 256K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + */ + em_eeprom (rw) : ORIGIN = _base_WORK_FLASH, LENGTH = _size_WORK_FLASH /* WORK flash */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = _base_SFLASH_USER_DATA, LENGTH = _size_SFLASH_USER_DATA /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = _base_SFLASH_NAR, LENGTH = _size_SFLASH_NAR /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = _base_SFLASH_PUB_KEY, LENGTH = _size_SFLASH_PUB_KEY /* Supervisory flash: Public Key */ + sflash_app_prot (rx) : ORIGIN = _base_SFLASH_APP_PROT, LENGTH = _size_SFLASH_APP_PROT + sflash_toc_2 (rx) : ORIGIN = _base_SFLASH_TOC2, LENGTH = _size_SFLASH_TOC2 /* Supervisory flash: Table of Content # 2 */ + xip (rx) : ORIGIN = _base_XIP, LENGTH = _size_XIP /* XIP: 128 MB */ + efuse (rx) : ORIGIN = _base_EFUSE, LENGTH = _size_EFUSE /* 1MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +SECTIONS +{ + /* Cortex-M4 application flash area */ + .text ORIGIN(cm0_flash) : + { + /* Cortex-M4 flash vector table */ + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > cm0_flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > cm0_flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > cm0_flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG ((__data_end__ - __data_start__)/4) /* Size */ + + __copy_table_end__ = .; + } > cm0_flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG ((__bss_end__ - __bss_start__)/4) + __zero_table_end__ = .; + } > cm0_flash + + __etext = . ; + + + .ramVectors (NOLOAD) : + { + . = ALIGN(RAMVECTORS_ALIGNMENT); + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > cm0_ram + + + .data __ram_vectors_end__ : + { + . = ALIGN(4); + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > cm0_ram AT>cm0_flash + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > cm0_ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > cm0_ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(cm0_ram) + LENGTH(cm0_ram) - STACK_SIZE; + __HeapLimit = .; + } > cm0_ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > cm0_ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(cm0_ram) + LENGTH(cm0_ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse +} + + +/* EOF */ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker_d.ld b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker_d.ld new file mode 100644 index 00000000000..97b015ed22a --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker_d.ld @@ -0,0 +1,367 @@ +/***************************************************************************//** +* \file xmc7100d_x4160_cm0plus.ld +* \version 1.0.0 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +GROUP(-lgcc -lc -lnosys ) +SEARCH_DIR(.) +GROUP(libgcc.a libc.a libm.a libnosys.a) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM7_1 SRAM */ +STACK_SIZE = 0x1000; +RAMVECTORS_ALIGNMENT = 128; + +sram_start_reserve = 0; +sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing). Reserved at the beginning */ + +cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */ +cm0plus_code_flash_reserve = 0x00080000; /* 512K: cm0 flash size */ + +sram_base_address = 0x28000000; +code_flash_base_address = 0x10000000; + +_base_SRAM_CM0P = sram_base_address + sram_start_reserve + sram_private_for_srom; +_size_SRAM_CM0P = cm0plus_sram_reserve - sram_start_reserve - sram_private_for_srom; +_base_CODE_FLASH_CM0P = code_flash_base_address; +_size_CODE_FLASH_CM0P = cm0plus_code_flash_reserve; + +/* Fixed Addesses */ +_base_WORK_FLASH = 0x14000000; +_size_WORK_FLASH = 0x00040000; /* 256K Work flash */ +_base_SFLASH_USER_DATA = 0x17000800; +_size_SFLASH_USER_DATA = 0x00000800; +_base_SFLASH_NAR = 0x17001A00; +_size_SFLASH_NAR = 0x00000200; +_base_SFLASH_PUB_KEY = 0x17006400; +_size_SFLASH_PUB_KEY = 0x00000C00; +_base_SFLASH_APP_PROT = 0x17007600; +_size_SFLASH_APP_PROT = 0x00000200; +_base_SFLASH_TOC2 = 0x17007C00; +_size_SFLASH_TOC2 = 0x00000200; +_base_XIP = 0x60000000; +_size_XIP = 0x08000000; +_base_EFUSE = 0x90700000; +_size_EFUSE = 0x00100000; + + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM33 core. + */ + cm0_ram (rxw) : ORIGIN = _base_SRAM_CM0P, LENGTH = _size_SRAM_CM0P + cm0_flash (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P + + /* This is a 256K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + */ + em_eeprom (rw) : ORIGIN = _base_WORK_FLASH, LENGTH = _size_WORK_FLASH /* WORK flash */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = _base_SFLASH_USER_DATA, LENGTH = _size_SFLASH_USER_DATA /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = _base_SFLASH_NAR, LENGTH = _size_SFLASH_NAR /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = _base_SFLASH_PUB_KEY, LENGTH = _size_SFLASH_PUB_KEY /* Supervisory flash: Public Key */ + sflash_app_prot (rx) : ORIGIN = _base_SFLASH_APP_PROT, LENGTH = _size_SFLASH_APP_PROT + sflash_toc_2 (rx) : ORIGIN = _base_SFLASH_TOC2, LENGTH = _size_SFLASH_TOC2 /* Supervisory flash: Table of Content # 2 */ + xip (rx) : ORIGIN = _base_XIP, LENGTH = _size_XIP /* XIP: 128 MB */ + efuse (rx) : ORIGIN = _base_EFUSE, LENGTH = _size_EFUSE /* 1MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +SECTIONS +{ + /* Cortex-M4 application flash area */ + .text ORIGIN(cm0_flash) : + { + /* Cortex-M4 flash vector table */ + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > cm0_flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > cm0_flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > cm0_flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG ((__data_end__ - __data_start__)/4) /* Size */ + + __copy_table_end__ = .; + } > cm0_flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG ((__bss_end__ - __bss_start__)/4) + __zero_table_end__ = .; + } > cm0_flash + + __etext = . ; + + + .ramVectors (NOLOAD) : + { + . = ALIGN(RAMVECTORS_ALIGNMENT); + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > cm0_ram + + + .data __ram_vectors_end__ : + { + . = ALIGN(4); + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > cm0_ram AT>cm0_flash + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > cm0_ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > cm0_ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(cm0_ram) + LENGTH(cm0_ram) - STACK_SIZE; + __HeapLimit = .; + } > cm0_ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > cm0_ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(cm0_ram) + LENGTH(cm0_ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse +} + + +/* EOF */ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_cm0plus.S b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_cm0plus.S new file mode 100644 index 00000000000..7765114c1fe --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_cm0plus.S @@ -0,0 +1,200 @@ +/**************************************************************************//** + * @file startup_cm0plus.S + * @brief CMSIS-Core(M) Device Startup File for Cortex-M0plus Device + * @version V2.2.0 + * @date 26. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define CPUSS_RAM0_CTL0 0x40201300 +#define CPUSS_RAM1_CTL0 0x40201380 +#define CPUSS_RAM2_CTL0 0x402013a0 + + + .syntax unified + .arch armv6-m + + .section .vectors + .align 2 + .globl __Vectors + .globl __Vectors_End + .globl __Vectors_Size + .global CM0P_CpuIntr2_Handler + .global CM0P_CpuIntr3_Handler + .global CM0P_CpuIntr4_Handler + .global CM0P_CpuIntr5_Handler + .global CM0P_CpuIntr6_Handler + .global CM0P_CpuIntr7_Handler + +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* -14 NMI Handler */ + .long HardFault_Handler /* -13 Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* -5 SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* -2 PendSV Handler */ + .long SysTick_Handler /* -1 SysTick Handler */ + + /* Interrupts */ + .long Default_Intr_Handler /* CPU User Interrupt #0 */ + .long Default_Intr_Handler /* CPU User Interrupt #1 */ + .long CM0P_CpuIntr2_Handler /* CPU User Interrupt #2 */ + .long CM0P_CpuIntr3_Handler /* CPU User Interrupt #3 */ + .long CM0P_CpuIntr4_Handler /* CPU User Interrupt #4 */ + .long CM0P_CpuIntr5_Handler /* CPU User Interrupt #5 */ + .long CM0P_CpuIntr6_Handler /* CPU User Interrupt #6 */ + .long CM0P_CpuIntr7_Handler /* CPU User Interrupt #7 */ + .long Default_Intr_Handler /* Internal SW Interrupt #0 */ + .long Default_Intr_Handler /* Internal SW Interrupt #1 */ + .long Default_Intr_Handler /* Internal SW Interrupt #2 */ + .long Default_Intr_Handler /* Internal SW Interrupt #3 */ + .long Default_Intr_Handler /* Internal SW Interrupt #4 */ + .long Default_Intr_Handler /* Internal SW Interrupt #5 */ + .long Default_Intr_Handler /* Internal SW Interrupt #6 */ + .long Default_Intr_Handler /* Internal SW Interrupt #7 */ + +__Vectors_End: + .equ __Vectors_Size, __Vectors_End - __Vectors + .size __Vectors, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __Vectors_Size + .size __ramVectors, . - __ramVectors + + .thumb + .section .text + .align 2 + + .thumb_func + .type Reset_Handler, %function + .globl Reset_Handler + .extern __cmsis_start + .fnstart +Reset_Handler: + /* CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7 core + * Set CPUSS->RAMx_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC has not been initialized yet + * Generic code can be used, even if RAMx_CTL0 (x > 0) registers are not implemented in a device + * or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC SRAM + */ + movs r0, #1 + lsls r0, r0, #19 + ldr r1, =CPUSS_RAM0_CTL0 + ldr r2, [r1] + orrs r2, r0 + str r2, [r1] + ldr r1, =CPUSS_RAM1_CTL0 + ldr r2, [r1] + orrs r2, r0 + str r2, [r1] + ldr r1, =CPUSS_RAM2_CTL0 + ldr r2, [r1] + orrs r2, r0 + str r2, [r1] + + /* Initialize ECC of startup stack (needed for local variables in C startup code) by processing 8 bytes per loop iteration, + * because the ECC initialization feature uses this generic granularity that will cover any memory (SRAM/TCM) in any TVII device + * Prerequisite: Stack Pointer (SP) has not been modified (from the vector table init value) by above code (otherwise code must be adapted) + */ + ldr r0, =__StackTop-0x100 + ldr r1, =__StackTop + movs r2, #0 + movs r3, #0 +loopstackclean: + stmia r0!, {r2, r3} + cmp r0, r1 + bcc.n loopstackclean + + bl SystemInit + + bl CyMain + + .fnend + .size Reset_Handler, . - Reset_Handler + + .thumb_func + .type Default_Handler, %function + .weak Default_Handler +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: +/* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +/* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 +.L_API_call: + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + + .macro Def_Fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default exception/interrupt handlers. + * Default handler are weak symbols with an endless loop. + * They can be overwritten by real handlers. + */ + .macro Def_Irq_Handler Handler_Name + .weak \Handler_Name + .set \Handler_Name, Default_Handler + .endm + +/* Default exception/interrupt handlers */ + Def_Irq_Handler NMI_Handler + + Def_Fault_Handler HardFault_Handler + + Def_Irq_Handler SVC_Handler + Def_Irq_Handler PendSV_Handler + Def_Irq_Handler SysTick_Handler + Def_Irq_Handler Default_Intr_Handler + + .end + +/* [] END OF FILE */ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_IAR/linker.icf b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_IAR/linker.icf new file mode 100644 index 00000000000..0e3f6928b52 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_IAR/linker.icf @@ -0,0 +1,147 @@ +/******************************************************************************* +* \file xmc7100_x4160_cm0plus.icf +* \version 1.0.0 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ +define symbol RAMVECTORS_ALIGNMENT = 128; + +define symbol sram_start_reserve = 0; +define symbol sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing). Reserved at the beginning */ + +define symbol cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */ +define symbol cm0plus_code_flash_reserve = 0x00080000; /* 512K: cm0 flash size */ + +define symbol sram_base_address = 0x28000000; +define symbol code_flash_base_address = 0x10000000; + +define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "normal" memories (SRAM, DTCM, ITCM) in any Traveo II derivate is used to keep the code generic */ + +define symbol cm0plus_heap_reserve = 0x00001000; +define symbol cm0plus_stack_reserve = 0x00001000; + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash values. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM7 core in 'xx_cm7.icf', + * where 'xx' is the device group; for example, 'xmc7200d_x8384_cm7.icf'. + * any changes here must also be aligned in file 'xmc7xxx_partition.h'. + * after which cm0p core aplication must be build and flashed again. + */ +/* RAM */ +define symbol __ICFEDIT_region_RAM_start__ = 0x28000800; // sram_base_address + sram_start_reserve + sram_private_for_srom; +define symbol __ICFEDIT_region_RAM_end__ = 0x28003FFF; // cm0plus_sram_reserve - 1 + +/* Flash */ +define symbol __ICFEDIT_region_ROM_start__ = 0x10000000; // code_flash_base_address +define symbol __ICFEDIT_region_ROM_end__ = 0x1007FFFF; // cm0plus_code_flash_reserve - 1 + +/*-Sizes-*/ + +define symbol __ICFEDIT_size_cstack__ = 0x00001000; //cm0plus_stack_reserve +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +define symbol __ICFEDIT_size_heap__ = 0x00001000; //cm0plus_heap_reserve + +/**** End of ICF editor section. ###ICF###*/ + +define symbol heap_reserve = __ICFEDIT_size_heap__; +define symbol stack_reserve = (__ICFEDIT_size_cstack__ + (ecc_init_width - 1)) & (~((ecc_init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */ + +define symbol _base_SRAM_CM0P = __ICFEDIT_region_RAM_start__; +define symbol _size_SRAM_CM0P = __ICFEDIT_region_RAM_end__ - __ICFEDIT_region_RAM_start__ + 1; +define symbol _base_CODE_FLASH_CM0P = __ICFEDIT_region_ROM_start__; +define symbol _size_CODE_FLASH_CM0P = __ICFEDIT_region_ROM_end__ - __ICFEDIT_region_ROM_start__ + 1; + +/*============================================================ + * Memory definitions + *============================================================ + */ + +define memory mem with size = 4G; + +define region SRAM = mem:[from _base_SRAM_CM0P size _size_SRAM_CM0P ]; +define region CODE_FLASH = mem:[from _base_CODE_FLASH_CM0P size _size_CODE_FLASH_CM0P ]; + +/*============================================================ + * Block definitions + *============================================================ + */ +define block CSTACK with alignment = 8, size = stack_reserve { }; +define block HEAP with expanding size, alignment = 8, minimum size = heap_reserve { }; +define block HEAP_STACK { block HEAP, last block CSTACK }; + +/*============================================================ + * Initialization + *============================================================ + */ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*============================================================ + * Placement + *============================================================ + */ + +/* Link location specific assignment of 'readonly' type sections to either SRAM or CODE_FLASH */ +/* Note: .intvec must be the first section in ROM in order for __cm7_vector_base_linker_symbol to be correctly calculated! */ + +place at start of CODE_FLASH { section .intvec }; +place in CODE_FLASH { readonly }; + +place in SRAM { readwrite }; +place at end of SRAM { block HEAP_STACK }; + +keep { section .intvec }; + +/*============================================================ + * Symbols for use by application + *============================================================ + */ +/* The start of CM7_0/1 vector table is required by CM0+ application to correctly + * set CPUSS->CM7_0/1_VECTOR_TABLE_BASE register before releasing CM7_0 or CM7_1 from reset + */ + +define exported symbol __ecc_init_sram_start_address = start(SRAM); +define exported symbol __ecc_init_sram_end_address = end(SRAM); + +/* EOF */ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_IAR/linker_d.icf b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_IAR/linker_d.icf new file mode 100644 index 00000000000..d92e893c871 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_IAR/linker_d.icf @@ -0,0 +1,148 @@ +/******************************************************************************* +* \file xmc7100d_x4160_cm0plus.icf +* \version 1.0.0 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ +define symbol RAMVECTORS_ALIGNMENT = 128; + +define symbol sram_start_reserve = 0; +define symbol sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing). Reserved at the beginning */ + +define symbol cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */ +define symbol cm0plus_code_flash_reserve = 0x00080000; /* 512K: cm0 flash size */ + +define symbol sram_base_address = 0x28000000; +define symbol code_flash_base_address = 0x10000000; + +define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "normal" memories (SRAM, DTCM, ITCM) in any Traveo II derivate is used to keep the code generic */ + +define symbol cm0plus_heap_reserve = 0x00001000; +define symbol cm0plus_stack_reserve = 0x00001000; + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash values. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM7 core in 'xx_cm7.icf', + * where 'xx' is the device group; for example, 'xmc7100d_x4160_cm7.icf'. + * any changes here must also be aligned in file 'xmc7xxx_partition.h'. + * after which cm0p core aplication must be build and flashed again. + */ +/* RAM */ +define symbol __ICFEDIT_region_RAM_start__ = 0x28000800; // sram_base_address + sram_start_reserve + sram_private_for_srom; +define symbol __ICFEDIT_region_RAM_end__ = 0x28003FFF; // cm0plus_sram_reserve - 1 + +/* Flash */ +define symbol __ICFEDIT_region_ROM_start__ = 0x10000000; // code_flash_base_address +define symbol __ICFEDIT_region_ROM_end__ = 0x1007FFFF; // cm0plus_code_flash_reserve - 1 + +/*-Sizes-*/ + +define symbol __ICFEDIT_size_cstack__ = 0x00001000; //cm0plus_stack_reserve +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +define symbol __ICFEDIT_size_heap__ = 0x00001000; //cm0plus_heap_reserve + +/**** End of ICF editor section. ###ICF###*/ + +define symbol heap_reserve = __ICFEDIT_size_heap__; +define symbol stack_reserve = (__ICFEDIT_size_cstack__ + (ecc_init_width - 1)) & (~((ecc_init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */ + + +define symbol _base_SRAM_CM0P = __ICFEDIT_region_RAM_start__; +define symbol _size_SRAM_CM0P = __ICFEDIT_region_RAM_end__ - __ICFEDIT_region_RAM_start__ + 1; +define symbol _base_CODE_FLASH_CM0P = __ICFEDIT_region_ROM_start__; +define symbol _size_CODE_FLASH_CM0P = __ICFEDIT_region_ROM_end__ - __ICFEDIT_region_ROM_start__ + 1; + +/*============================================================ + * Memory definitions + *============================================================ + */ + +define memory mem with size = 4G; + +define region SRAM = mem:[from _base_SRAM_CM0P size _size_SRAM_CM0P ]; +define region CODE_FLASH = mem:[from _base_CODE_FLASH_CM0P size _size_CODE_FLASH_CM0P ]; + +/*============================================================ + * Block definitions + *============================================================ + */ +define block CSTACK with alignment = 8, size = stack_reserve { }; +define block HEAP with expanding size, alignment = 8, minimum size = heap_reserve { }; +define block HEAP_STACK { block HEAP, last block CSTACK }; + +/*============================================================ + * Initialization + *============================================================ + */ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*============================================================ + * Placement + *============================================================ + */ + +/* Link location specific assignment of 'readonly' type sections to either SRAM or CODE_FLASH */ +/* Note: .intvec must be the first section in ROM in order for __cm7_vector_base_linker_symbol to be correctly calculated! */ + +place at start of CODE_FLASH { section .intvec }; +place in CODE_FLASH { readonly }; + +place in SRAM { readwrite }; +place at end of SRAM { block HEAP_STACK }; + +keep { section .intvec }; + +/*============================================================ + * Symbols for use by application + *============================================================ + */ +/* The start of CM7_0/1 vector table is required by CM0+ application to correctly + * set CPUSS->CM7_0/1_VECTOR_TABLE_BASE register before releasing CM7_0 or CM7_1 from reset + */ + +define exported symbol __ecc_init_sram_start_address = start(SRAM); +define exported symbol __ecc_init_sram_end_address = end(SRAM); + +/* EOF */ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_cm0plus.s b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_cm0plus.s new file mode 100644 index 00000000000..16e978254aa --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_cm0plus.s @@ -0,0 +1,370 @@ +;/**************************************************************************//** +; * @file startup_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device +; * @version V1.0.0 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + +;************************************************************************ +;* Local definitions +;************************************************************************ + +; Set a sufficient startup stack size for correct operation of C startup code (startup.c) +STARTUP_STACK_SIZE_DOUBLE_WORDS EQU 32 + +VTOR EQU 0xe000ed08 + +CPUSS_RAM0_CTL0 EQU 0x40201300 +CPUSS_RAM1_CTL0 EQU 0x40201380 +CPUSS_RAM2_CTL0 EQU 0x402013a0 + + +;************************************************************************ +;* Import symbols +;************************************************************************ + + EXTERN CM0P_CpuIntr2_Handler + EXTERN CM0P_CpuIntr3_Handler + EXTERN CM0P_CpuIntr4_Handler + EXTERN CM0P_CpuIntr5_Handler + EXTERN CM0P_CpuIntr6_Handler + EXTERN CM0P_CpuIntr7_Handler + EXTERN __iar_program_start + EXTERN __iar_data_init3 + EXTERN __iar_dynamic_initialization + EXTERN SystemInit + EXTERN CyMain + + +;************************************************************************ +;* Export symbols +;************************************************************************ + + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + PUBLIC Cy_u32StartupStackStartAddress + PUBLIC Cy_u32StartupStackEndAddress + + +;************************************************************************ +;* Vector Table and RAM Vector Table +;************************************************************************ + + SECTION CSTACK:DATA:NOROOT(3) + + ; align to 256 byte, because CM0_VECTOR_TABLE_BASE register only supports address bits [31:8] (Note: for VTOR a 128-byte alignment would be ok) + SECTION .intvec:CODE:ROOT(8) + DATA + +__vector_table: + DCD sfe(CSTACK) + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c: + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts PowerMode Description + + DCD DefaultInt_Handler ; DeepSleep CPU User Interrupt #0 ; updated in RAM vector table with corresponding SROM vector table entry (after ROM-to-RAM copy) + DCD DefaultInt_Handler ; DeepSleep CPU User Interrupt #1 ; updated in RAM vector table with corresponding SROM vector table entry (after ROM-to-RAM copy) + DCD CM0P_CpuIntr2_Handler ; DeepSleep CPU User Interrupt #2 + DCD CM0P_CpuIntr3_Handler ; DeepSleep CPU User Interrupt #3 + DCD CM0P_CpuIntr4_Handler ; DeepSleep CPU User Interrupt #4 + DCD CM0P_CpuIntr5_Handler ; DeepSleep CPU User Interrupt #5 + DCD CM0P_CpuIntr6_Handler ; DeepSleep CPU User Interrupt #6 + DCD CM0P_CpuIntr7_Handler ; DeepSleep CPU User Interrupt #7 + + ; These IRQs can only be triggered by SW via NVIC regs + DCD CpuUserInt8_Handler ; Active CPU User Interrupt #8 + DCD CpuUserInt9_Handler ; Active CPU User Interrupt #9 + DCD CpuUserInt10_Handler ; Active CPU User Interrupt #10 + DCD CpuUserInt11_Handler ; Active CPU User Interrupt #11 + DCD CpuUserInt12_Handler ; Active CPU User Interrupt #12 + DCD CpuUserInt13_Handler ; Active CPU User Interrupt #13 + DCD CpuUserInt14_Handler ; Active CPU User Interrupt #14 + DCD CpuUserInt15_Handler ; Active CPU User Interrupt #15 +__Vectors_End: + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + ; use same alignment like vector table in ROM above (even though VTOR minimum requirement would be 128 bytes if not used in combination with CM0_VECTOR_TABLE_BASE register) + SECTION .intvec_ram:DATA:ROOT(8) +__ramVectors: + DS8 __Vectors_Size + + +;************************************************************************ +;* Start-up Code +;************************************************************************ + + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler: + +; Disable global interrupts + CPSID I + +; Update Vector Table Offset Register with address of user ROM table +; (will be updated later to user RAM table address in C startup code) + LDR r0, =__vector_table + LDR r1, =VTOR + STR r0, [r1] + DSB + +; CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7 core +; Set CPUSS->RAMx_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC has not been initialized yet +; Generic code can be used, even if RAMx_CTL0 (x > 0) registers are not implemented in a device +; or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC SRAM + MOVS r0, #1 + LSLS r0, r0, #19 + LDR r1, =CPUSS_RAM0_CTL0 + LDR r2, [r1] + ORRS r2, r0 + STR r2, [r1] + LDR r1, =CPUSS_RAM1_CTL0 + LDR r2, [r1] + ORRS r2, r0 + STR r2, [r1] + LDR r1, =CPUSS_RAM2_CTL0 + LDR r2, [r1] + ORRS r2, r0 + STR r2, [r1] + +; Initialize ECC of startup stack (needed for local variables in C startup code) by processing 8 bytes per loop iteration, +; because the ECC initialization feature uses this generic granularity that will cover any memory (SRAM/TCM) in any TVII device +; Prerequisite: Stack Pointer (SP) has not been modified (from the vector table init value) by above code (otherwise code must be adapted) + MOVS r0, #0 ; clear value + MOVS r1, #0 ; clear value + LDR r2, Cy_u32StartupStackStartAddress +startup_stack_ecc_init_loop: + STM r2!, {r0, r1} + CMP r2, sp + BNE startup_stack_ecc_init_loop +; Call C startup code (no ANSI C context established yet!) + LDR r0, =SystemInit + BLX r0 + + LDR r0, =CyMain + BLX r0 + +; Note: Control flow does not necessarily return here. +; On some tool-chains (e.g. IAR) control flow will never return from +; the system library. +Cy_Main_Exited: + B Cy_Main_Exited + +;************************************************************************ +;* Literal pool +;************************************************************************ + + ALIGNROM 2 + + LTORG + + DATA + + ALIGNROM 2 + +STARTUP_STACK_SIZE_BYTES EQU (STARTUP_STACK_SIZE_DOUBLE_WORDS * 8) ; Multiplication does not work in below data definition directive, so an additional define is created + +Cy_u32StartupStackStartAddress: + DCD (sfe(CSTACK) - STARTUP_STACK_SIZE_BYTES) + +Cy_u32StartupStackEndAddress: + DCD (sfe(CSTACK) - 1) + + + +;************************************************************************ +;* Default and weak implementation of interrupt handlers +;************************************************************************ + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +NMI_Handler: + B NMI_Handler + +;----------------------------------------- + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_SysLib_FaultHandler: + B Cy_SysLib_FaultHandler + +;----------------------------------------- + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +HardFault_Handler: + IMPORT Cy_SysLib_FaultHandler + MOVS r0, #4 + MOV r1, lr + TST r0, r1 + BEQ L_MSP + MRS r0, PSP + B L_API_call +L_MSP + MRS r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + PUSH {lr} + LDR r1, =Cy_SysLib_FaultHandler + BLX r1 + +;----------------------------------------- + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +SVC_Handler: + B SVC_Handler + +;----------------------------------------- + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +PendSV_Handler: + B PendSV_Handler + +;----------------------------------------- + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +SysTick_Handler: + B SysTick_Handler + + +;----------------------------------------- + + + PUBWEAK DefaultInt_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +DefaultInt_Handler: + B DefaultInt_Handler + +;----------------------------------------- + + ; External interrupts + ; Traveo II CPU User Interrupts 0-7 handlers are defined in the project interrupt mapping file + ; Traveo II CPU User Interrupts 8-15 can only be used as SW interrupts and need to be defined by user (weak implementation provided below) + + + PUBWEAK CpuUserInt8_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +CpuUserInt8_Handler: + B CpuUserInt8_Handler + +;----------------------------------------- + + PUBWEAK CpuUserInt9_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +CpuUserInt9_Handler: + B CpuUserInt9_Handler + +;----------------------------------------- + + PUBWEAK CpuUserInt10_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +CpuUserInt10_Handler: + B CpuUserInt10_Handler + +;----------------------------------------- + + PUBWEAK CpuUserInt11_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +CpuUserInt11_Handler: + B CpuUserInt11_Handler + +;----------------------------------------- + + PUBWEAK CpuUserInt12_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +CpuUserInt12_Handler: + B CpuUserInt12_Handler + +;----------------------------------------- + + PUBWEAK CpuUserInt13_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +CpuUserInt13_Handler: + B CpuUserInt13_Handler + +;----------------------------------------- + + PUBWEAK CpuUserInt14_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +CpuUserInt14_Handler: + B CpuUserInt14_Handler + +;----------------------------------------- + + PUBWEAK CpuUserInt15_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +CpuUserInt15_Handler: + B CpuUserInt15_Handler + +;----------------------------------------- + + +;************************************************************************ +;* File end +;************************************************************************ + + END + + diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/system_cm0plus.c b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/system_cm0plus.c new file mode 100644 index 00000000000..bebb8a19803 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/system_cm0plus.c @@ -0,0 +1,692 @@ +/***************************************************************************//** +* \file system_cm0plus.c +* \version 1.1 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2021-2024 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* +* Initializes the system: +* - Unlocks and disables WDT. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref SystemCoreClockUpdate(). +* +*******************************************************************************/ + + +#include +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_sysclk.h" +#include "cy_wdt.h" +#include "cmsis_compiler.h" + +#define CY_SYS_CM7_PWR_CTL_KEY_OPEN (0x05FAUL) +#define CY_SYS_CM7_PWR_CTL_KEY_CLOSE (0xFA05UL) + +void Cy_DefaultUserHandler(void); +static void CopyVectorTable(void); +static void InitMemoryEccClearArea(uint32_t u32StartAddr, uint32_t u32EndAddr); +static void InitMemoryEcc(void); +static void EnableEcc(void); +static void PrepareSystemCallInfrastructure(void); + +#define DEFAULT_HANDLER_NAME Cy_DefaultUserHandler + +CY_NOINIT cy_israddress Cy_SystemIrqUserTable[CPUSS_SYSTEM_INT_NR] ; + +CY_NOINIT cy_israddress * Cy_SysInt_SystemIrqUserTableRamPointer ; + +extern uint32_t Cy_u32StartupStackStartAddress; +extern uint32_t Cy_u32StartupStackEndAddress; +extern void * __Vectors; +extern void * __Vectors_Size; +extern cy_israddress __ramVectors[]; + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (8000000UL) + +/** Default system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (100000000UL) + +/** Holds the CLK_SLOW(Cortex-M0+) or CLK_FAST0(Cortex-M7_0) or CLK_FAST(Cortex-M7_1) system core clock */ +CY_NOINIT uint32_t SystemCoreClock ; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +CY_NOINIT uint32_t cy_Hfclk0FreqHz ; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +CY_NOINIT uint32_t cy_PeriClkFreqHz ; + +/** Holds the AHB frequency. Updated by \ref SystemCoreClockUpdate(). */ +CY_NOINIT uint32_t cy_AhbFreqHz ; + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) + +CY_NOINIT uint32_t cy_delayFreqHz ; + +CY_NOINIT uint32_t cy_delayFreqKhz ; + +CY_NOINIT uint32_t cy_delayFreqMhz ; + + +/***************************************************************************** +* Global variable definitions (declared in header file with 'extern') +*****************************************************************************/ +// CAUTION: Static or global initialized and non-const variables will not have their init value yet! + + +#define SRAM_BEGIN_ADDR (BASE_SRAM_CM0P) +#define SRAM_END_ADDR (CY_SRAM_BASE + CY_SRAM_SIZE) +#define STARTUP_STACK_OFFSEST (0x100) /* 32 2-words are cleaned by startup */ + +#define ECC_INIT_WIDTH_BYTES 8 +#define SROM_VECTOR_TABLE_BASE_ADDRESS 0x00000000 +#define VECTOR_TABLE_OFFSET_IRQ0 0x40 +#define VECTOR_TABLE_OFFSET_IRQ1 0x44 + +#if defined(__ARMCC_VERSION) +extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit; /* for (default) One Region model */ +extern void __main(void); +#elif defined (__GNUC__) +extern unsigned int __StackTop; +#elif defined (__ICCARM__) +extern unsigned int CSTACK$$Limit; /* for (default) One Region model */ +#endif + +/******************************************************************************/ + +/** Define an abstract type for the chosen ECC initialization granularity */ +typedef uint64_t ecc_init_width_t; + +/* Provide empty __WEAK implementation for the low-level initialization + routine required by the RTOS-enabled applications. + clib-support library provides FreeRTOS-specific implementation: + https://github.com/Infineon/clib-support */ +void cy_toolchain_init(void); +__WEAK void cy_toolchain_init(void) +{ +} + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +/* GCC: newlib crt0 _start executes software_init_hook. + The cy_toolchain_init hook provided by clib-support library must execute + after static data initialization and before static constructors. */ +void software_init_hook(); +void software_init_hook() +{ + cy_toolchain_init(); +} +#elif defined(__ICCARM__) +/* Initialize data section */ +void __iar_data_init3(void); + +/* Call the constructors of all global objects */ +void __iar_dynamic_initialization(void); + +/* Define strong version to return zero for __iar_program_start + to skip data sections initialization (__iar_data_init3). */ +int __low_level_init(void); +int __low_level_init(void) +{ + return 0; +} +#else +/**/ +#endif /* defined(__GNUC__) && !defined(__ARMCC_VERSION) */ + + +void CyMain(void) +{ +#if defined(__ICCARM__) + /* Initialize data section */ + __iar_data_init3(); + + /* Initialization hook for RTOS environment */ + cy_toolchain_init(); + + /* Call the constructors of all global objects */ + __iar_dynamic_initialization(); +#endif + + __PROGRAM_START(); +} + + +void SystemInit(void) +{ + /* startup Init */ + InitMemoryEcc(); + EnableEcc(); + CopyVectorTable(); + PrepareSystemCallInfrastructure(); + /* startup Init done */ + + Cy_PDL_Init(CY_DEVICE_CFG); + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + + Cy_SystemInit(); + SystemCoreClockUpdate(); + + SystemIrqInit(); +} + + +/******************************************************************************* +* Function Name: EnableEcc +****************************************************************************//** +* +* The function is called during device startup. +* +*******************************************************************************/ +static void EnableEcc(void) +{ + /* Enable ECC checking in SRAM controllers again (had been switched off by assembly startup code) */ + CPUSS->RAM0_CTL0 &= ~(0x80000); /* set bit 19 to 0 */ +#if (CPUSS_RAMC1_PRESENT == 1u) + CPUSS->RAM1_CTL0 &= ~(0x80000); /* set bit 19 to 0 */ +#endif +#if (CPUSS_RAMC2_PRESENT == 1u) + CPUSS->RAM2_CTL0 &= ~(0x80000); /* set bit 19 to 0 */ +#endif +} + + +/******************************************************************************* +* Function Name: InitMemoryEcc +****************************************************************************//** +* +* The function is called during device startup. +* +*******************************************************************************/ +static void InitMemoryEcc(void) +{ + uint32_t *sp = (uint32_t*)&__INITIAL_SP; + uint32_t u32StckLow = (uint32_t)sp - STARTUP_STACK_OFFSEST; + uint32_t u32StackHigh = (uint32_t)sp; + + InitMemoryEccClearArea(SRAM_BEGIN_ADDR, u32StckLow); + InitMemoryEccClearArea(u32StackHigh, SRAM_END_ADDR); +} + + +/** + ***************************************************************************** + ** Clears an area by writing '0' using a pointer of type #ecc_init_width_t + ** + ** \param u32StartAddr Start address of area to be cleared, + ** must be aligned to #ECC_INIT_WIDTH_BYTES + ** \param u32EndAddr Last address within area to be cleared, (u32EndAddr+1) + ** must be aligned to #ECC_INIT_WIDTH_BYTES + ** + ** \return none + *****************************************************************************/ +static void InitMemoryEccClearArea(uint32_t u32StartAddr, uint32_t u32EndAddr) +{ + volatile ecc_init_width_t * pRam = (volatile ecc_init_width_t *) u32StartAddr; + ecc_init_width_t Zero = 0; + + for(; (uint32_t)pRam < u32EndAddr; pRam++) + { + // Note: Even if ecc_init_width_t is uint64_t, this will be compiled as two 32-bit accesses + // in case of CM0+, because there is no STRD instruction specified in ARMv6-M Thumb + *pRam = Zero; + } +} + + +/** + ***************************************************************************** + ** Copies the vector table from ROM to RAM and updates the VTOR (CMx vector + ** table base register) accordingly + ** + ** \return none + *****************************************************************************/ +static void CopyVectorTable(void) +{ + const uint8_t numVectors = (uint8_t)((uint32_t)&__Vectors_Size / 4); + uint32_t * const ramTable = (uint32_t *)__ramVectors; + uint32_t * const romTable = (uint32_t *)(&__Vectors); + + // Copy the vector table from ROM into RAM + for(uint8_t index = 0; index < numVectors; index++) + { + ramTable[index] = romTable[index]; + } + + // Update the ARM System Control Block vector table base address. + SCB->VTOR = (uint32_t)ramTable; +} + +/** + ***************************************************************************** + ** Prepares necessary settings to get SROM system calls working + ** + ** \return none + *****************************************************************************/ +static void PrepareSystemCallInfrastructure(void) +{ + const uint8_t u8Irq0Index = (uint8_t) (VECTOR_TABLE_OFFSET_IRQ0 / 4); + const uint8_t u8Irq1Index = (uint8_t) (VECTOR_TABLE_OFFSET_IRQ1 / 4); + volatile uint32_t * const ramTable = (uint32_t *)__ramVectors; + volatile uint32_t * const sromTable = (uint32_t *)SROM_VECTOR_TABLE_BASE_ADDRESS; + + // Use IRQ0 and IRQ1 handlers from SROM vector table + ramTable[u8Irq0Index] = sromTable[u8Irq0Index]; + ramTable[u8Irq1Index] = sromTable[u8Irq1Index]; + + NVIC_SetPriority(NvicMux0_IRQn, 1); + NVIC_SetPriority(NvicMux1_IRQn, 0); + NVIC_EnableIRQ(NvicMux0_IRQn); + NVIC_EnableIRQ(NvicMux1_IRQn); + + // Only item left is clearing of PRIMASK: + // This should be done by the application at a later point in time (e.g. in main()) +} + +/******************************************************************************* +* Function Name: SystemIrqInit +****************************************************************************//** +* +* The function is called during device startup. +* +*******************************************************************************/ +void SystemIrqInit(void) +{ + for (int i=0; i<(int)CPUSS_SYSTEM_INT_NR; i++) + { + Cy_SystemIrqUserTable[i] = DEFAULT_HANDLER_NAME; + } + + Cy_SysInt_SystemIrqUserTableRamPointer = Cy_SystemIrqUserTable; +} + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the app + * generated strong function. + */ +} + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + /* Get frequency for the high-frequency clock*/ + cy_Hfclk0FreqHz = Cy_SysClk_ClkHfGetFrequency(CY_SYSCLK_CLK_CORE_HF_PATH_NUM); + + /* The CM0P core's clock source is the slow clock. */ + SystemCoreClock = Cy_SysClk_ClkSlowGetFrequency(); + + /* Get Peripheral clock Frequency*/ + cy_PeriClkFreqHz = Cy_SysClk_ClkHfGetFrequency(CY_SYSCLK_CLK_PERI_HF_PATH_NUM); + + /* Sets clock frequency for Delay API */ + cy_delayFreqHz = SystemCoreClock; + cy_delayFreqMhz = (uint32_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + + /* Get the frequency of AHB source, CLK HF0 is the source for AHB*/ + cy_AhbFreqHz = Cy_SysClk_ClkHfGetFrequency(0UL); +} + + +uint32_t Cy_SysGetCM7Status(uint8_t core) +{ + uint32_t regValue = 0u; + + CY_ASSERT(core < CORE_MAX); + + if(core == CORE_CM7_0) + { + /* Get current power mode */ + regValue = _FLD2VAL(CPUSS_CM7_0_PWR_CTL_PWR_MODE, CPUSS->CM7_0_PWR_CTL); + } + else if(core == CORE_CM7_1) + { + /* Get current power mode */ + regValue = _FLD2VAL(CPUSS_CM7_1_PWR_CTL_PWR_MODE, CPUSS->CM7_1_PWR_CTL); + } + else + { + /* */ + } + + return (regValue); +} + + +void Cy_SysEnableCM7(uint8_t core, uint32_t vectorTableOffset) +{ + uint32_t cmStatus; + uint32_t interruptState; + uint32_t regValue; + + CY_ASSERT(core < CORE_MAX); + + interruptState = Cy_SaveIRQ(); + + cmStatus = Cy_SysGetCM7Status(core); + if(cmStatus == CY_SYS_CM7_STATUS_ENABLED) + { + // Set core into reset first, so that new settings can get effective + // This branch is e.g. entered if a debugger is connected that would power-up the CM7, + // but let it run in ROM boot or pause its execution by keeping CPU_WAIT bit set. + Cy_SysResetCM7(core); + } + + // CLK_HF1, by default is disabled for use by CM7_0/1, hence enable + SRSS->CLK_ROOT_SELECT[1] |= SRSS_CLK_ROOT_SELECT_ENABLE_Msk; + + if(core == CORE_CM7_0) + { + /* Adjust the vector address */ + CPUSS->CM7_0_VECTOR_TABLE_BASE = vectorTableOffset; + + /* Enable the Power Control Key */ + regValue = CPUSS->CM7_0_PWR_CTL & ~(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_0_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM7_STATUS_ENABLED; + CPUSS->CM7_0_PWR_CTL = regValue; + + while((CPUSS->CM7_0_STATUS & CPUSS_CM7_0_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + CPUSS->CM7_0_CTL &= ~(0x1 << CPUSS_CM7_0_CTL_CPU_WAIT_Pos); + } + else if(core == CORE_CM7_1) + { + /* Adjust the vector address */ + CPUSS->CM7_1_VECTOR_TABLE_BASE = vectorTableOffset; + + /* Enable the Power Control Key */ + regValue = CPUSS->CM7_1_PWR_CTL & ~(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_1_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM7_STATUS_ENABLED; + CPUSS->CM7_1_PWR_CTL = regValue; + + while((CPUSS->CM7_1_STATUS & CPUSS_CM7_1_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + CPUSS->CM7_1_CTL &= ~(0x1 << CPUSS_CM7_1_CTL_CPU_WAIT_Pos); + } + + Cy_RestoreIRQ(interruptState); + +} + + +void Cy_SysDisableCM7(uint8_t core) +{ + uint32_t regValue; + + CY_ASSERT(core < CORE_MAX); + + if(core == CORE_CM7_0) + { + regValue = CPUSS->CM7_0_PWR_CTL & ~(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_0_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM7_STATUS_DISABLED; + CPUSS->CM7_0_PWR_CTL = regValue; + + while((CPUSS->CM7_0_STATUS & CPUSS_CM7_0_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + } + else if(core == CORE_CM7_1) + { + regValue = CPUSS->CM7_1_PWR_CTL & ~(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_1_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM7_STATUS_DISABLED; + CPUSS->CM7_1_PWR_CTL = regValue; + + while((CPUSS->CM7_1_STATUS & CPUSS_CM7_0_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + } +} + + +void Cy_SysRetainCM7(uint8_t core) +{ + uint32_t cmStatus; + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SaveIRQ(); + + cmStatus = Cy_SysGetCM7Status(core); + if(cmStatus == CY_SYS_CM7_STATUS_ENABLED) + { + if(core == CORE_CM7_0) + { + regValue = CPUSS->CM7_0_PWR_CTL & ~(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_0_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM7_STATUS_RETAINED; + CPUSS->CM7_0_PWR_CTL = regValue; + } + else if(core == CORE_CM7_1) + { + regValue = CPUSS->CM7_1_PWR_CTL & ~(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_1_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM7_STATUS_RETAINED; + CPUSS->CM7_1_PWR_CTL = regValue; + } + } + + Cy_RestoreIRQ(interruptState); +} + + +void Cy_SysResetCM7(uint8_t core) +{ + uint32_t regValue; + + CY_ASSERT(core < CORE_MAX); + + if(core == CORE_CM7_0) + { + regValue = CPUSS->CM7_0_PWR_CTL & ~(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_0_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM7_STATUS_RESET; + CPUSS->CM7_0_PWR_CTL = regValue; + + while((CPUSS->CM7_0_STATUS & CPUSS_CM7_0_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + } + else if(core == CORE_CM7_1) + { + regValue = CPUSS->CM7_1_PWR_CTL & ~(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_1_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM7_STATUS_RESET; + CPUSS->CM7_1_PWR_CTL = regValue; + + while((CPUSS->CM7_1_STATUS & CPUSS_CM7_1_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + } +} + + +/******************************************************************************* +* Function Name: Cy_DefaultUserHandler +****************************************************************************//** +* +* The Handler is called when the CPU attempts to call IRQ that has not been mapped to user functions. +* +*******************************************************************************/ +void Cy_DefaultUserHandler(void) +{ + // This IRQ occurred because CPU attempted to call IRQ that has not been mapped to user function + while(1); +} + + +/******************************************************************************* +* Function Name: CM0P_CpuIntr_HandlerInline +****************************************************************************//** +* +* The Inline handler for CPU interrupt. +* The system interrupt mapped to CPU interrupt will be fetched and executed +* +*******************************************************************************/ +__STATIC_FORCEINLINE void CM0P_CpuIntr_HandlerInline(uint8_t intrNum) +{ + uint32_t system_int_idx; + cy_israddress handler; + + if (_FLD2VAL(CPUSS_CM0_INT0_STATUS_SYSTEM_INT_VALID, CPUSS_CM0_INT_STATUS_BASE[intrNum])) + { + system_int_idx = _FLD2VAL(CPUSS_CM0_INT0_STATUS_SYSTEM_INT_IDX, CPUSS_CM0_INT_STATUS_BASE[intrNum]); + handler = Cy_SystemIrqUserTable[system_int_idx]; + if(handler != NULL) + handler(); // jump to system interrupt handler + } + else + { + // Triggered by software or because of software cleared a peripheral interrupt flag but did not clear the pending flag at NVIC + } + NVIC_ClearPendingIRQ((IRQn_Type)intrNum); +} + + +/******************************************************************************* +* Function Name: CpuIntr2_Handler +****************************************************************************//** +* +* The Handler is called when the CPU interrupt2 occurs. +* +*******************************************************************************/ +void CM0P_CpuIntr2_Handler(void) +{ + CM0P_CpuIntr_HandlerInline(2); +} + + +/******************************************************************************* +* Function Name: CpuIntr3_Handler +****************************************************************************//** +* +* The Handler is called when the CPU interrupt3 occurs. +* +*******************************************************************************/ +void CM0P_CpuIntr3_Handler(void) +{ + CM0P_CpuIntr_HandlerInline(3); +} + + +/******************************************************************************* +* Function Name: CpuIntr4_Handler +****************************************************************************//** +* +* The Handler is called when the CPU interrupt4 occurs. +* +*******************************************************************************/ +void CM0P_CpuIntr4_Handler(void) +{ + CM0P_CpuIntr_HandlerInline(4); +} + +/******************************************************************************* +* Function Name: CpuIntr5_Handler +****************************************************************************//** +* +* The Handler is called when the CPU interrupt5 occurs. +* +*******************************************************************************/ +void CM0P_CpuIntr5_Handler(void) +{ + CM0P_CpuIntr_HandlerInline(5); +} + + +/******************************************************************************* +* Function Name: CpuIntr6_Handler +****************************************************************************//** +* +* The Handler is called when the CPU interrupt6 occurs. +* +*******************************************************************************/ +void CM0P_CpuIntr6_Handler(void) +{ + CM0P_CpuIntr_HandlerInline(6); +} + + +/******************************************************************************* +* Function Name: CpuIntr7_Handler +****************************************************************************//** +* +* The Handler is called when the CPU interrupt7 occurs. +* +*******************************************************************************/ +void CM0P_CpuIntr7_Handler(void) +{ + CM0P_CpuIntr_HandlerInline(7); +} + + diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/TOOLCHAIN_ARM/linker.sct b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/TOOLCHAIN_ARM/linker.sct new file mode 100644 index 00000000000..d355a16b7ce --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/TOOLCHAIN_ARM/linker.sct @@ -0,0 +1,149 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m7 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file xmc7100_x4160_cm7.sct +;* \version 1.0 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2021 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM7 core in 'xxx_cm7.sct', +; where 'xx' is the device group; for example, 'xmc7200d_x8384_cm7.sct'. + + +; RAM +#define SRAM_TOTAL_SIZE 0x000C0000 /* 768K: SRAM0 + SRAM1 */ + +; FLASH +#define CODE_FLASH_TOTAL_SIZE 0x00410000 /* 4160K: TOTAL FLASH SIZE */ + +#define SRAM_START_RESERVE 0 +#define SRAM_PRIVATE_FOR_SROM 0x800 /* 2K Private SRAM for SROM (e.g. API processing). Reserved at the beginning */ +#define STACK_SIZE 0x1000 +#define RAMVECTORS_ALIGNMENT 128 + +; RAM +#define SRAM_BASE_ADDRESS 0x28000000 /* SRAM START */ +#define CM0PLUS_SRAM_RESERVE 0x00004000 /* 16K : cm0 sram size */ +#define CM7_0_SRAM_RESERVE 0x000BC000 /* 752K: cm7_0 sram size */ + +; FLASH +#define CODE_FLASH_BASE_ADDRESS 0x10000000 /* FLASH START */ +#define CM0PLUS_CODE_FLASH_RESERVE 0x00080000 /* 512K : cm0 flash size */ +#define CM7_0_CODE_FLASH_RESERVE 0x00390000 /* 3648K: cm7_0 flash size */ + +; SRAM reservations +#define BASE_SRAM_CM0P SRAM_BASE_ADDRESS + SRAM_START_RESERVE + SRAM_PRIVATE_FOR_SROM +#define SIZE_SRAM_CM0P CM0PLUS_SRAM_RESERVE - SRAM_START_RESERVE - SRAM_PRIVATE_FOR_SROM +#define BASE_SRAM_CM7_0 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE +#define SIZE_SRAM_CM7_0 CM7_0_SRAM_RESERVE + +; Code flash reservations +#define BASE_CODE_FLASH_CM0P CODE_FLASH_BASE_ADDRESS +#define SIZE_CODE_FLASH_CM0P CM0PLUS_CODE_FLASH_RESERVE +#define BASE_CODE_FLASH_CM7_0 CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE +#define SIZE_CODE_FLASH_CM7_0 CM7_0_CODE_FLASH_RESERVE + +#define BASE_SRAM BASE_SRAM_CM7_0 +#define SIZE_SRAM SIZE_SRAM_CM7_0 +#define BASE_CODE_FLASH BASE_CODE_FLASH_CM7_0 +#define SIZE_CODE_FLASH SIZE_CODE_FLASH_CM7_0 + +#ifdef _CORE_CM7_0_ +; Cortex-M0+ application flash image area +LR_IROM BASE_CODE_FLASH_CM0P SIZE_CODE_FLASH_CM0P +{ + .cy_m0p_image +0 + { + * (.cy_m0p_image) + } +} +#endif + +; Cortex-M7 application flash area +LR_IROM1 BASE_CODE_FLASH SIZE_CODE_FLASH +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS BASE_SRAM UNINIT + { + * (.bss.noinit.RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (+RW, +ZI) + } + + RW_RAM_SHARED_DATA +0 ALIGN 32 + { + * (.cy_sharedmem) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + * (.bss.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY BASE_SRAM+SIZE_SRAM-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM1), 8) + { + } + + ; Stack region growing down + ARM_LIB_STACK (BASE_SRAM+SIZE_SRAM) EMPTY -STACK_SIZE + { + } +} diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/TOOLCHAIN_GCC_ARM/linker.ld b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/TOOLCHAIN_GCC_ARM/linker.ld new file mode 100644 index 00000000000..52959a58ec2 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/TOOLCHAIN_GCC_ARM/linker.ld @@ -0,0 +1,439 @@ +/***************************************************************************//** +* \file xmc7100_x4160_cm7.ld +* \version 1.0.0 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +GROUP(-lgcc -lc -lnosys ) +SEARCH_DIR(.) +GROUP(libgcc.a libc.a libm.a libnosys.a) +ENTRY(Reset_Handler) + +/* The size of the stack section at the end of CM7 SRAM */ +STACK_SIZE = 0x1000; +RAMVECTORS_ALIGNMENT = 128; + +sram_start_reserve = 0; + +sram_total_size = 0x000C0000; /* 768K: SRAM0 + SRAM1 */ +sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing) */ +sram_used_by_boot = 0x0; /* Used during boot by Cypress firmware (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations) */ + +cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */ +cm7_0_sram_reserve = 0x000BC000; /* 752K : cm7_0 sram size */ + +code_flash_total_size = 0x00410000; /* 4160K: total flash size */ +cm0plus_code_flash_reserve = 0x00080000; /* 512K : cm0 flash size */ +cm7_0_code_flash_reserve = 0x00390000; /* 3648K: cm7_0 flash size */ + +code_flash_base_address = 0x10000000; +sram_base_address = 0x28000000; + +/* SRAM reservations */ +_base_SRAM_CM7_0 = sram_base_address + cm0plus_sram_reserve; +_size_SRAM_CM7_0 = cm7_0_sram_reserve; + +/* Code flash reservations */ +_base_CODE_FLASH_CM0P = code_flash_base_address; +_size_CODE_FLASH_CM0P = cm0plus_code_flash_reserve; +_base_CODE_FLASH_CM7_0 = code_flash_base_address + cm0plus_code_flash_reserve; +_size_CODE_FLASH_CM7_0 = cm7_0_code_flash_reserve; + +/* Fixed Addresses */ +_base_WORK_FLASH = 0x14000000; +_size_WORK_FLASH = 0x00040000; /* 256K Work flash */ +_base_CM7_0_ITCM = 0x00000000; +_size_CM7_0_ITCM = 0x00004000; +_base_CM7_0_DTCM = 0x20000000; +_size_CM7_0_DTCM = 0x00004000; + +/* For the non-dual cm7 device, _CORE_CM7_0_ should be defined and _CORE_CM7_1_ should not be defined */ +_base_SRAM = _base_SRAM_CM7_0; +_size_SRAM = _size_SRAM_CM7_0; +_base_CODE_FLASH = _base_CODE_FLASH_CM7_0; +_size_CODE_FLASH = _size_CODE_FLASH_CM7_0; +_base_SFLASH_USER_DATA = 0x17000800; +_size_SFLASH_USER_DATA = 0x00000800; +_base_SFLASH_NAR = 0x17001A00; +_size_SFLASH_NAR = 0x00000200; +_base_SFLASH_PUB_KEY = 0x17006400; +_size_SFLASH_PUB_KEY = 0x00000C00; +_base_SFLASH_APP_PROT = 0x17007600; +_size_SFLASH_APP_PROT = 0x00000200; +_base_SFLASH_TOC2 = 0x17007C00; +_size_SFLASH_TOC2 = 0x00000200; +_base_XIP = 0x60000000; +_size_XIP = 0x08000000; +_base_EFUSE = 0x90700000; +_size_EFUSE = 0x00100000; +_base_ITCM = _base_CM7_0_ITCM; +_size_ITCM = _size_CM7_0_ITCM; +_base_DTCM = _base_CM7_0_DTCM; +_size_DTCM = _size_CM7_0_DTCM; + + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM7_0/CM7_1 core. */ + ram (rxw) : ORIGIN = _base_SRAM, LENGTH = _size_SRAM /* SRAM */ + flash_cm0p (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P /* CODE flash CM0+ */ + flash (rx) : ORIGIN = _base_CODE_FLASH, LENGTH = _size_CODE_FLASH /* CODE flash CM7_0/1 */ + + /* This is a 256K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + */ + em_eeprom (rw) : ORIGIN = _base_WORK_FLASH, LENGTH = _size_WORK_FLASH /* WORK flash */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = _base_SFLASH_USER_DATA, LENGTH = _size_SFLASH_USER_DATA /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = _base_SFLASH_NAR, LENGTH = _size_SFLASH_NAR /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = _base_SFLASH_PUB_KEY, LENGTH = _size_SFLASH_PUB_KEY /* Supervisory flash: Public Key */ + sflash_app_prot (rx) : ORIGIN = _base_SFLASH_APP_PROT, LENGTH = _size_SFLASH_APP_PROT + sflash_toc_2 (rx) : ORIGIN = _base_SFLASH_TOC2, LENGTH = _size_SFLASH_TOC2 /* Supervisory flash: Table of Content # 2 */ + xip (rx) : ORIGIN = _base_XIP, LENGTH = _size_XIP /* XIP: 128 MB */ + efuse (rx) : ORIGIN = _base_EFUSE, LENGTH = _size_EFUSE /* 1MB */ + itcm (rx) : ORIGIN = _base_ITCM, LENGTH = _size_ITCM /* ITCM */ + dtcm (rx) : ORIGIN = _base_DTCM, LENGTH = _base_DTCM /* DTCM */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +SECTIONS +{ + /* Cortex-M0+ application flash image area. Comment this section if you don't want to include CM0+ image */ + .cy_cm0p_image ORIGIN(flash_cm0p): + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > flash_cm0p + + /* Check if .cy_m0p_image size exceeds cm0plus_code_flash_reserve */ + ASSERT(__cy_m0p_code_end < ORIGIN(flash), "CM0+ flash image overflows with CM7, increase CM7 base address ") + + /* Cortex-M7 application flash area */ + .text ORIGIN(flash) : + { + /* Cortex-M7 flash vector table */ + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG ((__data_end__ - __data_start__)/4) /* Size */ + + /* Copy code to ITCM */ + LONG (__zero_table_end__) /* From */ + LONG (__itcm_start__) /* To */ + LONG ((__itcm_end__ - __itcm_start__)/4) /* Size */ + + /* Copy data to DTCM */ + LONG (__itcm_flash_end__) /* From */ + LONG (__dtcm_start__) /* To */ + LONG ((__dtcm_end__ - __dtcm_start__)/4) /* Size */ + + __copy_table_end__ = .; + } > flash + + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG ((__bss_end__ - __bss_start__)/4) + __zero_table_end__ = .; + } > flash + + /* itcm */ + .cy_itcm ORIGIN(itcm): + { + __itcm_start__ = .; + KEEP(*(.cy_itcm)) + __itcm_end__ = .; + } > itcm AT>flash + + __itcm_flash_end__ = __zero_table_end__ + (__itcm_end__ - __itcm_start__); + + /* dtcm */ + .cy_dtcm ORIGIN(dtcm): + { + __dtcm_start__ = .; + KEEP(*(.cy_dtcm)) + __dtcm_end__ = .; + } > dtcm AT>flash + + __etext = __itcm_flash_end__ + (__dtcm_end__ - __dtcm_start__) ; + + + .ramVectors (NOLOAD) : + { + . = ALIGN(RAMVECTORS_ALIGNMENT); + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : + { + . = ALIGN(4); + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(32); + + KEEP(*(cy_sharedmem*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram AT>flash + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + cy_xip : + { + __cy_xip_start = .; + KEEP(*(.cy_xip)) + __cy_xip_end = .; + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse +} + + +/*============================================================ + * Symbols for use by application + *============================================================ + */ + +__ecc_init_sram_start_address = ORIGIN(ram); +__ecc_init_sram_end_address = ORIGIN(ram) + LENGTH(ram); + +/* EOF */ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/TOOLCHAIN_IAR/linker.icf b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/TOOLCHAIN_IAR/linker.icf new file mode 100644 index 00000000000..8585d37a7ca --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/TOOLCHAIN_IAR/linker.icf @@ -0,0 +1,187 @@ +/******************************************************************************* +* \file xmc7100_x4160_cm7.icf +* \version 1.0.0 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +define symbol sram_start_reserve = 0; + +define symbol sram_total_size = 0x000C0000; /* 768K: SRAM0 + SRAM1 */ +define symbol sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing) */ +define symbol sram_used_by_boot = 0x0; /* Used during boot by Cypress firmware (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations) */ + +define symbol cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */ +define symbol cm7_0_sram_reserve = 0x000BC000; /* 752K : cm7_0 sram size */ + +define symbol code_flash_total_size = 0x00410000; /* 4160K: total flash size */ +define symbol cm0plus_code_flash_reserve = 0x00080000; /* 512K : cm0 flash size */ +define symbol cm7_0_code_flash_reserve = 0x00390000; /* 3648K: cm7_0 flash size */ + + +define symbol code_flash_base_address = 0x10000000; +define symbol sram_base_address = 0x28000000; + +define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "normal" memories (SRAM, DTCM, ITCM) in any Traveo II derivate is used to keep the code generic */ + +define symbol cm7_heap_reserve = 0x00001000; +define symbol cm7_stack_reserve = 0x00001000; + + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM7 cores. + * You can change the memory allocation by editing RAM and Flash values. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'xmc7100d_x4160_cm0plus.icf'. + * any changes here must also be aligned in file 'xmc7xxx_partition.h'. + * after which cm0p core aplication must be build and flashed again. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x28004000; //_base_SRAM_CM7_0 = sram_base_address + cm0plus_sram_reserve; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x280BFFFF; //_size_SRAM_CM7_0 = cm7_0_sram_reserve; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; + +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; //_base_CODE_FLASH_CM7_0 = code_flash_base_address + cm0plus_code_flash_reserve +define symbol __ICFEDIT_region_IROM1_end__ = 0x1040FFFF; //_size_CODE_FLASH_CM7_0 = cm7_0_code_flash_reserve +define symbol __ICFEDIT_region_IROM2_start__ = 0x0; +define symbol __ICFEDIT_region_IROM2_end__ = 0x0; + +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ + +define symbol __ICFEDIT_size_cstack__ = 0x00001000; //cm7_stack_reserve +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +define symbol __ICFEDIT_size_heap__ = 0x00001000; //cm7_heap_reserve + +/**** End of ICF editor section. ###ICF###*/ + +define symbol heap_reserve = __ICFEDIT_size_heap__; +define symbol stack_reserve = (__ICFEDIT_size_cstack__ + (ecc_init_width - 1)) & (~((ecc_init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */ + +/* SRAM reservations */ +define symbol _base_SRAM_CM7_0 = __ICFEDIT_region_IRAM1_start__; +define symbol _size_SRAM_CM7_0 = __ICFEDIT_region_IRAM1_end__ - __ICFEDIT_region_IRAM1_start__ + 1; + +/* Code flash reservations */ +define symbol _base_CODE_FLASH_CM0P = code_flash_base_address; +define symbol _size_CODE_FLASH_CM0P = cm0plus_code_flash_reserve; +define symbol _base_CODE_FLASH_CM7_0 = __ICFEDIT_region_IROM1_start__; +define symbol _size_CODE_FLASH_CM7_0 = __ICFEDIT_region_IROM1_end__ - __ICFEDIT_region_IROM1_start__ + 1; + +define symbol _base_SRAM = _base_SRAM_CM7_0; +define symbol _size_SRAM = _size_SRAM_CM7_0; +define symbol _base_CODE_FLASH = _base_CODE_FLASH_CM7_0; +define symbol _size_CODE_FLASH = _size_CODE_FLASH_CM7_0; + +/*============================================================ + * Memory definitions + *============================================================ + */ + +define memory mem with size = 4G; + +define region SRAM = mem:[from _base_SRAM size _size_SRAM ]; +define region CODE_FLASH = mem:[from _base_CODE_FLASH size _size_CODE_FLASH ]; + +/*============================================================ + * Block definitions + *============================================================ + */ +define block CSTACK with alignment = 8, size = stack_reserve { }; +define block HEAP with expanding size, alignment = 8, minimum size = heap_reserve { }; +define block HEAP_STACK { block HEAP, last block CSTACK }; +define block CM0P_RO with size = (_size_CODE_FLASH_CM0P) { readonly section .cy_m0p_image }; +define block CY_SHAREDMEM with alignment = 32 { section .cy_sharedmem }; + +/*============================================================ + * Initialization + *============================================================ + */ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*============================================================ + * Placement + *============================================================ + */ + +/* Flash - Cortex-M0+ application image */ +place at address (_base_CODE_FLASH_CM0P) { block CM0P_RO }; + +/* Link location specific assignment of 'readonly' type sections to either SRAM or CODE_FLASH */ +/* Note: .intvec must be the first section in ROM in order for __cm7_vector_base_linker_symbol to be correctly calculated! */ + +place at start of CODE_FLASH { section .intvec }; +place in CODE_FLASH { readonly }; + +place in SRAM { readwrite }; +place in SRAM { block CY_SHAREDMEM }; +place at end of SRAM { block HEAP_STACK }; + +keep { section .intvec }; +keep { section .cy_m0p_image }; + +/* Following definitions ensure that SRAM will not be touched at all by startup ECC initialization when code is linked to SRAM, + * use debugger script to initialize the SRAM before downloading the application or adjust below symbols to not include + * the area of SRAM where "ROM type" sections are linked to + */ +define exported symbol __ecc_init_sram_start_address = start(SRAM); +define exported symbol __ecc_init_sram_end_address = end(SRAM); + +/* EOF */ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/startup_cm7.c b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/startup_cm7.c new file mode 100644 index 00000000000..4b6253f3397 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/startup_cm7.c @@ -0,0 +1,435 @@ +/***************************************************************************//** +* \file startup_cm7.c +* \version 1.0 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + + +#include "cy_syslib.h" +#include "cmsis_compiler.h" +#include "startup_cat1c.h" +#include "core_cm7.h" +#include "system_cat1c.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +extern void CM7_CpuIntr_Handler(uint8_t intrNum); + +void Reset_Handler(void); + +/* Internal Reference */ +void Default_Handler(void); +void Default_NMIException_Handler(void); +void Default_Fault_Handler(void); +void SysLib_FaultHandler(uint32_t const *faultStackAddr); +__WEAK void cy_toolchain_init(void); +void FpuEnable(void); + + +#if defined(__ARMCC_VERSION) +extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit; +interrupt_type extern void __main(void); +cy_israddress __ramVectors[VECTORTABLE_SIZE] __attribute__( ( section(".bss.noinit.RESET_RAM"))) __attribute__((aligned(VECTORTABLE_ALIGN))); +#elif defined (__GNUC__) +extern unsigned int __StackTop; +extern uint32_t __StackLimit; +cy_israddress __ramVectors[VECTORTABLE_SIZE] __attribute__( ( section(".ram_vectors"))) __attribute__((aligned(VECTORTABLE_ALIGN))); +#elif defined (__ICCARM__) +extern unsigned int CSTACK$$Limit; +interrupt_type extern void __cmain(); +cy_israddress __ramVectors[VECTORTABLE_SIZE] __attribute__( ( section(".intvec_ram"))) __attribute__((aligned(VECTORTABLE_ALIGN))); +#else + #error "An unsupported toolchain" +#endif /* (__ARMCC_VERSION) */ + +/* SCB->CPACR */ +#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) + +/******************************************************************************* +* Function Name: FpuEnable +****************************************************************************//** +* +* Enables the FPU if it is used. The function is called from the startup file. +* +*******************************************************************************/ +void FpuEnable(void) +{ + #if defined (__FPU_USED) && (__FPU_USED == 1U) + uint32_t interruptState; + interruptState = Cy_SaveIRQ(); + SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; + __DSB(); + __ISB(); + Cy_RestoreIRQ(interruptState); + #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ +} + + +void SysLib_FaultHandler(uint32_t const *faultStackAddr) +{ + Cy_SysLib_FaultHandler(faultStackAddr); +} + +/* Exception Vector Table & Handlers */ +/*----------------------------------------------------------------*/ +void Default_NMIException_Handler(void) +{ + __asm volatile( + "bkpt #10\n" + "B .\n" + ); +} + +void Default_Fault_Handler(void) +{ + __asm ( + "MRS R0, CONTROL\n" + "TST R0, #2\n" + "ITE EQ\n" + "MRSEQ R0, MSP\n" + "MRSNE R0, PSP\n" + "B SysLib_FaultHandler\n" + ); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + + +/******************************************************************************* +* Function Name: Default_CM7_CpuIntr0_Handler +****************************************************************************//** +* +* The Handler is called when the CPU interrupt0 occurs. +* +*******************************************************************************/ +CY_SECTION_ITCM_BEGIN +void Default_CpuIntr0_Handler(void) +{ + CM7_CpuIntr_Handler(0); +} +CY_SECTION_ITCM_END + + +/******************************************************************************* +* Function Name: Default_CM7_CpuIntr1_Handler +****************************************************************************//** +* +* The Handler is called when the CPU interrupt1 occurs. +* +*******************************************************************************/ +CY_SECTION_ITCM_BEGIN +void Default_CpuIntr1_Handler(void) +{ + CM7_CpuIntr_Handler(1); +} +CY_SECTION_ITCM_END + + +/******************************************************************************* +* Function Name: Default_CM7_CpuIntr2_Handler +****************************************************************************//** +* +* The Handler is called when the CPU interrupt2 occurs. +* +*******************************************************************************/ +CY_SECTION_ITCM_BEGIN +void Default_CpuIntr2_Handler(void) +{ + CM7_CpuIntr_Handler(2); +} +CY_SECTION_ITCM_END + + +/******************************************************************************* +* Function Name: Default_CM7_CpuIntr3_Handler +****************************************************************************//** +* +* The Handler is called when the CPU interrupt3 occurs. +* +*******************************************************************************/ +CY_SECTION_ITCM_BEGIN +void Default_CpuIntr3_Handler(void) +{ + CM7_CpuIntr_Handler(3); +} +CY_SECTION_ITCM_END + + +/******************************************************************************* +* Function Name: Default_CM7_CpuIntr4_Handler +****************************************************************************//** +* +* The Handler is called when the CPU interrupt4 occurs. +* +*******************************************************************************/ +CY_SECTION_ITCM_BEGIN +void Default_CpuIntr4_Handler(void) +{ + CM7_CpuIntr_Handler(4); +} +CY_SECTION_ITCM_END + + +/******************************************************************************* +* Function Name: Default_CM7_CpuIntr5_Handler +****************************************************************************//** +* +* The Handler is called when the CPU interrupt5 occurs. +* +*******************************************************************************/ +CY_SECTION_ITCM_BEGIN +void Default_CpuIntr5_Handler(void) +{ + CM7_CpuIntr_Handler(5); +} +CY_SECTION_ITCM_END + + +/******************************************************************************* +* Function Name: Default_CM7_CpuIntr6_Handler +****************************************************************************//** +* +* The Handler is called when the CPU interrupt6 occurs. +* +*******************************************************************************/ +CY_SECTION_ITCM_BEGIN +void Default_CpuIntr6_Handler(void) +{ + CM7_CpuIntr_Handler(6); +} +CY_SECTION_ITCM_END + + +/******************************************************************************* +* Function Name: Default_CM7_CpuIntr7_Handler +****************************************************************************//** +* +* The Handler is called when the CPU interrupt7 occurs. +* +*******************************************************************************/ +CY_SECTION_ITCM_BEGIN +void Default_CpuIntr7_Handler(void) +{ + CM7_CpuIntr_Handler(7); +} +CY_SECTION_ITCM_END + + +void NMIException_Handler (void) __attribute__ ((weak, alias("Default_NMIException_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Fault_Handler"))); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Fault_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Fault_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Fault_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CM7_CpuIntr0_Handler (void) __attribute__ ((weak, alias("Default_CpuIntr0_Handler"))); +void CM7_CpuIntr1_Handler (void) __attribute__ ((weak, alias("Default_CpuIntr1_Handler"))); +void CM7_CpuIntr2_Handler (void) __attribute__ ((weak, alias("Default_CpuIntr2_Handler"))); +void CM7_CpuIntr3_Handler (void) __attribute__ ((weak, alias("Default_CpuIntr3_Handler"))); +void CM7_CpuIntr4_Handler (void) __attribute__ ((weak, alias("Default_CpuIntr4_Handler"))); +void CM7_CpuIntr5_Handler (void) __attribute__ ((weak, alias("Default_CpuIntr5_Handler"))); +void CM7_CpuIntr6_Handler (void) __attribute__ ((weak, alias("Default_CpuIntr6_Handler"))); +void CM7_CpuIntr7_Handler (void) __attribute__ ((weak, alias("Default_CpuIntr7_Handler"))); + +extern const cy_israddress __Vectors[VECTORTABLE_SIZE]; +#if defined (__GNUC__) +_Pragma("GCC diagnostic push") +_Pragma("GCC diagnostic ignored \"-Wpedantic\"") +#endif /* __GNUC__ */ +const cy_israddress __Vectors[VECTORTABLE_SIZE] __VECTOR_TABLE_ATTRIBUTE = { + (cy_israddress)&__INITIAL_SP, + (cy_israddress)Reset_Handler, /* initial PC/Reset */ + (cy_israddress)NMIException_Handler, /* NMI */ + (cy_israddress)HardFault_Handler, /* Hard Fault*/ + (cy_israddress)MemManage_Handler, /* Memory Manage Fault */ + (cy_israddress)BusFault_Handler, /* Bus Fault */ + (cy_israddress)UsageFault_Handler, /* Usage Fault */ + 0, /* RESERVED */ + 0, /* RESERVED */ + 0, /* RESERVED */ + 0, /* RESERVED */ + (cy_israddress)SVC_Handler, /* SVC */ + (cy_israddress)DebugMon_Handler, /* debug */ + 0, /* RESERVED */ + (cy_israddress)PendSV_Handler, /* Pend SV */ + (cy_israddress)SysTick_Handler, /* systick */ + /* External interrupts */ + (cy_israddress)CM7_CpuIntr0_Handler, + (cy_israddress)CM7_CpuIntr1_Handler, + (cy_israddress)CM7_CpuIntr2_Handler, + (cy_israddress)CM7_CpuIntr3_Handler, + (cy_israddress)CM7_CpuIntr4_Handler, + (cy_israddress)CM7_CpuIntr5_Handler, + (cy_israddress)CM7_CpuIntr6_Handler, + (cy_israddress)CM7_CpuIntr7_Handler, + /* Internal interrupts */ + (cy_israddress)Default_Handler, + (cy_israddress)Default_Handler, + (cy_israddress)Default_Handler, + (cy_israddress)Default_Handler, + (cy_israddress)Default_Handler, + (cy_israddress)Default_Handler, + (cy_israddress)Default_Handler, + (cy_israddress)Default_Handler +}; +#if defined (__GNUC__) +_Pragma("GCC diagnostic pop") +#endif /* __GNUC__ */ + +/* Provide empty __WEAK implementation for the low-level initialization + routine required by the RTOS-enabled applications. + clib-support library provides FreeRTOS-specific implementation: + https://github.com/Infineon/clib-support */ +void cy_toolchain_init(void); +__WEAK void cy_toolchain_init(void) +{ +} + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +/* GCC: newlib crt0 _start executes software_init_hook. + The cy_toolchain_init hook provided by clib-support library must execute + after static data initialization and before static constructors. */ +void software_init_hook(); +void software_init_hook() +{ + cy_toolchain_init(); +} +#elif defined(__ICCARM__) +/* Initialize data section */ +void __iar_data_init3(void); + +/* Call the constructors of all global objects */ +void __iar_dynamic_initialization(void); + +/* Define strong version to return zero for __iar_program_start + to skip data sections initialization (__iar_data_init3). */ +int __low_level_init(void); +int __low_level_init(void) +{ + return 0; +} +#else +/**/ +#endif /* defined(__GNUC__) && !defined(__ARMCC_VERSION) */ + + +// Reset Handler +void Reset_Handler(void) +{ + /* disable global interrupt */ + __disable_irq(); + + /* Allow write access to Vector Table Offset Register and ITCM/DTCM configuration register + * (CPUSS_CM7_X_CTL.PPB_LOCK[3] and CPUSS_CM7_X_CTL.PPB_LOCK[1:0]) */ +#ifdef CORE_NAME_CM7_1 + CPUSS->CM7_1_CTL &= ~(0xB); +#elif CORE_NAME_CM7_0 + CPUSS->CM7_0_CTL &= ~(0xB); +#else + #error "Not valid" +#endif + + __DSB(); + __ISB(); + + /* Enable ITCM and DTCM */ + SCB->ITCMCR = SCB->ITCMCR | 0x7; /* Set ITCMCR.EN, .RMW and .RETEN fields */ + SCB->DTCMCR = SCB->DTCMCR | 0x7; /* Set DTCMCR.EN, .RMW and .RETEN fields */ + +#ifdef CORE_NAME_CM7_0 + CPUSS_CM7_0_CTL |= (0x1 << CPUSS_CM7_0_CTL_INIT_TCM_EN_Pos); + CPUSS_CM7_0_CTL |= (0x2 << CPUSS_CM7_0_CTL_INIT_TCM_EN_Pos); + CPUSS_CM7_0_CTL |= (0x1 << CPUSS_CM7_0_CTL_INIT_RMW_EN_Pos); + CPUSS_CM7_0_CTL |= (0x2 << CPUSS_CM7_0_CTL_INIT_RMW_EN_Pos); +#elif CORE_NAME_CM7_1 + CPUSS_CM7_1_CTL |= (0x1 << CPUSS_CM7_1_CTL_INIT_TCM_EN_Pos); + CPUSS_CM7_1_CTL |= (0x2 << CPUSS_CM7_1_CTL_INIT_TCM_EN_Pos); + CPUSS_CM7_1_CTL |= (0x1 << CPUSS_CM7_1_CTL_INIT_RMW_EN_Pos); + CPUSS_CM7_1_CTL |= (0x2 << CPUSS_CM7_1_CTL_INIT_RMW_EN_Pos); +#else +/**/ +#endif + + // ITCMCR EN/RMW/RETEN enabled to access ITCM + __UNALIGNED_UINT32_WRITE(((void const *)0xE000EF90), 0x2F); + // DTCMCR EN/RMW/RETEN enabled to access DTCM + __UNALIGNED_UINT32_WRITE(((void const *)0xE000EF94), 0x2F); + + /* Enable FPU if present */ + FpuEnable(); + + /* copy vector table */ + for (uint32_t count = 0; count < VECTORTABLE_SIZE; count++) + { + __ramVectors[count] =__Vectors[count]; + } + + SCB->VTOR = (uint32_t)__ramVectors; + + __DSB(); + __ISB(); + +#ifdef ENABLE_CM7_INSTRUCTION_CACHE + SCB_EnableICache(); +#endif /* ENABLE_CM7_INSTRUCTION_CACHE */ +#ifdef ENABLE_CM7_DATA_CACHE + SCB_EnableDCache(); +#else + // Ensure that the undefined valid bits in the cache RAM are set to invalid if cache is disabled, because the application + // may call further cache maintenance functions (e.g. SCB_CleanInvalidateDCache) independent of the "cache enabled" state. + SCB_InvalidateDCache(); +#endif /* ENABLE_CM7_DATA_CACHE */ + + SystemInit(); + +#if defined(__ICCARM__) + /* Initialize data section */ + __iar_data_init3(); + + /* Initialization hook for RTOS environment */ + cy_toolchain_init(); + + /* Call the constructors of all global objects */ + __iar_dynamic_initialization(); +#endif + + /* c-runtime */ + __PROGRAM_START(); +} + + +#if defined(__cplusplus) +} +#endif + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/system_cm7.c b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/system_cm7.c new file mode 100644 index 00000000000..11dd0e36d9c --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/system_cm7.c @@ -0,0 +1,240 @@ +/***************************************************************************//** +* \file system_cm7.c +* \version 1.2 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2021-2024 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_sysclk.h" +#include "cy_wdt.h" + + +void Cy_DefaultUserHandler(void); + +#define DEFAULT_HANDLER_NAME Cy_DefaultUserHandler + +CY_NOINIT cy_israddress Cy_SystemIrqUserTable[CPUSS_SYSTEM_INT_NR] ; + +CY_NOINIT cy_israddress * Cy_SysInt_SystemIrqUserTableRamPointer ; + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (8000000UL) + +/** Default system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) + +/** Holds the CLK_SLOW(Cortex-M0+) or CLK_FAST0(Cortex-M7_0) or CLK_FAST(Cortex-M7_1) system core clock */ +CY_NOINIT uint32_t SystemCoreClock ; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). Note that the HfClk0 does not source any CPU core directly. */ +CY_NOINIT uint32_t cy_Hfclk0FreqHz ; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +CY_NOINIT uint32_t cy_PeriClkFreqHz ; + +/** Holds the AHB frequency. Updated by \ref SystemCoreClockUpdate(). */ +CY_NOINIT uint32_t cy_AhbFreqHz ; + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) + +CY_NOINIT uint32_t cy_delayFreqHz ; + +CY_NOINIT uint32_t cy_delayFreqKhz ; + +CY_NOINIT uint32_t cy_delayFreqMhz ; + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* \cond +* Initializes the system: +* - Unlocks and disables WDT. +* - Calls the Cy_SystemInit() function. +* - Calls \ref SystemCoreClockUpdate(). +* \endcond +*******************************************************************************/ +void SystemInit(void) +{ + + /* if CM0+ is not enabled then unlock and disable WDT */ +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + + /* Release reset for all groups IP except group 0 */ + (void)Cy_SysClk_PeriGroupSetSlaveCtl(1, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */ + (void)Cy_SysClk_PeriGroupSetSlaveCtl(2, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */ + (void)Cy_SysClk_PeriGroupSetSlaveCtl(3, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */ + (void)Cy_SysClk_PeriGroupSetSlaveCtl(4, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */ + (void)Cy_SysClk_PeriGroupSetSlaveCtl(5, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */ + (void)Cy_SysClk_PeriGroupSetSlaveCtl(6, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */ + (void)Cy_SysClk_PeriGroupSetSlaveCtl(8, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */ + (void)Cy_SysClk_PeriGroupSetSlaveCtl(9, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */ + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + + Cy_SystemInit(); + SystemCoreClockUpdate(); + + SystemIrqInit(); +} + +/******************************************************************************* +* Function Name: SystemIrqInit +****************************************************************************//** +* +* The function is called during device startup. +* +*******************************************************************************/ +void SystemIrqInit(void) +{ + for (int i=0; i<(int)CPUSS_SYSTEM_INT_NR; i++) + { + Cy_SystemIrqUserTable[i] = DEFAULT_HANDLER_NAME; + } + + Cy_SysInt_SystemIrqUserTableRamPointer = Cy_SystemIrqUserTable; +} + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the user application + * as strong function. + */ +} + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + /* Get frequency for the fast clock source of the core we are currently building for. */ + #if defined (CORE_NAME_CM7_0) && (CORE_NAME_CM7_0 == 1) + SystemCoreClock = Cy_SysClk_ClkFastSrcGetFrequency(0); + #else + SystemCoreClock = Cy_SysClk_ClkFastSrcGetFrequency(1); + #endif + + /* This is part of the clock tree for the CM0+; do not use for CM7 clock calculations. */ + cy_Hfclk0FreqHz = Cy_SysClk_ClkHfGetFrequency(CY_SYSCLK_CLK_CORE_HF_PATH_NUM); + + /* Get frequency for the high-frequency clock # 2 , which is used for PERI PCLK. */ + cy_PeriClkFreqHz = Cy_SysClk_ClkHfGetFrequency(CY_SYSCLK_CLK_PERI_HF_PATH_NUM); + + /* Sets clock frequency for Delay API */ + cy_delayFreqHz = SystemCoreClock; + cy_delayFreqMhz = (uint32_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + + /* Get the frequency of AHB source, CLK HF0 is the source for AHB*/ + cy_AhbFreqHz = Cy_SysClk_ClkHfGetFrequency(0UL); +} + + +/******************************************************************************* +* Function Name: Cy_DefaultUserHandler +****************************************************************************//** +* +*The Handler is called when the CPU attempts to call IRQ that has not been mapped to user functions. +* +* +*******************************************************************************/ +void Cy_DefaultUserHandler(void) +{ + // This IRQ occurred because CPU attempted to call IRQ that has not been mapped to user function + while(1); +} + + +/******************************************************************************* +* Function Name: CM7_CpuIntr_Handler +****************************************************************************//** +* +* The Inline handler for CPU interrupt. +* The system interrupt mapped to CPU interrupt will be fetched and executed +* +*******************************************************************************/ +CY_SECTION_ITCM_BEGIN +void CM7_CpuIntr_Handler(uint8_t intrNum) +{ + uint32_t system_int_idx; + cy_israddress handler; + +#ifdef CORE_NAME_CM7_0 + if((_FLD2VAL(CPUSS_CM7_0_INT_STATUS_SYSTEM_INT_VALID, CPUSS_CM7_0_INT_STATUS[intrNum]))) + { + system_int_idx = _FLD2VAL(CPUSS_CM7_0_INT_STATUS_SYSTEM_INT_IDX, CPUSS_CM7_0_INT_STATUS[intrNum]); + handler = Cy_SystemIrqUserTable[system_int_idx]; + handler(); // jump to system interrupt handler + } +#endif +#ifdef CORE_NAME_CM7_1 + if((_FLD2VAL(CPUSS_CM7_1_INT_STATUS_SYSTEM_INT_VALID, CPUSS_CM7_1_INT_STATUS[intrNum]))) + { + system_int_idx = _FLD2VAL(CPUSS_CM7_1_INT_STATUS_SYSTEM_INT_IDX, CPUSS_CM7_1_INT_STATUS[intrNum]); + handler = Cy_SystemIrqUserTable[system_int_idx]; + handler(); // jump to system interrupt handler + } +#endif + NVIC_ClearPendingIRQ((IRQn_Type)intrNum); +} +CY_SECTION_ITCM_END + diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/EULA b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/EULA new file mode 100644 index 00000000000..01d5e5857d7 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/EULA @@ -0,0 +1,211 @@ +CYPRESS (AN INFINEON COMPANY) END USER LICENSE AGREEMENT + +PLEASE READ THIS END USER LICENSE AGREEMENT ("Agreement") CAREFULLY BEFORE +DOWNLOADING, INSTALLING, COPYING, OR USING THIS SOFTWARE AND ACCOMPANYING +DOCUMENTATION. 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Limitation of Liability. + +In no event and under no legal theory, whether in tort (including negligence), +contract, or otherwise, unless required by applicable law (such as deliberate +and grossly negligent acts) or agreed to in writing, shall any Contributor be +liable to You for damages, including any direct, indirect, special, incidental, +or consequential damages of any character arising as a result of this License or +out of the use or inability to use the Work (including but not limited to +damages for loss of goodwill, work stoppage, computer failure or malfunction, or +any and all other commercial damages or losses), even if such Contributor has +been advised of the possibility of such damages. + +9. Accepting Warranty or Additional Liability. + +While redistributing the Work or Derivative Works thereof, You may choose to +offer, and charge a fee for, acceptance of support, warranty, indemnity, or +other liability obligations and/or rights consistent with this License. However, +in accepting such obligations, You may act only on Your own behalf and on Your +sole responsibility, not on behalf of any other Contributor, and only if You +agree to indemnify, defend, and hold each Contributor harmless for any liability +incurred by, or claims asserted against, such Contributor by reason of your +accepting any such warranty or additional liability. diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/README.md b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/README.md new file mode 100644 index 00000000000..09b2869f4c5 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/README.md @@ -0,0 +1,89 @@ +# KIT_XMC71_EVK_LITE_V2 BSP + +## Overview + +The KIT_XMC71_EVK_LITE_V2, a 100-pin evaluation board is based on the XMC7100 family of devices. XMC7100 MCU is designed for industrial applications. The evaluation board carries a XMC7100D microcontroller,and headers compatible with Arduino for interfacing Arduino shields. In addition, the board features an on-board programmer/debugger (KitProg3), a 512-Mbit QSPI NOR flash, CAN FD transceiver, Ethernet PHY transceiver with RJ45 connector interface, a Shield2Go connector interface and MikroBUS connector interface, two user LEDs, one potentiometer, and two push buttons. The board supports operating voltages from 3.3 V to 5.0 V for XMC7100D device. + +**Note:** +KIT_XMC71_EVK_LITE_V2 is the board support package for the XMC7100 Lite Evaluation board with XMC7100D-F100K4160 MCU. Replace the XMC7100D-F176K4160 (default device) on the XMC7100 Lite Evaluation board with XMC7100D-F100K4160 to use this BSP. + + + +To use code from the BSP, simply include a reference to `cybsp.h`. + +## Features + +### Kit Features: + +* XMC7100D-F100K4160 8MB Flash 100-pin TEQFP device +* Programming interface (Arm® Standard JTAG, Cortex® Debug + ETM with Arm® ETM Mictor) +* Reset control with manual reset switch and voltage supervision +* CAN FD interface +* Ethernet interface +* One 512-Mbit external Quad SPI NOR Flash that provides a fast, expandable memory for data and code +* KitProg3 on-board SWD programmer/debugger, USB-UART and USB-I2C bridge functionality +* A Shield2Go connector interface and a MikroBUS connector interface +* Selectable input supply voltages of 3.3 V and 5.0 V for the XMC7100D device +* Two user LEDs, two user buttons, and a reset button for the XMC7100D device +* A potentiometer which can be used to simulate analog sensor output +* A mode button and a mode LED for KitProg3 + +### Kit Contents: + +* XMC7100 evaluation board +* USB Type-A to Micro-B cable +* Quick start guide (printed on the kit package) + +## BSP Configuration + +The BSP has a few hooks that allow its behavior to be configured. Some of these items are enabled by default while others must be explicitly enabled. Items enabled by default are specified in the KIT_XMC71_EVK_LITE_V2.mk file. The items that are enabled can be changed by creating a custom BSP or by editing the application makefile. + +Components: +* Device specific category reference (e.g.: CAT1) - This component, enabled by default, pulls in any device specific code for this board. + +Defines: +* CYBSP_WIFI_CAPABLE - This define, disabled by default, causes the BSP to initialize the interface to an onboard wireless chip if it has one. +* CY_USING_HAL - This define, enabled by default, specifies that the HAL is intended to be used by the application. This will cause the BSP to include the applicable header file and to initialize the system level drivers. +* CYBSP_CUSTOM_SYSCLK_PM_CALLBACK - This define, disabled by default, causes the BSP to skip registering its default SysClk Power Management callback, if any, and instead to invoke the application-defined function `cybsp_register_custom_sysclk_pm_callback` to register an application-specific callback. + +### Clock Configuration + +| Clock | Source | Output Frequency | +|----------|-----------|------------------| +| FLL | ECO | 100.0 MHz | +| PLL | ECO | 200.0 MHz | +| CLK_HF0 | CLK_PATH0 | 100 MHz | +| CLK_HF1 | CLK_PATH1 | 250 MHz | +| CLK_HF2 | CLK_PATH4 | 100 MHz | +| CLK_HF3 | CLK_PATH4 | 100 MHz | +| CLK_HF4 | CLK_PATH4 | 50 MHz | +| CLK_HF5 | CLK_PATH2 | 125 MHz | +| CLK_HF6 | CLK_PATH4 | 200 MHz | +| CLK_HF7 | CLK_PATH5 | 0 MHz | + +### Power Configuration + +* System Idle Power Mode: Deep Sleep +* VDDA Voltage: 3300 mV +* VDDD Voltage: 3300 mV + +See the [BSP Setttings][settings] for additional board specific configuration settings. + +## API Reference Manual + +The KIT_XMC71_EVK_LITE_V2 Board Support Package provides a set of APIs to configure, initialize and use the board resources. + +See the [BSP API Reference Manual][api] for the complete list of the provided interfaces. + +## More information +* [KIT_XMC71_EVK_LITE_V2 BSP API Reference Manual][api] +* [KIT_XMC71_EVK_LITE_V2 Documentation](https://www.infineon.com/KIT_XMC71_EVK_LITE_V1) +* [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com) +* [Infineon GitHub](https://github.com/infineon) +* [ModusToolbox™](https://www.cypress.com/products/modustoolbox-software-environment) + +[api]: https://infineon.github.io/TARGET_KIT_XMC71_EVK_LITE_V2/html/modules.html +[settings]: https://infineon.github.io/TARGET_KIT_XMC71_EVK_LITE_V2/html/md_bsp_settings.html + +--- +© Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2024. \ No newline at end of file diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/RELEASE.md b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/RELEASE.md new file mode 100644 index 00000000000..f7a5ec5e011 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/RELEASE.md @@ -0,0 +1,75 @@ +# KIT_XMC71_EVK_LITE_V2 BSP Release Notes +The KIT_XMC71_EVK_LITE_V2, a 100-pin evaluation board is based on the XMC7100 family of devices. XMC7100 MCU is designed for industrial applications. The evaluation board carries a XMC7100D microcontroller,and headers compatible with Arduino for interfacing Arduino shields. In addition, the board features an on-board programmer/debugger (KitProg3), a 512-Mbit QSPI NOR flash, CAN FD transceiver, Ethernet PHY transceiver with RJ45 connector interface, a Shield2Go connector interface and MikroBUS connector interface, two user LEDs, one potentiometer, and two push buttons. The board supports operating voltages from 3.3 V to 5.0 V for XMC7100D device. + +**Note:** +KIT_XMC71_EVK_LITE_V2 is the board support package for the XMC7100 Lite Evaluation board with XMC7100D-F100K4160 MCU. Replace the XMC7100D-F176K4160 (default device) on the XMC7100 Lite Evaluation board with XMC7100D-F100K4160 to use this BSP. + +NOTE: BSPs are versioned by family. This means that version 1.2.0 of any BSP in a family (eg: XMC™ ) will have the same software maturity level. However, not all updates are necessarily applicable for each BSP in the family so not all version numbers will exist for each board. Additionally, new BSPs may not start at version 1.0.0. In the event of adding a common feature across all BSPs, the libraries are assigned the same version number. For example if BSP_A is at v1.3.0 and BSP_B is at v1.2.0, the event will trigger a version update to v1.4.0 for both BSP_A and BSP_B. This allows the common feature to be tracked in a consistent way. + +### What's Included? +The KIT_XMC71_EVK_LITE_V2 library includes the following: +* BSP specific makefile to configure the build process for the board +* cybsp.c/h files to initialize the board and any system peripherals +* cybsp_types.h file describing basic board setup +* Linker script & startup code for GCC and ARM toolchains +* Configurator design files (and generated code) to setup board specific peripherals +* .lib file references for all dependent libraries +* API documentation + +### What Changed? +#### v2.3.0 +* Updated linker scripts and startup code to align with mtb-pdl-cat1 v3.14.0 +* Added bt-fw-mur-cyw43439 as a dependency for KIT_XMC72_EVK_MUR_43439M2 +#### v2.2.0 +* Added the BSP for KIT_T2G_C-2D-6M_LITE +#### v2.1.0 +* Updated the KIT_XMC72_EVK, KIT_XMC72_EVK_MUR_43439M2, KIT_XMC71_EVK_LITE_V1 and KIT_XMC71_EVK_LITE_V2 BSPs to use ECO as main clock source +#### v2.0.2 +* Updated the BSP description for KIT_XMC71_EVK_LITE_V1 and KIT_XMC71_EVK_LITE_V2 BSPs +#### v2.0.1 +* Updated the description in README file for KIT_XMC72_EVK and KIT_XMC72_EVK_MUR_43439M2 BSPs +#### v2.0.0 +* Fixed issue where CM0P prebuilt image would enable both CM7 cores on devices which contain + two CM7 cores, even for single core applications. +* Updated default clock divider selections to better align with frequency limitations documented + in the datasheet. + +##### Known issues: +Issue: Wifi companion radio connection may fail when the board is programmed using `make program` + +Workaround: Program the board using an IDE launch config. +#### v1.2.1 +* Updated the description in README file for KIT_XMC72_EVK and KIT_XMC72_EVK_MUR_43439M2 BSPs +#### v1.2.0 +* Updated linker scripts and startup code to align with mtb-pdl-cat1 v3.4.0 +* Added functionality to enable BSP Assistant chip flow +* Added capabilities to match BSPS created by BSP Assistant chip flow +#### v1.1.0 +* Add macro `CYBSP_USER_BTN_DRIVE` indicating the drive mode that should be used for user buttons +#### v1.0.0 +Note: This revision is only compatible with ModusToolbox Tools 3.0 and newer. +* Initial production release + +### Supported Software and Tools +This version of the KIT_XMC71_EVK_LITE_V2 BSP was validated for compatibility with the following Software and Tools: + +| Software and Tools | Version | +| :--- | :----: | +| ModusToolbox™ Software Environment | 3.2.0 | +| GCC Compiler | 11.3.1 | +| IAR Compiler | 9.50.2 | +| ARM Compiler | 6.22 | + +Minimum required ModusToolbox™ Software Environment: v3.0.0 + +### More information +* [KIT_XMC71_EVK_LITE_V2 BSP API Reference Manual][api] +* [KIT_XMC71_EVK_LITE_V2 Documentation](https://www.infineon.com/KIT_XMC71_EVK_LITE_V1) +* [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com) +* [Infineon GitHub](https://github.com/infineon) +* [ModusToolbox™](https://www.cypress.com/products/modustoolbox-software-environment) + +[api]: https://infineon.github.io/TARGET_KIT_XMC71_EVK_LITE_V2/html/modules.html + +--- +© Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2024. \ No newline at end of file diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/FlashLoaders/CAT1C_SMIF.FLM b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/FlashLoaders/CAT1C_SMIF.FLM new file mode 100644 index 00000000000..2c25449e605 Binary files /dev/null and b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/FlashLoaders/CAT1C_SMIF.FLM differ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/FlashLoaders/version.xml b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/FlashLoaders/version.xml new file mode 100644 index 00000000000..c38d173efde --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/FlashLoaders/version.xml @@ -0,0 +1 @@ +1.0.0.103 diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/.hardware-config-server.generated-files b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/.hardware-config-server.generated-files new file mode 100644 index 00000000000..55835bd725b --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/.hardware-config-server.generated-files @@ -0,0 +1,10 @@ +cycfg_clocks.c +cycfg_clocks.h +cycfg_notices.h +cycfg_peripherals.h +cycfg_pins.c +cycfg_pins.h +cycfg_routing.c +cycfg_routing.h +cycfg_system.c +cycfg_system.h diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/CAT1C_SMIF.FLM b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/CAT1C_SMIF.FLM new file mode 100644 index 00000000000..03bc15835b9 Binary files /dev/null and b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/CAT1C_SMIF.FLM differ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg.c b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg.c new file mode 100644 index 00000000000..56b526442cc --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg.c @@ -0,0 +1,50 @@ +/******************************************************************************* + * File Name: cycfg.c + * + * Description: + * Simple wrapper containing all generated files and function to initialize + * all generated code. + * This file was automatically generated and should not be modified. + * Configurator Backend 3.50.0 + * device-db 4.22.0.7873 + * mtb-pdl-cat1 3.15.0.40227 + * + ******************************************************************************* + * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#include "cycfg.h" + +/* This function is provided for compatibility with older 2.X style projects. */ +void init_cycfg_all(void) +{ + cycfg_config_init(); + cycfg_config_reservations(); +} +void cycfg_config_init(void) +{ + init_cycfg_system(); + init_cycfg_clocks(); + init_cycfg_routing(); + init_cycfg_pins(); +} +void cycfg_config_reservations(void) +{ + reserve_cycfg_system(); + reserve_cycfg_clocks(); + reserve_cycfg_pins(); +} diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg.h b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg.h new file mode 100644 index 00000000000..2c2669f0b1a --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg.h @@ -0,0 +1,52 @@ +/******************************************************************************* + * File Name: cycfg.h + * + * Description: + * Simple wrapper containing all generated files and function to initialize + * all generated code. + * This file was automatically generated and should not be modified. + * Configurator Backend 3.50.0 + * device-db 4.22.0.7873 + * mtb-pdl-cat1 3.15.0.40227 + * + ******************************************************************************* + * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#if !defined(CYCFG_H) +#define CYCFG_H + +#include "cycfg_notices.h" +#include "cycfg_system.h" +#include "cycfg_clocks.h" +#include "cycfg_routing.h" +#include "cycfg_peripherals.h" +#include "cycfg_pins.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* defined(__cplusplus) */ + +void init_cycfg_all(void); +void cycfg_config_init(void); +void cycfg_config_reservations(void); + +#if defined(__cplusplus) +} +#endif /* defined(__cplusplus) */ + +#endif /* CYCFG_H */ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg.timestamp b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg.timestamp new file mode 100644 index 00000000000..d2b4a3d1771 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg.timestamp @@ -0,0 +1,27 @@ +/******************************************************************************* + * File Name: cycfg.timestamp + * + * Description: + * Sentinel file for determining if generated source is up to date. + * This file was automatically generated and should not be modified. + * Configurator Backend 3.50.0 + * device-db 4.22.0.7873 + * mtb-pdl-cat1 3.15.0.40227 + * + ******************************************************************************* + * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_clocks.c b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_clocks.c new file mode 100644 index 00000000000..7c7bb809fff --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_clocks.c @@ -0,0 +1,131 @@ +/******************************************************************************* + * File Name: cycfg_clocks.c + * + * Description: + * Clock configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.50.0 + * device-db 4.22.0.7873 + * mtb-pdl-cat1 3.15.0.40227 + * + ******************************************************************************* + * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#include "cycfg_clocks.h" + +#if defined (CY_USING_HAL) +const cyhal_resource_inst_t CYBSP_TRACE_CLK_DIV2_obj = +{ + .type = CYHAL_RSC_CLOCK, + .block_num = CYBSP_TRACE_CLK_DIV2_HW, + .channel_num = CYBSP_TRACE_CLK_DIV2_NUM, +}; +const cyhal_resource_inst_t peri_0_group_1_div_8_0_obj = +{ + .type = CYHAL_RSC_CLOCK, + .block_num = peri_0_group_1_div_8_0_HW, + .channel_num = peri_0_group_1_div_8_0_NUM, +}; +const cyhal_resource_inst_t peri_0_group_1_div_8_1_obj = +{ + .type = CYHAL_RSC_CLOCK, + .block_num = peri_0_group_1_div_8_1_HW, + .channel_num = peri_0_group_1_div_8_1_NUM, +}; +const cyhal_resource_inst_t peri_0_group_1_div_8_2_obj = +{ + .type = CYHAL_RSC_CLOCK, + .block_num = peri_0_group_1_div_8_2_HW, + .channel_num = peri_0_group_1_div_8_2_NUM, +}; +const cyhal_resource_inst_t peri_0_group_1_div_8_3_obj = +{ + .type = CYHAL_RSC_CLOCK, + .block_num = peri_0_group_1_div_8_3_HW, + .channel_num = peri_0_group_1_div_8_3_NUM, +}; +const cyhal_resource_inst_t peri_0_group_1_div_8_4_obj = +{ + .type = CYHAL_RSC_CLOCK, + .block_num = peri_0_group_1_div_8_4_HW, + .channel_num = peri_0_group_1_div_8_4_NUM, +}; +const cyhal_resource_inst_t peri_0_group_1_div_8_5_obj = +{ + .type = CYHAL_RSC_CLOCK, + .block_num = peri_0_group_1_div_8_5_HW, + .channel_num = peri_0_group_1_div_8_5_NUM, +}; +const cyhal_resource_inst_t peri_0_group_1_div_8_6_obj = +{ + .type = CYHAL_RSC_CLOCK, + .block_num = peri_0_group_1_div_8_6_HW, + .channel_num = peri_0_group_1_div_8_6_NUM, +}; +const cyhal_resource_inst_t peri_0_group_1_div_8_7_obj = +{ + .type = CYHAL_RSC_CLOCK, + .block_num = peri_0_group_1_div_8_7_HW, + .channel_num = peri_0_group_1_div_8_7_NUM, +}; +#endif /* defined (CY_USING_HAL) */ + +void init_cycfg_clocks(void) +{ + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_TRACE_CLK_DIV2_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_TRACE_CLK_DIV2_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U, 0U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_TRACE_CLK_DIV2_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_0_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_0_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U, 108U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_0_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_1_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 1U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_1_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 1U, 0U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_1_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 1U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_2_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_2_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U, 0U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_2_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_3_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 3U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_3_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 3U, 0U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_3_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 3U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_4_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 4U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_4_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 4U, 0U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_4_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 4U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_5_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 5U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_5_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 5U, 0U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_5_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 5U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_6_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 6U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_6_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 6U, 0U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_6_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 6U); + Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_7_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 7U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_7_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 7U, 108U); + Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_7_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 7U); +} +void reserve_cycfg_clocks(void) +{ +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_TRACE_CLK_DIV2_obj); + cyhal_hwmgr_reserve(&peri_0_group_1_div_8_0_obj); + cyhal_hwmgr_reserve(&peri_0_group_1_div_8_1_obj); + cyhal_hwmgr_reserve(&peri_0_group_1_div_8_2_obj); + cyhal_hwmgr_reserve(&peri_0_group_1_div_8_3_obj); + cyhal_hwmgr_reserve(&peri_0_group_1_div_8_4_obj); + cyhal_hwmgr_reserve(&peri_0_group_1_div_8_5_obj); + cyhal_hwmgr_reserve(&peri_0_group_1_div_8_6_obj); + cyhal_hwmgr_reserve(&peri_0_group_1_div_8_7_obj); +#endif /* defined (CY_USING_HAL) */ +} diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_clocks.h b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_clocks.h new file mode 100644 index 00000000000..48464b0c39b --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_clocks.h @@ -0,0 +1,215 @@ +/******************************************************************************* + * File Name: cycfg_clocks.h + * + * Description: + * Clock configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.50.0 + * device-db 4.22.0.7873 + * mtb-pdl-cat1 3.15.0.40227 + * + ******************************************************************************* + * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#if !defined(CYCFG_CLOCKS_H) +#define CYCFG_CLOCKS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" + +#if defined (CY_USING_HAL) +#include "cyhal_hwmgr.h" +#endif /* defined (CY_USING_HAL) */ + +#if defined(__cplusplus) +extern "C" { +#endif /* defined(__cplusplus) */ + +#define CYBSP_TRACE_CLK_DIV2_ENABLED 1U + +#if defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) +#define CYBSP_TRACE_CLK_DIV2_HW CYHAL_CLOCK_BLOCK_PERIPHERAL0_8BIT +#endif /* defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) */ + +#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) +#define CYBSP_TRACE_CLK_DIV2_HW CY_SYSCLK_DIV_8_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define CYBSP_TRACE_CLK_DIV2_NUM 2U +#define CYBSP_TRACE_CLK_DIV2_GRP_NUM ((0U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined (CYBSP_TRACE_CLK_DIV2_GRP_NUM) +#define CYBSP_TRACE_CLK_DIV2_GRP_NUM CYBSP_TRACE_CLK_DIV2_GRP_NUM +#endif /* !defined (CYBSP_TRACE_CLK_DIV2_GRP_NUM) */ + +#define peri_0_group_1_div_8_0_ENABLED 1U + +#if defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) +#define peri_0_group_1_div_8_0_HW CYHAL_CLOCK_BLOCK_PERIPHERAL1_8BIT +#endif /* defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) */ + +#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) +#define peri_0_group_1_div_8_0_HW CY_SYSCLK_DIV_8_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define peri_0_group_1_div_8_0_NUM 0U +#define PERI_0_GROUP_1_DIV_8_0_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined (peri_0_group_1_div_8_0_GRP_NUM) +#define peri_0_group_1_div_8_0_GRP_NUM PERI_0_GROUP_1_DIV_8_0_GRP_NUM +#endif /* !defined (peri_0_group_1_div_8_0_GRP_NUM) */ + +#define peri_0_group_1_div_8_1_ENABLED 1U + +#if defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) +#define peri_0_group_1_div_8_1_HW CYHAL_CLOCK_BLOCK_PERIPHERAL1_8BIT +#endif /* defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) */ + +#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) +#define peri_0_group_1_div_8_1_HW CY_SYSCLK_DIV_8_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define peri_0_group_1_div_8_1_NUM 1U +#define PERI_0_GROUP_1_DIV_8_1_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined (peri_0_group_1_div_8_1_GRP_NUM) +#define peri_0_group_1_div_8_1_GRP_NUM PERI_0_GROUP_1_DIV_8_1_GRP_NUM +#endif /* !defined (peri_0_group_1_div_8_1_GRP_NUM) */ + +#define peri_0_group_1_div_8_2_ENABLED 1U + +#if defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) +#define peri_0_group_1_div_8_2_HW CYHAL_CLOCK_BLOCK_PERIPHERAL1_8BIT +#endif /* defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) */ + +#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) +#define peri_0_group_1_div_8_2_HW CY_SYSCLK_DIV_8_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define peri_0_group_1_div_8_2_NUM 2U +#define PERI_0_GROUP_1_DIV_8_2_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined (peri_0_group_1_div_8_2_GRP_NUM) +#define peri_0_group_1_div_8_2_GRP_NUM PERI_0_GROUP_1_DIV_8_2_GRP_NUM +#endif /* !defined (peri_0_group_1_div_8_2_GRP_NUM) */ + +#define peri_0_group_1_div_8_3_ENABLED 1U + +#if defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) +#define peri_0_group_1_div_8_3_HW CYHAL_CLOCK_BLOCK_PERIPHERAL1_8BIT +#endif /* defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) */ + +#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) +#define peri_0_group_1_div_8_3_HW CY_SYSCLK_DIV_8_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define peri_0_group_1_div_8_3_NUM 3U +#define PERI_0_GROUP_1_DIV_8_3_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined (peri_0_group_1_div_8_3_GRP_NUM) +#define peri_0_group_1_div_8_3_GRP_NUM PERI_0_GROUP_1_DIV_8_3_GRP_NUM +#endif /* !defined (peri_0_group_1_div_8_3_GRP_NUM) */ + +#define peri_0_group_1_div_8_4_ENABLED 1U + +#if defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) +#define peri_0_group_1_div_8_4_HW CYHAL_CLOCK_BLOCK_PERIPHERAL1_8BIT +#endif /* defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) */ + +#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) +#define peri_0_group_1_div_8_4_HW CY_SYSCLK_DIV_8_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define peri_0_group_1_div_8_4_NUM 4U +#define PERI_0_GROUP_1_DIV_8_4_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined (peri_0_group_1_div_8_4_GRP_NUM) +#define peri_0_group_1_div_8_4_GRP_NUM PERI_0_GROUP_1_DIV_8_4_GRP_NUM +#endif /* !defined (peri_0_group_1_div_8_4_GRP_NUM) */ + +#define peri_0_group_1_div_8_5_ENABLED 1U + +#if defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) +#define peri_0_group_1_div_8_5_HW CYHAL_CLOCK_BLOCK_PERIPHERAL1_8BIT +#endif /* defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) */ + +#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) +#define peri_0_group_1_div_8_5_HW CY_SYSCLK_DIV_8_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define peri_0_group_1_div_8_5_NUM 5U +#define PERI_0_GROUP_1_DIV_8_5_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined (peri_0_group_1_div_8_5_GRP_NUM) +#define peri_0_group_1_div_8_5_GRP_NUM PERI_0_GROUP_1_DIV_8_5_GRP_NUM +#endif /* !defined (peri_0_group_1_div_8_5_GRP_NUM) */ + +#define peri_0_group_1_div_8_6_ENABLED 1U + +#if defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) +#define peri_0_group_1_div_8_6_HW CYHAL_CLOCK_BLOCK_PERIPHERAL1_8BIT +#endif /* defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) */ + +#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) +#define peri_0_group_1_div_8_6_HW CY_SYSCLK_DIV_8_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define peri_0_group_1_div_8_6_NUM 6U +#define PERI_0_GROUP_1_DIV_8_6_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined (peri_0_group_1_div_8_6_GRP_NUM) +#define peri_0_group_1_div_8_6_GRP_NUM PERI_0_GROUP_1_DIV_8_6_GRP_NUM +#endif /* !defined (peri_0_group_1_div_8_6_GRP_NUM) */ + +#define peri_0_group_1_div_8_7_ENABLED 1U + +#if defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) +#define peri_0_group_1_div_8_7_HW CYHAL_CLOCK_BLOCK_PERIPHERAL1_8BIT +#endif /* defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) */ + +#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) +#define peri_0_group_1_div_8_7_HW CY_SYSCLK_DIV_8_BIT +#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */ + +#define peri_0_group_1_div_8_7_NUM 7U +#define PERI_0_GROUP_1_DIV_8_7_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos)) + +#if !defined (peri_0_group_1_div_8_7_GRP_NUM) +#define peri_0_group_1_div_8_7_GRP_NUM PERI_0_GROUP_1_DIV_8_7_GRP_NUM +#endif /* !defined (peri_0_group_1_div_8_7_GRP_NUM) */ + +#if defined (CY_USING_HAL) +extern const cyhal_resource_inst_t CYBSP_TRACE_CLK_DIV2_obj; +extern const cyhal_resource_inst_t peri_0_group_1_div_8_0_obj; +extern const cyhal_resource_inst_t peri_0_group_1_div_8_1_obj; +extern const cyhal_resource_inst_t peri_0_group_1_div_8_2_obj; +extern const cyhal_resource_inst_t peri_0_group_1_div_8_3_obj; +extern const cyhal_resource_inst_t peri_0_group_1_div_8_4_obj; +extern const cyhal_resource_inst_t peri_0_group_1_div_8_5_obj; +extern const cyhal_resource_inst_t peri_0_group_1_div_8_6_obj; +extern const cyhal_resource_inst_t peri_0_group_1_div_8_7_obj; +#endif /* defined (CY_USING_HAL) */ + +void init_cycfg_clocks(void); +void reserve_cycfg_clocks(void); + +#if defined(__cplusplus) +} +#endif /* defined(__cplusplus) */ + +#endif /* CYCFG_CLOCKS_H */ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_notices.h b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_notices.h new file mode 100644 index 00000000000..5775004d68a --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_notices.h @@ -0,0 +1,53 @@ +/******************************************************************************* + * File Name: cycfg_notices.h + * + * Description: + * Contains warnings and errors that occurred while generating code for the + * design. + * This file was automatically generated and should not be modified. + * Configurator Backend 3.50.0 + * device-db 4.22.0.7873 + * mtb-pdl-cat1 3.15.0.40227 + * + ******************************************************************************* + * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#if !defined(CYCFG_NOTICES_H) +#define CYCFG_NOTICES_H + +#if defined(__cplusplus) +extern "C" { +#endif /* defined(__cplusplus) */ + +#if defined(CY_SUPPORTS_DEVICE_VALIDATION) +#if !defined(XMC7100D_F144K4160) +#error "Unexpected MPN; expected DEVICE:=XMC7100D-F144K4160. There may be an inconsistency between the *.modus file and the makefile target configuration device sets." +#endif /* !defined(XMC7100D_F144K4160) */ +#endif /* defined(CY_SUPPORTS_DEVICE_VALIDATION) */ + +#if defined(CY_SUPPORTS_COMPLETE_DEVICE_VALIDATION) +#if !defined(XMC7100D_F144K4160) +#error "Unexpected MPN; expected DEVICE:=XMC7100D-F144K4160. There may be an inconsistency between the *.modus file and the makefile target configuration device sets." +#endif /* !defined(XMC7100D_F144K4160) */ +#endif /* defined(CY_SUPPORTS_COMPLETE_DEVICE_VALIDATION) */ + +#if defined(__cplusplus) +} +#endif /* defined(__cplusplus) */ + +#endif /* CYCFG_NOTICES_H */ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_peripherals.h b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_peripherals.h new file mode 100644 index 00000000000..2d054313c1c --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_peripherals.h @@ -0,0 +1,42 @@ +/******************************************************************************* + * File Name: cycfg_peripherals.h + * + * Description: + * Peripheral Hardware Block configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.50.0 + * device-db 4.22.0.7873 + * mtb-pdl-cat1 3.15.0.40227 + * + ******************************************************************************* + * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#if !defined(CYCFG_PERIPHERALS_H) +#define CYCFG_PERIPHERALS_H + +#include "cycfg_notices.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* defined(__cplusplus) */ + +#if defined(__cplusplus) +} +#endif /* defined(__cplusplus) */ + +#endif /* CYCFG_PERIPHERALS_H */ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_pins.c b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_pins.c new file mode 100644 index 00000000000..3fd803e5cb9 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_pins.c @@ -0,0 +1,249 @@ +/******************************************************************************* + * File Name: cycfg_pins.c + * + * Description: + * Pin configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.50.0 + * device-db 4.22.0.7873 + * mtb-pdl-cat1 3.15.0.40227 + * + ******************************************************************************* + * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#include "cycfg_pins.h" + +const cy_stc_smartio_config_t ioss_0_port_14_smartio_0_config = +{ + .clkSrc = CY_SMARTIO_CLK_ASYNC, + .bypassMask = CY_SMARTIO_CHANNEL0|CY_SMARTIO_CHANNEL1|0u|0u|CY_SMARTIO_CHANNEL4|CY_SMARTIO_CHANNEL5|0u|0u, + .ioSyncEn = 0u|0u|0u|0u|0u|0u|0u|0u, + .chipSyncEn = 0u|0u|0u|0u|0u|0u|0u|0u, + .lutCfg0 = NULL, + .lutCfg1 = NULL, + .lutCfg2 = NULL, + .lutCfg3 = NULL, + .lutCfg4 = NULL, + .lutCfg5 = NULL, + .lutCfg6 = NULL, + .lutCfg7 = NULL, + .duCfg = NULL, + .hldOvr = false, +}; +const cy_stc_gpio_pin_config_t M2B_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = M2B_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; + +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +const cyhal_resource_inst_t M2B_obj = +{ + .type = CYHAL_RSC_GPIO, + .block_num = M2B_PORT_NUM, + .channel_num = M2B_PIN, +}; +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ + +const cy_stc_gpio_pin_config_t M2A_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = M2A_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; + +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +const cyhal_resource_inst_t M2A_obj = +{ + .type = CYHAL_RSC_GPIO, + .block_num = M2A_PORT_NUM, + .channel_num = M2A_PIN, +}; +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ + +const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_ECO_IN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; + +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +const cyhal_resource_inst_t CYBSP_ECO_IN_obj = +{ + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_ECO_IN_PORT_NUM, + .channel_num = CYBSP_ECO_IN_PIN, +}; +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ + +const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_ECO_OUT_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; + +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +const cyhal_resource_inst_t CYBSP_ECO_OUT_obj = +{ + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_ECO_OUT_PORT_NUM, + .channel_num = CYBSP_ECO_OUT_PIN, +}; +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ + +const cy_stc_gpio_pin_config_t CYBSP_SWO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_SWO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; + +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +const cyhal_resource_inst_t CYBSP_SWO_obj = +{ + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SWO_PORT_NUM, + .channel_num = CYBSP_SWO_PIN, +}; +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ + +const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLDOWN, + .hsiom = CYBSP_SWDCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; + +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +const cyhal_resource_inst_t CYBSP_SWDCK_obj = +{ + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SWDCK_PORT_NUM, + .channel_num = CYBSP_SWDCK_PIN, +}; +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ + +const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = CYBSP_SWDIO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; + +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +const cyhal_resource_inst_t CYBSP_SWDIO_obj = +{ + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SWDIO_PORT_NUM, + .channel_num = CYBSP_SWDIO_PIN, +}; +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ + +void init_cycfg_pins(void) +{ + Cy_GPIO_Pin_Init(M2B_PORT, M2B_PIN, &M2B_config); + Cy_GPIO_Pin_Init(M2A_PORT, M2A_PIN, &M2A_config); + Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); + Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); + Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); +} +void reserve_cycfg_pins(void) +{ +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&M2B_obj); + cyhal_hwmgr_reserve(&M2A_obj); + cyhal_hwmgr_reserve(&CYBSP_ECO_IN_obj); + cyhal_hwmgr_reserve(&CYBSP_ECO_OUT_obj); + cyhal_hwmgr_reserve(&CYBSP_SWO_obj); + cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); + cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); +#endif /* defined (CY_USING_HAL) */ +} diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_pins.h b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_pins.h new file mode 100644 index 00000000000..84989809d40 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_pins.h @@ -0,0 +1,324 @@ +/******************************************************************************* + * File Name: cycfg_pins.h + * + * Description: + * Pin configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.50.0 + * device-db 4.22.0.7873 + * mtb-pdl-cat1 3.15.0.40227 + * + ******************************************************************************* + * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#if !defined(CYCFG_PINS_H) +#define CYCFG_PINS_H + +#include "cycfg_notices.h" +#include "cy_smartio.h" +#include "cy_gpio.h" +#include "cycfg_routing.h" + +#if defined (CY_USING_HAL) +#include "cyhal_hwmgr.h" +#endif /* defined (CY_USING_HAL) */ + +#if defined (CY_USING_HAL_LITE) +#include "cyhal_hw_types.h" +#endif /* defined (CY_USING_HAL_LITE) */ + +#if defined(__cplusplus) +extern "C" { +#endif /* defined(__cplusplus) */ + +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +#define CYBSP_D2 (P0_0) +#define CYBSP_S2G1_INT CYBSP_D2 +#define CYBSP_S2G2_INT CYBSP_D2 +#define CYBSP_D3 (P0_1) +#define CYBSP_I2C_SCL (P0_2) +#define CYBSP_S2G1_I2C_SCL CYBSP_I2C_SCL +#define CYBSP_MIKROBUS_I2C_SCL CYBSP_I2C_SCL +#define CYBSP_S2G2_I2C_SCL CYBSP_I2C_SCL +#define CYBSP_I2C_SDA (P0_3) +#define CYBSP_S2G1_I2C_SDA CYBSP_I2C_SDA +#define CYBSP_MIKROBUS_I2C_SDA CYBSP_I2C_SDA +#define CYBSP_S2G2_I2C_SDA CYBSP_I2C_SDA +#define CYBSP_DEBUG_UART_RX (P10_0) +#define CYBSP_DEBUG_UART_TX (P10_1) +#define CYBSP_A1 (P11_0) +#define CYBSP_S2G1_GPIO1 CYBSP_A1 +#define CYBSP_S2G2_GPIO1 CYBSP_A1 +#define CYBSP_A2 (P11_1) +#define CYBSP_MIKROBUS_INT CYBSP_A2 +#define CYBSP_A3 (P11_2) +#define CYBSP_MIKROBUS_UART_RX (P12_0) +#define CYBSP_MIKROBUS_UART_TX (P12_1) +#define CYBSP_D9 (P12_2) +#define CYBSP_D8 (P12_3) +#define CYBSP_SPI_MISO (P13_0) +#define CYBSP_S2G1_SPI_MISO CYBSP_SPI_MISO +#define CYBSP_MIKROBUS_SPI_MISO CYBSP_SPI_MISO +#define CYBSP_S2G2_SPI_MISO CYBSP_SPI_MISO +#define CYBSP_SPI_MOSI (P13_1) +#define CYBSP_S2G1_SPI_MOSI CYBSP_SPI_MOSI +#define CYBSP_MIKROBUS_SPI_MOSI CYBSP_SPI_MOSI +#define CYBSP_S2G2_SPI_MOSI CYBSP_SPI_MOSI +#define CYBSP_SPI_CLK (P13_2) +#define CYBSP_S2G1_SPI_SCK CYBSP_SPI_CLK +#define CYBSP_MIKROBUS_SPI_SCK CYBSP_SPI_CLK +#define CYBSP_S2G2_SPI_SCK CYBSP_SPI_CLK +#define CYBSP_SPI_CS (P13_3) +#define CYBSP_MIKROBUS_SPI_CS (P13_4) +#define CYBSP_S2G2_SPI_CS (P13_5) +#define CYBSP_S2G1_SPI_CS (P13_6) +#define CYBSP_A4 (P13_7) +#define CYBSP_S2G1_UART_RX (P14_0) +#define CYBSP_S2G2_UART_RX CYBSP_S2G1_UART_RX +#define CYBSP_S2G1_UART_TX (P14_1) +#define CYBSP_S2G2_UART_TX CYBSP_S2G1_UART_TX +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ + +#define ioss_0_port_14_smartio_0_ENABLED 1U +#define ioss_0_port_14_smartio_0_HW SMARTIO_PRT14 + +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +#define CYBSP_ETH_REF_CLK (P18_0) +#define CYBSP_ETH_TX_CTL (P18_1) +#define CYBSP_MIKROBUS_AN (P18_2) +#define CYBSP_ETH_TXD_0 (P18_4) +#define CYBSP_ETH_TXD_1 (P18_5) +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ +#define M2B_ENABLED 1U +#define M2B_PORT GPIO_PRT18 +#define M2B_PORT_NUM 18U +#define M2B_PIN 6U +#define M2B_NUM 6U +#define M2B_DRIVEMODE CY_GPIO_DM_HIGHZ +#define M2B_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_18_pin_6_HSIOM + #define ioss_0_port_18_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define M2B_HSIOM ioss_0_port_18_pin_6_HSIOM +#define M2B_IRQ ioss_interrupts_gpio_dpslp_18_IRQn + +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +#define M2B_HAL_PORT_PIN P18_6 +#define M2B P18_6 +#define M2B_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#define M2B_HAL_DIR CYHAL_GPIO_DIR_INPUT +#define M2B_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ +#define M2A_ENABLED 1U +#define M2A_PORT GPIO_PRT18 +#define M2A_PORT_NUM 18U +#define M2A_PIN 7U +#define M2A_NUM 7U +#define M2A_DRIVEMODE CY_GPIO_DM_HIGHZ +#define M2A_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_18_pin_7_HSIOM + #define ioss_0_port_18_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define M2A_HSIOM ioss_0_port_18_pin_7_HSIOM +#define M2A_IRQ ioss_interrupts_gpio_dpslp_18_IRQn + +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +#define M2A_HAL_PORT_PIN P18_7 +#define M2A P18_7 +#define M2A_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#define M2A_HAL_DIR CYHAL_GPIO_DIR_INPUT +#define M2A_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE +#define UART_RX (P19_0) +#define UART_TX (P19_1) +#define CYBSP_MIKROBUS_PWM (P19_3) +#define CYBSP_WCO_IN (P21_0) +#define CYBSP_WCO_OUT (P21_1) +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ +#define CYBSP_ECO_IN_ENABLED 1U +#define CYBSP_ECO_IN_PORT GPIO_PRT21 +#define CYBSP_ECO_IN_PORT_NUM 21U +#define CYBSP_ECO_IN_PIN 2U +#define CYBSP_ECO_IN_NUM 2U +#define CYBSP_ECO_IN_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_ECO_IN_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_21_pin_2_HSIOM + #define ioss_0_port_21_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_ECO_IN_HSIOM ioss_0_port_21_pin_2_HSIOM +#define CYBSP_ECO_IN_IRQ ioss_interrupts_gpio_dpslp_21_IRQn + +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +#define CYBSP_ECO_IN_HAL_PORT_PIN P21_2 +#define CYBSP_ECO_IN P21_2 +#define CYBSP_ECO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#define CYBSP_ECO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT +#define CYBSP_ECO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ +#define CYBSP_ECO_OUT_ENABLED 1U +#define CYBSP_ECO_OUT_PORT GPIO_PRT21 +#define CYBSP_ECO_OUT_PORT_NUM 21U +#define CYBSP_ECO_OUT_PIN 3U +#define CYBSP_ECO_OUT_NUM 3U +#define CYBSP_ECO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_ECO_OUT_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_21_pin_3_HSIOM + #define ioss_0_port_21_pin_3_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_ECO_OUT_HSIOM ioss_0_port_21_pin_3_HSIOM +#define CYBSP_ECO_OUT_IRQ ioss_interrupts_gpio_dpslp_21_IRQn +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +#define CYBSP_ECO_OUT_HAL_PORT_PIN P21_3 +#define CYBSP_ECO_OUT P21_3 +#define CYBSP_ECO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#define CYBSP_ECO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT +#define CYBSP_ECO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#define CYBSP_ETH_RX_CTL (P21_5) +#define CYBSP_S2G1_PWM (P23_3) +#define CYBSP_S2G2_PWM CYBSP_S2G1_PWM +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ +#define CYBSP_SWO_ENABLED 1U +#define CYBSP_SWO_PORT GPIO_PRT23 +#define CYBSP_SWO_PORT_NUM 23U +#define CYBSP_SWO_PIN 4U +#define CYBSP_SWO_NUM 4U +#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_SWO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_23_pin_4_HSIOM + #define ioss_0_port_23_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWO_HSIOM ioss_0_port_23_pin_4_HSIOM +#define CYBSP_SWO_IRQ ioss_interrupts_gpio_dpslp_23_IRQn +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +#define CYBSP_SWO_HAL_PORT_PIN P23_4 +#define CYBSP_SWO P23_4 +#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT +#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ +#define CYBSP_SWDCK_ENABLED 1U +#define CYBSP_SWDCK_PORT GPIO_PRT23 +#define CYBSP_SWDCK_PORT_NUM 23U +#define CYBSP_SWDCK_PIN 5U +#define CYBSP_SWDCK_NUM 5U +#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN +#define CYBSP_SWDCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_23_pin_5_HSIOM + #define ioss_0_port_23_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWDCK_HSIOM ioss_0_port_23_pin_5_HSIOM +#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_dpslp_23_IRQn +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +#define CYBSP_SWDCK_HAL_PORT_PIN P23_5 +#define CYBSP_SWDCK P23_5 +#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ +#define CYBSP_SWDIO_ENABLED 1U +#define CYBSP_SWDIO_PORT GPIO_PRT23 +#define CYBSP_SWDIO_PORT_NUM 23U +#define CYBSP_SWDIO_PIN 6U +#define CYBSP_SWDIO_NUM 6U +#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP +#define CYBSP_SWDIO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_23_pin_6_HSIOM + #define ioss_0_port_23_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWDIO_HSIOM ioss_0_port_23_pin_6_HSIOM +#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_dpslp_23_IRQn +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +#define CYBSP_SWDIO_HAL_PORT_PIN P23_6 +#define CYBSP_SWDIO P23_6 +#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP +#define CYBSP_ETH_RX_ERR (P2_2) +#define CYBSP_ETH_MDIO (P3_0) +#define CYBSP_ETH_MDC (P3_1) +#define CYBSP_USER_LED2 (P5_1) +#define LED2 CYBSP_USER_LED2 +#define CYBSP_CANFD_STB (P5_2) +#define CYBSP_USER_BTN1 (P5_3) +#define CYBSP_USER_BTN CYBSP_USER_BTN1 +#define CYBSP_POT (P6_0) +#define CYBSP_D4 (P6_1) +#define CYBSP_QSPI_SCK (P6_3) +#define CYBSP_FLASH_RST (P6_4) +#define CYBSP_QSPI_SS (P7_0) +#define CYBSP_QSPI_D0 (P7_1) +#define CYBSP_QSPI_D1 (P7_2) +#define CYBSP_QSPI_D2 (P7_3) +#define CYBSP_QSPI_D3 (P7_4) +#define CYBSP_USER_BUZZER (P7_5) +#define CYBSP_CAN_TX (P8_0) +#define CYBSP_CAN_RX (P8_1) +#define M1B (P8_2) +#define M1A (P8_3) +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ + +extern const cy_stc_smartio_config_t ioss_0_port_14_smartio_0_config; +extern const cy_stc_gpio_pin_config_t M2B_config; + +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +extern const cyhal_resource_inst_t M2B_obj; +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ + +extern const cy_stc_gpio_pin_config_t M2A_config; + +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +extern const cyhal_resource_inst_t M2A_obj; +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ + +extern const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config; + +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +extern const cyhal_resource_inst_t CYBSP_ECO_IN_obj; +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ + +extern const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config; + +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +extern const cyhal_resource_inst_t CYBSP_ECO_OUT_obj; +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ + +extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; + +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +extern const cyhal_resource_inst_t CYBSP_SWO_obj; +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ + +extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config; + +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +extern const cyhal_resource_inst_t CYBSP_SWDCK_obj; +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ + +extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config; + +#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE) +extern const cyhal_resource_inst_t CYBSP_SWDIO_obj; +#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */ + +void init_cycfg_pins(void); +void reserve_cycfg_pins(void); + +#if defined(__cplusplus) +} +#endif /* defined(__cplusplus) */ + +#endif /* CYCFG_PINS_H */ \ No newline at end of file diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_qspi_memslot.c b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_qspi_memslot.c new file mode 100644 index 00000000000..a8d63c73423 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_qspi_memslot.c @@ -0,0 +1,484 @@ +/******************************************************************************* + * File Name: cycfg_qspi_memslot.c + * + * Description: + * Provides definitions of the SMIF-driver memory configuration. + * This file was automatically generated and should not be modified. + * QSPI Configurator 4.50.0.2481 + * + ******************************************************************************* + * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#include "cycfg_qspi_memslot.h" + +cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_readCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0xECU, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_QUAD, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0x01U, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_QUAD, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 8U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_QUAD, +#if (CY_IP_MXSMIF_VERSION >= 2) + /* The Data rate of data */ + .dataRate = CY_SMIF_SDR, + /* This specifies the presence of the dummy field */ + .dummyCyclesPresence = CY_SMIF_PRESENT_1BYTE, + /* This specifies the presence of the mode field */ + .modePresence = CY_SMIF_PRESENT_1BYTE, + /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */ + .modeH = 0x00, + /* The Data rate of mode */ + .modeRate = CY_SMIF_SDR, + /* The Data rate of address */ + .addrRate = CY_SMIF_SDR, + /* This specifies the width of the command field */ + .cmdPresence = CY_SMIF_PRESENT_1BYTE, + /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */ + .commandH = 0x00, + /* The Data rate of command */ + .cmdRate = CY_SMIF_SDR, +#endif /* CY_IP_MXSMIF_VERSION */ +}; + +cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_writeEnCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x06U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE, +#if (CY_IP_MXSMIF_VERSION >= 2) + /* The Data rate of data */ + .dataRate = CY_SMIF_SDR, + /* This specifies the presence of the dummy field */ + .dummyCyclesPresence = CY_SMIF_NOT_PRESENT, + /* This specifies the presence of the mode field */ + .modePresence = CY_SMIF_NOT_PRESENT, + /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */ + .modeH = 0x00, + /* The Data rate of mode */ + .modeRate = CY_SMIF_SDR, + /* The Data rate of address */ + .addrRate = CY_SMIF_SDR, + /* This specifies the width of the command field */ + .cmdPresence = CY_SMIF_PRESENT_1BYTE, + /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */ + .commandH = 0x00, + /* The Data rate of command */ + .cmdRate = CY_SMIF_SDR, +#endif /* CY_IP_MXSMIF_VERSION */ +}; + +cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_writeDisCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x04U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE, +#if (CY_IP_MXSMIF_VERSION >= 2) + /* The Data rate of data */ + .dataRate = CY_SMIF_SDR, + /* This specifies the presence of the dummy field */ + .dummyCyclesPresence = CY_SMIF_NOT_PRESENT, + /* This specifies the presence of the mode field */ + .modePresence = CY_SMIF_NOT_PRESENT, + /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */ + .modeH = 0x00, + /* The Data rate of mode */ + .modeRate = CY_SMIF_SDR, + /* The Data rate of address */ + .addrRate = CY_SMIF_SDR, + /* This specifies the width of the command field */ + .cmdPresence = CY_SMIF_PRESENT_1BYTE, + /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */ + .commandH = 0x00, + /* The Data rate of command */ + .cmdRate = CY_SMIF_SDR, +#endif /* CY_IP_MXSMIF_VERSION */ +}; + +cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_eraseCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0xDCU, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE, +#if (CY_IP_MXSMIF_VERSION >= 2) + /* The Data rate of data */ + .dataRate = CY_SMIF_SDR, + /* This specifies the presence of the dummy field */ + .dummyCyclesPresence = CY_SMIF_NOT_PRESENT, + /* This specifies the presence of the mode field */ + .modePresence = CY_SMIF_NOT_PRESENT, + /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */ + .modeH = 0x00, + /* The Data rate of mode */ + .modeRate = CY_SMIF_SDR, + /* The Data rate of address */ + .addrRate = CY_SMIF_SDR, + /* This specifies the width of the command field */ + .cmdPresence = CY_SMIF_PRESENT_1BYTE, + /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */ + .commandH = 0x00, + /* The Data rate of command */ + .cmdRate = CY_SMIF_SDR, +#endif /* CY_IP_MXSMIF_VERSION */ +}; + +cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_chipEraseCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x60U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE, +#if (CY_IP_MXSMIF_VERSION >= 2) + /* The Data rate of data */ + .dataRate = CY_SMIF_SDR, + /* This specifies the presence of the dummy field */ + .dummyCyclesPresence = CY_SMIF_NOT_PRESENT, + /* This specifies the presence of the mode field */ + .modePresence = CY_SMIF_NOT_PRESENT, + /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */ + .modeH = 0x00, + /* The Data rate of mode */ + .modeRate = CY_SMIF_SDR, + /* The Data rate of address */ + .addrRate = CY_SMIF_SDR, + /* This specifies the width of the command field */ + .cmdPresence = CY_SMIF_PRESENT_1BYTE, + /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */ + .commandH = 0x00, + /* The Data rate of command */ + .cmdRate = CY_SMIF_SDR, +#endif /* CY_IP_MXSMIF_VERSION */ +}; + +cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_programCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x12U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE, +#if (CY_IP_MXSMIF_VERSION >= 2) + /* The Data rate of data */ + .dataRate = CY_SMIF_SDR, + /* This specifies the presence of the dummy field */ + .dummyCyclesPresence = CY_SMIF_NOT_PRESENT, + /* This specifies the presence of the mode field */ + .modePresence = CY_SMIF_NOT_PRESENT, + /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */ + .modeH = 0x00, + /* The Data rate of mode */ + .modeRate = CY_SMIF_SDR, + /* The Data rate of address */ + .addrRate = CY_SMIF_SDR, + /* This specifies the width of the command field */ + .cmdPresence = CY_SMIF_PRESENT_1BYTE, + /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */ + .commandH = 0x00, + /* The Data rate of command */ + .cmdRate = CY_SMIF_SDR, +#endif /* CY_IP_MXSMIF_VERSION */ +}; + +cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_readStsRegQeCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x35U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE, +#if (CY_IP_MXSMIF_VERSION >= 2) + /* The Data rate of data */ + .dataRate = CY_SMIF_SDR, + /* This specifies the presence of the dummy field */ + .dummyCyclesPresence = CY_SMIF_NOT_PRESENT, + /* This specifies the presence of the mode field */ + .modePresence = CY_SMIF_NOT_PRESENT, + /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */ + .modeH = 0x00, + /* The Data rate of mode */ + .modeRate = CY_SMIF_SDR, + /* The Data rate of address */ + .addrRate = CY_SMIF_SDR, + /* This specifies the width of the command field */ + .cmdPresence = CY_SMIF_PRESENT_1BYTE, + /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */ + .commandH = 0x00, + /* The Data rate of command */ + .cmdRate = CY_SMIF_SDR, +#endif /* CY_IP_MXSMIF_VERSION */ +}; + +cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_readStsRegWipCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x05U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE, +#if (CY_IP_MXSMIF_VERSION >= 2) + /* The Data rate of data */ + .dataRate = CY_SMIF_SDR, + /* This specifies the presence of the dummy field */ + .dummyCyclesPresence = CY_SMIF_NOT_PRESENT, + /* This specifies the presence of the mode field */ + .modePresence = CY_SMIF_NOT_PRESENT, + /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */ + .modeH = 0x00, + /* The Data rate of mode */ + .modeRate = CY_SMIF_SDR, + /* The Data rate of address */ + .addrRate = CY_SMIF_SDR, + /* This specifies the width of the command field */ + .cmdPresence = CY_SMIF_PRESENT_1BYTE, + /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */ + .commandH = 0x00, + /* The Data rate of command */ + .cmdRate = CY_SMIF_SDR, +#endif /* CY_IP_MXSMIF_VERSION */ +}; + +cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_writeStsRegQeCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x01U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE, +#if (CY_IP_MXSMIF_VERSION >= 2) + /* The Data rate of data */ + .dataRate = CY_SMIF_SDR, + /* This specifies the presence of the dummy field */ + .dummyCyclesPresence = CY_SMIF_NOT_PRESENT, + /* This specifies the presence of the mode field */ + .modePresence = CY_SMIF_NOT_PRESENT, + /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */ + .modeH = 0x00, + /* The Data rate of mode */ + .modeRate = CY_SMIF_SDR, + /* The Data rate of address */ + .addrRate = CY_SMIF_SDR, + /* This specifies the width of the command field */ + .cmdPresence = CY_SMIF_PRESENT_1BYTE, + /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */ + .commandH = 0x00, + /* The Data rate of command */ + .cmdRate = CY_SMIF_SDR, +#endif /* CY_IP_MXSMIF_VERSION */ +}; + +cy_stc_smif_mem_device_cfg_t deviceCfg_S25HL512T_SlaveSlot_1 = +{ + /* Specifies the number of address bytes used by the memory slave device. */ + .numOfAddrBytes = 0x04U, + /* The size of the memory. */ + .memSize = 0x04000000U, + /* Specifies the Read command. */ + .readCmd = &S25HL512T_SlaveSlot_1_readCmd, + /* Specifies the Write Enable command. */ + .writeEnCmd = &S25HL512T_SlaveSlot_1_writeEnCmd, + /* Specifies the Write Disable command. */ + .writeDisCmd = &S25HL512T_SlaveSlot_1_writeDisCmd, + /* Specifies the Erase command. */ + .eraseCmd = &S25HL512T_SlaveSlot_1_eraseCmd, + /* Specifies the sector size of each erase. */ + .eraseSize = 0x0040000U, + /* Specifies the Chip Erase command. */ + .chipEraseCmd = &S25HL512T_SlaveSlot_1_chipEraseCmd, + /* Specifies the Program command. */ + .programCmd = &S25HL512T_SlaveSlot_1_programCmd, + /* Specifies the page size for programming. */ + .programSize = 0x0000100U, + /* Specifies the command to read the QE-containing status register. */ + .readStsRegQeCmd = &S25HL512T_SlaveSlot_1_readStsRegQeCmd, + /* Specifies the command to read the WIP-containing status register. */ + .readStsRegWipCmd = &S25HL512T_SlaveSlot_1_readStsRegWipCmd, + /* Specifies the command to write into the QE-containing status register. */ + .writeStsRegQeCmd = &S25HL512T_SlaveSlot_1_writeStsRegQeCmd, + /* The mask for the status register. */ + .stsRegBusyMask = 0x01U, + /* The mask for the status register. */ + .stsRegQuadEnableMask = 0x02U, + /* The max time for the erase type-1 cycle-time in ms. */ + .eraseTime = 5869U, + /* The max time for the chip-erase cycle-time in ms. */ + .chipEraseTime = 696000U, + /* The max time for the page-program cycle-time in us. */ + .programTime = 2175U, +#if (CY_SMIF_DRV_VERSION_MAJOR > 1) || (CY_SMIF_DRV_VERSION_MINOR >= 50) + /* Points to NULL or to structure with info about sectors for hybrid memory. */ + .hybridRegionCount = 0U, + .hybridRegionInfo = 0, +#endif + /* Specifies the command to read variable latency cycles configuration register */ + .readLatencyCmd = 0, + /* Specifies the command to write variable latency cycles configuration register */ + .writeLatencyCmd = 0, + /* Specifies the address for variable latency cycle address */ + .latencyCyclesRegAddr = 0x00U, + /* Specifies variable latency cycles Mask */ + .latencyCyclesMask = 0x00U, +#if (CY_IP_MXSMIF_VERSION >= 2) + /* Specifies data for memory with hybrid sectors */ + .octalDDREnableSeq = 0, + /* Specifies the command to read the OE-containing status register. */ + .readStsRegOeCmd = 0, + /* Specifies the command to write the OE-containing status register. */ + .writeStsRegOeCmd = 0, + /* QE mask for the status registers */ + .stsRegOctalEnableMask = 0x00U, + /* Octal enable register address */ + .octalEnableRegAddr = 0x00U, + /* Frequency of operation used in Octal mode */ + .freq_of_operation = CY_SMIF_100MHZ_OPERATION, +#endif +}; + +cy_stc_smif_mem_config_t S25HL512T_SlaveSlot_1 = +{ + /* Determines the slot number where the memory device is placed. */ + .slaveSelect = CY_SMIF_SLAVE_SELECT_1, + /* Flags. */ +#if (CY_IP_MXSMIF_VERSION >= 2) + .flags = CY_SMIF_FLAG_SMIF_REV_3 | CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN, +#else + .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN, +#endif /* CY_IP_MXSMIF_VERSION */ + /* The data-line selection options for a slave device. */ + .dataSelect = CY_SMIF_DATA_SEL0, + /* The base address the memory slave is mapped to in the PSoC memory map. + Valid when the memory-mapped mode is enabled. */ + .baseAddress = 0x60000000U, + /* The size allocated in the PSoC memory map, for the memory slave device. + The size is allocated from the base address. Valid when the memory mapped mode is enabled. */ + .memMappedSize = 0x10000U, + /* If this memory device is one of the devices in the dual quad SPI configuration. + Valid when the memory mapped mode is enabled. */ + .dualQuadSlots = 0, + /* The configuration of the device. */ + .deviceCfg = &deviceCfg_S25HL512T_SlaveSlot_1, +#if (CY_IP_MXSMIF_VERSION >= 2) + /** Continous transfer merge timeout. + * After this period the memory device is deselected. A later transfer, even from a + * continuous address, starts with the overhead phases (command, address, mode, dummy cycles). + * This configuration parameter is available for CAT1B devices. */ + .mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE, +#endif /* CY_IP_MXSMIF_VERSION */ +}; + +cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM] = { + &S25HL512T_SlaveSlot_1, +}; + +cy_stc_smif_block_config_t smifBlockConfig = +{ + /* The number of SMIF memories defined. */ + .memCount = CY_SMIF_DEVICE_NUM, + /* The pointer to the array of memory config structures of size memCount. */ + .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs, + /* The version of the SMIF driver. */ + .majorVersion = CY_SMIF_DRV_VERSION_MAJOR, + /* The version of the SMIF driver. */ + .minorVersion = CY_SMIF_DRV_VERSION_MINOR, +}; diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_qspi_memslot.h b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_qspi_memslot.h new file mode 100644 index 00000000000..8ee42ae4d53 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_qspi_memslot.h @@ -0,0 +1,69 @@ +/******************************************************************************* + * File Name: cycfg_qspi_memslot.h + * + * Description: + * Provides declarations of the SMIF-driver memory configuration. + * This file was automatically generated and should not be modified. + * QSPI Configurator 4.50.0.2481 + * + ******************************************************************************* + * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#ifndef CYCFG_QSPI_MEMSLOT_H +#define CYCFG_QSPI_MEMSLOT_H +#include "cy_smif_memslot.h" + +#define CY_SMIF_CFG_TOOL_VERSION (450) + +/* Supported QSPI Driver version */ +#define CY_SMIF_DRV_VERSION_REQUIRED (100) + +#if !defined(CY_SMIF_DRV_VERSION) + #define CY_SMIF_DRV_VERSION (100) +#endif + +/* Check the used Driver version */ +#if (CY_SMIF_DRV_VERSION_REQUIRED > CY_SMIF_DRV_VERSION) + #error The QSPI Configurator requires a newer version of the PDL. Update the PDL in your project. +#endif + +typedef cy_stc_smif_mem_config_t cy_serial_flash_mem_config_t; +typedef cy_stc_smif_block_config_t cy_serial_flash_block_config_t; + +#define CY_SMIF_DEVICE_NUM 1 + +extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_readCmd; +extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_writeEnCmd; +extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_writeDisCmd; +extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_eraseCmd; +extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_chipEraseCmd; +extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_programCmd; +extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_readStsRegQeCmd; +extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_readStsRegWipCmd; +extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_writeStsRegQeCmd; + +extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25HL512T_SlaveSlot_1; + +extern cy_stc_smif_mem_config_t S25HL512T_SlaveSlot_1; + +extern cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM]; + +extern cy_stc_smif_block_config_t smifBlockConfig; + + +#endif /*CYCFG_QSPI_MEMSLOT_H*/ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_qspi_memslot.timestamp b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_qspi_memslot.timestamp new file mode 100644 index 00000000000..1716d358a77 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_qspi_memslot.timestamp @@ -0,0 +1,25 @@ +/******************************************************************************* + * File Name: cycfg_qspi_memslot.timestamp + * + * Description: + * Sentinel file for determining if generated source is up to date. + * This file was automatically generated and should not be modified. + * QSPI Configurator 4.50.0.2481 + * + ******************************************************************************* + * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_routing.h b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_routing.h new file mode 100644 index 00000000000..d604facd0f9 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_routing.h @@ -0,0 +1,50 @@ +/******************************************************************************* + * File Name: cycfg_routing.h + * + * Description: + * Establishes all necessary connections between hardware elements. + * This file was automatically generated and should not be modified. + * Configurator Backend 3.50.0 + * device-db 4.22.0.7873 + * mtb-pdl-cat1 3.15.0.40227 + * + ******************************************************************************* + * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#if !defined(CYCFG_ROUTING_H) +#define CYCFG_ROUTING_H + +#include "cycfg_notices.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* defined(__cplusplus) */ + +#define ioss_0_port_21_pin_2_ANALOG P21_2_SRSS_ECO_IN +#define ioss_0_port_21_pin_3_ANALOG P21_3_SRSS_ECO_OUT +#define ioss_0_port_23_pin_4_HSIOM P23_4_CPUSS_SWJ_SWO_TDO +#define ioss_0_port_23_pin_5_HSIOM P23_5_CPUSS_SWJ_SWCLK_TCLK +#define ioss_0_port_23_pin_6_HSIOM P23_6_CPUSS_SWJ_SWDIO_TMS + +static inline void init_cycfg_routing(void) {} + +#if defined(__cplusplus) +} +#endif /* defined(__cplusplus) */ + +#endif /* CYCFG_ROUTING_H */ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_system.c b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_system.c new file mode 100644 index 00000000000..32366ff8cc4 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_system.c @@ -0,0 +1,988 @@ +/******************************************************************************* + * File Name: cycfg_system.c + * + * Description: + * System configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.50.0 + * device-db 4.22.0.7873 + * mtb-pdl-cat1 3.15.0.40227 + * + ******************************************************************************* + * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#include "cycfg_system.h" + +#define CY_CFG_SYSCLK_ECO_ERROR 1 +#define CY_CFG_SYSCLK_ALTHF_ERROR 2 +#define CY_CFG_SYSCLK_PLL_ERROR 3 +#define CY_CFG_SYSCLK_FLL_ERROR 4 +#define CY_CFG_SYSCLK_WCO_ERROR 5 + +#if (CY_CPU_CORTEX_M7) +#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE CY_SYSTICK_CLOCK_SOURCE_CLK_IMO +#define CY_CFG_SYSCLK_CLKALTSYSTICK_INTERVAL 1000 +#define CY_CFG_SYSCLK_CLKALTSYSTICK_FREQUENCY 8000000 +#define CY_CFG_SYSCLK_CLKALTSYSTICK_TICKS ((1000)/1000000.0)*8000000 +#endif /* (CY_CPU_CORTEX_M7) */ + +#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_CLKLF +#define CY_CFG_SYSCLK_ECO_ENABLED 1 +#define CY_CFG_SYSCLK_ECO_FREQ 20000000UL +#define CY_CFG_SYSCLK_ECO_GPIO_IN_PRT GPIO_PRT21 +#define CY_CFG_SYSCLK_ECO_GPIO_IN_PIN 2 +#define CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT GPIO_PRT21 +#define CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN 3 +#define CY_CFG_SYSCLK_ECO_CLOAD 8UL +#define CY_CFG_SYSCLK_ECO_ESR 50UL +#define CY_CFG_SYSCLK_ECO_DRIVE_LEVEL 100UL +#define CY_CFG_SYSCLK_CLKFAST_0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKFAST_0_INT_DIVIDER 0 +#define CY_CFG_SYSCLK_CLKFAST_0_FRAC_DIVIDER 0 +#define CY_CFG_SYSCLK_CLKFAST_1_ENABLED 1 +#define CY_CFG_SYSCLK_CLKFAST_1_INT_DIVIDER 0 +#define CY_CFG_SYSCLK_CLKFAST_1_FRAC_DIVIDER 0 +#define CY_CFG_SYSCLK_FLL_ENABLED 1 +#define CY_CFG_SYSCLK_FLL_MULT 500U +#define CY_CFG_SYSCLK_FLL_REFDIV 50U +#define CY_CFG_SYSCLK_FLL_CCO_RANGE CY_SYSCLK_FLL_CCO_RANGE4 +#define CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV true +#define CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE 2U +#define CY_CFG_SYSCLK_FLL_IGAIN 9U +#define CY_CFG_SYSCLK_FLL_PGAIN 5U +#define CY_CFG_SYSCLK_FLL_SETTLING_COUNT 20U +#define CY_CFG_SYSCLK_FLL_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT +#define CY_CFG_SYSCLK_FLL_CCO_FREQ 355U +#define CY_CFG_SYSCLK_FLL_OUT_FREQ 100000000 +#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE +#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_CLKHF1_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF1_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE +#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 250UL +#define CY_CFG_SYSCLK_CLKHF1_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1 +#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF2_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_2 +#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH4 +#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF3_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_2 +#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH4 +#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF4_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_4 +#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 50UL +#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH4 +#define CY_CFG_SYSCLK_CLKHF5_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF5_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_2 +#define CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ 125UL +#define CY_CFG_SYSCLK_CLKHF5_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH2 +#define CY_CFG_SYSCLK_CLKHF6_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF6_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE +#define CY_CFG_SYSCLK_CLKHF6_FREQ_MHZ 200UL +#define CY_CFG_SYSCLK_CLKHF6_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH4 +#define CY_CFG_SYSCLK_CLKHF7_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF7_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE +#define CY_CFG_SYSCLK_CLKHF7_FREQ_MHZ 0UL +#define CY_CFG_SYSCLK_CLKHF7_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH5 +#define CY_CFG_SYSCLK_ILO0_ENABLED 1 +#define CY_CFG_SYSCLK_ILO0_HIBERNATE true +#define CY_CFG_SYSCLK_ILO1_ENABLED 1 +#define CY_CFG_SYSCLK_ILO1_HIBERNATE true +#define CY_CFG_SYSCLK_IMO_ENABLED 1 +#define CY_CFG_SYSCLK_CLKLF_ENABLED 1 +#define CY_CFG_SYSCLK_CLKMEM_ENABLED 1 +#define CY_CFG_SYSCLK_CLKMEM_DIVIDER 0 +#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_ECO +#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_ECO +#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_ECO +#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_ECO +#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_ECO +#define CY_CFG_SYSCLK_CLKPATH5_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH5_SOURCE CY_SYSCLK_CLKPATH_IN_ILO0 +#define CY_CFG_SYSCLK_CLKPATH6_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH6_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_PLL0_ENABLED 1 +#define CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV 25 +#define CY_CFG_SYSCLK_PLL0_REFERENCE_DIV 1 +#define CY_CFG_SYSCLK_PLL0_OUTPUT_DIV 2 +#define CY_CFG_SYSCLK_PLL0_FRAC_DIV 0 +#define CY_CFG_SYSCLK_PLL0_FRAC_DITHER_EN false +#define CY_CFG_SYSCLK_PLL0_FRAC_EN false +#define CY_CFG_SYSCLK_PLL0_LF_MODE false +#define CY_CFG_SYSCLK_PLL0_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO +#define CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ 250000000 +#define CY_CFG_SYSCLK_PLL1_ENABLED 1 +#define CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV 25 +#define CY_CFG_SYSCLK_PLL1_REFERENCE_DIV 1 +#define CY_CFG_SYSCLK_PLL1_OUTPUT_DIV 2 +#define CY_CFG_SYSCLK_PLL1_FRAC_DIV 0 +#define CY_CFG_SYSCLK_PLL1_FRAC_DITHER_EN false +#define CY_CFG_SYSCLK_PLL1_FRAC_EN false +#define CY_CFG_SYSCLK_PLL1_LF_MODE false +#define CY_CFG_SYSCLK_PLL1_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO +#define CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ 250000000 +#define CY_CFG_SYSCLK_PLL2_ENABLED 1 +#define CY_CFG_SYSCLK_PLL2_FEEDBACK_DIV 48 +#define CY_CFG_SYSCLK_PLL2_REFERENCE_DIV 3 +#define CY_CFG_SYSCLK_PLL2_OUTPUT_DIV 2 +#define CY_CFG_SYSCLK_PLL2_LF_MODE false +#define CY_CFG_SYSCLK_PLL2_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO +#define CY_CFG_SYSCLK_PLL2_OUTPUT_FREQ 160000000 +#define CY_CFG_SYSCLK_PLL3_ENABLED 1 +#define CY_CFG_SYSCLK_PLL3_FEEDBACK_DIV 60 +#define CY_CFG_SYSCLK_PLL3_REFERENCE_DIV 3 +#define CY_CFG_SYSCLK_PLL3_OUTPUT_DIV 2 +#define CY_CFG_SYSCLK_PLL3_LF_MODE false +#define CY_CFG_SYSCLK_PLL3_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO +#define CY_CFG_SYSCLK_PLL3_OUTPUT_FREQ 200000000 +#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 +#define CY_CFG_SYSCLK_CLKSLOW_DIVIDER 0 +#define CY_CFG_PWR_ENABLED 1 +#define CY_CFG_PWR_INIT 1 +#define CY_CFG_PWR_VBACKUP_USING_VDDD 1 +#define CY_CFG_PWR_REGULATOR_MODE_MIN 0 +#define CY_CFG_PWR_USING_ULP 0 + +#if (!defined(CY_DEVICE_SECURE)) +static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = +{ + .fllMult = 500U, + .refDiv = 50U, + .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, + .enableOutputDiv = true, + .lockTolerance = 2U, + .igain = 9U, + .pgain = 5U, + .settlingCount = 20U, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, + .cco_Freq = 355U, +}; +#endif /* (!defined(CY_DEVICE_SECURE)) */ + +#if defined (CY_USING_HAL) +const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = +{ + .type = CYHAL_RSC_CLKPATH, + .block_num = 0U, + .channel_num = 0U, +}; +const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = +{ + .type = CYHAL_RSC_CLKPATH, + .block_num = 1U, + .channel_num = 0U, +}; +const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = +{ + .type = CYHAL_RSC_CLKPATH, + .block_num = 2U, + .channel_num = 0U, +}; +const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = +{ + .type = CYHAL_RSC_CLKPATH, + .block_num = 3U, + .channel_num = 0U, +}; +const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = +{ + .type = CYHAL_RSC_CLKPATH, + .block_num = 4U, + .channel_num = 0U, +}; +const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj = +{ + .type = CYHAL_RSC_CLKPATH, + .block_num = 5U, + .channel_num = 0U, +}; +const cyhal_resource_inst_t srss_0_clock_0_pathmux_6_obj = +{ + .type = CYHAL_RSC_CLKPATH, + .block_num = 6U, + .channel_num = 0U, +}; +#endif /* defined (CY_USING_HAL) */ + +typedef enum +{ + CY_SYSCLK_SSCG_DEPTH_MINUS_0_5 = 0x029u, /**< - 0.5 [%] (down spread) */ + CY_SYSCLK_SSCG_DEPTH_MINUS_1_0 = 0x052u, /**< - 1.0 [%] (down spread) */ + CY_SYSCLK_SSCG_DEPTH_MINUS_2_0 = 0x0A4u, /**< - 2.0 [%] (down spread) */ + CY_SYSCLK_SSCG_DEPTH_MINUS_3_0 = 0x0F6u, /**< - 3.0 [%] (down spread) */ +} cy_en_pll_400M_ssgc_depth_t; + +typedef enum +{ + CY_SYSCLK_SSCG_RATE_DIV_4096 = 0u, /**< Modulation rate = fPFD/4096 */ + CY_SYSCLK_SSCG_RATE_DIV_2048 = 1u, /**< Modulation rate = fPFD/2048 */ + CY_SYSCLK_SSCG_RATE_DIV_1024 = 2u, /**< Modulation rate = fPFD/1024 */ + CY_SYSCLK_SSCG_RATE_DIV_512 = 3u, /**< Modulation rate = fPFD/512 */ + CY_SYSCLK_SSCG_RATE_DIV_256 = 4u, /**< Modulation rate = fPFD/256 */ +} cy_en_pll_400M_ssgc_rate_t; + +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll400m_0_pllConfig = +{ + .feedbackDiv = 25, + .referenceDiv = 1, + .outputDiv = 2, + .lfMode = false, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, + .fracDiv = 0, + .fracDitherEn = false, + .fracEn = false, + .sscgEn = false, + .sscgRate = CY_SYSCLK_SSCG_RATE_DIV_4096, + .sscgDepth = CY_SYSCLK_SSCG_DEPTH_MINUS_0_5, +}; +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll400m_1_pllConfig = +{ + .feedbackDiv = 25, + .referenceDiv = 1, + .outputDiv = 2, + .lfMode = false, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, + .fracDiv = 0, + .fracDitherEn = false, + .fracEn = false, + .sscgEn = false, + .sscgRate = CY_SYSCLK_SSCG_RATE_DIV_4096, + .sscgDepth = CY_SYSCLK_SSCG_DEPTH_MINUS_0_5, +}; + +#if (!defined(CY_DEVICE_SECURE)) +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = +{ + .feedbackDiv = 48, + .referenceDiv = 3, + .outputDiv = 2, + .lfMode = false, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, +}; +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig = +{ + .feedbackDiv = 60, + .referenceDiv = 3, + .outputDiv = 2, + .lfMode = false, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, +}; +#endif /* (!defined(CY_DEVICE_SECURE)) */ + +__WEAK void cycfg_ClockStartupError(uint32_t error); + +#if !defined (CY_CFG_SYSCLK_ILO0_ENABLED) +__STATIC_INLINE void Cy_SysClk_Ilo0DeInit(void); +#endif /* !defined (CY_CFG_SYSCLK_ILO0_ENABLED) */ + +#if !defined (CY_CFG_SYSCLK_ILO1_ENABLED) +__STATIC_INLINE void Cy_SysClk_Ilo1DeInit(void); +#endif /* !defined (CY_CFG_SYSCLK_ILO1_ENABLED) */ + +#if ((!defined(CY_DEVICE_SECURE))) +__STATIC_INLINE void Cy_SysClk_FllDeInit(void); +#endif /* ((!defined(CY_DEVICE_SECURE))) */ + +#if (CY_CPU_CORTEX_M7) +__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit(void); +#endif /* (CY_CPU_CORTEX_M7) */ + +#if (!defined(CY_DEVICE_SECURE)) +__STATIC_INLINE void Cy_SysClk_ClkBakInit(void); +__STATIC_INLINE void Cy_SysClk_EcoInit(void); +#endif /* (!defined(CY_DEVICE_SECURE)) */ + +__STATIC_INLINE void Cy_SysClk_ClkFast_0_Init(void); +__STATIC_INLINE void Cy_SysClk_ClkFast_1_Init(void); + +#if (!defined(CY_DEVICE_SECURE)) +__STATIC_INLINE void Cy_SysClk_FllInit(void); +#endif /* (!defined(CY_DEVICE_SECURE)) */ + +__STATIC_INLINE void Cy_SysClk_ClkHf0Init(void); +__STATIC_INLINE void Cy_SysClk_ClkHf1Init(void); +__STATIC_INLINE void Cy_SysClk_ClkHf2Init(void); +__STATIC_INLINE void Cy_SysClk_ClkHf3Init(void); +__STATIC_INLINE void Cy_SysClk_ClkHf4Init(void); +__STATIC_INLINE void Cy_SysClk_ClkHf5Init(void); +__STATIC_INLINE void Cy_SysClk_ClkHf6Init(void); +__STATIC_INLINE void Cy_SysClk_ClkHf7Init(void); + +#if (!defined(CY_DEVICE_SECURE)) +__STATIC_INLINE void Cy_SysClk_Ilo0Init(void); +__STATIC_INLINE void Cy_SysClk_Ilo1Init(void); +#endif /* (!defined(CY_DEVICE_SECURE)) */ + +__STATIC_INLINE void Cy_SysClk_ClkLfInit(void); +__STATIC_INLINE void Cy_SysClk_ClkMemInit(void); + +#if (!defined(CY_DEVICE_SECURE)) +__STATIC_INLINE void Cy_SysClk_ClkPath0Init(void); +__STATIC_INLINE void Cy_SysClk_ClkPath1Init(void); +__STATIC_INLINE void Cy_SysClk_ClkPath2Init(void); +__STATIC_INLINE void Cy_SysClk_ClkPath3Init(void); +__STATIC_INLINE void Cy_SysClk_ClkPath4Init(void); +__STATIC_INLINE void Cy_SysClk_ClkPath5Init(void); +__STATIC_INLINE void Cy_SysClk_ClkPath6Init(void); +__STATIC_INLINE void Cy_SysClk_ClkPeriInit(void); +#endif /* (!defined(CY_DEVICE_SECURE)) */ + +__STATIC_INLINE void Cy_SysClk_Pll0Init(void); +__STATIC_INLINE void Cy_SysClk_Pll1Init(void); +__STATIC_INLINE void Cy_SysClk_Pll2Init(void); +__STATIC_INLINE void Cy_SysClk_Pll3Init(void); + +#if (!defined(CY_DEVICE_SECURE)) +__STATIC_INLINE void Cy_SysClk_ClkSlowInit(void); +#endif /* (!defined(CY_DEVICE_SECURE)) */ + +__STATIC_INLINE void init_cycfg_power(void); + +__WEAK void cycfg_ClockStartupError(uint32_t error) +{ + (void)error; /* Suppress the compiler warning */ + while(1); +} + +#if !defined (CY_CFG_SYSCLK_ILO0_ENABLED) +__STATIC_INLINE void Cy_SysClk_Ilo0DeInit(void) +{ + if(Cy_SysPm_IsBgRefCtrl()) + { + Cy_SysPm_BgRefCtrl(false); + Cy_WDT_Unlock(); + Cy_SysClk_IloSrcDisable(0); + Cy_SysClk_IloSrcHibernateOn(0, false); + Cy_WDT_Lock(); + Cy_SysPm_BgRefCtrl(true); + } + else + { + Cy_WDT_Unlock(); + Cy_SysClk_IloSrcDisable(0); + Cy_SysClk_IloSrcHibernateOn(0, false); + Cy_WDT_Lock(); + } +} +#endif /* !defined (CY_CFG_SYSCLK_ILO0_ENABLED) */ + +#if !defined (CY_CFG_SYSCLK_ILO1_ENABLED) +__STATIC_INLINE void Cy_SysClk_Ilo1DeInit(void) +{ + Cy_SysClk_IloSrcDisable(1); + Cy_SysClk_IloSrcHibernateOn(1, false); +} +#endif /* !defined (CY_CFG_SYSCLK_ILO1_ENABLED) */ + +#if ((!defined(CY_DEVICE_SECURE))) +__STATIC_INLINE void Cy_SysClk_FllDeInit(void) +{ + Cy_SysClk_FllDisable(); +} +#endif /* ((!defined(CY_DEVICE_SECURE))) */ + +#if (CY_CPU_CORTEX_M7) +__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit(void) +{ + Cy_SysTick_Init(CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE, CY_CFG_SYSCLK_CLKALTSYSTICK_TICKS); +} +#endif /* (CY_CPU_CORTEX_M7) */ + +#if (!defined(CY_DEVICE_SECURE)) +__STATIC_INLINE void Cy_SysClk_ClkBakInit(void) +{ + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF); +} +__STATIC_INLINE void Cy_SysClk_EcoInit(void) +{ + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT21, 2, CY_GPIO_DM_ANALOG, 0UL, HSIOM_SEL_GPIO); + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT21, 3, CY_GPIO_DM_ANALOG, 0UL, HSIOM_SEL_GPIO); + if (CY_SYSCLK_BAD_PARAM == Cy_SysClk_EcoConfigure(CY_CFG_SYSCLK_ECO_FREQ, 15UL, 50UL, 100UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_ECO_ERROR); + } + if (CY_SYSCLK_TIMEOUT == Cy_SysClk_EcoEnable(3000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_ECO_ERROR); + } +} +#endif /* (!defined(CY_DEVICE_SECURE)) */ + +__STATIC_INLINE void Cy_SysClk_ClkFast_0_Init(void) +{ + Cy_SysClk_ClkFastSrcSetDivider(0, CY_CFG_SYSCLK_CLKFAST_0_INT_DIVIDER, CY_CFG_SYSCLK_CLKFAST_0_FRAC_DIVIDER); +} +__STATIC_INLINE void Cy_SysClk_ClkFast_1_Init(void) +{ + Cy_SysClk_ClkFastSrcSetDivider(1, CY_CFG_SYSCLK_CLKFAST_1_INT_DIVIDER, CY_CFG_SYSCLK_CLKFAST_1_FRAC_DIVIDER); +} + +#if (!defined(CY_DEVICE_SECURE)) +__STATIC_INLINE void Cy_SysClk_FllInit(void) +{ + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } +} +#endif /* (!defined(CY_DEVICE_SECURE)) */ + +__STATIC_INLINE void Cy_SysClk_ClkHf0Init(void) +{ + Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF0, false); +} +__STATIC_INLINE void Cy_SysClk_ClkHf1Init(void) +{ + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF1, CY_CFG_SYSCLK_CLKHF1_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF1, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF1, false); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF1); +} +__STATIC_INLINE void Cy_SysClk_ClkHf2Init(void) +{ + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2); + Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF2, false); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2); +} +__STATIC_INLINE void Cy_SysClk_ClkHf3Init(void) +{ + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_DIVIDE_BY_2); + Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF3, false); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3); +} +__STATIC_INLINE void Cy_SysClk_ClkHf4Init(void) +{ + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_DIVIDE_BY_4); + Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF4, false); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4); +} +__STATIC_INLINE void Cy_SysClk_ClkHf5Init(void) +{ + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF5, CY_CFG_SYSCLK_CLKHF5_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF5, CY_SYSCLK_CLKHF_DIVIDE_BY_2); + Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF5, false); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF5); +} +__STATIC_INLINE void Cy_SysClk_ClkHf6Init(void) +{ + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF6, CY_CFG_SYSCLK_CLKHF6_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF6, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF6, false); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF6); +} +__STATIC_INLINE void Cy_SysClk_ClkHf7Init(void) +{ + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF7, CY_CFG_SYSCLK_CLKHF7_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF7, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF7, false); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF7); +} + +#if (!defined(CY_DEVICE_SECURE)) +__STATIC_INLINE void Cy_SysClk_Ilo0Init(void) +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_IloSrcEnable(0); + Cy_SysClk_IloSrcHibernateOn(0, true); +} +__STATIC_INLINE void Cy_SysClk_Ilo1Init(void) +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_IloSrcEnable(1); + Cy_SysClk_IloSrcHibernateOn(1, true); +} +#endif /* (!defined(CY_DEVICE_SECURE)) */ + +__STATIC_INLINE void Cy_SysClk_ClkLfInit(void) +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_ClkLfSetSource(CY_CFG_SYSCLK_CLKLF_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkMemInit(void) +{ + Cy_SysClk_ClkMemSetDivider(0U); +} + +#if (!defined(CY_DEVICE_SECURE)) +__STATIC_INLINE void Cy_SysClk_ClkPath0Init(void) +{ + Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath1Init(void) +{ + Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath2Init(void) +{ + Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath3Init(void) +{ + Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath4Init(void) +{ + Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath5Init(void) +{ + Cy_SysClk_ClkPathSetSource(5U, CY_CFG_SYSCLK_CLKPATH5_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath6Init(void) +{ + Cy_SysClk_ClkPathSetSource(6U, CY_CFG_SYSCLK_CLKPATH6_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPeriInit(void) +{ + Cy_SysClk_ClkPeriSetDivider(0U); +} +#endif /* (!defined(CY_DEVICE_SECURE)) */ + +__STATIC_INLINE void Cy_SysClk_Pll0Init(void) +{ + Cy_SysClk_PllDisable(SRSS_PLL_400M_0_PATH_NUM); + + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(SRSS_PLL_400M_0_PATH_NUM, &srss_0_clock_0_pll400m_0_pllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(SRSS_PLL_400M_0_PATH_NUM, 10000u)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } +} +__STATIC_INLINE void Cy_SysClk_Pll1Init(void) +{ + Cy_SysClk_PllDisable(SRSS_PLL_400M_1_PATH_NUM); + + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(SRSS_PLL_400M_1_PATH_NUM, &srss_0_clock_0_pll400m_1_pllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(SRSS_PLL_400M_1_PATH_NUM, 10000u)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } +} +__STATIC_INLINE void Cy_SysClk_Pll2Init(void) +{ + Cy_SysClk_PllDisable(SRSS_PLL_200M_0_PATH_NUM); + + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(SRSS_PLL_200M_0_PATH_NUM, &srss_0_clock_0_pll_0_pllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(SRSS_PLL_200M_0_PATH_NUM, 10000u)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } +} +__STATIC_INLINE void Cy_SysClk_Pll3Init(void) +{ + Cy_SysClk_PllDisable(SRSS_PLL_200M_1_PATH_NUM); + + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(SRSS_PLL_200M_1_PATH_NUM, &srss_0_clock_0_pll_1_pllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(SRSS_PLL_200M_1_PATH_NUM, 10000u)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } +} + +#if (!defined(CY_DEVICE_SECURE)) +__STATIC_INLINE void Cy_SysClk_ClkSlowInit(void) +{ + Cy_SysClk_ClkSlowSetDivider(0U); +} +#endif /* (!defined(CY_DEVICE_SECURE)) */ + +__STATIC_INLINE void init_cycfg_power(void) +{ + /* **Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD** */ + #if (CY_CFG_PWR_VBACKUP_USING_VDDD) + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) + { + Cy_SysLib_ResetBackupDomain(); + Cy_SysClk_IloDisable(); + Cy_SysClk_IloInit(); + } + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ + #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ + + /* **REGHC Configuration** */ + #if (CY_CFG_PWR_REGHC_ENABLED) + Cy_SysPm_ReghcConfigure(CY_CFG_PWR_REGHC_MODE, CY_CFG_PWR_REGHC_TRANS_VADJ_VOLT); + #endif /* CY_CFG_PWR_REGHC_ENABLED */ + + /* **System Active Low Power Profile(LPACTIVE/LPSLEEP) Configuration** */ + #if (CY_CFG_PWR_SYS_LP_PROFILE_MODE) + Cy_SysPm_SystemLpActiveEnter(); + #endif /* CY_CFG_PWR_SYS_ACTIVE_MODE */ + + /* **System Regulators Low Current Configuration** */ + #if CY_CFG_PWR_REGULATOR_MODE_MIN + Cy_SysPm_SystemSetMinRegulatorCurrent(); + #else + Cy_SysPm_SystemSetNormalRegulatorCurrent(); + #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */ +} +void init_cycfg_system(void) +{ + Cy_SysClk_PeriPclkAssignDivider(PCLK_CPUSS_CLOCK_TRACE_IN, CY_SYSCLK_DIV_8_BIT, 2U); + /* Set worst case memory wait states (! ultra low power, 180 MHz), will update at the end */ + Cy_SysLib_SetWaitStates(false, 180UL); + #ifdef CY_CFG_PWR_ENABLED + #ifdef CY_CFG_PWR_INIT + init_cycfg_power(); + #else + #warning Power system will not be configured. Update power personality to v1.20 or later. + #endif /* CY_CFG_PWR_INIT */ + #endif /* CY_CFG_PWR_ENABLED */ + /* Disable FLL */ + Cy_SysClk_FllDeInit(); + /* Enable all source clocks */ + #ifdef CY_CFG_SYSCLK_ILO0_ENABLED + Cy_SysClk_Ilo0Init(); + #else + Cy_SysClk_Ilo0DeInit(); + #endif + #ifdef CY_CFG_SYSCLK_ILO1_ENABLED + Cy_SysClk_Ilo1Init(); + #else + Cy_SysClk_Ilo1DeInit(); + #endif + #ifdef CY_CFG_SYSCLK_PILO_ENABLED + Cy_SysClk_PiloInit(); + #endif + #ifdef CY_CFG_SYSCLK_WCO_ENABLED + Cy_SysClk_WcoInit(); + #endif + #ifdef CY_CFG_SYSCLK_ECO_ENABLED + Cy_SysClk_EcoInit(); + #endif + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + Cy_SysClk_ClkLfInit(); + #endif + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED + Cy_SysClk_ExtClkInit(); + #endif + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED + Cy_SysClk_AltHfInit(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED + Cy_SysClk_ClkPeriInit(); + #endif + /* Configure Path Clocks */ + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + Cy_SysClk_ClkPath1Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED + Cy_SysClk_ClkPath2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED + Cy_SysClk_ClkPath3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED + Cy_SysClk_ClkPath4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED + Cy_SysClk_ClkPath5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED + Cy_SysClk_ClkPath6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED + Cy_SysClk_ClkPath7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED + Cy_SysClk_ClkPath8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED + Cy_SysClk_ClkPath9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED + Cy_SysClk_ClkPath10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED + Cy_SysClk_ClkPath11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED + Cy_SysClk_ClkPath12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED + Cy_SysClk_ClkPath13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED + Cy_SysClk_ClkPath14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED + Cy_SysClk_ClkPath15Init(); + #endif + /* Configure and enable PLLs */ + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED + Cy_SysClk_Pll0Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED + Cy_SysClk_Pll1Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL2_ENABLED + Cy_SysClk_Pll2Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL3_ENABLED + Cy_SysClk_Pll3Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL4_ENABLED + Cy_SysClk_Pll4Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL5_ENABLED + Cy_SysClk_Pll5Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL6_ENABLED + Cy_SysClk_Pll6Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL7_ENABLED + Cy_SysClk_Pll7Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL8_ENABLED + Cy_SysClk_Pll8Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL9_ENABLED + Cy_SysClk_Pll9Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL10_ENABLED + Cy_SysClk_Pll10Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL11_ENABLED + Cy_SysClk_Pll11Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL12_ENABLED + Cy_SysClk_Pll12Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL13_ENABLED + Cy_SysClk_Pll13Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL14_ENABLED + Cy_SysClk_Pll14Init(); + #endif + /* Configure HF clocks */ + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED + Cy_SysClk_ClkHf1Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED + Cy_SysClk_ClkHf2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED + Cy_SysClk_ClkHf3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED + Cy_SysClk_ClkHf4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED + Cy_SysClk_ClkHf5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED + Cy_SysClk_ClkHf6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED + Cy_SysClk_ClkHf7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED + Cy_SysClk_ClkHf8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED + Cy_SysClk_ClkHf9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED + Cy_SysClk_ClkHf10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED + Cy_SysClk_ClkHf11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED + Cy_SysClk_ClkHf12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED + Cy_SysClk_ClkHf13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED + Cy_SysClk_ClkHf14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED + Cy_SysClk_ClkHf15Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + Cy_SysClk_ClkAltSysTickInit(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED + Cy_SysClk_ClkPumpInit(); + #endif + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED + Cy_SysClk_ClkBakInit(); + #endif + /* Configure default enabled clocks */ + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + Cy_SysClk_IloInit(); + #endif + #ifndef CY_CFG_SYSCLK_IMO_ENABLED + #error the IMO must be enabled for proper chip operation + #endif + #ifdef CY_CFG_SYSCLK_MFO_ENABLED + Cy_SysClk_MfoInit(); + #endif + #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED + Cy_SysClk_ClkMfInit(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPWR_ENABLED + Cy_SysClk_ClkPwrInit(); + #endif + /* Set accurate flash wait states */ + #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF1_ENABLED)) + Cy_SysLib_SetWaitStates(false, CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED + Cy_SysClk_ClkPath0Init(); + #endif + /* Configure and enable FLL */ + #ifdef CY_CFG_SYSCLK_FLL_ENABLED + Cy_SysClk_FllInit(); + #endif + Cy_SysClk_ClkHf0Init(); + #ifdef CY_CFG_SYSCLK_CLKFAST_0_ENABLED + Cy_SysClk_ClkFast_0_Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKFAST_1_ENABLED + Cy_SysClk_ClkFast_1_Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED + Cy_SysClk_ClkSlowInit(); + #endif + #ifdef CY_CFG_SYSCLK_CLKMEM_ENABLED + Cy_SysClk_ClkMemInit(); + #endif +#if defined(CY_CFG_SYSCLK_ECO_PRESCALER_ENABLED) + Cy_SysClk_EcoPrescalerInit(); +#endif /* defined(CY_CFG_SYSCLK_ECO_PRESCALER_ENABLED) */ + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + Cy_SysClk_ClkAltSysTickInit(); + #endif + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ + SystemCoreClockUpdate(); + /* Configure HF clocks CSV */ + #ifdef CY_CFG_SYSCLK_CLKHF0_CSV_ENABLED + Cy_SysClk_ClkHf0CsvInit(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF1_CSV_ENABLED + Cy_SysClk_ClkHf1CsvInit(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF2_CSV_ENABLED + Cy_SysClk_ClkHf2CsvInit(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF3_CSV_ENABLED + Cy_SysClk_ClkHf3CsvInit(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF4_CSV_ENABLED + Cy_SysClk_ClkHf4CsvInit(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF5_CSV_ENABLED + Cy_SysClk_ClkHf5CsvInit(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF6_CSV_ENABLED + Cy_SysClk_ClkHf6CsvInit(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF7_CSV_ENABLED + Cy_SysClk_ClkHf7CsvInit(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF8_CSV_ENABLED + Cy_SysClk_ClkHf8CsvInit(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF9_CSV_ENABLED + Cy_SysClk_ClkHf9CsvInit(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF10CSV_ENABLED + Cy_SysClk_ClkHf10CsvInit(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF11_CSV_ENABLED + Cy_SysClk_ClkHf11CsvInit(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF12_CSV_ENABLED + Cy_SysClk_ClkHf12CsvInit(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF13_CSV_ENABLED + Cy_SysClk_ClkHf13CsvInit(); + #endif + /* Configure LF clocks CSV */ + #ifdef CY_CFG_SYSCLK_CLKLF_CSV_ENABLED + Cy_SysClk_ClkLfCsvInit(); + #endif +#if defined (CY_USING_HAL) + if(CY_RSLT_SUCCESS != (cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj))) + { + CY_HALT(); + } + if(CY_RSLT_SUCCESS != (cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj))) + { + CY_HALT(); + } + if(CY_RSLT_SUCCESS != (cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj))) + { + CY_HALT(); + } + if(CY_RSLT_SUCCESS != (cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj))) + { + CY_HALT(); + } + if(CY_RSLT_SUCCESS != (cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj))) + { + CY_HALT(); + } + if(CY_RSLT_SUCCESS != (cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_5_obj))) + { + CY_HALT(); + } + if(CY_RSLT_SUCCESS != (cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_6_obj))) + { + CY_HALT(); + } +#endif /* defined (CY_USING_HAL) */ +} +void reserve_cycfg_system(void) +{ + Cy_SysClk_EcoSetFrequency(CY_CFG_SYSCLK_ECO_FREQ); + SystemCoreClockUpdate(); +} \ No newline at end of file diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_system.h b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_system.h new file mode 100644 index 00000000000..0e4dd3e5fb7 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_system.h @@ -0,0 +1,138 @@ +/******************************************************************************* + * File Name: cycfg_system.h + * + * Description: + * System configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.50.0 + * device-db 4.22.0.7873 + * mtb-pdl-cat1 3.15.0.40227 + * + ******************************************************************************* + * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#if !defined(CYCFG_SYSTEM_H) +#define CYCFG_SYSTEM_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#include "cy_wdt.h" +#include "cy_systick.h" +#include "cy_gpio.h" +#include "cy_syspm.h" + +#if defined (CY_USING_HAL) +#include "cyhal_hwmgr.h" +#endif /* defined (CY_USING_HAL) */ + +#if defined(__cplusplus) +extern "C" { +#endif /* defined(__cplusplus) */ + +#define cpuss_0_dap_0_ENABLED 1U +#define srss_0_clock_0_ENABLED 1U +#define srss_0_clock_0_altsystickclk_0_ENABLED 1U +#define srss_0_clock_0_bakclk_0_ENABLED 1U +#define srss_0_clock_0_eco_0_ENABLED 1U +#define srss_0_clock_0_fastclk_0_ENABLED 1U +#define srss_0_clock_0_fastclk_1_ENABLED 1U +#define srss_0_clock_0_fll_0_ENABLED 1U +#define srss_0_clock_0_hfclk_0_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF0 0UL +#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL +#define srss_0_clock_0_hfclk_1_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF1 1UL +#define CY_CFG_SYSCLK_CLKHF1_CLKPATH_NUM 1UL +#define srss_0_clock_0_hfclk_2_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF2 2UL +#define CY_CFG_SYSCLK_CLKHF2_CLKPATH_NUM 4UL +#define srss_0_clock_0_hfclk_3_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF3 3UL +#define CY_CFG_SYSCLK_CLKHF3_CLKPATH_NUM 4UL +#define srss_0_clock_0_hfclk_4_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF4 4UL +#define CY_CFG_SYSCLK_CLKHF4_CLKPATH_NUM 4UL +#define srss_0_clock_0_hfclk_5_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF5 5UL +#define CY_CFG_SYSCLK_CLKHF5_CLKPATH_NUM 2UL +#define srss_0_clock_0_hfclk_6_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF6 6UL +#define CY_CFG_SYSCLK_CLKHF6_CLKPATH_NUM 4UL +#define srss_0_clock_0_hfclk_7_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF7 7UL +#define CY_CFG_SYSCLK_CLKHF7_CLKPATH_NUM 5UL +#define srss_0_clock_0_ilo_0_ENABLED 1U +#define srss_0_clock_0_ilo_1_ENABLED 1U +#define srss_0_clock_0_imo_0_ENABLED 1U +#define srss_0_clock_0_lfclk_0_ENABLED 1U +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 +#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_ILO +#define srss_0_clock_0_memclk_0_ENABLED 1U +#define srss_0_clock_0_pathmux_0_ENABLED 1U +#define srss_0_clock_0_pathmux_1_ENABLED 1U +#define srss_0_clock_0_pathmux_2_ENABLED 1U +#define srss_0_clock_0_pathmux_3_ENABLED 1U +#define srss_0_clock_0_pathmux_4_ENABLED 1U +#define srss_0_clock_0_pathmux_5_ENABLED 1U +#define srss_0_clock_0_pathmux_6_ENABLED 1U +#define srss_0_clock_0_periclk_0_ENABLED 1U +#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPERI_DIVIDER 0 +#define srss_0_clock_0_pll400m_0_ENABLED 1U +#define srss_0_clock_0_pll400m_1_ENABLED 1U +#define srss_0_clock_0_pll_0_ENABLED 1U +#define srss_0_clock_0_pll_1_ENABLED 1U +#define srss_0_clock_0_slowclk_0_ENABLED 1U +#define srss_0_clock_0_timerclk_0_ENABLED 1U +#define srss_0_power_0_ENABLED 1U +#define CY_CFG_PWR_MODE_LP 0x01UL +#define CY_CFG_PWR_MODE_ULP 0x02UL +#define CY_CFG_PWR_MODE_ACTIVE 0x04UL +#define CY_CFG_PWR_MODE_SLEEP 0x08UL +#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL +#define CY_CFG_PWR_MODE_DEEPSLEEP_RAM 0x11UL +#define CY_CFG_PWR_MODE_DEEPSLEEP_OFF 0x12UL +#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP +#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL +#define CY_CFG_PWR_SYS_LP_PROFILE_MODE 0 +#define CY_CFG_PWR_VDDA_MV 3300 +#define CY_CFG_PWR_VDDD_MV 3300 +#define CY_CFG_PWR_VDDIO0_MV 3300 +#define CY_CFG_PWR_VDDIO1_MV 3300 +#define CY_CFG_PWR_REGHC_ENABLED false +#define CY_CFG_PWR_REGHC_MODE 255 +#define CY_CFG_PWR_REGHC_TRANS_VADJ_VOLT 0 + +#if defined (CY_USING_HAL) +extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj; +extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj; +extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj; +extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj; +extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj; +extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj; +extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_6_obj; +#endif /* defined (CY_USING_HAL) */ + +void init_cycfg_system(void); +void reserve_cycfg_system(void); + +#if defined(__cplusplus) +} +#endif /* defined(__cplusplus) */ + +#endif /* CYCFG_SYSTEM_H */ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/qspi_config.cfg b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/qspi_config.cfg new file mode 100644 index 00000000000..00d541979eb --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/qspi_config.cfg @@ -0,0 +1,29 @@ +################################################################################ +# File Name: qspi_config.cfg +# +# Description: +# This file contains a SMIF Bank layout for use with OpenOCD. +# This file was automatically generated and should not be modified. +# QSPI Configurator: 4.50.0.2481 +# +################################################################################ +# Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or +# an affiliate of Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +set SMIF_BANKS { + 1 {addr 0x60000000 size 0x10000 psize 0x0000100 esize 0x0040000} +} diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/design.cyqspi b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/design.cyqspi new file mode 100644 index 00000000000..80aa7670f4e --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/design.cyqspi @@ -0,0 +1,70 @@ + + + + cat1c.xml + FlashLoaders + 4096 + 262144 + + + 0 + Not used + true + None + 0x60000000 + 0x800000 + 0x607FFFFF + true + false + QUAD_SPI_DATA_0_3 + default_memory.xml + false + CY_SMIF_MERGE_TIMEOUT_DISABLED + + + 1 + S25HL512T (Uniform) + true + None + 0x60000000 + 0x10000 + 0x6000FFFF + true + false + QUAD_SPI_DATA_0_3 + S25HL512T (Uniform) + false + CY_SMIF_MERGE_TIMEOUT_DISABLED + + + 2 + Not used + false + None + 0x60000000 + 0x10000 + 0x6000FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + CY_SMIF_MERGE_TIMEOUT_DISABLED + + + 3 + Not used + false + None + 0x60000000 + 0x10000 + 0x6000FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + CY_SMIF_MERGE_TIMEOUT_DISABLED + + + \ No newline at end of file diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/design.modus b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/design.modus new file mode 100644 index 00000000000..73b44a72705 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/design.modus @@ -0,0 +1,930 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/cybsp.c b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/cybsp.c new file mode 100644 index 00000000000..00c25fd8700 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/cybsp.c @@ -0,0 +1,138 @@ +/***************************************************************************//** +* \file cybsp.c +* +* Description: +* Provides initialization code for starting up the hardware contained on the +* Infineon board. +* +******************************************************************************** +* \copyright +* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation +* +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "cy_syspm.h" +#include "cy_sysclk.h" +#include "cybsp.h" +#if defined(CY_USING_HAL) +#include "cyhal_hwmgr.h" +#include "cyhal_syspm.h" +#endif +#if defined(COMPONENT_MW_CAT1CM0P) + #include "mtb_cat1cm0p.h" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +// The sysclk deep sleep callback is recommended to be the last callback that is executed before +// entry into deep sleep mode and the first one upon exit the deep sleep mode. +// Doing so minimizes the time spent on low power mode entry and exit. +#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER + #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) +#endif + +#if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK) +//-------------------------------------------------------------------------------------------------- +// cybsp_register_sysclk_pm_callback +// +// Registers a power management callback that prepares the clock system for entering deep sleep mode +// and restore the clocks upon wakeup from deep sleep. +// NOTE: This is called automatically as part of \ref cybsp_init +//-------------------------------------------------------------------------------------------------- +static cy_rslt_t cybsp_register_sysclk_pm_callback(void) +{ + cy_rslt_t result = CY_RSLT_SUCCESS; + static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = { NULL, NULL }; + static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = + { + .callback = &Cy_SysClk_DeepSleepCallback, + .type = CY_SYSPM_DEEPSLEEP, + .callbackParams = &cybsp_sysclk_pm_callback_param, + .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER + }; + + if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) + { + result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK; + } + return result; +} + + +#endif // if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK) + + +//-------------------------------------------------------------------------------------------------- +// cybsp_init +//-------------------------------------------------------------------------------------------------- +cy_rslt_t cybsp_init(void) +{ + // Setup hardware manager to track resource usage then initialize all system (clock/power) board + // configuration + #if defined(CY_USING_HAL) + cy_rslt_t result = cyhal_hwmgr_init(); + + if (CY_RSLT_SUCCESS == result) + { + result = cyhal_syspm_init(); + } + + #ifdef CY_CFG_PWR_VDDA_MV + if (CY_RSLT_SUCCESS == result) + { + cyhal_syspm_set_supply_voltage(CYHAL_VOLTAGE_SUPPLY_VDDA, CY_CFG_PWR_VDDA_MV); + } + #endif + + #else // if defined(CY_USING_HAL) + cy_rslt_t result = CY_RSLT_SUCCESS; + #endif // if defined(CY_USING_HAL) + + // By default, the peripheral configuration will be done on the first core running user code. + // This is the CM0+ if it is available and not running a pre-built image, and the CM7 otherwise. + // This is done to ensure configuration is available for all cores that might need to use it. + // In the case of a dual core project, this can be changed below to perform initialization on + // the CM7 if necessary. + #if defined(CORE_NAME_CM0P_0) || !(__CM0P_PRESENT) || (defined(CORE_NAME_CM7_0) && \ + defined(CY_USING_PREBUILT_CM0P_IMAGE)) + cycfg_config_init(); + #endif + + cycfg_config_reservations(); + + if (CY_RSLT_SUCCESS == result) + { + #if defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK) + result = cybsp_register_custom_sysclk_pm_callback(); + #else + result = cybsp_register_sysclk_pm_callback(); + #endif + } + + // CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was + // reserved by user previously. Please review the Device Configurator (design.modus) and the BSP + // reservation list (cyreservedresources.list) to make sure no resources are reserved by both. + return result; +} + + +#if defined(__cplusplus) +} +#endif diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/cybsp.h b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/cybsp.h new file mode 100644 index 00000000000..cd27cf68f26 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/cybsp.h @@ -0,0 +1,83 @@ +/***********************************************************************************************//** + * \file cybsp.h + * + * \brief + * Basic API for setting up boards containing a Cypress MCU. + * + *************************************************************************************************** + * \copyright + * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ + +#pragma once + +#include "cy_result.h" +#include "cybsp_types.h" +#include "cybsp_hw_config.h" +#if defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE) +#include "cybsp_bt_config.h" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * \addtogroup group_bsp_errors Error Codes + * \{ + * Error codes specific to the board. + */ + +/** Failed to configure sysclk power management callback */ +#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK \ + (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) + +/** \} group_bsp_errors */ + +/** + * \addtogroup group_bsp_functions Functions + * \{ + * All functions exposed by the board. + */ + +/** + * \brief Initialize all hardware on the board + * \returns CY_RSLT_SUCCESS if the board is successfully initialized, if there is + * a problem initializing any hardware it returns an error code specific + * to the hardware module that had a problem. + */ +cy_rslt_t cybsp_init(void); + +#if defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK) +//-------------------------------------------------------------------------------------------------- +// cybsp_register_custom_sysclk_pm_callback +// +// Registers a power management callback that prepares the clock system for entering deep sleep mode +// and restore the clocks upon wakeup from deep sleep. The application should implement this +// function and define `CYBSP_CUSTOM_SYSCLK_PM_CALLBACK` if it needs to replace the default SysClk +// DeepSleep callback behavior with application specific logic. +// NOTE: This is called automatically as part of \ref cybsp_init +//-------------------------------------------------------------------------------------------------- +cy_rslt_t cybsp_register_custom_sysclk_pm_callback(void); +#endif // defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK) + +/** \} group_bsp_functions */ + +#ifdef __cplusplus +} +#endif // __cplusplus diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/cybsp_doc.h b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/cybsp_doc.h new file mode 100644 index 00000000000..30363dc963e --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/cybsp_doc.h @@ -0,0 +1,847 @@ +/***********************************************************************************************//** + * \copyright + * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ + +#pragma once + +#if defined(CY_USING_HAL) +#include "cyhal_pin_package.h" +#endif +/* CAT4 and CAT5 do not have configurators so the BSP defines pins in a non-generated header */ +#if defined(COMPONENT_CAT4) +#include "cybsp_pins.h" +#else +#include "cycfg.h" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * \addtogroup group_bsp_pins Pin Mappings + * \{ + * Macro definitions for common peripheral pins on the board. + */ + +#if defined(CYBSP_USER_LED) +/** + * \addtogroup group_bsp_pins_led LED Pins + * \{ + * Pins connected to user LEDs on the board. + */ + +#ifdef CYBSP_LED_RGB_RED +/** RGB LED - Red \def CYBSP_LED_RGB_RED + */ +#endif +#ifdef CYBSP_LED_RGB_GREEN +/** RGB LED - Green \def CYBSP_LED_RGB_GREEN + */ +#endif +#ifdef CYBSP_LED_RGB_BLUE +/** RGB LED - Blue \def CYBSP_LED_RGB_BLUE + */ +#endif +#ifdef CYBSP_USER_LED +/** User LED \def CYBSP_USER_LED + */ +#endif +#ifdef CYBSP_USER_LED1 +/** User LED1 \def CYBSP_USER_LED1 + */ +#endif +#ifdef CYBSP_USER_LED2 +/** User LED2 \def CYBSP_USER_LED2 + */ +#endif +#ifdef CYBSP_USER_LED3 +/** User LED3 \def CYBSP_USER_LED3 + */ +#endif +#ifdef CYBSP_USER_LED4 +/** User LED 4 \def CYBSP_USER_LED4 + */ +#endif +#ifdef CYBSP_USER_LED5 +/** User LED 5 \def CYBSP_USER_LED5 + */ +#endif +#ifdef CYBSP_USER_LED6 +/** User LED 6 \def CYBSP_USER_LED6 + */ +#endif +#ifdef CYBSP_USER_LED7 +/** User LED 7 \def CYBSP_USER_LED7 + */ +#endif +#ifdef CYBSP_USER_LED8 +/** User LED 8 \def CYBSP_USER_LED8 + */ +#endif +#ifdef CYBSP_USER_LED9 +/** User LED 9 \def CYBSP_USER_LED9 + */ +#endif +#ifdef CYBSP_USER_LED10 +/** User LED 10 \def CYBSP_USER_LED10 + */ +#endif +#ifdef CYBSP_LED1 +/** LED 1 \def CYBSP_LED1 + */ +#endif +#ifdef CYBSP_LED2 +/** LED 2 \def CYBSP_LED2 + */ +#endif +#ifdef CYBSP_LED3 +/** LED 3 \def CYBSP_LED3 + */ +#endif +#ifdef CYBSP_LED3_RGB_RED +/** LED 3: RGB LED - Red \def CYBSP_LED3_RGB_RED + */ +#endif +#ifdef CYBSP_LED3_RGB_GREEN +/** LED 3: RGB LED - Green \def CYBSP_LED3_RGB_GREEN + */ +#endif +#ifdef CYBSP_LED3_RGB_BLUE +/** LED 3: RGB LED - Blue \def CYBSP_LED3_RGB_BLUE + */ +#endif +#ifdef CYBSP_LED4 +/** LED 4 \def CYBSP_LED4 + */ +#endif +#ifdef CYBSP_LED5 +/** LED 5 \def CYBSP_LED5 + */ +#endif +#ifdef CYBSP_LED6 +/** LED 6 \def CYBSP_LED6 + */ +#endif +#ifdef CYBSP_LED7 +/** LED 7 \def CYBSP_LED7 + */ +#endif +#ifdef CYBSP_LED8 +/** LED 8 \def CYBSP_LED8 + */ +#endif +#ifdef CYBSP_LED9 +/** LED 9 \def CYBSP_LED9 + */ +#endif +#ifdef CYBSP_LED10 +/** LED 10 \def CYBSP_LED10 + */ +#endif +#ifdef CYBSP_LED11 +/** LED 11 \def CYBSP_LED11 + */ +#endif +#ifdef CYBSP_LED12 +/** LED 12 \def CYBSP_LED12 + */ +#endif +#ifdef CYBSP_LED13 +/** LED 13 \def CYBSP_LED13 + */ +#endif +#ifdef CYBSP_LED_SLD0 +/** Slider LED 0 \def CYBSP_LED_SLD0 + */ +#endif +#ifdef CYBSP_LED_SLD1 +/** Slider LED 1 \def CYBSP_LED_SLD1 + */ +#endif +#ifdef CYBSP_LED_SLD2 +/** Slider LED 2 \def CYBSP_LED_SLD2 + */ +#endif +#ifdef CYBSP_LED_SLD3 +/** Slider LED 3 \def CYBSP_LED_SLD3 + */ +#endif +#ifdef CYBSP_LED_SLD4 +/** Slider LED 4 \def CYBSP_LED_SLD4 + */ +#endif +#ifdef CYBSP_LED_SLD5 +/** LED 10; Slider LED 5 \def CYBSP_LED_SLD5 + */ +#endif +#ifdef CYBSP_LED_BTN0 +/** Button LED 0 \def CYBSP_LED_BTN0 + */ +#endif +#ifdef CYBSP_LED_BTN1 +/** Button LED 1 \def CYBSP_LED_BTN1 + */ +#endif +#ifdef CYBSP_LED_BTN2 +/** Button LED 2 \def CYBSP_LED_BTN2 + */ +#endif + +/** \} group_bsp_pins_led */ +#endif // defined(CYBSP_USER_LED) + +#if defined(CYBSP_USER_BTN) +/** + * \addtogroup group_bsp_pins_btn Button Pins + * \{ + * Pins connected to user buttons on the board. + */ + +#ifdef CYBSP_SW1 +/** Switch 1 \def CYBSP_SW1 + */ +#endif +#ifdef CYBSP_SW2 +/** Switch 2 \def CYBSP_SW2 + */ +#endif +#ifdef CYBSP_SW3 +/** Switch 3 \def CYBSP_SW3 + */ +#endif +#ifdef CYBSP_SW4 +/** Switch 4 \def CYBSP_SW4 + */ +#endif +#ifdef CYBSP_USER_BTN +/** User Button 1 \def CYBSP_USER_BTN + */ +#endif +#ifdef CYBSP_USER_BTN1 +/** User Button 1 \def CYBSP_USER_BTN1 + */ +#endif +#ifdef CYBSP_USER_BTN2 +/** User Button 2 \def CYBSP_USER_BTN2 + */ +#endif +#ifdef CYBSP_POTENTIOMETER_INPUT +/** Potentiometer input \def CYBSP_POTENTIOMETER_INPUT + */ +#endif + +/** \} group_bsp_pins_btn */ +#endif // defined(CYBSP_USER_BTN) + +#if defined(CYBSP_DEBUG_UART_RX) || defined(CYBSP_SWDIO) +/** + * \addtogroup group_bsp_pins_comm Communication Pins + * \{ + * Pins associated with connections on the board for communication interfaces (UART/I2C/SPI/...) + */ + +#ifdef CYBSP_DEBUG_UART_RX +/** Pin: UART RX \def CYBSP_DEBUG_UART_RX + */ +#endif +#ifdef CYBSP_DEBUG_UART_TX +/** Pin: UART TX \def CYBSP_DEBUG_UART_TX + */ +#endif +#ifdef CYBSP_I2C_SCL +/** Pin: I2C SCL \def CYBSP_I2C_SCL + */ +#endif +#ifdef CYBSP_I2C_SDA +/** Pin: I2C SDA \def CYBSP_I2C_SDA + */ +#endif +#ifdef CYBSP_SWDIO +/** Pin: SWDIO \def CYBSP_SWDIO + */ +#endif +#ifdef CYBSP_SWDCK +/** Pin: SWDCK \def CYBSP_SWDCK + */ +#endif +#ifdef CYBSP_SPI_MOSI +/** Pin: SPI MOSI \def CYBSP_SPI_MOSI + */ +#endif +#ifdef CYBSP_SPI_MISO +/** Pin: SPI MISO \def CYBSP_SPI_MISO + */ +#endif +#ifdef CYBSP_SPI_CLK +/** Pin: SPI CLK \def CYBSP_SPI_CLK + */ +#endif +#ifdef CYBSP_SPI_CS +/** Pin: SPI CS \def CYBSP_SPI_CS + */ +#endif +#ifdef CYBSP_SWO +/** Pin: SWO \def CYBSP_SWO + */ +#endif +#ifdef CYBSP_QSPI_SS +/** Pin: QUAD SPI SS \def CYBSP_QSPI_SS + */ +#endif +#ifdef CYBSP_QSPI_D3 +/** Pin: QUAD SPI D3 \def CYBSP_QSPI_D3 + */ +#endif +#ifdef CYBSP_QSPI_D2 +/** Pin: QUAD SPI D2 \def CYBSP_QSPI_D2 + */ +#endif +#ifdef CYBSP_QSPI_D1 +/** Pin: QUAD SPI D1 \def CYBSP_QSPI_D1 + */ +#endif +#ifdef CYBSP_QSPI_D0 +/** Pin: QUAD SPI D0 \def CYBSP_QSPI_D0 + */ +#endif +#ifdef CYBSP_QSPI_SCK +/** Pin: QUAD SPI SCK \def CYBSP_QSPI_SCK + */ +#endif +#ifdef CYBSP_WIFI_SDIO_D0 +/** Pin: WIFI SDIO D0 \def CYBSP_WIFI_SDIO_D0 + */ +#endif +#ifdef CYBSP_WIFI_SDIO_D1 +/** Pin: WIFI SDIO D1 \def CYBSP_WIFI_SDIO_D1 + */ +#endif +#ifdef CYBSP_WIFI_SDIO_D2 +/** Pin: WIFI SDIO D2 \def CYBSP_WIFI_SDIO_D2 + */ +#endif +#ifdef CYBSP_WIFI_SDIO_D3 +/** Pin: WIFI SDIO D3 \def CYBSP_WIFI_SDIO_D3 + */ +#endif +#ifdef CYBSP_WIFI_SDIO_CMD +/** Pin: WIFI SDIO CMD \def CYBSP_WIFI_SDIO_CMD + */ +#endif +#ifdef CYBSP_WIFI_SDIO_CLK +/** Pin: WIFI SDIO CLK \def CYBSP_WIFI_SDIO_CLK + */ +#endif +#ifdef CYBSP_WIFI_WL_REG_ON +/** Pin: WIFI ON \def CYBSP_WIFI_WL_REG_ON + */ +#endif +#ifdef CYBSP_WIFI_HOST_WAKE +/** Pin: WIFI Host Wakeup \def CYBSP_WIFI_HOST_WAKE + */ + +#ifndef CYBSP_WIFI_HOST_WAKE_GPIO_DM +/** WiFi host-wake GPIO drive mode */ +#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) +#endif +#ifndef CYBSP_WIFI_HOST_WAKE_IRQ_EVENT +/** WiFi host-wake IRQ event */ +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE) +#endif +#endif // ifdef CYBSP_WIFI_HOST_WAKE +#ifdef CYBSP_BT_UART_RX +/** Pin: BT UART RX \def CYBSP_BT_UART_RX + */ +#endif +#ifdef CYBSP_BT_UART_TX +/** Pin: BT UART TX \def CYBSP_BT_UART_TX + */ +#endif +#ifdef CYBSP_BT_UART_RTS +/** Pin: BT UART RTS \def CYBSP_BT_UART_RTS + */ +#endif +#ifdef CYBSP_BT_UART_CTS +/** Pin: BT UART CTS \def CYBSP_BT_UART_CTS + */ +#endif +#ifdef CYBSP_BT_POWER +/** Pin: BT Power \def CYBSP_BT_POWER + */ +#endif +#ifdef CYBSP_BT_HOST_WAKE +/** Pin: BT Host Wakeup \def CYBSP_BT_HOST_WAKE + */ +/** BT host-wake GPIO drive mode */ +#define CYBSP_BT_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_NONE) +/** BT host wake IRQ event */ +#define CYBSP_BT_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_FALL) +#endif +#ifdef CYBSP_BT_DEVICE_WAKE +/** Pin: BT Device Wakeup \def CYBSP_BT_DEVICE_WAKE + */ +/** BT device wakeup GPIO drive mode */ +#define CYBSP_BT_DEVICE_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_STRONG) +/** BT device wakeup polarity */ +#define CYBSP_BT_DEVICE_WAKE_POLARITY (0u) +#endif +#ifdef CYBSP_PDM_CLK +/** Pin: PDM PCM CLK \def CYBSP_PDM_CLK + */ +#endif +#ifdef CYBSP_PDM_DATA +/** Pin PDM PCM DATA \def CYBSP_PDM_DATA + */ +#endif +#ifdef CYBSP_I2S_MCLK +/** Pin: I2S MCLK \def CYBSP_I2S_MCLK + */ +#endif +#ifdef CYBSP_I2S_TX_SCK +/** Pin: I2S TX SCK \def CYBSP_I2S_TX_SCK + */ +#endif +#ifdef CYBSP_I2S_TX_WS +/** Pin: I2S TX WS \def CYBSP_I2S_TX_WS + */ +#endif +#ifdef CYBSP_I2S_TX_DATA +/** Pin: I2S TX DATA \def CYBSP_I2S_TX_DATA + */ +#endif +#ifdef CYBSP_I2S_RX_SCK +/** Pin: I2S RX SCK \def CYBSP_I2S_RX_SCK + */ +#endif +#ifdef CYBSP_I2S_RX_WS +/** Pin: I2S RX WS \def CYBSP_I2S_RX_WS + */ +#endif +#ifdef CYBSP_I2S_RX_DATA +/** Pin: I2S RX DATA \def CYBSP_I2S_RX_DATA + */ +#endif +#ifdef CYBSP_DEBUG_UART_RTS +/** Pin: UART RX \def CYBSP_DEBUG_UART_RTS + */ +#endif +#ifdef CYBSP_DEBUG_UART_CTS +/** Pin: UART TX \def CYBSP_DEBUG_UART_CTS + */ +#endif +#ifdef CYBSP_UART_RX +/** Pin: UART RX \def CYBSP_UART_RX + */ +#endif +#ifdef CYBSP_UART_TX +/** Pin: UART TX \def CYBSP_UART_TX + */ +#endif +#ifdef CYBSP_TDO_SWO +/** Pin: \def CYBSP_TDO_SWO + */ +#endif +#ifdef CYBSP_TMS_SWDIO +/** Pin: \def CYBSP_TMS_SWDIO + */ +#endif +#ifdef CYBSP_SWCLK +/** Pin: \def CYBSP_SWCLK + */ +#endif + +/** \} group_bsp_pins_comm */ +#endif // defined(CYBSP_DEBUG_UART_RX) || defined(CYBSP_SWDIO) + +#if defined(CYBSP_A0) +/** + * \addtogroup group_bsp_pins_arduino Arduino Header Pins + * \{ + * Pins mapped to the Arduino header on the board. + */ + +#ifdef CYBSP_A0 +/** Arduino A0 \def CYBSP_A0 + */ +#endif +#ifdef CYBSP_A1 +/** Arduino A1 \def CYBSP_A1 + */ +#endif +#ifdef CYBSP_A2 +/** Arduino A2 \def CYBSP_A2 + */ +#endif +#ifdef CYBSP_A3 +/** Arduino A3 \def CYBSP_A3 + */ +#endif +#ifdef CYBSP_A4 +/** Arduino A4 \def CYBSP_A4 + */ +#endif +#ifdef CYBSP_A5 +/** Arduino A5 \def CYBSP_A5 + */ +#endif +#ifdef CYBSP_D0 +/** Arduino D0 \def CYBSP_D0 + */ +#endif +#ifdef CYBSP_D1 +/** Arduino D1 \def CYBSP_D1 + */ +#endif +#ifdef CYBSP_D2 +/** Arduino D2 \def CYBSP_D2 + */ +#endif +#ifdef CYBSP_D3 +/** Arduino D3 \def CYBSP_D3 + */ +#endif +#ifdef CYBSP_D4 +/** Arduino D4 \def CYBSP_D4 + */ +#endif +#ifdef CYBSP_D5 +/** Arduino D5 \def CYBSP_D5 + */ +#endif +#ifdef CYBSP_D6 +/** Arduino D6 \def CYBSP_D6 + */ +#endif +#ifdef CYBSP_D7 +/** Arduino D7 \def CYBSP_D7 + */ +#endif +#ifdef CYBSP_D8 +/** Arduino D8 \def CYBSP_D8 + */ +#endif +#ifdef CYBSP_D9 +/** Arduino D9 \def CYBSP_D9 + */ +#endif +#ifdef CYBSP_D10 +/** Arduino D10 \def CYBSP_D10 + */ +#endif +#ifdef CYBSP_D11 +/** Arduino D11 \def CYBSP_D11 + */ +#endif +#ifdef CYBSP_D12 +/** Arduino D12 \def CYBSP_D12 + */ +#endif +#ifdef CYBSP_D13 +/** Arduino D13 \def CYBSP_D13 + */ +#endif +#ifdef CYBSP_D14 +/** Arduino D14 \def CYBSP_D14 + */ +#endif +#ifdef CYBSP_D15 +/** Arduino D15 \def CYBSP_D15 + */ +#endif + +/** \} group_bsp_pins_arduino */ +#endif // defined(CYBSP_A0) + +#if defined(CYBSP_J2_1) +/** + * \addtogroup group_bsp_pins_j2 J2 Header Pins + * \{ + * Pins mapped to the J2 header on the board. + */ + +#ifdef CYBSP_J2_1 +/** Infineon J2 Header pin 1 \def CYBSP_J2_1 + */ +#endif +#ifdef CYBSP_J2_2 +/** Infineon J2 Header pin 2 \def CYBSP_J2_2 + */ +#endif +#ifdef CYBSP_J2_3 +/** Infineon J2 Header pin 3 \def CYBSP_J2_3 + */ +#endif +#ifdef CYBSP_J2_4 +/** Infineon J2 Header pin 4 \def CYBSP_J2_4 + */ +#endif +#ifdef CYBSP_J2_5 +/** Infineon J2 Header pin 5 \def CYBSP_J2_5 + */ +#endif +#ifdef CYBSP_J2_7 +/** Infineon J2 Header pin 7 \def CYBSP_J2_7 + */ +#endif +#ifdef CYBSP_J2_8 +/** Infineon J2 Header pin 8 \def CYBSP_J2_8 + */ +#endif +#ifdef CYBSP_J2_9 +/** Infineon J2 Header pin 9 \def CYBSP_J2_9 + */ +#endif +#ifdef CYBSP_J2_10 +/** Infineon J2 Header pin 10 \def CYBSP_J2_10 + */ +#endif +#ifdef CYBSP_J2_11 +/** Infineon J2 Header pin 11 \def CYBSP_J2_11 + */ +#endif +#ifdef CYBSP_J2_12 +/** Infineon J2 Header pin 12 \def CYBSP_J2_12 + */ +#endif +#ifdef CYBSP_J2_13 +/** Infineon J2 Header pin 13 \def CYBSP_J2_13 + */ +#endif +#ifdef CYBSP_J2_15 +/** Infineon J2 Header pin 15 \def CYBSP_J2_15 + */ +#endif +#ifdef CYBSP_J2_16 +/** Infineon J2 Header pin 16 \def CYBSP_J2_16 + */ +#endif +#ifdef CYBSP_J2_16 +/** Infineon J2 Header pin 16 \def CYBSP_J2_16 + */ +#endif +#ifdef CYBSP_J2_6 +/** Infineon J2 Header pin 6 \def CYBSP_J2_6 + */ +#endif +#ifdef CYBSP_J2_17 +/** Infineon J2 Header pin 17 \def CYBSP_J2_17 + */ +#endif +#ifdef CYBSP_J2_18 +/** Infineon J2 Header pin 18 \def CYBSP_J2_18 + */ +#endif +#ifdef CYBSP_J2_19 +/** Infineon J2 Header pin 19 \def CYBSP_J2_19 + */ +#endif +#ifdef CYBSP_J2_20 +/** Infineon J2 Header pin 20 \def CYBSP_J2_20 + */ +#endif +#ifdef CYBSP_J2_14 +/** Infineon J2 Header pin 14 \def CYBSP_J2_14 + */ +#endif + +/** \} group_bsp_pins_j2 */ +#endif // defined(CYBSP_J2_1) + +#if defined(CYBSP_J6_1) +/** + * \addtogroup group_bsp_pins_j6 J6 Header Pins + * \{ + * Pins mapped to the J6 header on the board. + */ + +#ifdef CYBSP_J6_1 +/** Infineon J6 Header pin 1 \def CYBSP_J6_1 + */ +#endif +#ifdef CYBSP_J6_2 +/** Infineon J6 Header pin 2 \def CYBSP_J6_2 + */ +#endif +#ifdef CYBSP_J6_3 +/** Infineon J6 Header pin 3 \def CYBSP_J6_3 + */ +#endif +#ifdef CYBSP_J6_4 +/** Infineon J6 Header pin 4 \def CYBSP_J6_4 + */ +#endif +#ifdef CYBSP_J6_5 +/** Infineon J6 Header pin 5 \def CYBSP_J6_5 + */ +#endif +#ifdef CYBSP_J6_6 +/** Infineon J6 Header pin 6 \def CYBSP_J6_6 + */ +#endif +#ifdef CYBSP_J6_7 +/** Infineon J6 Header pin 7 \def CYBSP_J6_7 + */ +#endif +#ifdef CYBSP_J6_8 +/** Infineon J6 Header pin 8 \def CYBSP_J6_8 + */ +#endif +#ifdef CYBSP_J6_9 +/** Infineon J6 Header pin 9 \def CYBSP_J6_9 + */ +#endif +#ifdef CYBSP_J6_10 +/** Infineon J6 Header pin 10 \def CYBSP_J6_10 + */ +#endif +#ifdef CYBSP_J6_11 +/** Infineon J6 Header pin 11 \def CYBSP_J6_11 + */ +#endif +#ifdef CYBSP_J6_12 +/** Infineon J6 Header pin 12 \def CYBSP_J6_12 + */ +#endif +#ifdef CYBSP_J6_13 +/** Infineon J6 Header pin 13 \def CYBSP_J6_13 + */ +#endif +#ifdef CYBSP_J6_14 +/** Infineon J6 Header pin 14 \def CYBSP_J6_14 + */ +#endif +#ifdef CYBSP_J6_15 +/** Infineon J6 Header pin 15 \def CYBSP_J6_15 + */ +#endif +#ifdef CYBSP_J6_16 +/** Infineon J6 Header pin 16 \def CYBSP_J6_16 + */ +#endif + +/** \} group_bsp_pins_j6 */ +#endif // defined(CYBSP_J6_1) + +#if defined(CYBSP_CMOD) || defined(CYBSP_CINA) || defined(CYBSP_CINTA) +/** + * \addtogroup group_bsp_pins_capsense Capsense + * \{ + * Pins connected to CAPSENSE™ sensors on the board. + */ + +#ifdef CYBSP_CSD_TX +/** Pin: CapSesnse TX \def CYBSP_CSD_TX + */ +#endif +#ifdef CYBSP_CINA +/** Pin: CapSesnse CINA \def CYBSP_CINA + */ +#endif +#ifdef CYBSP_CINTA +/** Pin: CapSesnse CINTA \def CYBSP_CINTA + */ +#endif +#ifdef CYBSP_CINB +/** Pin: CapSesnse CINB \def CYBSP_CINB + */ +#endif +#ifdef CYBSP_CINTB +/** Pin: CapSesnse CINTB \def CYBSP_CINTB + */ +#endif +#ifdef CYBSP_CMOD +/** Pin: CapSesnse CMOD \def CYBSP_CMOD + */ +#endif +#ifdef CYBSP_CSD_BTN0 +/** Pin: CapSesnse Button 0 \def CYBSP_CSD_BTN0 + */ +#endif +#ifdef CYBSP_CSD_BTN1 +/** Pin: CapSesnse Button 1 \def CYBSP_CSD_BTN1 + */ +#endif +#ifdef CYBSP_CSD_SLD0 +/** Pin: CapSesnse Slider 0 \def CYBSP_CSD_SLD0 + */ +#endif +#ifdef CYBSP_CSD_SLD1 +/** Pin: CapSesnse Slider 1 \def CYBSP_CSD_SLD1 + */ +#endif +#ifdef CYBSP_CSD_SLD2 +/** Pin: CapSesnse Slider 2 \def CYBSP_CSD_SLD2 + */ +#endif +#ifdef CYBSP_CSD_SLD3 +/** Pin: CapSesnse Slider 3 \def CYBSP_CSD_SLD3 + */ +#endif +#ifdef CYBSP_CSD_SLD4 +/** Pin: CapSesnse Slider 4 \def CYBSP_CSD_SLD4 + */ +#endif +#ifdef CYBSP_CSD_SLD5 +/** Pin: CapSesnse Slider 5 \def CYBSP_CSD_SLD5 + */ +#endif +#ifdef CYBSP_CSX_BTN_TX +/** Pin: CapSesnse Button TX \def CYBSP_CSX_BTN_TX + */ +#endif +#ifdef CYBSP_CSX_BTN0 +/** Pin: CapSesnse Button 0 \def CYBSP_CSX_BTN0 + */ +#endif +#ifdef CYBSP_CSX_BTN1 +/** Pin: CapSesnse Button 1 \def CYBSP_CSX_BTN1 + */ +#endif +#ifdef CYBSP_CSX_BTN2 +/** Pin: CapSesnse Button 2 \def CYBSP_CSX_BTN2 + */ +#endif + +/** \} group_bsp_pins_capsense */ +#endif // defined(CYBSP_CMOD) || defined(CYBSP_CINA) || defined(CYBSP_CINTA) + +#if defined(CYBSP_WCO_IN) +/** + * \addtogroup group_bsp_pins_wco WCO + * \{ + * Pins connected to the WCO on the board. + */ +#ifdef CYBSP_WCO_IN +/** Pin: WCO input \def CYBSP_WCO_IN + */ +#endif +#ifdef CYBSP_WCO_OUT +/** Pin: WCO output \def CYBSP_WCO_OUT + */ +#endif + +/** \} group_bsp_pins_wco */ +#endif // defined(CYBSP_WCO_IN) + +/** \} group_bsp_pins */ + +#if defined(__cplusplus) +} +#endif diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/cybsp_hw_config.h b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/cybsp_hw_config.h new file mode 100644 index 00000000000..a6c9badcfcb --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/cybsp_hw_config.h @@ -0,0 +1,50 @@ +/***********************************************************************************************//** + * \file cybsp_hw_config.h + * + * \brief + * Basic API for handling defaults for hardware so code examples behave the same across different + * devices. + * + *************************************************************************************************** + * \copyright + * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ +#pragma once + +#include "cy_result.h" +#include "cybsp_types.h" +#include "cycfg_pins.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#ifndef CYBSP_USER_BTN_DRIVE +#define CYBSP_USER_BTN_DRIVE (CYHAL_GPIO_DRIVE_PULLUP) +#endif + +#ifndef CYBSP_DEBUG_UART_CTS +#define CYBSP_DEBUG_UART_CTS (NC) +#endif +#ifndef CYBSP_DEBUG_UART_RTS +#define CYBSP_DEBUG_UART_RTS (NC) +#endif + +#if defined(__cplusplus) +} +#endif diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/cybsp_types.h b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/cybsp_types.h new file mode 100644 index 00000000000..aeb7023cb73 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/cybsp_types.h @@ -0,0 +1,73 @@ +/***********************************************************************************************//** + * \copyright + * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ + +#pragma once + +#include "cybsp_doc.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * \cond INTERNAL + */ +/* WIFI interface types */ +#define CYBSP_SDIO_INTERFACE (0) +#define CYBSP_SPI_INTERFACE (1) +#define CYBSP_M2M_INTERFACE (2) + +/* Map from the new components to the old interface names for + * compatibility with code that still depends on those defines */ +#if defined(COMPONENT_WIFI_INTERFACE_SDIO) +#define CYBSP_WIFI_INTERFACE_TYPE (CYBSP_SDIO_INTERFACE) +#elif defined(COMPONENT_WIFI_INTERFACE_SPI) +#define CYBSP_WIFI_INTERFACE_TYPE (CYBSP_SPI_INTERFACE) +#elif defined(COMPONENT_WIFI_INTERFACE_M2M) +#define CYBSP_WIFI_INTERFACE_TYPE (CYBSP_M2M_INTERFACE) +#endif +/** \endcond */ + +/** + * \addtogroup group_bsp_pin_state Pin States + * \{ + * Macros to abstract out whether the LEDs & Buttons are wired high or active low. + */ +/** Pin state for the LED on. */ +#ifndef CYBSP_LED_STATE_ON +#define CYBSP_LED_STATE_ON (0U) +#endif +/** Pin state for the LED off. */ +#ifndef CYBSP_LED_STATE_OFF +#define CYBSP_LED_STATE_OFF (1U) +#endif +/** Pin state for when a button is pressed. */ +#ifndef CYBSP_BTN_PRESSED +#define CYBSP_BTN_PRESSED (0U) +#endif +/** Pin state for when a button is released. */ +#ifndef CYBSP_BTN_OFF +#define CYBSP_BTN_OFF (1U) +#endif +/** \} group_bsp_pin_state */ + +#if defined(__cplusplus) +} +#endif diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/deps/cat1cm0p.mtbx b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/deps/cat1cm0p.mtbx new file mode 100644 index 00000000000..ad1b8925711 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/deps/cat1cm0p.mtbx @@ -0,0 +1 @@ +https://github.com/Infineon/cat1cm0p#release-v1.8.0#$$ASSET_REPO$$/cat1cm0p/release-v1.8.0 diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/deps/core-lib.mtbx b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/deps/core-lib.mtbx new file mode 100644 index 00000000000..9f5da3261b8 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/deps/core-lib.mtbx @@ -0,0 +1 @@ +https://github.com/cypresssemiconductorco/core-lib#release-v1.4.3#$$ASSET_REPO$$/core-lib/release-v1.4.3 diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/deps/core-make.mtbx b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/deps/core-make.mtbx new file mode 100644 index 00000000000..acc7d008a60 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/deps/core-make.mtbx @@ -0,0 +1 @@ +https://github.com/cypresssemiconductorco/core-make#release-v3.4.1#$$ASSET_REPO$$/core-make/release-v3.4.1 diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/deps/mtb-hal-cat1.mtbx b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/deps/mtb-hal-cat1.mtbx new file mode 100644 index 00000000000..a715e02d607 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/deps/mtb-hal-cat1.mtbx @@ -0,0 +1 @@ +https://github.com/cypresssemiconductorco/mtb-hal-cat1#release-v2.6.2#$$ASSET_REPO$$/mtb-hal-cat1/release-v2.6.2 diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/deps/mtb-pdl-cat1.mtbx b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/deps/mtb-pdl-cat1.mtbx new file mode 100644 index 00000000000..3daa43979e7 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/deps/mtb-pdl-cat1.mtbx @@ -0,0 +1 @@ +https://github.com/cypresssemiconductorco/mtb-pdl-cat1#release-v3.15.0#$$ASSET_REPO$$/mtb-pdl-cat1/release-v3.15.0 diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/deps/recipe-make-cat1c.mtbx b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/deps/recipe-make-cat1c.mtbx new file mode 100644 index 00000000000..a934a8d16e8 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/deps/recipe-make-cat1c.mtbx @@ -0,0 +1 @@ +https://github.com/Infineon/recipe-make-cat1c#release-v1.4.1#$$ASSET_REPO$$/recipe-make-cat1c/release-v1.4.1 diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/props.json b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/props.json new file mode 100644 index 00000000000..94e0a824d9d --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/props.json @@ -0,0 +1,58 @@ +{ + "core": { + "version": "2.3.0.44500" + }, + "opt": { + "props": { + "capabilities": [ + "adc", + "arduino", + "bsp_gen5", + "can", + "cat1", + "cat1c", + "dma", + "ethernet", + "flash_4160k", + "hal", + "i2c", + "i2s", + "kit_xmc71_evk_lite_v2", + "led", + "low_power", + "lptimer", + "mcu_gp", + "memory", + "memory_qspi", + "multi_core", + "nor_flash", + "qspi", + "rtc", + "sdhc", + "sdio", + "smart_io", + "spi", + "sram_768k", + "std_crypto", + "switch", + "uart", + "xmc7000" + ], + "dependencies": { + "cat1cm0p": "release-v1.8.0", + "core-lib": "release-v1.4.3", + "core-make": "release-v3.4.1", + "mtb-hal-cat1": "release-v2.6.2", + "mtb-pdl-cat1": "release-v3.15.0", + "recipe-make-cat1c": "release-v1.4.1" + }, + "docs_dir": "docs", + "flow_version": "2.0", + "min_tools": "3.0.0", + "template": { + "id": "mtb-template-cat1", + "version": "release-v1.6.0" + } + } + } +} diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/startup_cat1c.h b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/startup_cat1c.h new file mode 100644 index 00000000000..354037901ae --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/startup_cat1c.h @@ -0,0 +1,9 @@ +#ifndef __STARTUP_CAT1C_H__ +#define __STARTUP_CAT1C_H__ + +#define FIXED_EXP_NR (15u) +#define VECTORTABLE_SIZE (16u + FIXED_EXP_NR + 1u) /* +1 is for Stack pointer */ +#define VECTORTABLE_ALIGN (128) /* alignment for 85 entries (32x4=128) is 2^7=128 bytes */ + + +#endif /* __STARTUP_CAT1C_H__ */ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/system_cat1c.h b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/system_cat1c.h new file mode 100644 index 00000000000..200bd6ef071 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/system_cat1c.h @@ -0,0 +1,582 @@ +/***************************************************************************//** +* \file system_cat1c.h +* \version 1.0 +* +* \brief Device system header file. +* +******************************************************************************** +* \copyright +* Copyright 2021 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + + +#ifndef _SYSTEM_FACELIFT_H_ +#define _SYSTEM_FACELIFT_H_ + +/** +* \addtogroup group_system_config_cm7 +* \{ +* Provides device startup, system configuration, and linker script files. +* The system startup provides the followings features: +* - \ref group_system_config_device_memory_definition_cm7 +* - \ref group_system_config_device_initialization_cm7 +* - \ref group_system_config_heap_stack_config_cm7 +* - \ref group_system_config_default_handlers_cm7 +* - \ref group_system_config_device_vector_table_cm7 +* - \ref group_system_config_cm7_functions +* +* \section group_system_config_configuration_cm7 Configuration Considerations +* +* \subsection group_system_config_device_memory_definition_cm7 Device Memory Definition +* Allocation of different types of memory such as the flash, RAM etc., for the CPU is defined by the linker scripts. +* +* \note - The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see warnings during the build process. To eliminate build +* warnings in your project, you can simply comment out or remove the relevant +* code in the linker file. +* +* \note - There is a common linker script for both CM7_0 and CM7_1 core. +* By default it links for CM7_0 core. But if the application is built for CM7_1, then a linker option _CORE_cm7_1 is provided in build system. +* For example, below piece of code is implemented in the build system. +* \code +* ifeq ($(TOOLCHAIN),IAR) +* LDFLAGS += --config_def _CORE_cm7_1_=1 +* else ifeq ($(TOOLCHAIN),GCC_ARM) +* LDFLAGS += -Wl,'--defsym=_CORE_cm7_1_=1' +* endif +* \endcode +* +* ARM GCC\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU; +* for example, 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'. +* \note If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value +* of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR macro should be used as the parameter for the +* Cy_SysEnableCM7() function call. +* By default, +* - the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0). +* - the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1). +* +* Change the flash and RAM sizes by editing the macro values in the +* linker files for both CPUs: +* - 'xx_yy_cm0plus.ld', where 'xx_yy' is the device group: +* \code +* cm0_ram (rxw) : ORIGIN = _base_SRAM_CM0P, LENGTH = _size_SRAM_CM0P +* cm0_flash (rx) : ORIGIN = _base_CODE_FLASH_CM0P,LENGTH = _size_CODE_FLASH_CM0P +* \endcode +* - 'xx_yy_cm7.ld', where 'xx_yy' is the device group: +* \code +* ram (rxw) : ORIGIN = _base_SRAM, LENGTH = _size_SRAM +* flash_cm0p (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P +* flash (rx) : ORIGIN = _base_CODE_FLASH, LENGTH = _size_CODE_FLASH +* \endcode +* +* Change the value of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR +* macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE +* value (0x80000, the size of a flash image of the Cortex-M0+ application should be the +* same value as the flash LENGTH in 'xx_yy_cm0plus.ld') in the 'xx_yy_cm7.ld' file, +* where 'xx_yy' is the device group. +* +* - Do this by editing the the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR value +* in the 'system_xx.h', where 'xx' is the device family:\n +* \code +* #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0 +* #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1 +* \endcode +* 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h +* +* ARM Compiler\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU; +* for example 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and 'xmc7100d_x4160_cm0plus.sct'. +* +* \note If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value +* of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR macro should be used as the parameter for the +* Cy_SysEnableCM7() function call. +* By default, +* - the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0). +* - the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1). +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see the warnings during the build process: +* L6314W (no section matches pattern) and/or L6329W +* (pattern only matches removed unused sections). In your project, you can +* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +* the linker. You can also comment out or remove the relevant code in the linker +* file. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_yy_cm0plus.sct', where 'xx_yy' is the device group: +* \code +* #define SRAM_BASE_ADDRESS 0x28000000 +* #define CM0PLUS_SRAM_RESERVE 0x00020000 +* #define CODE_FLASH_BASE_ADDRESS 0x10000000 +* #define CM0PLUS_CODE_FLASH_RESERVE 0x00080000 +* \endcode +* - 'xx_yy_cm7.sct', where 'xx_yy' is the device group: +* \code +* #define SRAM_BASE_ADDRESS 0x28000000 //SRAM START +* #define CM7_0_SRAM_RESERVE 0x00060000 //cm7_0 sram size +* #define BASE_SRAM_CM7_0 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE +* #define SIZE_SRAM_CM7_0 CM7_0_SRAM_RESERVE +* //In case of dual CM7-core MCU device device +* #define SIZE_SRAM_CM7_1 SRAM_TOTAL_SIZE - CM0PLUS_SRAM_RESERVE - CM7_0_SRAM_RESERVE +* #define BASE_SRAM_CM7_1 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE + CM7_0_SRAM_RESERVE +* +* #define CODE_FLASH_BASE_ADDRESS 0x10000000 //FLASH START +* #define CM7_0_CODE_FLASH_RESERVE 0x00200000 //cm7_0 flash size +* #define BASE_CODE_FLASH_CM7_0 CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE +* #define SIZE_CODE_FLASH_CM7_0 CM7_0_CODE_FLASH_RESERVE +* //In case of dual CM7-core MCU device device +* #define BASE_CODE_FLASH_CM7_1 CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE + CM7_0_CODE_FLASH_RESERVE +* #define SIZE_CODE_FLASH_CM7_1 CODE_FLASH_TOTAL_SIZE - CM0PLUS_CODE_FLASH_RESERVE - CM7_0_CODE_FLASH_RESERVE +* \endcode +* +* Change the value of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR +* macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE +* value (0x80000, the size of a flash image of the Cortex-M0+ application should be the +* same value as the flash LENGTH in 'xx_yy_cm0plus.sct') in the 'xx_yy_cm7.sct' file, +* where 'xx_yy' is the device group. +* +* - Do this by editing the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR value +* in the 'system_xx.h', where 'xx' is the device family:\n +* \code +* #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0 +* #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1 +* \endcode +* 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h + +* IAR\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy_zz.icf', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example, +* 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and 'xmc7100d_x4160_cm0plus.icf'. +* \note If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value +* of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR macro should be used as the parameter for the +* Cy_SysEnableCM7() function call. +* By default, +* - the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0). +* - the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1). +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_yy_cm0plus.icf', where 'xx_yy' is the device group: +* \code +* define symbol sram_base_address = 0x28000000; +* define symbol cm0plus_sram_reserve = 0x00020000; //cm0 sram size +* define symbol code_flash_base_address = 0x10000000; +* define symbol cm0plus_code_flash_reserve = 0x00080000; //cm0 flash size +* \endcode +* - 'xx_yy_cm7.icf', where 'xx_yy' is the device group: +* \code +* define symbol sram_base_address = 0x28000000; +* define symbol cm7_0_sram_reserve = 0x00060000; +* define symbol _base_SRAM_CM7_0 = sram_base_address + cm0plus_sram_reserve; +* define symbol _size_SRAM_CM7_0 = cm7_0_sram_reserve; +* //In case of dual CM7-core MCU device device +* define symbol _base_SRAM_CM7_1 = sram_base_address + cm0plus_sram_reserve + cm7_0_sram_reserve; +* define symbol _size_SRAM_CM7_1 = sram_total_size - cm0plus_sram_reserve - cm7_0_sram_reserve; +* +* define symbol code_flash_base_address = 0x10000000; +* define symbol cm7_0_code_flash_reserve = 0x00200000; +* define symbol _base_CODE_FLASH_CM7_0 = code_flash_base_address + cm0plus_code_flash_reserve; +* define symbol _size_CODE_FLASH_CM7_0 = cm7_0_code_flash_reserve; +* //In case of dual CM7-core MCU device device +* define symbol _base_CODE_FLASH_CM7_1 = code_flash_base_address + cm0plus_code_flash_reserve + cm7_0_code_flash_reserve; +* define symbol _size_CODE_FLASH_CM7_1 = code_flash_total_size - cm0plus_code_flash_reserve - cm7_0_code_flash_reserve; +* \endcode +* +* Change the value of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR +* macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE +* value (0x80000, the size of a flash image of the Cortex-M0+ application should be the +* same value as the flash LENGTH in 'xx_yy_cm0plus.icf') in the 'xx_yy_cm7.icf' file, +* where 'xx_yy' is the device group. +* +* - Do this by editing the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR value +* in the 'system_xx.h', where 'xx' is the device family:\n +* \code +* #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0 +* #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1 +* \endcode +* 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h +* +* \subsection group_system_config_device_initialization_cm7 Device Initialization +* After a power-on-reset (POR), the CM0+ starts boot-ROM directly from ROM and boot-ROM starts CM0+ startup. +* The CM0+ startup starts CM0+ user application. The CM0+ user application enables CM7 cores and starts CM7 startup. +* The startup code is the piece of code which is executed after every system reset. +* It initializes the system components like, memory, FPU, interrupts, clock, etc. and calls application's main() function. +* The startup code is always build as part of user application. There are two different startup codes for CM0+ and CM7 core. +* +* The CM0+ startup code implements the following functions to run the CM0+ application: +* +* 1. In the Reset Handler, it disables global interrupts +* 3. Disables the SRAM ECC checking: CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Facelift parts with CM7 core, +* sets CPUSS->RAMx_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC has not been initialized yet. +* 4. Calls SystemInit() function +* - Initializes and enables the SRAM memory for ECC +* - Copies the vector table from ROM to RAM and updates the VTOR (Vector Table Offset Register) +* - Sets the CM0+ IRQ0 and IRQ1 handlers from SROM vector table, sets the CM0+ IRQ0 and IRQ1priority, +* then enables these interrupts: the SROM APIs are executed by CM0+ core in interrupt context using IRQ0 and IRQ1. +* So, proper interrupt handler addresses and priorities need to be configured for IRQ0 and IRQ1 +* - Unlocks and disable WDT (Watchdog timer) +* - Calls the SystemCoreClockUpdate() +* 5. Executes main() application +* +* The CM7 startup code implement the following functions to run the CM7 user application: +* +* 1. In the Reset handler, it disables global interrupts +* 2. Allows write access to Vector Table Offset Register and ITCM/DTCM configuration register +* 3. Enables CM7 core ITCM and DTCM +* 4. Enables the FPU if it is used +* 5. Copies the vector table from ROM to RAM and updates the VTOR (Vector Table Offset Register) +* 6. Enables the CM7 core instruction and data cache +* 7. Calls SystemInit() function +* - Unlocks and disable WDT (Watchdog timer) +* - Calls the SystemCoreClockUpdate() +* 6. Executes CM7 main() application +* +* \subsection group_system_config_heap_stack_config_cm7 Heap and Stack Configuration +* By default, the stack size is set to 0x00001000 and the Heap size is allocated +* dynamically to the whole available free memory up to stack memory. +* The Stack grows from higher to lower address. The Stack top or start is assigned to end of SRAM address. +* The Heap grows opposite of Stack. It grows from lower to higher address. +* The Heap top starts from end of used data section till Stack end. +* +* \subsubsection group_system_config_heap_stack_config_gcc_cm7 ARM GCC +* Editing source code files\n +* The stack size is defined in the linker script files: 'xx_yy_zz.ld', +* 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example, +* 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'. +* Change the stack size by modifying the following line:\n +* \code STACK_SIZE = 0x1000; \endcode +* +* \note Correct operation of malloc and related functions depends on the working +* implementation of the 'sbrk' function. Newlib-nano (default C runtime library +* used by the GNU Arm Embedded toolchain) provides weak 'sbrk' implementation that +* doesn't check for heap and stack collisions during excessive memory allocations. +* To ensure the heap always remains within the range defined by __HeapBase and +* __HeapLimit linker symbols, provide a strong override for the 'sbrk' function: +* \snippet startup/snippet/main.c snippet_sbrk +* For FreeRTOS-enabled multi-threaded applications, it is sufficient to include +* clib-support library that provides newlib-compatible implementations of +* 'sbrk', '__malloc_lock' and '__malloc_unlock': +*
+* https://github.com/Infineon/clib-support. +* +* \subsubsection group_system_config_heap_stack_config_mdk_cm7 ARM Compiler +* Editing source code files\n +* The stack size is defined in the linker script files: 'xx_yy_zz.sct', +* 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example, +* 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and 'xmc7100d_x4160_cm0plus.sct'. +* Change the stack size by modifying the following line:\n +* \code #define STACK_SIZE 0x1000 \endcode +* +* \subsubsection group_system_config_heap_stack_config_iar_cm7 IAR +* Editing source code files\n +* The heap and stack sizes are defined in the linker script files: 'xx_yy_zz.icf', +* where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example, +* 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and 'xmc7100d_x4160_cm0plus.icf'. +* Change the heap and stack sizes by modifying the following lines:\n +* \code define symbol cm7_stack_reserve = 0x00001000; \endcode +* +* \subsection group_system_config_default_handlers_cm7 Default Interrupt Handlers Definition +* The default interrupt handler functions are defined as weak functions to a dummy +* handler in the startup file. The naming convention for the interrupt handler names +* is \_IRQHandler. A default interrupt handler can be overwritten in +* user code by defining the handler function using the same name. For example: +* \code +* void scb_0_interrupt_IRQHandler(void) +*{ +* ... +*} +* \endcode +* +* \subsection group_system_config_device_vector_table_cm7 Vectors Table Copy from Flash to RAM +* This process uses memory sections defined in the linker script. The startup +* code actually defines the contents of the vector table and performs the copy. +* +* \subsubsection group_system_config_device_vector_table_gcc_cm7 ARM GCC +* The linker script file is 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU; +* for example, 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'. +* It defines sections and locations in memory.\n +* Copy interrupt vectors from flash to RAM: \n +* From: \code LONG (__Vectors) \endcode +* To: \code LONG (__ram_vectors_start__) \endcode +* Size: \code LONG (__Vectors_End - __Vectors) \endcode +* The vector table address (and the vector table itself) are defined in the +* startup files (e.g. startup_cm0plus.S and startup_cm7.c). +* The code in these files copies the vector table from Flash to RAM. +* +* \subsubsection group_system_config_device_vector_table_mdk_cm7 ARM Compiler +* The linker script file is 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU; +* for example 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and +* 'xmc7100d_x4160_cm0plus.sct'. The linker script specifies that the vector table +* (RESET_RAM) shall be first in the RAM section.\n +* RESET_RAM represents the vector table. It is defined in the startup +* files (e.g. startup_cm0plus.S and startup_cm7.c). +* The code in these files copies the vector table from Flash to RAM. +* +* \subsubsection group_system_config_device_vector_table_iar_cm7 IAR +* The linker script file is 'xx_yy_zz.icf', where 'xx_ yy' is the device group, and 'zz' is the target CPU; +* for example, 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and ' +* 'xmc7100d_x4160_cm0plus.icf'.\n +* The vector table address (and the vector table itself) are defined in the +* startup files (e.g. startup_cm0plus.S and startup_cm7.c). +* The code in these files copies the vector table from Flash to RAM. +* +* \section group_system_config_changelog_cm7 Changelog +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_system_config_macro_cm7 Macros +* \{ +* \defgroup group_system_config_system_macro_cm7 System Macros +* \} +* \defgroup group_system_config_functions_cm7 Functions +* \{ +* \defgroup group_system_config_cm7_functions Cortex-M7 Control +* \} +* \} +*/ +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Include files +*******************************************************************************/ +#include +#if defined (CY_DEVICE_TVIIC2D6M) +#include "tviic_partition.h" +#else +#include "xmc7xxx_partition.h" +#endif + +/******************************************************************************* +* Global preprocessor symbols/macros ('define') +*******************************************************************************/ +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) + #define CY_SYSTEM_CPU_CM0P 1UL +#else + #define CY_SYSTEM_CPU_CM0P 0UL +#endif + + +/******************************************************************************* +* +* START OF USER SETTINGS HERE +* =========================== +* +* All lines with '<<<' can be set by user. +* +*******************************************************************************/ + +/** +* \addtogroup group_system_config_system_macro_cm7 +* \{ +*/ + +/******************************************************************************* +* +* END OF USER SETTINGS HERE +* ========================= +* +*******************************************************************************/ + +/** Start address of the Cortex-M7_0 application */ +#ifndef CY_CORTEX_M7_0_APPL_ADDR + #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0 +#endif + +/** Start address of the Cortex-M7_1 application */ +#ifndef CY_CORTEX_M7_1_APPL_ADDR + #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1 +#endif + +/** The Cortex-M7 core is enabled: power on, clock on, no isolate, no reset and no retain. */ +#define CY_SYS_CM7_STATUS_ENABLED (3U) +/** The Cortex-M7 core is disabled: power off, clock off, isolate, reset and no retain. */ +#define CY_SYS_CM7_STATUS_DISABLED (0U) +/** The Cortex-M7 core is retained. power off, clock off, isolate, no reset and retain. */ +#define CY_SYS_CM7_STATUS_RETAINED (2U) +/** The Cortex-M7 core is in the Reset mode: clock off, no isolated, no retain and reset. */ +#define CY_SYS_CM7_STATUS_RESET (1U) +/** \} group_system_config_system_macro_cm7 */ + +/** \cond */ +/** Cortex-M7 core 0 */ +#define CORE_CM7_0 (0U) +/** Cortex-M7 core 1 */ +#define CORE_CM7_1 (1U) +/** Error Selection */ +#define CORE_MAX (2U) + +/** Define start of the function placed to the ITCM area by the linker */ +#ifndef CY_SECTION_ITCM_BEGIN +#define CY_SECTION_ITCM_BEGIN CY_SECTION(".cy_itcm") +#endif + +/** Define end of the function placed to the ITCM area by the linker */ +#ifndef CY_SECTION_ITCM_END +#define CY_SECTION_ITCM_END +#endif + +extern uint32_t cy_delayFreqHz; +extern uint32_t cy_delayFreqKhz; +extern uint32_t cy_delayFreqMhz; + +extern uint32_t SystemCoreClock; +extern uint32_t cy_Hfclk0FreqHz; +extern uint32_t cy_PeriClkFreqHz; +extern uint32_t cy_AhbFreqHz; + +extern void SystemInit(void); +extern void SystemIrqInit(void); +extern void SystemCoreClockUpdate(void); + +/** \endcond */ + +/** +* \addtogroup group_system_config_cm7_functions +* \{ +*/ +/******************************************************************************* +* Function Name: Cy_SysGetCM7Status +****************************************************************************//** +* +* Gets the Cortex-M7 core power mode. +* +* \param core Core type (CM7_0 or CM7_1). +* +* \return \ref group_system_config_system_macro_cm7 \n +* If 0: CY_SYS_CM7_STATUS_DISABLED \n +* 1: CY_SYS_CM7_STATUS_RESET \n +* 2: CY_SYS_CM7_STATUS_RETAINED \n +* 3: CY_SYS_CM7_STATUS_ENABLED \n +* +******************************************************************************/ +extern uint32_t Cy_SysGetCM7Status(uint8_t core); +/******************************************************************************* +* Function Name: Cy_SysEnableCM7 +****************************************************************************//** +* +* Enables the Cortex-M7 core. The CPU is enabled once if it was in the disabled +* or retained mode. +* +* \param core Core type (CM7_0 or CM7_1). +* +* \param vectorTableOffset The offset of the vector table base address from +* memory address 0x00000000. The offset should be multiple to 1024 bytes. +* +*******************************************************************************/ +extern void Cy_SysEnableCM7(uint8_t core, uint32_t vectorTableOffset); +/******************************************************************************* +* Function Name: Cy_SysDisableCM7 +****************************************************************************//** +* +* Disables the Cortex-M7 core. +* +* \param core Core type (CM7_0 or CM7_1). +* +* \warning Do not call the function while the Cortex-M7 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M7 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +extern void Cy_SysDisableCM7(uint8_t core); +/******************************************************************************* +* Function Name: Cy_SysRetainCM7 +****************************************************************************//** +* +* Retains the Cortex-M7 core. +* +* \param core Core type (CM7_0 or CM7_1). +* +* \warning Do not call the function while the Cortex-M7 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M7 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +extern void Cy_SysRetainCM7(uint8_t core); +/******************************************************************************* +* Function Name: Cy_SysResetCM7 +****************************************************************************//** +* +* Resets the Cortex-M7 core. +* +* \param core Core type (CM7_0 or CM7_1). +* +* \warning Do not call the function while the Cortex-M7 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M7 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +extern void Cy_SysResetCM7(uint8_t core); +/** \} group_system_config_cm7_functions */ + + +/** \cond */ + +extern void Default_Handler (void); + +extern void Cy_SystemInit(void); +extern void Cy_SystemInitFpuEnable(void); +extern void CyMain(void); + +#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection +#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection +/** \endcond */ + + + + + + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_FACELIFT_H_ */ + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/xmc7xxx_partition.h b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/xmc7xxx_partition.h new file mode 100644 index 00000000000..b6a3f2db841 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/xmc7xxx_partition.h @@ -0,0 +1,57 @@ +#if !defined(LAYOUT_CAT1C_H) +#define LAYOUT_CAT1C_H + +#define STACK_SIZE 0x1000 +#define RAMVECTORS_ALIGNMENT 128 + +#define SRAM_START_RESERVE 0 +#define SRAM_PRIVATE_FOR_SROM 0x800 /* 2K Private SRAM for SROM (e.g. API processing). Reserved at the beginning */ + +/* RAM */ +#define SRAM_BASE_ADDRESS CY_SRAM_BASE /* SRAM START */ +#define TOTAL_RAM CY_SRAM_SIZE +#define CM0PLUS_SRAM_RESERVE 0x00004000 /* 16K cm0plus */ + +/* FLASH */ +#define CODE_FLASH_BASE_ADDRESS CY_FLASH_LG_SBM_BASE /* FLASH START */ +#define TOTAL_FLASH (CY_FLASH_LG_SBM_SIZE + CY_FLASH_SM_SBM_SIZE) +#define CM0PLUS_CODE_FLASH_RESERVE 0x00080000 /* 512K CM0P FLASH SIZE */ + +/* CM7_1 RAM and FLASH */ +#if defined (__CM7_1_PRESENT) + #define CM7_1_SRAM_RESERVE 0x00010000 /* (SRAM0/64KB) -> cm7_1 */ +#else + #define CM7_1_SRAM_RESERVE 0x00000000UL +#endif + +#if (TOTAL_FLASH == 0x830000) /** 8M device */ + #define CM7_0_CODE_FLASH_RESERVE 0x00200000 +#elif (TOTAL_FLASH == 0x410000) /** 4M device */ + #define CM7_0_CODE_FLASH_RESERVE 0x00200000 +#elif (TOTAL_FLASH == 0x210000) /** 2M device */ + #define CM7_0_CODE_FLASH_RESERVE 0x00100000 +#elif (TOTAL_FLASH == 0x110000) /** 1M device */ + #define CM7_0_CODE_FLASH_RESERVE 0x00090000 +#else + #error "Invalid device" +#endif + + +/* SRAM reservations */ +#define BASE_SRAM_CM0P (SRAM_BASE_ADDRESS + SRAM_START_RESERVE + SRAM_PRIVATE_FOR_SROM) +#define SIZE_SRAM_CM0P (CM0PLUS_SRAM_RESERVE - SRAM_START_RESERVE - SRAM_PRIVATE_FOR_SROM) +#define BASE_SRAM_CM7_0 (SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE) +#define SIZE_SRAM_CM7_0 TOTAL_RAM - CM0PLUS_SRAM_RESERVE - CM7_1_SRAM_RESERVE +#define BASE_SRAM_CM7_1 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE + SIZE_SRAM_CM7_0 + +/* Code flash reservations */ +#define BASE_CODE_FLASH_CM0P CODE_FLASH_BASE_ADDRESS +#define SIZE_CODE_FLASH_CM0P CM0PLUS_CODE_FLASH_RESERVE +#define BASE_CODE_FLASH_CM7_0 CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE +#define SIZE_CODE_FLASH_CM7_0 CM7_0_CODE_FLASH_RESERVE +#define BASE_CODE_FLASH_CM7_1 CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE + CM7_0_CODE_FLASH_RESERVE + +#endif /* LAYOUT_CAT1C_H */ + + +/* [] END OF FILE */ diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/libs/cat1c4m.svd b/bsp/Infineon/xmc7100d-f144k4160aa/libs/cat1c4m.svd new file mode 100644 index 00000000000..33bc15b72f2 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/libs/cat1c4m.svd @@ -0,0 +1,50279 @@ + + + Infineon Technologies + Infineon + cat1c4m + XMC7100 + 1.0 + XMC7100 + (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)\n + or an affiliate of Cypress Semiconductor Corporation.\n +\n + SPDX-License-Identifier: Apache-2.0\n +\n + Licensed under the Apache License, Version 2.0 (the "License");\n + you may not use this file except in compliance with the License.\n + You may obtain a copy of the License at\n +\n + http://www.apache.org/licenses/LICENSE-2.0\n +\n + Unless required by applicable law or agreed to in writing, software\n + distributed under the License is distributed on an "AS IS" BASIS,\n + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n + See the License for the specific language governing permissions and\n + limitations under the License. + + CM7 + r0p1 + little + true + true + true + 3 + false + + 8 + 32 + 0x00000000 + 0xFFFFFFFF + + + PERI + Peripheral interconnect + 0x40000000 + + 0 + 65536 + registers + + + + TIMEOUT_CTL + Timeout control + 0x200 + 32 + read-write + 0xFFFF + 0xFFFF + + + TIMEOUT + This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). +'0x0000'-'0xfffe': Number of clock cycles. +'0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated. + [15:0] + read-write + + + + + TR_CMD + Trigger command + 0x220 + 32 + read-write + 0x0 + 0xE0001FFF + + + TR_SEL + Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present, the trigger activation has no effect. + [7:0] + read-write + + + GROUP_SEL + Specifies the trigger group: +'0'-'15': trigger multiplexer groups. +'16'-'31': trigger 1-to-1 groups. + [12:8] + read-write + + + TR_EDGE + Specifies if the activated trigger is treated as a level sensitive or edge sensitive trigger. +'0': level sensitive. The trigger reflects TR_CMD.ACTIVATE. +'1': edge sensitive trigger. The trigger is activated for two clk_peri cycles. + [29:29] + read-write + + + OUT_SEL + Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only. +'0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer. +'1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer. + +Note: this field is not used for trigger 1-to-1 groups. + [30:30] + read-write + + + ACTIVATE + SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL, TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles. + +Note: when ACTIVATE is '1', SW should not modify the other register fields. +SW MUST NOT set ACTIVATE bit to '1' while updating the other register bits simultaneously. At first the SW MUST update the other register bits as needed, and then set ACTIVATE to '1' with a new register write. + [31:31] + read-write + + + + + ECC_CTL + ECC control + 0x2000 + 32 + read-write + 0x10000 + 0xFF0507FF + + + WORD_ADDR + Specifies the word address where the parity is injected. +- On a 32-bit write access to this SRAM address and when ECC_INJ_EN bit is '1', the parity (PARITY) is injected. + [10:0] + read-write + + + ECC_EN + Enable ECC: +'0': Disabled (on write ECC parity bits will not be correctly written). +'1': Enabled. + [16:16] + read-write + + + ECC_INJ_EN + Enable error injection for PERI protection structure SRAM. +When '1', the parity (PARITY) is used when a write is done to the WORD_ADDR word address of the SRAM. + [18:18] + read-write + + + PARITY + ECC parity to use for ECC error injection at address WORD_ADDR. + [31:24] + read-write + + + + + 10 + 64 + GR[%s] + Peripheral group structure + 0x00004000 + + CLOCK_CTL + Clock control + 0x0 + 32 + read-write + 0x0 + 0xFF00 + + + INT8_DIV + Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + SL_CTL + Slave control + 0x10 + 32 + read-write + 0xFFFF + 0xFFFF + + + ENABLED_0 + Peripheral group, slave 0 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. + +Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. + [0:0] + read-write + + + ENABLED_1 + Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. + +Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. + [1:1] + read-write + + + ENABLED_2 + Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. + +Note: For peripheral group 0 (the peripheral interconnect, PCLK group MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. + [2:2] + read-write + + + ENABLED_3 + N/A + [3:3] + read-write + + + ENABLED_4 + N/A + [4:4] + read-write + + + ENABLED_5 + N/A + [5:5] + read-write + + + ENABLED_6 + N/A + [6:6] + read-write + + + ENABLED_7 + N/A + [7:7] + read-write + + + ENABLED_8 + N/A + [8:8] + read-write + + + ENABLED_9 + N/A + [9:9] + read-write + + + ENABLED_10 + N/A + [10:10] + read-write + + + ENABLED_11 + N/A + [11:11] + read-write + + + ENABLED_12 + N/A + [12:12] + read-write + + + ENABLED_13 + N/A + [13:13] + read-write + + + ENABLED_14 + N/A + [14:14] + read-write + + + ENABLED_15 + N/A + [15:15] + read-write + + + + + + 13 + 1024 + TR_GR[%s] + Trigger group + 0x00008000 + + 256 + 4 + TR_CTL[%s] + Trigger control register + 0x0 + 32 + read-write + 0x0 + 0x13FF + + + TR_SEL + Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. + [7:0] + read-write + + + TR_INV + Specifies if the output trigger is inverted. + [8:8] + read-write + + + TR_EDGE + Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. +'0': level sensitive. +'1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. + [9:9] + read-write + + + DBG_FREEZE_EN + Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. + [12:12] + read-write + + + + + + 11 + 1024 + TR_1TO1_GR[%s] + Trigger 1-to-1 group + 0x0000C000 + + 256 + 4 + TR_CTL[%s] + Trigger control register + 0x0 + 32 + read-write + 0x0 + 0x1301 + + + TR_SEL + Specifies input trigger: +'0'': constant signal level '0'. +'1': input trigger. + [0:0] + read-write + + + TR_INV + Specifies if the output trigger is inverted. + [8:8] + read-write + + + TR_EDGE + Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. +'0': level sensitive. +'1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. + [9:9] + read-write + + + DBG_FREEZE_EN + Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation. + [12:12] + read-write + + + + + + + + PERI_MS + Peripheral interconnect, master interface + 0x40020000 + + 0 + 131072 + registers + + + + 16 + 64 + PPU_PR[%s] + Programmable protection structure pair + 0x00000000 + + SL_ADDR + Slave region, base address + 0x0 + 32 + read-write + 0x0 + 0x0 + + + ADDR30 + This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's. + [31:2] + read-write + + + + + SL_SIZE + Slave region, size + 0x4 + 32 + read-write + 0x0 + 0x80000000 + + + REGION_SIZE + This field specifies the size of the slave region: +'0': Undefined. +'1': 4 B region (this is the smallest region size). +'2': 8 B region +'3': 16 B region +'4': 32 B region +'5': 64 B region +'6': 128 B region +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'29': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-write + + + VALID + Slave region enable: +'0': Disabled. A disabled region will never result in a match on the transfer address. +'1': Enabled. + [31:31] + read-write + + + + + SL_ATT0 + Slave attributes 0 + 0x10 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC0_UR + Protection context 0, user read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-only + + + PC0_UW + Protection context 0, user write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-only + + + PC0_PR + Protection context 0, privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [2:2] + read-only + + + PC0_PW + Protection context 0, privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [3:3] + read-only + + + PC0_NS + Protection context 0, non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [4:4] + read-only + + + PC1_UR + Protection context 1, user read enable. + [8:8] + read-write + + + PC1_UW + Protection context 1, user write enable. + [9:9] + read-write + + + PC1_PR + Protection context 1, privileged read enable. + [10:10] + read-write + + + PC1_PW + Protection context 1, privileged write enable. + [11:11] + read-write + + + PC1_NS + Protection context 1, non-secure. + [12:12] + read-write + + + PC2_UR + Protection context 2, user read enable. + [16:16] + read-write + + + PC2_UW + Protection context 2, user write enable. + [17:17] + read-write + + + PC2_PR + Protection context 2, privileged read enable. + [18:18] + read-write + + + PC2_PW + Protection context 2, privileged write enable. + [19:19] + read-write + + + PC2_NS + Protection context 2, non-secure. + [20:20] + read-write + + + PC3_UR + Protection context 3, user read enable. + [24:24] + read-write + + + PC3_UW + Protection context 3, user write enable. + [25:25] + read-write + + + PC3_PR + Protection context 3, privileged read enable. + [26:26] + read-write + + + PC3_PW + Protection context 3, privileged write enable. + [27:27] + read-write + + + PC3_NS + Protection context 3, non-secure. + [28:28] + read-write + + + + + SL_ATT1 + Slave attributes 1 + 0x14 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC4_UR + Protection context 4, user read enable. + [0:0] + read-write + + + PC4_UW + Protection context 4, user write enable. + [1:1] + read-write + + + PC4_PR + Protection context 4, privileged read enable. + [2:2] + read-write + + + PC4_PW + Protection context 4, privileged write enable. + [3:3] + read-write + + + PC4_NS + Protection context 4, non-secure. + [4:4] + read-write + + + PC5_UR + Protection context 5, user read enable. + [8:8] + read-write + + + PC5_UW + Protection context 5, user write enable. + [9:9] + read-write + + + PC5_PR + Protection context 5, privileged read enable. + [10:10] + read-write + + + PC5_PW + Protection context 5, privileged write enable. + [11:11] + read-write + + + PC5_NS + Protection context 5, non-secure. + [12:12] + read-write + + + PC6_UR + Protection context 6, user read enable. + [16:16] + read-write + + + PC6_UW + Protection context 6, user write enable. + [17:17] + read-write + + + PC6_PR + Protection context 6, privileged read enable. + [18:18] + read-write + + + PC6_PW + Protection context 6, privileged write enable. + [19:19] + read-write + + + PC6_NS + Protection context 6, non-secure. + [20:20] + read-write + + + PC7_UR + Protection context 7, user read enable. + [24:24] + read-write + + + PC7_UW + Protection context 7, user write enable. + [25:25] + read-write + + + PC7_PR + Protection context 7, privileged read enable. + [26:26] + read-write + + + PC7_PW + Protection context 7, privileged write enable. + [27:27] + read-write + + + PC7_NS + Protection context 7, non-secure. + [28:28] + read-write + + + + + SL_ATT2 + Slave attributes 2 + 0x18 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC8_UR + Protection context 8, user read enable. + [0:0] + read-write + + + PC8_UW + Protection context 8, user write enable. + [1:1] + read-write + + + PC8_PR + Protection context 8, privileged read enable. + [2:2] + read-write + + + PC8_PW + Protection context 8, privileged write enable. + [3:3] + read-write + + + PC8_NS + Protection context 8, non-secure. + [4:4] + read-write + + + PC9_UR + Protection context 9, user read enable. + [8:8] + read-write + + + PC9_UW + Protection context 9, user write enable. + [9:9] + read-write + + + PC9_PR + Protection context 9, privileged read enable. + [10:10] + read-write + + + PC9_PW + Protection context 9, privileged write enable. + [11:11] + read-write + + + PC9_NS + Protection context 9, non-secure. + [12:12] + read-write + + + PC10_UR + Protection context 10, user read enable. + [16:16] + read-write + + + PC10_UW + Protection context 10, user write enable. + [17:17] + read-write + + + PC10_PR + Protection context 10, privileged read enable. + [18:18] + read-write + + + PC10_PW + Protection context 10, privileged write enable. + [19:19] + read-write + + + PC10_NS + Protection context 10, non-secure. + [20:20] + read-write + + + PC11_UR + Protection context 11, user read enable. + [24:24] + read-write + + + PC11_UW + Protection context 11, user write enable. + [25:25] + read-write + + + PC11_PR + Protection context 11, privileged read enable. + [26:26] + read-write + + + PC11_PW + Protection context 11, privileged write enable. + [27:27] + read-write + + + PC11_NS + Protection context 11, non-secure. + [28:28] + read-write + + + + + SL_ATT3 + Slave attributes 3 + 0x1C + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC12_UR + Protection context 12, user read enable. + [0:0] + read-write + + + PC12_UW + Protection context 12, user write enable. + [1:1] + read-write + + + PC12_PR + Protection context 12, privileged read enable. + [2:2] + read-write + + + PC12_PW + Protection context 12, privileged write enable. + [3:3] + read-write + + + PC12_NS + Protection context 12, non-secure. + [4:4] + read-write + + + PC13_UR + Protection context 13, user read enable. + [8:8] + read-write + + + PC13_UW + Protection context 13, user write enable. + [9:9] + read-write + + + PC13_PR + Protection context 13, privileged read enable. + [10:10] + read-write + + + PC13_PW + Protection context 13, privileged write enable. + [11:11] + read-write + + + PC13_NS + Protection context 13, non-secure. + [12:12] + read-write + + + PC14_UR + Protection context 14, user read enable. + [16:16] + read-write + + + PC14_UW + Protection context 14, user write enable. + [17:17] + read-write + + + PC14_PR + Protection context 14, privileged read enable. + [18:18] + read-write + + + PC14_PW + Protection context 14, privileged write enable. + [19:19] + read-write + + + PC14_NS + Protection context 14, non-secure. + [20:20] + read-write + + + PC15_UR + Protection context 15, user read enable. + [24:24] + read-write + + + PC15_UW + Protection context 15, user write enable. + [25:25] + read-write + + + PC15_PR + Protection context 15, privileged read enable. + [26:26] + read-write + + + PC15_PW + Protection context 15, privileged write enable. + [27:27] + read-write + + + PC15_NS + Protection context 15, non-secure. + [28:28] + read-write + + + + + MS_ADDR + Master region, base address + 0x20 + 32 + read-only + 0x0 + 0xFFFFFFC0 + + + ADDR26 + This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register. + [31:6] + read-only + + + + + MS_SIZE + Master region, size + 0x24 + 32 + read-only + 0x85000000 + 0x9F000000 + + + REGION_SIZE + This field specifies the size of the master region: +'5': 64 B region + +The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3. + [28:24] + read-only + + + VALID + Master region enable: +'1': Enabled. + [31:31] + read-only + + + + + MS_ATT0 + Master attributes 0 + 0x30 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC0_UR + Protection context 0, user read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-only + + + PC0_UW + Protection context 0, user write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-only + + + PC0_PR + Protection context 0, privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [2:2] + read-only + + + PC0_PW + Protection context 0, privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [3:3] + read-only + + + PC0_NS + Protection context 0, non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [4:4] + read-only + + + PC1_UR + Protection context 1, user read enable. + [8:8] + read-only + + + PC1_UW + Protection context 1, user write enable. + [9:9] + read-write + + + PC1_PR + Protection context 1, privileged read enable. + [10:10] + read-only + + + PC1_PW + Protection context 1, privileged write enable. + [11:11] + read-write + + + PC1_NS + Protection context 1, non-secure. + [12:12] + read-write + + + PC2_UR + Protection context 2, user read enable. + [16:16] + read-only + + + PC2_UW + Protection context 2, user write enable. + [17:17] + read-write + + + PC2_PR + Protection context 2, privileged read enable. + [18:18] + read-only + + + PC2_PW + Protection context 2, privileged write enable. + [19:19] + read-write + + + PC2_NS + Protection context 2, non-secure. + [20:20] + read-write + + + PC3_UR + Protection context 3, user read enable. + [24:24] + read-only + + + PC3_UW + Protection context 3, user write enable. + [25:25] + read-write + + + PC3_PR + Protection context 3, privileged read enable. + [26:26] + read-only + + + PC3_PW + Protection context 3, privileged write enable. + [27:27] + read-write + + + PC3_NS + Protection context 3, non-secure. + [28:28] + read-write + + + + + MS_ATT1 + Master attributes 1 + 0x34 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC4_UR + Protection context 4, user read enable. + [0:0] + read-only + + + PC4_UW + Protection context 4, user write enable. + [1:1] + read-write + + + PC4_PR + Protection context 4, privileged read enable. + [2:2] + read-only + + + PC4_PW + Protection context 4, privileged write enable. + [3:3] + read-write + + + PC4_NS + Protection context 4, non-secure. + [4:4] + read-write + + + PC5_UR + Protection context 5, user read enable. + [8:8] + read-only + + + PC5_UW + Protection context 5, user write enable. + [9:9] + read-write + + + PC5_PR + Protection context 5, privileged read enable. + [10:10] + read-only + + + PC5_PW + Protection context 5, privileged write enable. + [11:11] + read-write + + + PC5_NS + Protection context 5, non-secure. + [12:12] + read-write + + + PC6_UR + Protection context 6, user read enable. + [16:16] + read-only + + + PC6_UW + Protection context 6, user write enable. + [17:17] + read-write + + + PC6_PR + Protection context 6, privileged read enable. + [18:18] + read-only + + + PC6_PW + Protection context 6, privileged write enable. + [19:19] + read-write + + + PC6_NS + Protection context 6, non-secure. + [20:20] + read-write + + + PC7_UR + Protection context 7, user read enable. + [24:24] + read-only + + + PC7_UW + Protection context 7, user write enable. + [25:25] + read-write + + + PC7_PR + Protection context 7, privileged read enable. + [26:26] + read-only + + + PC7_PW + Protection context 7, privileged write enable. + [27:27] + read-write + + + PC7_NS + Protection context 7, non-secure. + [28:28] + read-write + + + + + MS_ATT2 + Master attributes 2 + 0x38 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC8_UR + Protection context 8, user read enable. + [0:0] + read-only + + + PC8_UW + Protection context 8, user write enable. + [1:1] + read-write + + + PC8_PR + Protection context 8, privileged read enable. + [2:2] + read-only + + + PC8_PW + Protection context 8, privileged write enable. + [3:3] + read-write + + + PC8_NS + Protection context 8, non-secure. + [4:4] + read-write + + + PC9_UR + Protection context 9, user read enable. + [8:8] + read-only + + + PC9_UW + Protection context 9, user write enable. + [9:9] + read-write + + + PC9_PR + Protection context 9, privileged read enable. + [10:10] + read-only + + + PC9_PW + Protection context 9, privileged write enable. + [11:11] + read-write + + + PC9_NS + Protection context 9, non-secure. + [12:12] + read-write + + + PC10_UR + Protection context 10, user read enable. + [16:16] + read-only + + + PC10_UW + Protection context 10, user write enable. + [17:17] + read-write + + + PC10_PR + Protection context 10, privileged read enable. + [18:18] + read-only + + + PC10_PW + Protection context 10, privileged write enable. + [19:19] + read-write + + + PC10_NS + Protection context 10, non-secure. + [20:20] + read-write + + + PC11_UR + Protection context 11, user read enable. + [24:24] + read-only + + + PC11_UW + Protection context 11, user write enable. + [25:25] + read-write + + + PC11_PR + Protection context 11, privileged read enable. + [26:26] + read-only + + + PC11_PW + Protection context 11, privileged write enable. + [27:27] + read-write + + + PC11_NS + Protection context 11, non-secure. + [28:28] + read-write + + + + + MS_ATT3 + Master attributes 3 + 0x3C + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC12_UR + Protection context 12, user read enable. + [0:0] + read-only + + + PC12_UW + Protection context 12, user write enable. + [1:1] + read-write + + + PC12_PR + Protection context 12, privileged read enable. + [2:2] + read-only + + + PC12_PW + Protection context 12, privileged write enable. + [3:3] + read-write + + + PC12_NS + Protection context 12, non-secure. + [4:4] + read-write + + + PC13_UR + Protection context 13, user read enable. + [8:8] + read-only + + + PC13_UW + Protection context 13, user write enable. + [9:9] + read-write + + + PC13_PR + Protection context 13, privileged read enable. + [10:10] + read-only + + + PC13_PW + Protection context 13, privileged write enable. + [11:11] + read-write + + + PC13_NS + Protection context 13, non-secure. + [12:12] + read-write + + + PC14_UR + Protection context 14, user read enable. + [16:16] + read-only + + + PC14_UW + Protection context 14, user write enable. + [17:17] + read-write + + + PC14_PR + Protection context 14, privileged read enable. + [18:18] + read-only + + + PC14_PW + Protection context 14, privileged write enable. + [19:19] + read-write + + + PC14_NS + Protection context 14, non-secure. + [20:20] + read-write + + + PC15_UR + Protection context 15, user read enable. + [24:24] + read-only + + + PC15_UW + Protection context 15, user write enable. + [25:25] + read-write + + + PC15_PR + Protection context 15, privileged read enable. + [26:26] + read-only + + + PC15_PW + Protection context 15, privileged write enable. + [27:27] + read-write + + + PC15_NS + Protection context 15, non-secure. + [28:28] + read-write + + + + + + 579 + 64 + PPU_FX[%s] + Fixed protection structure pair + 0x00000800 + + SL_ADDR + Slave region, base address + 0x0 + 32 + read-only + 0x0 + 0xFFFFFFFC + + + ADDR30 + This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's. + [31:2] + read-only + + + + + SL_SIZE + Slave region, size + 0x4 + 32 + read-only + 0x80000000 + 0x9F000000 + + + REGION_SIZE + This field specifies the size of the slave region: +'0': Undefined. +'1': 4 B region (this is the smallest region size). +'2': 8 B region +'3': 16 B region +'4': 32 B region +'5': 64 B region +'6': 128 B region +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'29': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-only + + + VALID + Slave region enable: +'0': Disabled. A disabled region will never result in a match on the transfer address. +'1': Enabled. + [31:31] + read-only + + + + + SL_ATT0 + Slave attributes 0 + 0x10 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC0_UR + Protection context 0, user read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-only + + + PC0_UW + Protection context 0, user write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-only + + + PC0_PR + Protection context 0, privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [2:2] + read-only + + + PC0_PW + Protection context 0, privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [3:3] + read-only + + + PC0_NS + Protection context 0, non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [4:4] + read-only + + + PC1_UR + Protection context 1, user read enable. + [8:8] + read-write + + + PC1_UW + Protection context 1, user write enable. + [9:9] + read-write + + + PC1_PR + Protection context 1, privileged read enable. + [10:10] + read-write + + + PC1_PW + Protection context 1, privileged write enable. + [11:11] + read-write + + + PC1_NS + Protection context 1, non-secure. + [12:12] + read-write + + + PC2_UR + Protection context 2, user read enable. + [16:16] + read-write + + + PC2_UW + Protection context 2, user write enable. + [17:17] + read-write + + + PC2_PR + Protection context 2, privileged read enable. + [18:18] + read-write + + + PC2_PW + Protection context 2, privileged write enable. + [19:19] + read-write + + + PC2_NS + Protection context 2, non-secure. + [20:20] + read-write + + + PC3_UR + Protection context 3, user read enable. + [24:24] + read-write + + + PC3_UW + Protection context 3, user write enable. + [25:25] + read-write + + + PC3_PR + Protection context 3, privileged read enable. + [26:26] + read-write + + + PC3_PW + Protection context 3, privileged write enable. + [27:27] + read-write + + + PC3_NS + Protection context 3, non-secure. + [28:28] + read-write + + + + + SL_ATT1 + Slave attributes 1 + 0x14 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC4_UR + Protection context 4, user read enable. + [0:0] + read-write + + + PC4_UW + Protection context 4, user write enable. + [1:1] + read-write + + + PC4_PR + Protection context 4, privileged read enable. + [2:2] + read-write + + + PC4_PW + Protection context 4, privileged write enable. + [3:3] + read-write + + + PC4_NS + Protection context 4, non-secure. + [4:4] + read-write + + + PC5_UR + Protection context 5, user read enable. + [8:8] + read-write + + + PC5_UW + Protection context 5, user write enable. + [9:9] + read-write + + + PC5_PR + Protection context 5, privileged read enable. + [10:10] + read-write + + + PC5_PW + Protection context 5, privileged write enable. + [11:11] + read-write + + + PC5_NS + Protection context 5, non-secure. + [12:12] + read-write + + + PC6_UR + Protection context 6, user read enable. + [16:16] + read-write + + + PC6_UW + Protection context 6, user write enable. + [17:17] + read-write + + + PC6_PR + Protection context 6, privileged read enable. + [18:18] + read-write + + + PC6_PW + Protection context 6, privileged write enable. + [19:19] + read-write + + + PC6_NS + Protection context 6, non-secure. + [20:20] + read-write + + + PC7_UR + Protection context 7, user read enable. + [24:24] + read-write + + + PC7_UW + Protection context 7, user write enable. + [25:25] + read-write + + + PC7_PR + Protection context 7, privileged read enable. + [26:26] + read-write + + + PC7_PW + Protection context 7, privileged write enable. + [27:27] + read-write + + + PC7_NS + Protection context 7, non-secure. + [28:28] + read-write + + + + + SL_ATT2 + Slave attributes 2 + 0x18 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC8_UR + Protection context 8, user read enable. + [0:0] + read-write + + + PC8_UW + Protection context 8, user write enable. + [1:1] + read-write + + + PC8_PR + Protection context 8, privileged read enable. + [2:2] + read-write + + + PC8_PW + Protection context 8, privileged write enable. + [3:3] + read-write + + + PC8_NS + Protection context 8, non-secure. + [4:4] + read-write + + + PC9_UR + Protection context 9, user read enable. + [8:8] + read-write + + + PC9_UW + Protection context 9, user write enable. + [9:9] + read-write + + + PC9_PR + Protection context 9, privileged read enable. + [10:10] + read-write + + + PC9_PW + Protection context 9, privileged write enable. + [11:11] + read-write + + + PC9_NS + Protection context 9, non-secure. + [12:12] + read-write + + + PC10_UR + Protection context 10, user read enable. + [16:16] + read-write + + + PC10_UW + Protection context 10, user write enable. + [17:17] + read-write + + + PC10_PR + Protection context 10, privileged read enable. + [18:18] + read-write + + + PC10_PW + Protection context 10, privileged write enable. + [19:19] + read-write + + + PC10_NS + Protection context 10, non-secure. + [20:20] + read-write + + + PC11_UR + Protection context 11, user read enable. + [24:24] + read-write + + + PC11_UW + Protection context 11, user write enable. + [25:25] + read-write + + + PC11_PR + Protection context 11, privileged read enable. + [26:26] + read-write + + + PC11_PW + Protection context 11, privileged write enable. + [27:27] + read-write + + + PC11_NS + Protection context 11, non-secure. + [28:28] + read-write + + + + + SL_ATT3 + Slave attributes 3 + 0x1C + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC12_UR + Protection context 12, user read enable. + [0:0] + read-write + + + PC12_UW + Protection context 12, user write enable. + [1:1] + read-write + + + PC12_PR + Protection context 12, privileged read enable. + [2:2] + read-write + + + PC12_PW + Protection context 12, privileged write enable. + [3:3] + read-write + + + PC12_NS + Protection context 12, non-secure. + [4:4] + read-write + + + PC13_UR + Protection context 13, user read enable. + [8:8] + read-write + + + PC13_UW + Protection context 13, user write enable. + [9:9] + read-write + + + PC13_PR + Protection context 13, privileged read enable. + [10:10] + read-write + + + PC13_PW + Protection context 13, privileged write enable. + [11:11] + read-write + + + PC13_NS + Protection context 13, non-secure. + [12:12] + read-write + + + PC14_UR + Protection context 14, user read enable. + [16:16] + read-write + + + PC14_UW + Protection context 14, user write enable. + [17:17] + read-write + + + PC14_PR + Protection context 14, privileged read enable. + [18:18] + read-write + + + PC14_PW + Protection context 14, privileged write enable. + [19:19] + read-write + + + PC14_NS + Protection context 14, non-secure. + [20:20] + read-write + + + PC15_UR + Protection context 15, user read enable. + [24:24] + read-write + + + PC15_UW + Protection context 15, user write enable. + [25:25] + read-write + + + PC15_PR + Protection context 15, privileged read enable. + [26:26] + read-write + + + PC15_PW + Protection context 15, privileged write enable. + [27:27] + read-write + + + PC15_NS + Protection context 15, non-secure. + [28:28] + read-write + + + + + MS_ADDR + Master region, base address + 0x20 + 32 + read-only + 0x0 + 0xFFFFFFC0 + + + ADDR26 + This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register. + [31:6] + read-only + + + + + MS_SIZE + Master region, size + 0x24 + 32 + read-only + 0x85000000 + 0x9F000000 + + + REGION_SIZE + This field specifies the size of the master region: +'5': 64 B region + +The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3. + [28:24] + read-only + + + VALID + Master region enable: +'1': Enabled. + [31:31] + read-only + + + + + MS_ATT0 + Master attributes 0 + 0x30 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC0_UR + Protection context 0, user read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-only + + + PC0_UW + Protection context 0, user write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-only + + + PC0_PR + Protection context 0, privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [2:2] + read-only + + + PC0_PW + Protection context 0, privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [3:3] + read-only + + + PC0_NS + Protection context 0, non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [4:4] + read-only + + + PC1_UR + Protection context 1, user read enable. + [8:8] + read-only + + + PC1_UW + Protection context 1, user write enable. + [9:9] + read-write + + + PC1_PR + Protection context 1, privileged read enable. + [10:10] + read-only + + + PC1_PW + Protection context 1, privileged write enable. + [11:11] + read-write + + + PC1_NS + Protection context 1, non-secure. + [12:12] + read-write + + + PC2_UR + Protection context 2, user read enable. + [16:16] + read-only + + + PC2_UW + Protection context 2, user write enable. + [17:17] + read-write + + + PC2_PR + Protection context 2, privileged read enable. + [18:18] + read-only + + + PC2_PW + Protection context 2, privileged write enable. + [19:19] + read-write + + + PC2_NS + Protection context 2, non-secure. + [20:20] + read-write + + + PC3_UR + Protection context 3, user read enable. + [24:24] + read-only + + + PC3_UW + Protection context 3, user write enable. + [25:25] + read-write + + + PC3_PR + Protection context 3, privileged read enable. + [26:26] + read-only + + + PC3_PW + Protection context 3, privileged write enable. + [27:27] + read-write + + + PC3_NS + Protection context 3, non-secure. + [28:28] + read-write + + + + + MS_ATT1 + Master attributes 1 + 0x34 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC4_UR + Protection context 4, user read enable. + [0:0] + read-only + + + PC4_UW + Protection context 4, user write enable. + [1:1] + read-write + + + PC4_PR + Protection context 4, privileged read enable. + [2:2] + read-only + + + PC4_PW + Protection context 4, privileged write enable. + [3:3] + read-write + + + PC4_NS + Protection context 4, non-secure. + [4:4] + read-write + + + PC5_UR + Protection context 5, user read enable. + [8:8] + read-only + + + PC5_UW + Protection context 5, user write enable. + [9:9] + read-write + + + PC5_PR + Protection context 5, privileged read enable. + [10:10] + read-only + + + PC5_PW + Protection context 5, privileged write enable. + [11:11] + read-write + + + PC5_NS + Protection context 5, non-secure. + [12:12] + read-write + + + PC6_UR + Protection context 6, user read enable. + [16:16] + read-only + + + PC6_UW + Protection context 6, user write enable. + [17:17] + read-write + + + PC6_PR + Protection context 6, privileged read enable. + [18:18] + read-only + + + PC6_PW + Protection context 6, privileged write enable. + [19:19] + read-write + + + PC6_NS + Protection context 6, non-secure. + [20:20] + read-write + + + PC7_UR + Protection context 7, user read enable. + [24:24] + read-only + + + PC7_UW + Protection context 7, user write enable. + [25:25] + read-write + + + PC7_PR + Protection context 7, privileged read enable. + [26:26] + read-only + + + PC7_PW + Protection context 7, privileged write enable. + [27:27] + read-write + + + PC7_NS + Protection context 7, non-secure. + [28:28] + read-write + + + + + MS_ATT2 + Master attributes 2 + 0x38 + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC8_UR + Protection context 8, user read enable. + [0:0] + read-only + + + PC8_UW + Protection context 8, user write enable. + [1:1] + read-write + + + PC8_PR + Protection context 8, privileged read enable. + [2:2] + read-only + + + PC8_PW + Protection context 8, privileged write enable. + [3:3] + read-write + + + PC8_NS + Protection context 8, non-secure. + [4:4] + read-write + + + PC9_UR + Protection context 9, user read enable. + [8:8] + read-only + + + PC9_UW + Protection context 9, user write enable. + [9:9] + read-write + + + PC9_PR + Protection context 9, privileged read enable. + [10:10] + read-only + + + PC9_PW + Protection context 9, privileged write enable. + [11:11] + read-write + + + PC9_NS + Protection context 9, non-secure. + [12:12] + read-write + + + PC10_UR + Protection context 10, user read enable. + [16:16] + read-only + + + PC10_UW + Protection context 10, user write enable. + [17:17] + read-write + + + PC10_PR + Protection context 10, privileged read enable. + [18:18] + read-only + + + PC10_PW + Protection context 10, privileged write enable. + [19:19] + read-write + + + PC10_NS + Protection context 10, non-secure. + [20:20] + read-write + + + PC11_UR + Protection context 11, user read enable. + [24:24] + read-only + + + PC11_UW + Protection context 11, user write enable. + [25:25] + read-write + + + PC11_PR + Protection context 11, privileged read enable. + [26:26] + read-only + + + PC11_PW + Protection context 11, privileged write enable. + [27:27] + read-write + + + PC11_NS + Protection context 11, non-secure. + [28:28] + read-write + + + + + MS_ATT3 + Master attributes 3 + 0x3C + 32 + read-write + 0x1F1F1F1F + 0x1F1F1F1F + + + PC12_UR + Protection context 12, user read enable. + [0:0] + read-only + + + PC12_UW + Protection context 12, user write enable. + [1:1] + read-write + + + PC12_PR + Protection context 12, privileged read enable. + [2:2] + read-only + + + PC12_PW + Protection context 12, privileged write enable. + [3:3] + read-write + + + PC12_NS + Protection context 12, non-secure. + [4:4] + read-write + + + PC13_UR + Protection context 13, user read enable. + [8:8] + read-only + + + PC13_UW + Protection context 13, user write enable. + [9:9] + read-write + + + PC13_PR + Protection context 13, privileged read enable. + [10:10] + read-only + + + PC13_PW + Protection context 13, privileged write enable. + [11:11] + read-write + + + PC13_NS + Protection context 13, non-secure. + [12:12] + read-write + + + PC14_UR + Protection context 14, user read enable. + [16:16] + read-only + + + PC14_UW + Protection context 14, user write enable. + [17:17] + read-write + + + PC14_PR + Protection context 14, privileged read enable. + [18:18] + read-only + + + PC14_PW + Protection context 14, privileged write enable. + [19:19] + read-write + + + PC14_NS + Protection context 14, non-secure. + [20:20] + read-write + + + PC15_UR + Protection context 15, user read enable. + [24:24] + read-only + + + PC15_UW + Protection context 15, user write enable. + [25:25] + read-write + + + PC15_PR + Protection context 15, privileged read enable. + [26:26] + read-only + + + PC15_PW + Protection context 15, privileged write enable. + [27:27] + read-write + + + PC15_NS + Protection context 15, non-secure. + [28:28] + read-write + + + + + + + + PERI_PCLK + Peripheral PCLK groups + 0x40040000 + + 0 + 131072 + registers + + + + 2 + 8192 + GR[%s] + PERI clock domains + 0x00000000 + + DIV_CMD + Divider command + 0x0 + 32 + read-write + 0x3FF03FF + 0xC3FF03FF + + + DIV_SEL + (TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed. + +If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated. + [7:0] + read-write + + + TYPE_SEL + Specifies the divider type of the divider on which the command is performed: +0: 8.0 (integer) clock dividers. +1: 16.0 (integer) clock dividers. +2: 16.5 (fractional) clock dividers. +3: 24.5 (fractional) clock dividers. + [9:8] + read-write + + + PA_DIV_SEL + (PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times. + +If PA_DIV_SEL is '255' and PA_TYPE_SEL is '3', 'clk_pclk_root[i]' is used as reference. + [23:16] + read-write + + + PA_TYPE_SEL + Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: +0: 8.0 (integer) clock dividers. +1: 16.0 (integer) clock dividers. +2: 16.5 (fractional) clock dividers. +3: 24.5 (fractional) clock dividers. + [25:24] + read-write + + + DISABLE + Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'. + +The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled. + +The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately. + [30:30] + read-write + + + ENABLE + Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: +0: Disable the divider using the DIV_CMD.DISABLE field. +1: Configure the divider's DIV_XXX_CTL register. +2: Enable the divider using the DIV_CMD_ENABLE field. + +The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_pclk_root[i]' (typical usage) or to ANY enabled divider. + +The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider. + +The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_pclk_root[i]'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_pclk_root[i]' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process. + [31:31] + read-write + + + + + 256 + 4 + CLOCK_CTL[%s] + Clock control + 0xC00 + 32 + read-write + 0x3FF + 0x3FF + + + DIV_SEL + Specifies one of the dividers of the divider type specified by TYPE_SEL. + +If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. + +When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_pclk_root[i]' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods. + [7:0] + read-write + + + TYPE_SEL + Specifies divider type: +0: 8.0 (integer) clock dividers. +1: 16.0 (integer) clock dividers. +2: 16.5 (fractional) clock dividers. +3: 24.5 (fractional) clock dividers. + [9:8] + read-write + + + + + 256 + 4 + DIV_8_CTL[%s] + Divider control (for 8.0 divider) + 0x1000 + 32 + read-write + 0x0 + 0xFF01 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + INT8_DIV + Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. + +For the generation of a divided clock, the integer division range is restricted to [2, 256]. + +For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + 256 + 4 + DIV_16_CTL[%s] + Divider control (for 16.0 divider) + 0x1400 + 32 + read-write + 0x0 + 0xFFFF01 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + INT16_DIV + Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. + +For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. + +For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [23:8] + read-write + + + + + 256 + 4 + DIV_16_5_CTL[%s] + Divider control (for 16.5 divider) + 0x1800 + 32 + read-write + 0x0 + 0xFFFFF9 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + FRAC5_DIV + Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_pclk_root[i]' cycle longer than other clock periods. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [7:3] + read-write + + + INT16_DIV + Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. + +For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. + +For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [23:8] + read-write + + + + + 255 + 4 + DIV_24_5_CTL[%s] + Divider control (for 24.5 divider) + 0x1C00 + 32 + read-write + 0x0 + 0xFFFFFFF9 + + + EN + Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. + +Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. + [0:0] + read-only + + + FRAC5_DIV + Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_pclk_root[i]' cycle longer than other clock periods. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [7:3] + read-write + + + INT24_DIV + Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. + +For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. + +For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [31:8] + read-write + + + + + + + + CRYPTO + Cryptography component + 0x40100000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x10002 + 0x800300F3 + + + P + User/privileged access control: +'0': user mode. +'1': privileged mode. + +This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. + +All IP master transactions use the P field for the user/privileged access control ('hprot[1]'). + [0:0] + read-write + + + NS + Secure/on-secure access control: +'0': secure. +'1': non-secure. + +This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. + +All IP master transactions use the NS field for the secure/non-secure access control ('hprot[4]'). + [1:1] + read-write + + + PC + Protection context. + +This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data. + +All IP master transactions use the PC field for the protection context. There is one exception: the LOAD_DEV_KEY instruction IP master transactions are always performed with protection context '0'. + [7:4] + read-write + + + ECC_EN + Enable ECC checking: +'0': Disabled. +'1': Enabled. + [16:16] + read-write + + + ECC_INJ_EN + Enable parity injection for SRAM. +When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM. + [17:17] + read-write + + + ENABLED + IP enable: +'0': Disabled. All non-retention registers (command and status registers, instruct FIFO, internal component state machines) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. +'1': Enabled. When the IP is enabled, the IP register buffer is set to '0'. + [31:31] + read-write + + + DISABLED + N/A + 0 + + + ENABLED + N/A + 1 + + + + + + + RAM_PWR_CTL + SRAM power control + 0x8 + 32 + read-write + 0x3 + 0x3 + + + PWR_MODE + Set power mode for memory buffer SRAM. + [1:0] + read-write + + + OFF + See CM4_PWR_CTL + 0 + + + RSVD + undefined + 1 + + + RETAINED + See CM4_PWR_CTL + 2 + + + ENABLED + See CM4_PWR_CTL + 3 + + + + + + + RAM_PWR_DELAY_CTL + SRAM power delay control + 0xC + 32 + read-write + 0x96 + 0x3FF + + + UP + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + ECC_CTL + ECC control + 0x10 + 32 + read-write + 0x0 + 0xFE001FFF + + + WORD_ADDR + Specifies the word address where the parity is injected. +- On a 32-bit write access to this SRAM address and when CTL.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. + [12:0] + read-write + + + PARITY + ECC parity to use for ECC error injection at address WORD_ADDR. + [31:25] + read-write + + + + + ERROR_STATUS0 + Error status 0 + 0x20 + 32 + read-only + 0x0 + 0x0 + + + DATA32 + Specifies error description information. +- For INSTR_OPC_ERROR/ INSTR_CC_ERROR/ INSTR_DEV_KEY_ERROR: + - Violating instruction (from instruction FIFO). +- For BUS_ERROR: + - Violating transfer, address. + [31:0] + read-only + + + + + ERROR_STATUS1 + Error status 1 + 0x24 + 32 + read-write + 0x0 + 0x80000000 + + + DATA24 + Specifies error description information. +- For BUS_ERROR: + - Violating transfer, read attribute (DATA[0]). + - Violating transfer, size attribute (DATA[5:4]). '0': 8-bit transfer, '1': 16 bits transfer, '2': 32-bit transfer. + [23:0] + read-only + + + IDX + Error source: +'0': INSTR_OPC_ERROR (instruction FIFO decoder error). +'1': INSTR_CC_ERROR (instruction FIFO decoder, VU CC error). +'2': BUS_ERROR (bus master interface AHB-Lite bus error). +'3': TR_AP_DETECT_ERROR. +'4': TR_RC_DETECT_ERROR. +'5': INSTR_DEV_KEY_ERROR. +'6'-'7': Undefined. + [26:24] + read-only + + + VALID + Specifies if ERROR_STATUS0 and ERROR_STATUS1 specify valid error information. No new error information is captured as long as VALID is '1'; i.e. the error information of the first detected error is NOT overwritten. + [31:31] + read-write + + + + + INTR + Interrupt register + 0x100 + 32 + read-write + 0x0 + 0x3F001F + + + INSTR_FF_LEVEL + This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO event is activated. + [0:0] + read-write + + + INSTR_FF_OVERFLOW + This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO overflows (an attempt is made to write to a full FIFO). + [1:1] + read-write + + + TR_INITIALIZED + This interrupt cause is activated (HW sets the field to '1') when the true random number generator is initialized. + [2:2] + read-write + + + TR_DATA_AVAILABLE + This interrupt cause is activated (HW sets the field to '1') when the true random number generator has generated a data value of the specified bit size. + [3:3] + read-write + + + PR_DATA_AVAILABLE + This interrupt cause is activated (HW sets the field to '1') when the pseudo random number generator has generated a data value. + [4:4] + read-write + + + INSTR_OPC_ERROR + This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined operation code (opcode). + +When the interrupt cause is activated, HW sets INSTR_FF_CTL.CLEAR to '1'. + [16:16] + read-write + + + INSTR_CC_ERROR + This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined condition code. This error is only generated for VU instructions. + +When the interrupt cause is activated, HW sets INSTR_FF_CTL.CLEAR to '1'. + [17:17] + read-write + + + BUS_ERROR + This interrupt cause is activated (HW sets the field to '1') when a AHB-Lite bus error is observed on the AHB-Lite master interface. + +When the interrupt cause is activated, HW sets INSTR_FF_CTL.CLEAR to '1'. + [18:18] + read-write + + + TR_AP_DETECT_ERROR + This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a repetition of a specific bit value. + [19:19] + read-write + + + TR_RC_DETECT_ERROR + This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a disproportionate occurrence of a specific bit value. + [20:20] + read-write + + + INSTR_DEV_KEY_ERROR + This interrupt cause is activated (HW sets the field to '1') when the LOAD_DEV_KEY instruction tries to load a device key whose DEV_KEY_ADDR_CTL.VALID or DEV_KEY_CTL.ALLOWED is set to '0'. + [21:21] + read-write + + + + + INTR_SET + Interrupt set register + 0x104 + 32 + read-write + 0x0 + 0x3F001F + + + INSTR_FF_LEVEL + SW writes a '1' to this field to set the corresponding field in interrupt request register. + [0:0] + read-write + + + INSTR_FF_OVERFLOW + SW writes a '1' to this field to set the corresponding field in interrupt request register. + [1:1] + read-write + + + TR_INITIALIZED + SW writes a '1' to this field to set the corresponding field in interrupt request register. + [2:2] + read-write + + + TR_DATA_AVAILABLE + SW writes a '1' to this field to set the corresponding field in interrupt request register. + [3:3] + read-write + + + PR_DATA_AVAILABLE + SW writes a '1' to this field to set the corresponding field in interrupt request register. + [4:4] + read-write + + + INSTR_OPC_ERROR + SW writes a '1' to this field to set the corresponding field in interrupt request register. + [16:16] + read-write + + + INSTR_CC_ERROR + SW writes a '1' to this field to set the corresponding field in interrupt request register. + [17:17] + read-write + + + BUS_ERROR + SW writes a '1' to this field to set the corresponding field in interrupt request register. + [18:18] + read-write + + + TR_AP_DETECT_ERROR + SW writes a '1' to this field to set the corresponding field in interrupt request register. + [19:19] + read-write + + + TR_RC_DETECT_ERROR + SW writes a '1' to this field to set the corresponding field in interrupt request register. + [20:20] + read-write + + + INSTR_DEV_KEY_ERROR + SW writes a '1' to this field to set the corresponding field in interrupt request register. + [21:21] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x108 + 32 + read-write + 0x0 + 0x3F001F + + + INSTR_FF_LEVEL + Mask bit for corresponding field in interrupt request register. + [0:0] + read-write + + + INSTR_FF_OVERFLOW + Mask bit for corresponding field in interrupt request register. + [1:1] + read-write + + + TR_INITIALIZED + Mask bit for corresponding field in interrupt request register. + [2:2] + read-write + + + TR_DATA_AVAILABLE + Mask bit for corresponding field in interrupt request register. + [3:3] + read-write + + + PR_DATA_AVAILABLE + Mask bit for corresponding field in interrupt request register. + [4:4] + read-write + + + INSTR_OPC_ERROR + Mask bit for corresponding field in interrupt request register. + [16:16] + read-write + + + INSTR_CC_ERROR + Mask bit for corresponding field in interrupt request register. + [17:17] + read-write + + + BUS_ERROR + Mask bit for corresponding field in interrupt request register. + [18:18] + read-write + + + TR_AP_DETECT_ERROR + Mask bit for corresponding field in interrupt request register. + [19:19] + read-write + + + TR_RC_DETECT_ERROR + Mask bit for corresponding field in interrupt request register. + [20:20] + read-write + + + INSTR_DEV_KEY_ERROR + Mask bit for corresponding field in interrupt request register. + [21:21] + read-write + + + + + INTR_MASKED + Interrupt masked register + 0x10C + 32 + read-only + 0x0 + 0x3F001F + + + INSTR_FF_LEVEL + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + INSTR_FF_OVERFLOW + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + TR_INITIALIZED + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + TR_DATA_AVAILABLE + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + PR_DATA_AVAILABLE + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + INSTR_OPC_ERROR + Logical and of corresponding request and mask bits. + [16:16] + read-only + + + INSTR_CC_ERROR + Logical and of corresponding request and mask bits. + [17:17] + read-only + + + BUS_ERROR + Logical and of corresponding request and mask bits. + [18:18] + read-only + + + TR_AP_DETECT_ERROR + Logical and of corresponding request and mask bits. + [19:19] + read-only + + + TR_RC_DETECT_ERROR + Logical and of corresponding request and mask bits. + [20:20] + read-only + + + INSTR_DEV_KEY_ERROR + Logical and of corresponding request and mask bits. + [21:21] + read-only + + + + + PR_LFSR_CTL0 + Pseudo random LFSR control 0 + 0x200 + 32 + read-write + 0xD8959BC9 + 0xFFFFFFFF + + + LFSR32 + State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. This register needs to be initialized by SW. The initialization value should be different from '0'. + +The three PR_LFSR_CTL registers represents the state of a 32-bit, 31-bit and 29-bit LFSR. Individually, these LFSRs generate a pseudo random bit sequence that repeats itself after (2^32)-1, (2^31)-1 and (2^29)-1 bits. The numbers (2^32)-1, (2^31)-1 and (2^29)-1 are relatively prime (their greatest common denominator is '1'). The three bit sequence are combined (XOR'd) into a single bitstream to create a pseudo random bit sequence that repeats itself after ((2^32)-1) * ((2^31)-1) * ((2*29)-1) bits. + +The following polynomials are used: +- 32-bit irreducible polynomial: x^32+x^30+x^26+x^25+1. +- 31-bit irreducible polynomial: x^31+x^28+1. +- 29-bit irreducible polynomial: x^29+x^27+1. + [31:0] + read-write + + + + + PR_LFSR_CTL1 + Pseudo random LFSR control 1 + 0x204 + 32 + read-write + 0x2BB911F8 + 0x7FFFFFFF + + + LFSR31 + State of a 31-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. See PR_LFSR_CTL0. + [30:0] + read-write + + + + + PR_LFSR_CTL2 + Pseudo random LFSR control 2 + 0x208 + 32 + read-write + 0x60C31B7 + 0x1FFFFFFF + + + LFSR29 + State of a 29-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. See PR_LFSR_CTL0. + [28:0] + read-write + + + + + PR_MAX_CTL + Pseudo random maximum control + 0x20C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + DATA32 + Maximum value of to be generated random number + [31:0] + read-write + + + + + PR_CMD + Pseudo random command + 0x210 + 32 + read-write + 0x0 + 0x1 + + + START + Pseudo random command. On a generated number, HW sets this field to '0' and sets INTR.PR_DATA_AVAILABLE to '1. + [0:0] + read-write + + + + + PR_RESULT + Pseudo random result + 0x218 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA32 + Result of a pseudo random number generation operation. The resulting value DATA is in the range [0, PR_MAX_CTL.DATA32]. The PR_DATA_AVAILABLE interrupt cause is activated when the number is generated. + +Note that SW can write this field. This functionality can be used prevent information leakage. + [31:0] + read-write + + + + + TR_CTL0 + True random control 0 + 0x280 + 32 + read-write + 0x30000 + 0x31FFFFFF + + + SAMPLE_CLOCK_DIV + Specifies the clock divider that is used to sample oscillator data. This clock divider is wrt. 'clk_sys'. +'0': sample clock is 'clk_sys'. +'1': sample clock is 'clk_sys'/2. +... +'255': sample clock is 'clk_sys'/256. + [7:0] + read-write + + + RED_CLOCK_DIV + Specifies the clock divider that is used to produce reduced bits. +'0': 1 reduced bit is produced for each sample. +'1': 1 reduced bit is produced for each 2 samples. +... +'255': 1 reduced bit is produced for each 256 samples. + +The reduced bits are considered random bits and shifted into TR_RESULT0.DATA32. + [15:8] + read-write + + + INIT_DELAY + Specifies an initialization delay: number of removed/dropped samples before reduced bits are generated. This field should be programmed in the range [1, 255]. After starting the oscillators, at least the first 2 samples should be removed/dropped to clear the state of internal synchronizers. In addition, it is advised to drop at least the second 2 samples from the oscillators (to circumvent the semi-predictable oscillator startup behavior). This result in the default field value of '3'. Field encoding is as follows: +'0': 1 sample is dropped. +'1': 2 samples are dropped. +... +'255': 256 samples are dropped. + +The TR_INITIALIZED interrupt cause is set to '1', when the initialization delay is passed. + [23:16] + read-write + + + VON_NEUMANN_CORR + Specifies if the 'von Neumann corrector' is disabled or enabled: +'0': disabled. +'1': enabled. +The 'von Neumann corrector' post-processes the reduced bits to remove a '0' or '1' bias. The corrector operates on reduced bit pairs ('oldest bit, newest bit'): +'00': no bit is produced. +'01': '0' bit is produced (oldest bit). +'10': '1' bit is produced (oldest bit). +'11': no bit is produced. +Note that the corrector produces bits at a random pace and at a frequency that is 1/4 of the reduced bit frequency (reduced bits are processed in pairs, and half of the pairs do NOT produce a bit). + [24:24] + read-write + + + STOP_ON_AP_DETECT + Specifies if TRNG functionality is stopped on an adaptive proportion test detection (when HW sets INTR.TR_AP_DETECT to '1'): +'0': Functionality is NOT stopped. +'1': Functionality is stopped (TR_CTL1 fields are set to '0' by HW). + [28:28] + read-write + + + STOP_ON_RC_DETECT + Specifies if TRNG functionality is stopped on a repetition count test detection (when HW sets INTR.TR_RC_DETECT to '1'): +'0': Functionality is NOT stopped. +'1': Functionality is stopped (TR_CTL1 fields are set to '0' by HW). + [29:29] + read-write + + + + + TR_CTL1 + True random control 1 + 0x284 + 32 + read-write + 0x0 + 0x3F + + + RO11_EN + FW sets this field to '1' to enable the ring oscillator with 11 inverters. + [0:0] + read-write + + + RO15_EN + FW sets this field to '1' to enable the ring oscillator with 15 inverters. + [1:1] + read-write + + + GARO15_EN + FW sets this field to '1' to enable the fixed Galois ring oscillator with 15 inverters. + [2:2] + read-write + + + GARO31_EN + FW sets this field to '1' to enable the programmable Galois ring oscillator with up to 31 inverters. The TR_GARO_CTL register specifies the programmable polynomial. + [3:3] + read-write + + + FIRO15_EN + FW sets this field to '1' to enable the fixed Fibonacci ring oscillator with 15 inverters. + [4:4] + read-write + + + FIRO31_EN + FW sets this field to '1' to enable the programmable Fibonacci ring oscillator with up to 31 inverters. The TR_FIRO_CTL register specifies the programmable polynomial. + [5:5] + read-write + + + + + TR_CTL2 + True random control 2 + 0x288 + 32 + read-write + 0x0 + 0x3F + + + SIZE + Bit size of generated random number in TR_RESULT. Legal range is in [0, 32]. + [5:0] + read-write + + + + + TR_STATUS + True random status + 0x28C + 32 + read-only + 0x0 + 0x1 + + + INITIALIZED + Reflects the state of the true random number generator: +'0': Not initialized (TR_CTL0.INIT_DELAY has NOT passed). +'1': Initialized (TR_CTL0.INIT_DELAY has passed). + [0:0] + read-only + + + + + TR_CMD + True random command + 0x290 + 32 + read-write + 0x0 + 0x1 + + + START + True random command. On completion of the command, HW sets this field to '0' and sets INTR.TR_DATA_AVAILABLE to '1 when: +- A random number is generated in TR_RESULT. +- All ring oscillators are off (per TR_CTL1). +- A repetition count (RC) or adaptive proportion (AP) error is detected during the random number generation (INTR.TR_RC/AP_DETECT_ERROR). + +Note: On completion of the command, SW should check TR_CTL1 and INTR.TR_RC/AP_DETECT_ERROR to ensure that no unexpected error occurred during random number generation. + [0:0] + read-write + + + + + TR_RESULT + True random result + 0x298 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA32 + Generated true random number. HW generates the number in the least significant bit positions (TR_CTL2.SIZE) of this field. The TR_DATA_AVAILABLE interrupt cause is activated when the number is generated. + +Note that SW can write this field. This functionality can be used prevent information leakage. + [31:0] + read-write + + + + + TR_GARO_CTL + True random GARO control + 0x2A0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + POLYNOMIAL31 + Polynomial for programmable Galois ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. + [30:0] + read-write + + + + + TR_FIRO_CTL + True random FIRO control + 0x2A4 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + POLYNOMIAL31 + Polynomial for programmable Fibonacci ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. + [30:0] + read-write + + + + + TR_MON_CTL + True random monitor control + 0x2C0 + 32 + read-write + 0x2 + 0x3 + + + BITSTREAM_SEL + Selection of the bitstream: +'0': DAS bitstream. +'1': RED bitstream. +'2': TR bitstream. +'3': Undefined. + [1:0] + read-write + + + + + TR_MON_CMD + True random monitor command + 0x2C8 + 32 + read-write + 0x0 + 0x3 + + + START_AP + Adaptive proportion (AP) test enable: +'0': Stopped. +'1': Started. + +On a AP detection, HW sets this field to '0' and sets INTR.TR_AP_DETECT to '1. + [0:0] + read-write + + + START_RC + Repetition count (RC) test enable: +'0': Disabled. +'1': Enabled. + +On a RC detection, HW sets this field to '0' and sets INTR.TR_RC_DETECT to '1. + [1:1] + read-write + + + + + TR_MON_RC_CTL + True random monitor RC control + 0x2D0 + 32 + read-write + 0xFF + 0xFF + + + CUTOFF_COUNT8 + Cutoff count (legal range is [1, 255]): +'0': Illegal. +'1': 1 repetition. +... +'255': 255 repetitions. + [7:0] + read-write + + + + + TR_MON_RC_STATUS0 + True random monitor RC status 0 + 0x2D8 + 32 + read-only + 0x0 + 0x1 + + + BIT + Current active bit value: +'0': '0'. +'1': '1'. + +This field is only valid when TR_MON_RC_STATUS1.REP_COUNT is NOT equal to '0'. + [0:0] + read-only + + + + + TR_MON_RC_STATUS1 + True random monitor RC status 1 + 0x2DC + 32 + read-only + 0x0 + 0xFF + + + REP_COUNT + Number of repetitions of the current active bit counter: +'0': 0 repetitions. +... +'255': 255 repetitions. + [7:0] + read-only + + + + + TR_MON_AP_CTL + True random monitor AP control + 0x2E0 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CUTOFF_COUNT16 + Cutoff count (legal range is [1, 65535]). +'0': Illegal. +'1': 1 occurrence. +... +'65535': 65535 occurrences. + [15:0] + read-write + + + WINDOW_SIZE + Window size (minus 1) : +'0': 1 bit. +... +'65535': 65536 bits. + [31:16] + read-write + + + + + TR_MON_AP_STATUS0 + True random monitor AP status 0 + 0x2E8 + 32 + read-only + 0x0 + 0x1 + + + BIT + Current active bit value: +'0': '0'. +'1': '1'. + +This field is only valid when TR_MON_AP_STATUS1.OCC_COUNT is NOT equal to '0'. + [0:0] + read-only + + + + + TR_MON_AP_STATUS1 + True random monitor AP status 1 + 0x2EC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + OCC_COUNT + Number of occurrences of the current active bit counter: +'0': 0 occurrences +... +'65535': 65535 occurrences + [15:0] + read-only + + + WINDOW_INDEX + Counter to keep track of the current index in the window (counts from '0' to TR_MON_AP_CTL.WINDOW_SIZE to '0'). + [31:16] + read-only + + + + + STATUS + Status + 0x1004 + 32 + read-only + 0x0 + 0x80000000 + + + BUSY + Reflects the state of the IP: +'0': Idle/no busy. +'1': Busy: + - Instruction is pending in the instruction FIFO. + - Instruction is busy in a IP component (e.g. SHA1, SHA2, SHA3, DES, TDES, AES, CHACHA, ...). + - Store FIFO is busy. + - TR or PR command is busy. + [31:31] + read-only + + + + + INSTR_FF_CTL + Instruction FIFO control + 0x1040 + 32 + read-write + 0x20000 + 0x30007 + + + EVENT_LEVEL + Event level. When the number of entries in the instruction FIFO is less than the amount of this field, an event is generated: +- 'event' = INSTR_FF_STATUS.USED < EVENT_LEVEL. + [2:0] + read-write + + + CLEAR + When '1', the instruction FIFO is cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + +HW sets this field to '1' on when a INSTR_OPC_ERROR, INSTR_CC_ERROR or BUS_ERROR interrupt cause is activated. + [16:16] + read-write + + + BLOCK + This field specifies the behavior when an instruction is written to a full FIFO (INSTR_FIFO_WR MMIO register): +'0': The write is ignored/dropped and the INTR.INSTR_FF_OVERFLOW interrupt cause is set to '1'. +'1': The write is blocked, resulting in AHB-Lite wait states and the INTR.INSTR_FF_OVERFLOW interrupt cause is set to '1' (this cause may be masked out). The instruction is written to the FIFO as soon as a FIFO entry becomes available. The maximum time is roughly the time of the execution of the slowest/longest instruction. Note that this setting may 'lock up' /stall the CPU. When the CPU is 'locked up'/stalled it can not respond to any system interrupts. As a result, the interrupt latency is increased. Note that this may not be an issue if the associated CPU is only performing cryptography functionality, e.g. the CM0+ during boot time. + [17:17] + read-write + + + + + INSTR_FF_STATUS + Instruction FIFO status + 0x1044 + 32 + read-only + 0x0 + 0x1000F + + + USED + Number of instructions in the instruction FIFO. The value of this field ranges from 0 to 8. + [3:0] + read-only + + + EVENT + Instruction FIFO event. + [16:16] + read-only + + + + + INSTR_FF_WR + Instruction FIFO write + 0x1048 + 32 + write-only + 0x0 + 0xFFFFFFFF + + + DATA32 + Instruction or instruction operand data that is written to the instruction FIFO. + [31:0] + write-only + + + + + LOAD0_FF_STATUS + Load 0 FIFO status + 0x10C0 + 32 + read-only + 0x0 + 0x8000001F + + + USED5 + Number of Bytes in the FIFO. The value of this field is in the range [0, 19]. + [4:0] + read-only + + + BUSY + Reflects the state of the FIFO: +'0': FIFO load engine is idle and a new FIFO instruction can be accepted. +'1': FIFO load engine is busy and NO new FIFO instruction can be accepted. + [31:31] + read-only + + + + + LOAD1_FF_STATUS + Load 1 FIFO status + 0x10D0 + 32 + read-only + 0x0 + 0x8000001F + + + USED5 + See LOAD1_FF_STATUS.USED. + [4:0] + read-only + + + BUSY + See LOAD1_FF_STATUS.BUSY. + [31:31] + read-only + + + + + STORE_FF_STATUS + Store FIFO status + 0x10F0 + 32 + read-only + 0x0 + 0x8000001F + + + USED5 + Number of Bytes in the FIFO. The value of this field is in the range [0, 16]. + [4:0] + read-only + + + BUSY + Reflects the state of the FIFO: +'0': FIFO store engine is idle and a new FIFO instruction can be accepted (USED is '0'). +'1': FIFO store engine is busy and NO new FIFO instruction can be accepted. + [31:31] + read-only + + + + + AES_CTL + AES control + 0x1100 + 32 + read-write + 0x0 + 0x3 + + + KEY_SIZE + AES key size: +'0': 128-bit key, 10 rounds AES (inverse) cipher operation. +'1': 192-bit key, 12 rounds AES (inverse) cipher operation. +'2': 256-bit key, 14 rounds AES (inverse) cipher operation. +'3': Undefined + [1:0] + read-write + + + AES128 + N/A + 0 + + + AES192 + N/A + 1 + + + AES256 + N/A + 2 + + + + + + + RESULT + Result + 0x1180 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + BLOCK_CMP operation (DATA[0]): +'0': source 0 equals source 1. +'1': source 0 does NOT equal source 1. + +CRC operation (DATA[31:0]). State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value. + +The seed value should be aligned such that the more significant bits (bit 31 and down) contain the seed value and the less significant bits (bit 0 and up) contain padding '0's. + +Note that SW can write this field. This functionality can be used prevent information leakage. + [31:0] + read-write + + + + + CRC_CTL + CRC control + 0x1400 + 32 + read-write + 0x0 + 0x101 + + + DATA_REVERSE + Specifies the bit order in which a data Byte is processed (reversal is performed after XORing): +'0': Most significant bit (bit 1) first. +'1': Least significant bit (bit 0) first. + [0:0] + read-write + + + REM_REVERSE + Specifies whether the remainder is bit reversed (reversal is performed after XORing): +'0': No. +'1': Yes. + [8:8] + read-write + + + + + CRC_DATA_CTL + CRC data control + 0x1410 + 32 + read-write + 0x0 + 0xFF + + + DATA_XOR + Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal. + [7:0] + read-write + + + + + CRC_POL_CTL + CRC polynomial control + 0x1420 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + POLYNOMIAL + CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials: +- CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1). +- CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions). +- CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions). + [31:0] + read-write + + + + + CRC_REM_CTL + CRC remainder control + 0x1440 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + REM_XOR + Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal. + [31:0] + read-write + + + + + CRC_REM_RESULT + CRC remainder result + 0x1448 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REM + Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE: +'0': the more significant bits (bit 31 and down) contain the remainder. +'1': the less significant bits (bit 0 and up) contain the remainder. + +Note: This field is combinatorially derived from CRC_LFSR_CTL.LFSR32, CRC_REM_CTL0.REM_REVERSE and CRC_REM_CTL1.REM_XOR. + [31:0] + read-only + + + + + VU_CTL0 + Vector unit control 0 + 0x1480 + 32 + read-write + 0x0 + 0x1 + + + ALWAYS_EXECUTE + Specifies if a conditional instruction is executed or not, when its condition code evaluates to false/'0'. +'0': The instruction is NOT executed. As a result, the instruction may be handled faster than when it is executed. +'1': The instruction is executed, but the execution result (including status field information) is not reflected in the IP. The instruction is handled just as fast as when it is executed. + +Note: a conditional instruction with a condition code that evaluates to false/'0' does not affect the architectural state: VU_STATUS fields, memory or register-file data. + +Note: Always execution is useful to prevent/complicate differential timing and differential power attacks. + [0:0] + read-write + + + + + VU_CTL1 + Vector unit control 1 + 0x1484 + 32 + read-write + 0x0 + 0xFFFFFF00 + + + ADDR24 + Specifies the memory address for the vector unit operand memory region. The register-file registers provide 13-bit word offsets within this memory region. Given ADDR[31:8], VU_VTL2.MASK[14:8] and a 13-bit word offset offset[14:2], a vector operand memory address VU_OPERAND_ADDR[31:0] is calculated as follows: +- VU_OPERAND_ADDR[31:15] = ADDR[31:15] +- VU_OPERAND_ADDR[14:8] = (ADDR[14:8] & MASK[14:8]) | (offset[14:8] & ~MASK[14:8]) +- VU_OPERAND_ADDR[7:2] = offset[7:2] +- VU_OPERAND_ADDR[1:0] = 0 (always word aligned) + +The vector unit operand memory region uses either the IP's memory buffer or system memory. For best performance, the IP's memory buffer should be used and ADDR should be set to MEM_BUFF and MASK should specify the IP memory buffer size. + +If a vector operand memory address is mapped on a memory hole, read accesses return a '0' and write accesses are ignored. + [31:8] + read-write + + + + + VU_CTL2 + Vector unit control 2 + 0x1488 + 32 + read-write + 0x7F00 + 0x7F00 + + + MASK + Specifies the size of the vector operand memory region. Legal values: +'0b0000000': 32 KB memory region (VU_VTL1.ADDR[14:8] ignored). +'0b1000000': 16 KB memory region (VU_VTL1.ADDR[13:8] ignored). +'0b1100000': 8 KB memory region (VU_VTL1.ADDR[12:8] ignored). +'0b1110000': 4 KB memory region (VU_VTL1.ADDR[11:8] ignored). +'0b1111000': 2 KB memory region (VU_VTL1.ADDR[10:8] ignored). +'0b1111100': 1 KB memory region (VU_VTL1.ADDR[9:8] ignored). +'0b1111110': 512 B memory region (VU_VTL1.ADDR[8] ignored). +'0b1111111': 256 B memory region. + +Note: the default specifies a 256 B memory region. + [14:8] + read-write + + + + + VU_STATUS + Vector unit status + 0x1490 + 32 + read-only + 0x0 + 0xF + + + CARRY + STATUS CARRY field. + [0:0] + read-only + + + EVEN + STATUS EVEN field. + [1:1] + read-only + + + ZERO + STATUS ZERO field. + [2:2] + read-only + + + ONE + STATUS ONE field. + [3:3] + read-only + + + + + 16 + 4 + VU_RF_DATA[%s] + Vector unit register-file + 0x14C0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA32 + Vector unit register-file data. A register-file register has the following layout: +DATA[28:16]: data (typically used as a word offset in vector unit operand memory). +DATA[12:0]: bit size minus 1. + [31:0] + read-only + + + + + DEV_KEY_ADDR0_CTL + Device key address 0 control + 0x2000 + 32 + read-write + 0x0 + 0x80000000 + + + VALID + Specifies if the address in the associated DEV_KEY_ADDR0 is valid: +'0': Address not valid; i.e. no device key specified. +'1': Address valid; i.e. device key specified. + +Note: A LOAD_DEV_KEY instruction requires that the device key's valid field is '1'. + [31:31] + read-write + + + + + DEV_KEY_ADDR0 + Device key address 0 + 0x2004 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR32 + Specifies the memory address of the device key in memory. A LOAD_DEV_KEY instruction uses this address to load a device key from memory into the IP register buffer blocks 4 and 5. + [31:0] + read-write + + + + + DEV_KEY_ADDR1_CTL + Device key address 1 control + 0x2020 + 32 + read-write + 0x0 + 0x80000000 + + + VALID + See DEV_KEY_ADDR0_CTL. + [31:31] + read-write + + + + + DEV_KEY_ADDR1 + Device key address 1 control + 0x2024 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR32 + See DEV_KEY_ADDR0. + [31:0] + read-write + + + + + DEV_KEY_STATUS + Device key status + 0x2080 + 32 + read-only + 0x0 + 0x1 + + + LOADED + Specifies if a device key is present in the IP register buffer blocks 4 and 5. + +HW sets this field to '1' on successful completion of a LOAD_DEV_KEY instruction. +HW clears this field to '0' when a CLEAR instruction is executed (the CLEAR instruction also sets the IP register buffer to '0'). + [0:0] + read-only + + + + + DEV_KEY_CTL0 + Device key control 0 + 0x2100 + 32 + read-write + 0x0 + 0x1 + + + ALLOWED + Specifies if a LOAD_DEV_KEY instruction is allowed to use the device key in memory: +'0': Not allowed. +'1': Allowed. + +Note: For successful completion of a LOAD_DEV_KEY instruction, both the associated DEV_KEY_ADDR_CTL.VALID and DEV_KEY_CTL.ALLOWED fields must be '1'. On successful instruction completion, DEV_KEY_STATUS.LOADED is set to '1'. On unsuccessful completion, the instruction FIFO is cleared and the IP is locked; an Active reset or an IP reset (CTL.ENABLED), which reinitializes the IP, is required. + +Note: A LOAD_DEV_KEY loads the device key from memory with protection context '0'. + [0:0] + read-write + + + + + DEV_KEY_CTL1 + Device key control 1 + 0x2120 + 32 + read-write + 0x0 + 0x1 + + + ALLOWED + See DEV_KEY_CTL0. + [0:0] + read-write + + + + + + + CPUSS + CPU subsystem (CPUSS) + 0x40200000 + + 0 + 65536 + registers + + + NvicMux0 + CPU User Interrupt #0 + 0 + + + NvicMux1 + CPU User Interrupt #1 + 1 + + + NvicMux2 + CPU User Interrupt #2 + 2 + + + NvicMux3 + CPU User Interrupt #3 + 3 + + + NvicMux4 + CPU User Interrupt #4 + 4 + + + NvicMux5 + CPU User Interrupt #5 + 5 + + + NvicMux6 + CPU User Interrupt #6 + 6 + + + NvicMux7 + CPU User Interrupt #7 + 7 + + + Internal0 + Internal SW Interrupt #0 + 8 + + + Internal1 + Internal SW Interrupt #1 + 9 + + + Internal2 + Internal SW Interrupt #2 + 10 + + + Internal3 + Internal SW Interrupt #3 + 11 + + + Internal4 + Internal SW Interrupt #4 + 12 + + + Internal5 + Internal SW Interrupt #5 + 13 + + + Internal6 + Internal SW Interrupt #6 + 14 + + + Internal7 + Internal SW Interrupt #7 + 15 + + + + IDENTITY + Identity + 0x0 + 32 + read-only + 0x0 + 0x0 + + + P + This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register. + [0:0] + read-only + + + NS + This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register. + [1:1] + read-only + + + PC + This field specifies the protection context of the transfer that reads the register. + [7:4] + read-only + + + MS + This field specifies the bus master identifier of the transfer that reads the register. + [11:8] + read-only + + + + + CM7_0_STATUS + CM7 0 status + 0x4 + 32 + read-only + 0x13 + 0x1E13 + + + SLEEPING + Specifies if the CPU is in Active, Sleep or DeepSleep power mode: +- Active power mode: SLEEPING is '0'. +- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. +- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. + [0:0] + read-only + + + SLEEPDEEP + Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. + [1:1] + read-only + + + PWR_DONE + After a PWR_MODE change this flag indicates if the new power mode has taken effect or not. +Note: this flag can also change as a result of a change in debug power up req + [4:4] + read-only + + + TCMC_CM7_1_MS + Outstanding transactions from CM7 1. +'0': There are no outstanding transactions to the CM7 I/D-TCM slave port (AHBS) from CM7 1. +'1': There are outstanding transactions to the CM7 I/D-TCM slave port (AHBS) from CM7 1. Do not switch the CM7 power off. + [9:9] + read-only + + + TCMC_EXT_MS_2_TO_0 + Outstanding transactions from external AXI masters 2 to 0. +'0': There are no outstanding transactions to the CM7 I/D-TCM slave port (AHBS) from external AXI masters 2 to 0. +'1': There are outstanding transactions to the CM7 I/D-TCM slave port (AHBS) from external AXI masters 2 to 0. Do not switch the CM7 power off. + [10:10] + read-only + + + TCMC_EXT_MS_3 + Outstanding transactions from external AXI master 3. +'0': There are no outstanding transactions to the CM7 I/D-TCM slave port (AHBS) from external AXI master 3. +'1': There are outstanding transactions to the CM7 I/D-TCM slave port (AHBS) from external AXI master 3. Do not switch the CM7 power off. + [11:11] + read-only + + + TCMC_AHB_MS + Ongoing AHB transaction. +'0': There is no ongoing transaction to the CM7 I/D-TCM slave port (AHBS) from an AHB master. +'1': There is an ongoing transaction to the CM7 I/D-TCM slave port (AHBS) from an AHB master. Do not switch the CM7 power off. + [12:12] + read-only + + + + + FAST_0_CLOCK_CTL + Fast 0 clock control + 0x8 + 32 + read-write + 0x0 + 0xFFF8 + + + FRAC_DIV + Fractional division by (FRAC_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf<x>' cycle longer than other clock periods. + [7:3] + read-write + + + INT_DIV + Integer division by (1+INT_DIV). Allows for integer divisions in the range [1, 256] (INT_DIV is in the range [0, 255]). + [15:8] + read-write + + + + + CM7_0_CTL + CM7 0 control + 0xC + 32 + read-write + 0x1F + 0x9FFF0F1F + + + PPB_LOCK + Write disable for specific CPU registers: +Bit 0: ITCMR register. '0': enabled; '1': disabled. +Bit 1: DTCMR register. '0': enabled; '1': disabled. +Bit 2: AHBPCR register. '0': enabled; '1': disabled. +Bit 3: VTOR register. '0': enabled; '1': disabled. + [3:0] + read-write + + + CPU_WAIT + When this signal is '1' out of reset, it forces the CPU into a quiescent state that delays its boot-up sequence and instruction execution until this signal is driven '0'. This allows the TCMs to be loaded by the system before the CPU performs any TCM accesses. The CPU AHBS interface functions while CPU_WAIT is '1' and services transactions initiated by the system (e.g. DMA controller) to load the TCMs. + [4:4] + read-write + + + INIT_TCM_EN + TCM enable initialization after reset: +Bit 0: ITCM. '0': disabled; '1': enabled. +Bit 1: DTCM. '0': disabled; '1': enabled. + [9:8] + read-write + + + INIT_RMW_EN + TCM read-modify-write enable initialization after reset: +Bit 0: ITCM. '0': disabled; '1': enabled. +Bit 1: DTCM. '0': disabled; '1': enabled. + +Note: When TCM ECC is enabled, the read-modify-write functionality should be enabled. This prevents partial (sub-word) writes to the TCM. + [11:10] + read-write + + + ITCM_ECC_EN + ITCM ECC enable: +'0': Disabled. +'1': Enabled. + [16:16] + read-write + + + ITCM_ECC_INJ_EN + ITCM ECC error injection enable: +'0': Disabled. +'1': Enabled. + [17:17] + read-write + + + ITCM_READ_WS + ITCM read wait states (writes have no wait states). +'0': 0 wait states. +'1': 1 wait state. + [18:18] + read-write + + + ITCM_ECC_CHECK_DIS + Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when TCM_ECC_EN=0. + [19:19] + read-write + + + DTCM_ECC_EN + DTCM ECC enable: +'0': Disabled. +'1': Enabled. + [20:20] + read-write + + + DTCM_ECC_INJ_EN + DTCM ECC error injection enable: +'0': Disabled. +'1': Enabled. + [21:21] + read-write + + + DTCM_READ_WS + DTCM read wait states (writes have no wait states). +'0': 0 wait states. +'1': 1 wait state. + [22:22] + read-write + + + TCMC_EN + CM7 TCMC access control: +'0': Disable access to the CM7 I/D-TCM slave port (AHBS). Access attempts will get a bus error response. +'1': Enable access to the CM7 I/D-TCM slave port (AHBS). + +Before switching the CM7 power off, set this field to 0, and confirm that there are no outstanding AXI transactions and no ongoing AHB transactions to the CM7 TCMs, by checking that bits TCMC_* in CM7_x_STATUS are '0'. + [23:23] + read-write + + + IOC_MASK + CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + +Note: the ARM architecture does NOT support FPU exceptions; i.e. there is no precise FPU exception handler. Instead, FPU conditions are captured in the CPU's FPCSR register and the conditions are provided as CPU interface signals. The interface signals are 'masked' with the fields a provide by this register (CM7_0_CTL). The 'masked' signals are reduced/OR-ed into a single CPU floating point interrupt signal. The associated CPU interrupt handler allows for imprecise handling of FPU exception conditions. + +Note: the CPU's FPCSR exception conditions are 'sticky'. Typically, the CPU FPU interrupt handler will clear the exception condition(s) to '0'. + +Note: by default, the FPU exception masks are '0'. Therefore, FPU exception conditions will NOT activate the CPU's floating point interrupt. + [24:24] + read-write + + + DZC_MASK + CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + [25:25] + read-write + + + OFC_MASK + CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + [26:26] + read-write + + + UFC_MASK + CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + [27:27] + read-write + + + IXC_MASK + CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + +Note: the 'inexact' condition is set as a result of rounding. Rounding may occur frequently and is typically not an error condition. To prevent frequent CPU FPU interrupts as a result of rounding, this field is typically set to '0'. + [28:28] + read-write + + + IDC_MASK + CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition: +'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. +'1': the CPU's exception condition activates the CPU's floating point interrupt. + +Note: if the CPU FPCSR.FZ field is set to '1', denormalized inputs are 'flushed to zero'. Dependent on the FPU algorithm, this may or may not occur frequently. To prevent frequent CPU FPU interrupts as a result of denormalized inputs, this field may be set to '0'. + [31:31] + read-write + + + + + 16 + 4 + CM7_0_INT_STATUS[%s] + CM7 0 interrupt status + 0x100 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM7_0 activated system interrupt index for CPU interrupt. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM7_0_VECTOR_TABLE_BASE + CM7 0 vector table base + 0x200 + 32 + read-write + 0x1000000 + 0xFFFFFF80 + + + ADDR25 + The default CM7 vector table base address is 0x0100:0000 (CM7 VTOR and reset exception handler address after reset). This is the location of the system ROM memory. + +The system ROM is mirrored at 0x0000:0000. This is required for the CM0+ boot process (the CM0+ VTOR and reset exception handler address is at fixed address 0x0000:00000 after reset). The system ROM requires mirroring as the CM7 CPUs' ITCMs are located at base address 0x0000:0000 and effectively cut a hole in the system ROM mirror address space (but the 0x0100:0000 address space is not affected). + [31:7] + read-write + + + + + 4 + 4 + CM7_0_NMI_CTL[%s] + CM7 0 NMI control + 0x240 + 32 + read-write + 0x3FF + 0x3FF + + + SYSTEM_INT_IDX + System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. + [9:0] + read-write + + + + + UDB_PWR_CTL + UDB power control + 0x300 + 32 + read-write + 0xFA050001 + 0xFFFF0003 + + + PWR_MODE + Set Power mode for UDBs + [1:0] + read-write + + + OFF + See CM7_0_PWR_CTL + 0 + + + RESET + See CM7_0_PWR_CTL + 1 + + + RETAINED + See CM7_0_PWR_CTL + 2 + + + ENABLED + See CM7_0_PWR_CTL + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + [31:16] + read-only + + + + + UDB_PWR_DELAY_CTL + UDB power control + 0x304 + 32 + read-write + 0x12C + 0x3FF + + + UP + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + TRC_DBG_CLOCK_CTL + Trace and debug clock control + 0x320 + 32 + read-write + 0x200 + 0xFF00 + + + INT_DIV + Integer division by (1+INT_DIV). Allows for integer divisions in the range [1, 256] (INT_DIV is in the range [0, 255]). +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + CM7_1_STATUS + CM7 1status + 0x404 + 32 + read-only + 0x13 + 0x1D13 + + + SLEEPING + Specifies if the CPU is in Active, Sleep or DeepSleep power mode: +- Active power mode: SLEEPING is '0'. +- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. +- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. + [0:0] + read-only + + + SLEEPDEEP + Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. + [1:1] + read-only + + + PWR_DONE + After a PWR_MODE change this flag indicates if the new power mode has taken effect or not. +Note: this flag can also change as a result of a change in debug power up req + [4:4] + read-only + + + TCMC_CM7_0_MS + Outstanding transactions from CM7 0. +'0': There are no outstanding transactions to the CM7 I/D-TCM slave port (AHBS) from CM7 0. +'1': There are outstanding transactions to the CM7 I/D-TCM slave port (AHBS) from CM7 0. Do not switch the CM7 power off. + [8:8] + read-only + + + TCMC_EXT_MS_2_TO_0 + Refer CM7_0_STATUS description. + [10:10] + read-only + + + TCMC_EXT_MS_3 + Refer CM7_0_STATUS description. + [11:11] + read-only + + + TCMC_AHB_MS + Refer CM7_0_STATUS description. + [12:12] + read-only + + + + + FAST_1_CLOCK_CTL + Fast 1 clock control + 0x408 + 32 + read-write + 0x0 + 0xFFF8 + + + FRAC_DIV + Refer FAST_0_CLOCK_CTL description. + [7:3] + read-write + + + INT_DIV + Refer FAST_0_CLOCK_CTL description. + [15:8] + read-write + + + + + CM7_1_CTL + CM7 1 control + 0x40C + 32 + read-write + 0x1F + 0x9FFF0F1F + + + PPB_LOCK + Refer CM7_0_CTL description. + [3:0] + read-write + + + CPU_WAIT + Refer CM7_0_CTL description. + [4:4] + read-write + + + INIT_TCM_EN + Refer CM7_0_CTL description. + [9:8] + read-write + + + INIT_RMW_EN + Refer CM7_0_CTL description. + [11:10] + read-write + + + ITCM_ECC_EN + Refer CM7_0_CTL description. + [16:16] + read-write + + + ITCM_ECC_INJ_EN + Refer CM7_0_CTL description. + [17:17] + read-write + + + ITCM_READ_WS + Refer CM7_0_CTL description. + [18:18] + read-write + + + ITCM_ECC_CHECK_DIS + Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when TCM_ECC_EN=0. + [19:19] + read-write + + + DTCM_ECC_EN + Refer CM7_0_CTL description. + [20:20] + read-write + + + DTCM_ECC_INJ_EN + Refer CM7_0_CTL description. + [21:21] + read-write + + + DTCM_READ_WS + Refer CM7_0_CTL description. + [22:22] + read-write + + + TCMC_EN + Refer CM7_0_CTL description. + [23:23] + read-write + + + IOC_MASK + Refer CM7_0_CTL description. + [24:24] + read-write + + + DZC_MASK + Refer CM7_0_CTL description. + [25:25] + read-write + + + OFC_MASK + Refer CM7_0_CTL description. + [26:26] + read-write + + + UFC_MASK + Refer CM7_0_CTL description. + [27:27] + read-write + + + IXC_MASK + Refer CM7_0_CTL description. + [28:28] + read-write + + + IDC_MASK + Refer CM7_0_CTL description. + [31:31] + read-write + + + + + 16 + 4 + CM7_1_INT_STATUS[%s] + CM7 1 interrupt status + 0x500 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM7_1 activated system interrupt index for CPU interrupt 0. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM7_1_VECTOR_TABLE_BASE + CM7 1 vector table base + 0x600 + 32 + read-write + 0x1000000 + 0xFFFFFF80 + + + ADDR25 + The default CM7 vector table base address is 0x0100:0000 (CM7 VTOR and reset exception handler address after reset). This is the location of the system ROM memory. + +The system ROM is mirrored at 0x0000:0000. This is required for the CM0+ boot process (the CM0+ VTOR and reset exception handler address is at fixed address 0x0000:00000 after reset). The system ROM requires mirroring as the CM7 CPUs' ITCMs are located at base address 0x0000:0000 and effectively cut a hole in the system ROM mirror address space (but the 0x0100:0000 address space is not affected). + [31:7] + read-write + + + + + 4 + 4 + CM7_1_NMI_CTL[%s] + CM7 1 NMI control + 0x640 + 32 + read-write + 0x3FF + 0x3FF + + + SYSTEM_INT_IDX + Refer CM7_0_NMI_CTL description. + [9:0] + read-write + + + + + CM0_CTL + CM0+ control + 0x1000 + 32 + read-write + 0xFA050002 + 0xFFFF0003 + + + SLV_STALL + Processor debug access control: +'0': Access. +'1': Stall access. + +This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses. + [0:0] + read-write + + + ENABLED + Processor enable: +'0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot. +'1': Enabled. +Note: The intent is that this bit is modified only through an external probe or by the CM7 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented). + +Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value; see CPU user manual for more details). + [1:1] + read-write + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. +Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. + [31:16] + read-only + + + + + CM0_STATUS + CM0+ status + 0x1004 + 32 + read-only + 0x0 + 0x3 + + + SLEEPING + Specifies if the CPU is in Active, Sleep or DeepSleep power mode: +- Active power mode: SLEEPING is '0'. +- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. +- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. + [0:0] + read-only + + + SLEEPDEEP + Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. + [1:1] + read-only + + + + + SLOW_CLOCK_CTL + Slow clock control + 0x1008 + 32 + read-write + 0x0 + 0xFF00 + + + INT_DIV + Specifies the slow clock divider (from the memory/AXI clock 'clk_mem' to the slow clock 'clk_slow'). Integer division by (1+INT_DIV). Allows for integer divisions in the range [1, 256] (INT_DIV is in the range [0, 255]). + +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + PERI_CLOCK_CTL + Peripheral interconnect clock control + 0x100C + 32 + read-write + 0x0 + 0xFF00 + + + INT_DIV + Integer division by (1+INT_DIV). Allows for integer divisions in the range [1, 256] (INT_DIV is in the range [0, 255]). +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + MEM_CLOCK_CTL + Memory clock control + 0x1010 + 32 + read-write + 0x0 + 0xFF00 + + + INT_DIV + Integer division by (1+INT_DIV). Allows for integer divisions in the range [1, 256] (INT_DIV is in the range [0, 255]). +Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. + [15:8] + read-write + + + + + CM0_INT0_STATUS + CM0+ interrupt 0 status + 0x1100 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 0. + +Multiple system interrupts can be mapped on the same CPU interrupt.The selected system interrupt is the system interrupt with the lowest system interrupt index that has an activated interrupt request at the time of the fetch (system_interrupts[SYSTEM_INT_IDX] is '1'). + +The CPU interrupt handler SW can read SYSTEM_INT_IDX to determine the system interrupt that activated the handler. + [9:0] + read-only + + + SYSTEM_INT_VALID + Valid indication for SYSTEM_INT_IDX. When '0', no system interrupt for CPU interrupt 0 is valid/activated. + [31:31] + read-only + + + + + CM0_INT1_STATUS + CM0+ interrupt 1 status + 0x1104 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 1. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT2_STATUS + CM0+ interrupt 2 status + 0x1108 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 2. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT3_STATUS + CM0+ interrupt 3 status + 0x110C + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 3. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT4_STATUS + CM0+ interrupt 4 status + 0x1110 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 4. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT5_STATUS + CM0+ interrupt 5 status + 0x1114 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 5. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT6_STATUS + CM0+ interrupt 6 status + 0x1118 + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 6. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_INT7_STATUS + CM0+ interrupt 7 status + 0x111C + 32 + read-only + 0x0 + 0x80000000 + + + SYSTEM_INT_IDX + Lowest CM0+ activated system interrupt index for CPU interrupt 7. + +See description of CM0_INT0_STATUS. + [9:0] + read-only + + + SYSTEM_INT_VALID + See description of CM0_INT0_STATUS. + [31:31] + read-only + + + + + CM0_VECTOR_TABLE_BASE + CM0+ vector table base + 0x1120 + 32 + read-write + 0x0 + 0xFFFFFF00 + + + ADDR24 + The default CM0+ vector table base address is 0x0000:0000 (CM0+ VTOR and reset exception handler address after reset). This is the location of the mirror system ROM memory. + +This register is provided for SW purposes. It 'survives' a CM0+ warm reset cycle (CM0_CTL.ENABLED). + +Note: the use of the mirror system ROM memory can be disabled using the protection infrastructure (SMPU). + [31:8] + read-write + + + + + 4 + 4 + CM0_NMI_CTL[%s] + CM0+ NMI control + 0x1140 + 32 + read-write + 0x3FF + 0x3FF + + + SYSTEM_INT_IDX + System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. + [9:0] + read-write + + + + + CM7_0_PWR_CTL + CM7 0 power control + 0x1200 + 32 + read-write + 0xFA050000 + 0xFFFF0003 + + + PWR_MODE + Power mode. + [1:0] + read-write + + + OFF + Switch CM7_0 off +Power off, clock off, isolate, reset and no retain. + 0 + + + RESET + Reset CM7_0 +Clock off, no isolated, no retain and reset. +... + 1 + + + RETAINED + Put CM7_0 in Retained mode +This can only become effective if CM7_0 is in SleepDeep mode. Check PWR_DONE flag to see if CM7_0 RETAINED state has been reached. +Power off, clock off, isolate, no reset and retain. + 2 + + + ENABLED + Switch CM7_0 on. +Power on, clock on, no isolate, no reset and no retain. + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. + +Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. + [31:16] + read-only + + + + + CM7_0_PWR_DELAY_CTL + CM7 0 power delay control + 0x1204 + 32 + read-write + 0x12C + 0x3FF + + + UP + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + CM7_1_PWR_CTL + CM7 1 power control + 0x1210 + 32 + read-write + 0xFA050000 + 0xFFFF0003 + + + PWR_MODE + Refer CM7_0_PWR_CTL description. + [1:0] + read-write + + + OFF + Refer CM7_0_PWR_CTL description. + 0 + + + RESET + Refer CM7_0_PWR_CTL description. + 1 + + + RETAINED + Refer CM7_0_PWR_CTL description. + 2 + + + ENABLED + Refer CM7_0_PWR_CTL description. + 3 + + + + + VECTKEYSTAT + Refer CM7_0_PWR_CTL description. + [31:16] + read-only + + + + + CM7_1_PWR_DELAY_CTL + CM7 1 power delay control + 0x1214 + 32 + read-write + 0x12C + 0x3FF + + + UP + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + RAM0_CTL0 + RAM 0 control + 0x1300 + 32 + read-write + 0x30001 + 0xF0303 + + + SLOW_WS + Memory wait states for the slow clock domain ('clk_slow') intefrace. The number of wait states is expressed in 'clk_mem' clock domain cycles. + [1:0] + read-write + + + FAST_WS + Memory wait states for the fast clock domain ('clk_fast_0/1') interface. The number of wait states is expressed in 'clk_mem' clock domain cycles. + [9:8] + read-write + + + ECC_EN + Enable ECC checking: +'0': Disabled. +'1': Enabled. + [16:16] + read-write + + + ECC_AUTO_CORRECT + HW ECC autocorrect functionality: +'0': Disabled. +'1': Enabled. HW automatically writes back SRAM with corrected data when a recoverable ECC error is detected. + [17:17] + read-write + + + ECC_INJ_EN + Enable ECC parity injection. Instead of calculating the parity from the write data to the RAM, the parity is taken from ECC_CTL PARITY upon a match of ECC_CTL WORD_ADDR. The write data can be of any size. This bit is ignored when ECC_EN=0. +Note: Parity injection invalidates the write buffer for this word address. If only a part of 64-bit data is written and consistency should be maintained, RAMC#_STATUS WB_EMPTY=1 should be checked before. + [18:18] + read-write + + + ECC_CHECK_DIS + Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when ECC_EN=0. + [19:19] + read-write + + + + + RAM0_STATUS + RAM 0 status + 0x1304 + 32 + read-only + 0x1 + 0x1 + + + WB_EMPTY + Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode. +'0': Write buffer NOT empty. +'1': Write buffer empty. + +Note: the SRAM controller write buffer is only used when ECC checking is enabled. (RAMi_CTL.ECC_EN is '1'). + [0:0] + read-only + + + + + 16 + 4 + RAM0_PWR_MACRO_CTL[%s] + RAM 0 power control + 0x1340 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Power mode. + [1:0] + read-write + + + OFF + Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost. + 0 + + + RSVD + undefined + 1 + + + RETAINED + Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. + 2 + + + ENABLED + Enable SRAM for regular operation. + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. +Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. + [31:16] + read-only + + + + + RAM1_CTL0 + RAM 1 control + 0x1380 + 32 + read-write + 0x30001 + 0xF0303 + + + SLOW_WS + Refer RAM0_CTL0 descriotion. + [1:0] + read-write + + + FAST_WS + Refer RAM0_CTL0 descriotion. + [9:8] + read-write + + + ECC_EN + Refer RAM0_CTL0 descriotion. + [16:16] + read-write + + + ECC_AUTO_CORRECT + Refer RAM0_CTL0 descriotion. + [17:17] + read-write + + + ECC_INJ_EN + Enable ECC parity injection. Instead of calculating the parity from the write data to the RAM, the parity is taken from ECC_CTL PARITY upon a match of ECC_CTL WORD_ADDR. The write data can be of any size. This bit is ignored when ECC_EN=0. +Note: Parity injection invalidates the write buffer for this word address. If only a part of 64-bit data is written and consistency should be maintained, RAMC#_STATUS WB_EMPTY=1 should be checked before. + [18:18] + read-write + + + ECC_CHECK_DIS + Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when ECC_EN=0. + [19:19] + read-write + + + + + RAM1_STATUS + RAM 1 status + 0x1384 + 32 + read-only + 0x1 + 0x1 + + + WB_EMPTY + Refer RAM0_STATUS description. + [0:0] + read-only + + + + + RAM1_PWR_CTL + RAM 1 power control + 0x1388 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Power mode. + [1:0] + read-write + + + OFF + Refer RAM0_PWR_MACRO_CTL description. + 0 + + + RSVD + Undefined. + 1 + + + RETAINED + Refer RAM0_PWR_MACRO_CTL description. + 2 + + + ENABLED + Refer RAM0_PWR_MACRO_CTL description. + 3 + + + + + VECTKEYSTAT + Refer RAM0_PWR_MACRO_CTL description. + [31:16] + read-only + + + + + RAM2_CTL0 + RAM 2 control + 0x13A0 + 32 + read-write + 0x30001 + 0xF0303 + + + SLOW_WS + Refer RAM0_CTL0 descriotion. + [1:0] + read-write + + + FAST_WS + Refer RAM0_CTL0 descriotion. + [9:8] + read-write + + + ECC_EN + Refer RAM0_CTL0 descriotion. + [16:16] + read-write + + + ECC_AUTO_CORRECT + Refer RAM0_CTL0 descriotion. + [17:17] + read-write + + + ECC_INJ_EN + Enable ECC parity injection. Instead of calculating the parity from the write data to the RAM, the parity is taken from ECC_CTL PARITY upon a match of ECC_CTL WORD_ADDR. The write data can be of any size. This bit is ignored when ECC_EN=0. +Note: Parity injection invalidates the write buffer for this word address. If only a part of 64-bit data is written and consistency should be maintained, RAMC#_STATUS WB_EMPTY=1 should be checked before. + [18:18] + read-write + + + ECC_CHECK_DIS + Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when ECC_EN=0. + [19:19] + read-write + + + + + RAM2_STATUS + RAM 2 status + 0x13A4 + 32 + read-only + 0x1 + 0x1 + + + WB_EMPTY + Refer RAM0_STATUS description. + [0:0] + read-only + + + + + RAM2_PWR_CTL + RAM 2 power control + 0x13A8 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Power mode. + [1:0] + read-write + + + OFF + Refer RAM0_PWR_MACRO_CTL description. + 0 + + + RSVD + Undefined. + 1 + + + RETAINED + Refer RAM0_PWR_MACRO_CTL description. + 2 + + + ENABLED + Refer RAM0_PWR_MACRO_CTL description. + 3 + + + + + VECTKEYSTAT + Refer RAM0_PWR_MACRO_CTL description. + [31:16] + read-only + + + + + RAM_PWR_DELAY_CTL + Power up delay used for all SRAM power domains + 0x13C0 + 32 + read-write + 0x96 + 0x3FF + + + UP + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + ROM_CTL + ROM control + 0x13C4 + 32 + read-write + 0x1 + 0x303 + + + SLOW_WS + Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_mem' clock domain cycles. + +Timing paths to and from the memory have a (fixed) minimum duration that always needs to be considered/met. The 'clk_mem' clock domain frequency determines this field's value such that the timing paths minimum duration is met. +ROM_CTL.SLOW_WS = '0' when clk_mem <=100 MHz. +ROM_CTL.SLOW_WS = '1' when 100MHz < clk_mem <=200MHz. + [1:0] + read-write + + + FAST_WS + Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_mem' clock domain cycles. +ROM_CTL.FAST_WS = '0' when clk_mem <= 200MHz. + [9:8] + read-write + + + + + ECC_CTL + ECC control + 0x13C8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WORD_ADDR + Specifies the word address where an error will be injected. +- On a write transfer to this SRAM address and when the corresponding RAM0/RAM1/RAM2/ITCM/DTCM ECC_INJ_EN bit is '1', the parity (PARITY) is injected. +This field needs to be written with the offset address within the memory, divided by the ECC word width in bytes (for RAM0/RAM1/RAM2/ITCM this is 8, for DTCM this is 4). For example, if the RAM0 start address is 0x2800000, and an error is to be injected to address 0x28000080, then this field needs to configured to 0x000010. + [23:0] + read-write + + + PARITY + ECC parity to use for ECC error injection at address WORD_ADDR. For the DTCM which has only 7 parity bits, PARITY[6:0] is used as ECC parity. + [31:24] + read-write + + + + + PRODUCT_ID + Product identifier and version (same as CoreSight RomTables) + 0x1400 + 32 + read-only + 0x0 + 0xFFF + + + FAMILY_ID + Family ID. Common ID for a product family. + [11:0] + read-only + + + MAJOR_REV + Major Revision, starts with 1, increments with all layer tape-out (implemented with metal ECO-able tie-off) + [19:16] + read-only + + + MINOR_REV + Minir Revision, starts with 1, increments with metal layer only tape-out (implemented with metal ECO-able tie-off) + [23:20] + read-only + + + + + DP_STATUS + Debug port status + 0x1410 + 32 + read-only + 0x4 + 0x7 + + + SWJ_CONNECTED + Specifies if the SWJ debug port is connected; i.e. debug host interface is active: +'0': Not connected/not active. +'1': Connected/active. + [0:0] + read-only + + + SWJ_DEBUG_EN + Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on: +'0': Disabled. +'1': Enabled. + [1:1] + read-only + + + SWJ_JTAG_SEL + Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected). +'0': SWD selected. +'1': JTAG selected. + [2:2] + read-only + + + + + AP_CTL + Access port control + 0x1414 + 32 + read-write + 0x0 + 0x70007 + + + CM0_ENABLE + Enables the CM0 AP interface: +'0': Disabled. +'1': Enabled. + [0:0] + read-write + + + CM7_ENABLE + Enables the CM7_0 and CM7_1 AP interface: +'0': Disabled. +'1': Enabled. + [1:1] + read-write + + + SYS_ENABLE + Enables the system AP interface: +'0': Disabled. +'1': Enabled. + [2:2] + read-write + + + CM0_DISABLE + Disables the CM0 AP interface: +'0': Enabled. +'1': Disabled. + +Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM0_DISABLE is '0' and CM0_ENABLE is '1'. + [16:16] + read-write + + + CM7_DISABLE + Disables the CM7_0 and CM7_1 AP interface: +'0': Enabled. +'1': Disabled. + +Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM7_DISABLE is '0' and CM7_ENABLE is '1'. + [17:17] + read-write + + + SYS_DISABLE + Disables the system AP interface: +'0': Enabled. +'1': Disabled. + +Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when SYS_DISABLE is '0' and SYS_ENABLE is '1'. + [18:18] + read-write + + + + + BUFF_CTL + Buffer control + 0x1500 + 32 + read-write + 0x1 + 0x1 + + + WRITE_BUFF + Specifies if write transfer can be buffered in the bus infrastructure bridges: +'0': Write transfers are not buffered, independent of the transfer's bufferable attribute. +'1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write. + [0:0] + read-write + + + + + SYSTICK_CTL + SysTick timer control + 0x1600 + 32 + read-write + 0x40000147 + 0xC3FFFFFF + + + TENMS + Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327. + [23:0] + read-write + + + CLOCK_SOURCE + Specifies an external clock source: +'0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise). +'1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock. +o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected. +'3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo'). + +Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used. +Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source. + [25:24] + read-write + + + SKEW + Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock: +'0': Precise. +'1': Imprecise. + [30:30] + read-write + + + NOREF + Specifies if an external clock source is provided: +'0': An external clock source is provided. +'1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source. + [31:31] + read-write + + + + + MBIST_STAT + Memory BIST status + 0x1704 + 32 + read-only + 0x0 + 0x3 + + + SFP_READY + Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0. + [0:0] + read-only + + + SFP_FAIL + Report status of the BIST run, only valid if SFP_READY=1 + [1:1] + read-only + + + + + CAL_SUP_SET + Calibration support set and read + 0x1800 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Read without side effect, write 1 to set + [31:0] + read-write + + + + + CAL_SUP_CLR + Calibration support clear and reset + 0x1804 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA + Read side effect: when read all bits are cleared, write 1 to clear a specific bit +Note: no exception for the debug host, it also causes the read side effect + [31:0] + read-write + + + + + CM0_PC_CTL + CM0+ protection context control + 0x2000 + 32 + read-write + 0x0 + 0xF + + + VALID + Valid fields for the protection context handler CM0_PCi_HANDLER registers: +Bit 0: Valid field for CM0_PC0_HANDLER. +Bit 1: Valid field for CM0_PC1_HANDLER. +Bit 2: Valid field for CM0_PC2_HANDLER. +Bit 3: Valid field for CM0_PC3_HANDLER. + [3:0] + read-write + + + + + CM0_PC0_HANDLER + CM0+ protection context 0 handler + 0x2040 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt. + [31:0] + read-write + + + + + CM0_PC1_HANDLER + CM0+ protection context 1 handler + 0x2044 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 1 handler. + [31:0] + read-write + + + + + CM0_PC2_HANDLER + CM0+ protection context 2 handler + 0x2048 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 2 handler. + [31:0] + read-write + + + + + CM0_PC3_HANDLER + CM0+ protection context 3 handler + 0x204C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDR + Address of the protection context 3 handler. + [31:0] + read-write + + + + + PROTECTION + Protection status + 0x20C4 + 32 + read-write + 0x0 + 0x7 + + + STATE + Protection state: +'0': UNKNOWN. +'1': VIRGIN. +'2': NORMAL. +'3': SECURE. +'4': DEAD. + +The following state transistions are allowed (and enforced by HW): +- UNKNOWN => VIRGIN/NORMAL/SECURE/DEAD +- NORMAL => DEAD +- SECURE => DEAD +An attempt to make a NOT allowed state transition will NOT affect this register field. + [2:0] + read-write + + + UNKNOWN + N/A + 0 + + + VIRGIN + N/A + 1 + + + NORMAL + N/A + 2 + + + SECURE + N/A + 3 + + + DEAD + N/A + 4 + + + + + + + TRIM_ROM_CTL + ROM trim control + 0x2100 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TRIM + N/A + [31:0] + read-write + + + + + TRIM_RAM_CTL + RAM trim control for less than 100MHz SRAMs + 0x2104 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TRIM + N/A + [31:0] + read-write + + + + + TRIM_RAM200_CTL + RAM trim control for 100MHz - 200MHz SRAMs + 0x2108 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TRIM + See TRIM_RAM_CTL for description. +System SRAM memories (SRAM0,1,2) are connected to this register. + +System SRAM0 uses bias control power switch,so bits [7:5] of this register controls the bias pins of the SRAM0 power switch. + [31:0] + read-write + + + + + TRIM_RAM350_CTL + RAM trim control for more than 200MHz SRAMs + 0x210C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TRIM + See TRIM_RAM_CTL for description. +CM7 Cache and TCM memories are connected to this register. + +All CM7 cache and TCM SRAM macros are controlled using bias control power switches, so bits [7:5] of this register controls the bias pins of the CM7 cache and TCM SRAM power switches. + [31:0] + read-write + + + + + 1023 + 4 + CM0_SYSTEM_INT_CTL[%s] + CM0+ system interrupt control + 0x8000 + 32 + read-write + 0x0 + 0x80000000 + + + CM0_CPU_INT_IDX + CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. + +Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. + [2:0] + read-write + + + CPU_INT_VALID + Interrupt enable: +'0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. +'1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. + +Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. + [31:31] + read-write + + + + + 1023 + 4 + CM7_0_SYSTEM_INT_CTL[%s] + CM7 0 system interrupt control + 0xA000 + 32 + read-write + 0x0 + 0x80000000 + + + CPU_INT_IDX + CPU interrupt index (legal range [0, 15]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. + +Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly. + [3:0] + read-write + + + CPU_INT_VALID + Interrupt enable: +'0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. +'1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. + +Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'. + [31:31] + read-write + + + + + 1023 + 4 + CM7_1_SYSTEM_INT_CTL[%s] + CM7 1 system interrupt control + 0xC000 + 32 + read-write + 0x0 + 0x80000000 + + + CPU_INT_IDX + Refer CM7_0_SYSTEM_INT_CTL description. + [3:0] + read-write + + + CPU_INT_VALID + Refer CM7_0_SYSTEM_INT_CTL description. + [31:31] + read-write + + + + + + + FAULT + Fault structures + 0x40210000 + + 0 + 65536 + registers + + + + 4 + 256 + STRUCT[%s] + Fault structure + 0x00000000 + + CTL + Fault control + 0x0 + 32 + read-write + 0x0 + 0x7 + + + TR_EN + Trigger output enable: +'0': Disabled. The trigger output 'tr_fault' is '0'. +'1': Enabled. The trigger output 'tr_fault' reflects STATUS.VALID. The trigger can be used to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3). + [0:0] + read-write + + + OUT_EN + IO output signal enable: +'0': Disabled. The IO output signal 'fault_out' is '0'. The IO output enable signal 'fault_out_en' is '0'. +'1': Enabled. The IO output signal 'fault_out' reflects STATUS.VALID. The IO output enable signal 'fault_out_en' is '1'. + [1:1] + read-write + + + RESET_REQ_EN + Reset request enable: +'0': Disabled. +'1': Enabled. The output reset request signal 'fault_reset_req' reflects STATUS.VALID. This reset causes a warm/soft/core reset. This warm/soft/core reset does not affect the fault logic STATUS, DATA0, ..., DATA3 registers (allowing for post soft reset failure analysis). + +The 'fault_reset_req' signals of the individual fault report structures are combined (logically OR'd) into a single SRSS 'fault_reset_req' signal. + [2:2] + read-write + + + + + STATUS + Fault status + 0xC + 32 + read-write + 0x0 + 0x80000000 + + + IDX + The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below. + +Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'. + [6:0] + read-write + + + VALID + Valid indication: +'0': Invalid. +'1': Valid. STATUS.IDX, DATA0, ..., DATA3 specify the fault. + +Note: Typically, HW sets this field to '1' (on an activated HW fault source that is 'enabled' by the MASK registers) and SW clears this field to '0' (typically by boot code SW (after a warm system reset, when the fault is handled). In this typical use case scenario, the HW source fault data is simultaneously captured into DATA0, ..., DATA3 when the VALID field is set to '1'. + +An exceptional SW use case scenario is identified as well. In this scenario, SW sets this field to '1' with a fault source index different to one of the defined HW fault sources. SW update is not restricted by the MASK registers). In both use case scenarios, the following holds: +- STATUS.IDX, DATA0, ..., DATA3 can only be written when STATUS.VALID is '0'; the fault structure is not in use yet. Writing STATUS.VALID to '1' effectively locks the fault structure (until SW clears STATUS.VALID to '0'). This restriction requires a SW update to sequentially update the DATA registers followed by an update of the STATUS register. + +Note: For the exceptional SW use case, sequential updates to the DATA and STATUS registers may be 'interrupted' by a HW fault capture. In this case, the SW DATA register updates are overwritten by the HW update (and the STATUS.IDX field will reflect the HW capture) + [31:31] + read-write + + + + + 4 + 4 + DATA[%s] + Fault data + 0x10 + 32 + read-write + 0x0 + 0x0 + + + DATA + Captured fault source data. + +Note: the DATA registers can only be written when STATUS.VALID is '0'. + +Note: the fault source index STATUS.IDX specifies the format of the DATA registers. + [31:0] + read-write + + + + + PENDING0 + Fault pending 0 + 0x40 + 32 + read-only + 0x0 + 0x0 + + + SOURCE + This field specifies the following sources: +Bit 0: CM0 MPU. +Bit 1: CRYPTO MPU. +Bit 2: DW 0 MPU. +Bit 3: DW 1 MPU. +Bit 4: DMA controller MPU. +... +Bit 15: DAP MPU. +Bit 16: CM4 system bus MPU. +Bit 17: CM4 code bus MPU (for non FLASH controller accesses). +Bit 18: CM4 code bus MPU (for FLASH controller accesses). + [31:0] + read-only + + + + + PENDING1 + Fault pending 1 + 0x44 + 32 + read-only + 0x0 + 0x0 + + + SOURCE + This field specifies the following sources: +Bit 0: Peripheral group 0 PPU. +Bit 1: Peripheral group 1 PPU. +Bit 2: Peripheral group 2 PPU. +Bit 3: Peripheral group 3 PPU. +Bit 4: Peripheral group 4 PPU. +Bit 5: Peripheral group 5 PPU. +Bit 6: Peripheral group 6 PPU. +Bit 7: Peripheral group 7 PPU. +... +Bit 15: Peripheral group 15 PPU. + +Bit 16 - 31: See STATUS register. + [31:0] + read-only + + + + + PENDING2 + Fault pending 2 + 0x48 + 32 + read-only + 0x0 + 0x0 + + + SOURCE + This field specifies the following sources: +Bit 0 - 31: See STATUS register. + [31:0] + read-only + + + + + MASK0 + Fault mask 0 + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOURCE + Fault source enables: +Bits 31-0: Fault sources 31 to 0. + [31:0] + read-write + + + + + MASK1 + Fault mask 1 + 0x54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOURCE + Fault source enables: +Bits 31-0: Fault sources 63 to 32. + [31:0] + read-write + + + + + MASK2 + Fault mask 2 + 0x58 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOURCE + Fault source enables: +Bits 31-0: Fault sources 95 to 64. + [31:0] + read-write + + + + + INTR + Interrupt + 0xC0 + 32 + read-write + 0x0 + 0x1 + + + FAULT + This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured: +- STATUS.VALID is set to '1'. +- STATUS.IDX specifies the fault source index. +- DATA0 through DATA3 captures the fault source data. + +SW writes a '1' to this field to clear the interrupt cause to '0'. SW clear STATUS.VALID to '0' to enable capture of the next fault. Note that when there is an enabled pending fault source, the pending fault source is captured immediately and INTR.FAULT is immediately activated (set to '1'). + [0:0] + read-write + + + + + INTR_SET + Interrupt set + 0xC4 + 32 + read-write + 0x0 + 0x1 + + + FAULT + SW writes a '1' to this field to set the corresponding field in the INTR register. + [0:0] + read-write + + + + + INTR_MASK + Interrupt mask + 0xC8 + 32 + read-write + 0x0 + 0x1 + + + FAULT + Mask bit for corresponding field in the INTR register. + [0:0] + read-write + + + + + INTR_MASKED + Interrupt masked + 0xCC + 32 + read-only + 0x0 + 0x1 + + + FAULT + Logical and of corresponding INTR and INTR_MASK fields. + [0:0] + read-only + + + + + + + + IPC + IPC + 0x40220000 + + 0 + 65536 + registers + + + + 8 + 32 + STRUCT[%s] + IPC structure + 0x00000000 + + ACQUIRE + IPC acquire + 0x0 + 32 + read-only + 0x0 + 0x80000000 + + + P + User/privileged access control: +'0': user mode. +'1': privileged mode. + +This field is set with the user/privileged access control of the access that successfully acquired the lock. + [0:0] + read-only + + + NS + Secure/non-secure access control: +'0': secure. +'1': non-secure. + +This field is set with the secure/non-secure access control of the access that successfully acquired the lock. + [1:1] + read-only + + + PC + This field specifies the protection context that successfully acquired the lock. + [7:4] + read-only + + + MS + This field specifies the bus master identifier that successfully acquired the lock. + [11:8] + read-only + + + SUCCESS + Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): +'0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. +'1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. + +Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value). + [31:31] + read-only + + + + + RELEASE + IPC release + 0x4 + 32 + write-only + 0x0 + 0xFFFF + + + INTR_RELEASE + Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. + +SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field. + [15:0] + write-only + + + + + NOTIFY + IPC notification + 0x8 + 32 + write-only + 0x0 + 0xFFFF + + + INTR_NOTIFY + This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. + +SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field. + [15:0] + write-only + + + + + DATA0 + IPC data 0 + 0xC + 32 + read-write + 0x0 + 0x0 + + + DATA + This field holds a 32-bit data element that is associated with the IPC structure. + [31:0] + read-write + + + + + DATA1 + IPC data 1 + 0x10 + 32 + read-write + 0x0 + 0x0 + + + DATA + This field holds a 32-bit data element that is associated with the IPC structure. + [31:0] + read-write + + + + + LOCK_STATUS + IPC lock status + 0x1C + 32 + read-only + 0x0 + 0x80000000 + + + P + This field specifies the user/privileged access control: +'0': user mode. +'1': privileged mode. + [0:0] + read-only + + + NS + This field specifies the secure/non-secure access control: +'0': secure. +'1': non-secure. + [1:1] + read-only + + + PC + This field specifies the protection context that successfully acquired the lock. + [7:4] + read-only + + + MS + This field specifies the bus master identifier that successfully acquired the lock. + [11:8] + read-only + + + ACQUIRED + Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero, P, NS, PC, and MS are not valid. + [31:31] + read-only + + + + + + 8 + 32 + INTR_STRUCT[%s] + IPC interrupt structure + 0x00001000 + + INTR + Interrupt + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RELEASE + These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. + [15:0] + read-write + + + NOTIFY + These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. + [31:16] + read-write + + + + + INTR_SET + Interrupt set + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RELEASE + SW writes a '1' to this field to set the corresponding field in the INTR register. + [15:0] + read-write + + + NOTIFY + SW writes a '1' to this field to set the corresponding field in the INTR register. + [31:16] + read-write + + + + + INTR_MASK + Interrupt mask + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RELEASE + Mask bit for corresponding field in the INTR register. + [15:0] + read-write + + + NOTIFY + Mask bit for corresponding field in the INTR register. + [31:16] + read-write + + + + + INTR_MASKED + Interrupt masked + 0xC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RELEASE + Logical and of corresponding request and mask bits. + [15:0] + read-only + + + NOTIFY + Logical and of corresponding INTR and INTR_MASK fields. + [31:16] + read-only + + + + + + + + PROT + Protection + 0x40230000 + + 0 + 65536 + registers + + + + SMPU + SMPU + 0x00000000 + + MS0_CTL + Master 0 protection context control + 0x0 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + Privileged setting ('0': user mode; '1': privileged mode). + +Notes: +This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute. +The default/reset field value provides privileged mode access capabilities. + [0:0] + read-write + + + NS + Security setting ('0': secure mode; '1': non-secure mode). + +Notes: +This field is ONLY used for masters that do NOT provide their own secure/non-secure access control attribute. +Note that the default/reset field value provides non-secure mode access capabilities to all masters. + [1:1] + read-write + + + PRIO + Device wide bus arbitration priority setting ('0': highest priority, '3': lowest priority). + +Notes: +The AHB-Lite interconnect performs arbitration on the individual beats/transfers of a burst (this optimizes latency over locality/bandwidth). +The AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency). +Masters with the same priority setting form a 'priority group'. Within a 'priority group', round robin arbitration is performed. + [9:8] + read-write + + + PC_MASK_0 + Protection context mask for protection context '0'. This field is a constant '0': +- PC_MASK_0 is '0': MPU MS_CTL.PC[3:0] can NOT be set to '0' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. + [16:16] + read-only + + + PC_MASK_15_TO_1 + Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1': +- PC_MASK_15_TO_1[i] is '0': MPU MS_CTL.PC[3:0] can NOT be set to 'i+1'; and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. +- PC_MASK_15_TO_1[i] is '1': MPU MS_CTL.PC[3:0] can be set to 'i+1'. + +Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]). + [31:17] + read-write + + + + + MS1_CTL + Master 1 protection context control + 0x4 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS2_CTL + Master 2 protection context control + 0x8 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS3_CTL + Master 3 protection context control + 0xC + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS4_CTL + Master 4 protection context control + 0x10 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS5_CTL + Master 5 protection context control + 0x14 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS6_CTL + Master 6 protection context control + 0x18 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS7_CTL + Master 7 protection context control + 0x1C + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS8_CTL + Master 8 protection context control + 0x20 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS9_CTL + Master 9 protection context control + 0x24 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS10_CTL + Master 10 protection context control + 0x28 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS11_CTL + Master 11 protection context control + 0x2C + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS12_CTL + Master 12 protection context control + 0x30 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS13_CTL + Master 13 protection context control + 0x34 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS14_CTL + Master 14 protection context control + 0x38 + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + MS15_CTL + Master 15 protection context control + 0x3C + 32 + read-write + 0x303 + 0xFFFF0303 + + + P + See MS0_CTL.P. + [0:0] + read-write + + + NS + See MS0_CTL.NS. + [1:1] + read-write + + + PRIO + See MS0_CTL.PRIO + [9:8] + read-write + + + PC_MASK_0 + See MS0_CTL.PC_MASK_0. + [16:16] + read-only + + + PC_MASK_15_TO_1 + See MS0_CTL.PC_MASK_15_TO_1. + [31:17] + read-write + + + + + 16 + 64 + SMPU_STRUCT[%s] + SMPU structure + 0x00002000 + + ADDR0 + SMPU region address 0 (slave structure) + 0x0 + 32 + read-write + 0x0 + 0x0 + + + SUBREGION_DISABLE + This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: +Bit 0: subregion 0 disable. +Bit 1: subregion 1 disable. +Bit 2: subregion 2 disable. +Bit 3: subregion 3 disable. +Bit 4: subregion 4 disable. +Bit 5: subregion 5 disable. +Bit 6: subregion 6 disable. +Bit 7: subregion 7 disable. +E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. + [7:0] + read-write + + + ADDR24 + This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. + [31:8] + read-write + + + + + ATT0 + SMPU region attributes 0 (slave structure) + 0x4 + 32 + read-write + 0x100 + 0x80000100 + + + UR + User read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-write + + + UW + User write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-write + + + UX + User execute enable: +'0': Disabled (user, execute accesses are NOT allowed). +'1': Enabled (user, execute accesses are allowed). + [2:2] + read-write + + + PR + Privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [3:3] + read-write + + + PW + Privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [4:4] + read-write + + + PX + Privileged execute enable: +'0': Disabled (privileged, execute accesses are NOT allowed). +'1': Enabled (privileged, execute accesses are allowed). + [5:5] + read-write + + + NS + Non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [6:6] + read-write + + + PC_MASK_0 + This field specifies protection context identifier based access control for protection context '0'. + [8:8] + read-only + + + PC_MASK_15_TO_1 + This field specifies protection context identifier based access control. +Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. + [23:9] + read-write + + + REGION_SIZE + This field specifies the region size: +'0'-'6': Undefined. +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'39': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-write + + + PC_MATCH + This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: +'0': PC field participates in 'access evaluation'. +'1': PC field participates in 'matching'. + +'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. +'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. + +Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. + [30:30] + read-write + + + ENABLED + Region enable: +'0': Disabled. A disabled region will never result in a match on the bus transfer address. +'1': Enabled. + +Note: a disabled address region performs logic gating to reduce dynamic power consumption. + [31:31] + read-write + + + + + ADDR1 + SMPU region address 1 (master structure) + 0x20 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SUBREGION_DISABLE + This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: +Bit 0: subregion 0 disable. +Bit 1: subregion 1 disable. +Bit 2: subregion 2 disable. +Bit 3: subregion 3 disable. +Bit 4: subregion 4 disable. +Bit 5: subregion 5 disable. +Bit 6: subregion 6 disable. +Bit 7: subregion 7 disable. + +Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. + +Note: this field is read-only. + [7:0] + read-only + + + ADDR24 + This field specifies the most significant bits of the 32-bit address of an address region. + +'ADDR_DEF1': base address of structure. + +Note: this field is read-only. + [31:8] + read-only + + + + + ATT1 + SMPU region attributes 1 (master structure) + 0x24 + 32 + read-write + 0x7000109 + 0x9F00012D + + + UR + User read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + +Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. + [0:0] + read-only + + + UW + User write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-write + + + UX + User execute enable: +'0': Disabled (user, execute accesses are NOT allowed). +'1': Enabled (user, execute accesses are allowed). + +Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. + [2:2] + read-only + + + PR + Privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + +Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. + [3:3] + read-only + + + PW + Privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [4:4] + read-write + + + PX + Privileged execute enable: +'0': Disabled (privileged, execute accesses are NOT allowed). +'1': Enabled (privileged, execute accesses are allowed). + +Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. + [5:5] + read-only + + + NS + Non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [6:6] + read-write + + + PC_MASK_0 + This field specifies protection context identifier based access control for protection context '0'. + [8:8] + read-only + + + PC_MASK_15_TO_1 + This field specifies protection context identifier based access control. +Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. + [23:9] + read-write + + + REGION_SIZE + This field specifies the region size: +'7': 256 B region (8 32 B subregions) + +Note: this field is read-only. + [28:24] + read-only + + + PC_MATCH + This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: +'0': PC field participates in 'access evaluation'. +'1': PC field participates in 'matching'. + +'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. +'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. + +Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. + [30:30] + read-write + + + ENABLED + Region enable: +'0': Disabled. A disabled region will never result in a match on the bus transfer address. +'1': Enabled. + [31:31] + read-write + + + + + + + 16 + 1024 + MPU[%s] + MPU + 0x00004000 + + MS_CTL + Master control + 0x0 + 32 + read-write + 0x0 + 0xF000F + + + PC + Active protection context (PC). Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition, a write transfer with protection context '0' can change this field (protection context 0 has unrestricted access). + +The CM0+ MPU MS_CTL register is special: the PC field is modifiable by BOTH HW and SW (for all other masters, the MPU MS_CTL.PC field is modifiable by SW ONLY. For CM0+ PC field HW modifications, the following holds: +* On entry of a CM0_PC0/1/2/3_HANDLER exception/interrupt handler: + IF (the new PC is the same as MS_CTL.PC) + PC is not affected; PC_SAVED is not affected. + ELSE IF (CM0_PC_CTL.VALID[MS_CTL.PC]) + An AHB-Lite bus error is generated for the exception handler fetch; + PC is not affected; PC_SAVED is not affected. + ELSE + PC = 'new PC'; PC_SAVED = PC (push operation). +* On entry of any other exception/interrupt handler: + PC = PC_SAVED; PC_SAVED is not affected (pop operation). + +Note that the CM0_PC0/1/2/3_HANDLER and CM0_PC_CTL registers are part of repecitve CPUSS MMIO registers. + +Note: this field is NOT used by the DW controllers, DMA controller, AXI DMA controller, CRYPTO component and VIDEOSS. + [3:0] + read-write + + + PC_SAVED + Saved protection context. Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. + +Note: this field is ONLY used by the CM0+. + [19:16] + read-write + + + + + 127 + 4 + MS_CTL_READ_MIR[%s] + Master control read mirror + 0x4 + 32 + read-only + 0x0 + 0xF000F + + + PC + Read-only mirror of MS_CTL.PC + [3:0] + read-only + + + PC_SAVED + Read-only mirror of MS_CTL.PC_SAVED + [19:16] + read-only + + + + + 8 + 32 + MPU_STRUCT[%s] + MPU structure + 0x00000200 + + ADDR + MPU region address + 0x0 + 32 + read-write + 0x0 + 0x0 + + + SUBREGION_DISABLE + This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: +Bit 0: subregion 0 disable. +Bit 1: subregion 1 disable. +Bit 2: subregion 2 disable. +Bit 3: subregion 3 disable. +Bit 4: subregion 4 disable. +Bit 5: subregion 5 disable. +Bit 6: subregion 6 disable. +Bit 7: subregion 7 disable. +E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by MPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. + [7:0] + read-write + + + ADDR24 + This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored. + [31:8] + read-write + + + + + ATT + MPU region attrributes + 0x4 + 32 + read-write + 0x0 + 0x80000000 + + + UR + User read enable: +'0': Disabled (user, read accesses are NOT allowed). +'1': Enabled (user, read accesses are allowed). + [0:0] + read-write + + + UW + User write enable: +'0': Disabled (user, write accesses are NOT allowed). +'1': Enabled (user, write accesses are allowed). + [1:1] + read-write + + + UX + User execute enable: +'0': Disabled (user, execute accesses are NOT allowed). +'1': Enabled (user, execute accesses are allowed). + [2:2] + read-write + + + PR + Privileged read enable: +'0': Disabled (privileged, read accesses are NOT allowed). +'1': Enabled (privileged, read accesses are allowed). + [3:3] + read-write + + + PW + Privileged write enable: +'0': Disabled (privileged, write accesses are NOT allowed). +'1': Enabled (privileged, write accesses are allowed). + [4:4] + read-write + + + PX + Privileged execute enable: +'0': Disabled (privileged, execute accesses are NOT allowed). +'1': Enabled (privileged, execute accesses are allowed). + [5:5] + read-write + + + NS + Non-secure: +'0': Secure (secure accesses allowed, non-secure access NOT allowed). +'1': Non-secure (both secure and non-secure accesses allowed). + [6:6] + read-write + + + REGION_SIZE + This field specifies the region size: +'0'-'6': Undefined. +'7': 256 B region +'8': 512 B region +'9': 1 KB region +'10': 2 KB region +'11': 4 KB region +'12': 8 KB region +'13': 16 KB region +'14': 32 KB region +'15': 64 KB region +'16': 128 KB region +'17': 256 KB region +'18': 512 KB region +'19': 1 MB region +'20': 2 MB region +'21': 4 MB region +'22': 8 MB region +'23': 16 MB region +'24': 32 MB region +'25': 64 MB region +'26': 128 MB region +'27': 256 MB region +'28': 512 MB region +'39': 1 GB region +'30': 2 GB region +'31': 4 GB region + [28:24] + read-write + + + ENABLED + Region enable: +'0': Disabled. A disabled region will never result in a match on the bus transfer address. +'1': Enabled. + +Note: a disabled address region performs logic gating to reduce dynamic power consumption. + [31:31] + read-write + + + + + + + + + FLASHC + Flash controller + 0x40240000 + + 0 + 65536 + registers + + + + FLASH_CTL + Control + 0x0 + 32 + read-write + 0x1000000 + 0x177330F + + + WS + FLASH macro wait states (same for main and work interfaces): +'0': 0 wait states. +... +'15': 15 wait states + [3:0] + read-write + + + MAIN_MAP + N/A + [8:8] + read-write + + + WORK_MAP + N/A + [9:9] + read-write + + + MAIN_BANK_MODE + N/A + [12:12] + read-write + + + WORK_BANK_MODE + N/A + [13:13] + read-write + + + MAIN_ECC_EN + N/A + [16:16] + read-write + + + MAIN_ECC_INJ_EN + N/A + [17:17] + read-write + + + MAIN_ERR_SILENT + Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error or a FLASH macro main interface internal error): +0: Bus transfer has a bus error. +1: Bus transfer does NOT have a bus error; i.e. the error is 'silent' +In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. + +This field is ONLY used by CPU (or debug i.e. SYS_AP/CM0_AP/CM7_0/1_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. + +Note: All CPU bus masters have dedicated status registers (CM0_STATUS, CM7_0_STATUS and CM7_1_STATUS) to register the occurrence of FLASH macro main interface internal errors (non-correctable ECC errors are NOT registered). + +Note: fault reporting can be used to identify the error that occurred: +- FLASH macro main interface internal error. +- FLASH macro main interface non-recoverable ECC error. +- FLASH macro main interface recoverable ECC error. + [18:18] + read-write + + + WORK_ECC_EN + N/A + [20:20] + read-write + + + WORK_ECC_INJ_EN + N/A + [21:21] + read-write + + + WORK_ERR_SILENT + Specifies bus transfer behavior for a non-recoverable error on the FLASH macro work interface (either a non-correctable ECC error or a FLASH macro work interface internal error): +0: Bus transfer has a bus error. +1: Bus transfer does NOT have a bus error; i.e. the error is 'silent' +In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. + +This field is ONLY used by CPU (or debug i.e. SYS_AP/CM0_AP/CM7_0/1_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. + +Note: All CPU bus masters have dedicated status registers (CM0_STATUS, CM7_0_STATUS and CM7_1_STATUS) to register the occurrence of FLASH macro work interface internal errors (non-correctable ECC errors are NOT registered). + +Note: fault reporting can be used to identify the error that occurred: +- FLASH macro work interface internal error. +- FLASH macro work interface non-recoverable ECC error. +- FLASH macro work interface recoverable ECC error. + [22:22] + read-write + + + WORK_SEQ_RD_EN + Enable sequential read mode for Work Flash for read accesses on the AXI port. +0: Sequential read mode for Work Flash is disabled. +1: Sequential read mode for Work Flash is enabled. This speeds up subsequent AXI read accesses to the same page (64 bytes) of the Work Flash. + +Setting this field to '1' has a side effect on the round-robin arbitration of the Work Flash macro between the different ports. When this field is set to '1', then as soon as the arbitration of the Work Flash is given to the AXI port, it is not released before the current AXI read burst either has been completed or leaves the current Work Flash page (64 bytes). This means that AHB masters accessing the Work Flash that have the same priority as the AXI port will not get their fair share of the Work Flash bandwidth. While an AHB master can perform one Work Flash access per round-robin cycle (4 bytes), an AXI master can read a whole AXI burst, or up to the next Work Flash page boundary. +So if this field is set to '1', and an AHB master requires a high Work Flash bandwidth, then it should have a higher priority than the AXI masters accessing the Work Flash. + [24:24] + read-write + + + + + FLASH_PWR_CTL + Flash power control + 0x4 + 32 + read-write + 0x3 + 0x3 + + + ENABLE + Controls 'enable' pin of the Flash memory. + [0:0] + read-write + + + ENABLE_HV + Controls 'enable_hv' pin of the Flash memory. + [1:1] + read-write + + + + + FLASH_CMD + Command + 0x8 + 32 + read-write + 0x0 + 0x3 + + + INV + Invalidation of ALL caches (for CM0+) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches LRU structures are also reset to their default state. + [0:0] + read-write + + + BUFF_INV + Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. + +Note: the caches only capture FLASH macro main array data. Therefore, invalidating just the buffers (BUFF_INV) does not invalidate captures main array data in the caches. + [1:1] + read-write + + + + + ECC_CTL + ECC control + 0x2A0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WORD_ADDR + N/A + [23:0] + read-write + + + PARITY + N/A + [31:24] + read-write + + + + + FM_SRAM_ECC_CTL0 + eCT Flash SRAM ECC control 0 + 0x2B0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ECC_INJ_DATA + 32-bit data for ECC error injection test of eCT Flash SRAM ECC logic. + [31:0] + read-write + + + + + FM_SRAM_ECC_CTL1 + eCT Flash SRAM ECC control 1 + 0x2B4 + 32 + read-write + 0x0 + 0x7F + + + ECC_INJ_PARITY + 7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic. + [6:0] + read-write + + + + + FM_SRAM_ECC_CTL2 + eCT Flash SRAM ECC control 2 + 0x2B8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CORRECTED_DATA + 32-bit corrected data output of the ECC syndrome logic. + [31:0] + read-only + + + + + FM_SRAM_ECC_CTL3 + eCT Flash SRAM ECC control 3 + 0x2BC + 32 + read-write + 0x1 + 0x111 + + + ECC_ENABLE + ECC generation/check enable for eCT Flash SRAM memory. + [0:0] + read-write + + + ECC_INJ_EN + eCT Flash SRAM ECC error injection test enable. Follow the steps below for ECC logic test: +1. Write corrupted or uncorrupted 39-bit data to FM_SRAM_ECC_CTL0/1 registers. +2. Set the ECC_INJ_EN bit to '1'. +3. Confirm that the bit ECC_TEST_FAIL is '0'. If this is not the case, start over at item 1 because the eCT Flash was not idle. +4. Check the corrected data in FM_SRAM_ECC_CTL2. +5. Confirm that fault was reported to fault structure, and check syndrome (only applicable if +corrupted data was written in step 1). +6. If not finished, start over at 1 with different data. + [4:4] + read-write + + + ECC_TEST_FAIL + Status of ECC test. +1: ECC test failed because eCT Flash macro is busy and using the SRAM. +0: ECC was performed. + [8:8] + read-only + + + + + CM0_CA_CTL0 + CM0+ cache control + 0x400 + 32 + read-write + 0xC0000001 + 0xC7030003 + + + RAM_ECC_EN + Enable ECC checking for cache accesses: +0: Disabled. +1: Enabled. + [0:0] + read-write + + + RAM_ECC_INJ_EN + Enable error injection for cache. +When '1', the parity (ECC_CTL.PARITY[6:0]) is used when a refill is done from the FLASH macro to the ECC_CTL.WORD_ADDR[24:0] word address. + [1:1] + read-write + + + WAY + Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2. + [17:16] + read-write + + + SET_ADDR + Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2. + [26:24] + read-write + + + PREF_EN + Prefetch enable: +0: Disabled. +1: Enabled. + +Prefetching requires the cache to be enabled; i.e. ENABLED is '1'. + [30:30] + read-write + + + CA_EN + Cache enable: +0: Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way). +1: Enabled.G269 + [31:31] + read-write + + + + + CM0_CA_CTL1 + CM0+ cache control + 0x404 + 32 + read-write + 0xFA050003 + 0xFFFF0003 + + + PWR_MODE + Specifies power mode for CM0 cache. +The following sequnece should be followed for truning OFF/ON the cache SRAM. +Turn OFF sequence: +a) Write CM0_CA_CTL0 to disable cache. +b) Write CM0_CA_CTL1 to turn OFF cache SRAM. +Turn ON sequence: +a) Write CM0_CA_CTL1 to turn ON cache SRAM. +b) Delay to allow power up of cache SRAM. Delay should be at a minimum of CM0_CA_CTL2.PWRUP_DELAY CLK_SLOW clock cycles. +c) Write CM0_CA_CTL0 to enable cache. + [1:0] + read-write + + + OFF + Power OFF the CM0 cache SRAM. + 0 + + + RSVD + Undefined + 1 + + + RETAINED + Put CM0 cache SRAM in retained mode. + 2 + + + ENABLED + Enable/Turn ON the CM0 cache SRAM. + 3 + + + + + VECTKEYSTAT + Register key (to prevent accidental writes). +- Should be written with a 0x05fa key value for the write to take effect. +- Always reads as 0xfa05. +Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW. + [31:16] + read-only + + + + + CM0_CA_CTL2 + CM0+ cache control + 0x408 + 32 + read-write + 0x12C + 0x3FF + + + PWRUP_DELAY + Number clock cycles delay needed after power domain power up + [9:0] + read-write + + + + + CM0_CA_STATUS0 + CM0+ cache status 0 + 0x440 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + VALID32 + Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. + [31:0] + read-only + + + + + CM0_CA_STATUS1 + CM0+ cache status 1 + 0x444 + 32 + read-only + 0x0 + 0x0 + + + TAG + Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. + [31:0] + read-only + + + + + CM0_CA_STATUS2 + CM0+ cache status 2 + 0x448 + 32 + read-only + 0x0 + 0x0 + + + LRU + Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y): +Bit 5: 0_LRU_1: way 0 less recently used than way 1. +Bit 4: 0_LRU_2. +Bit 3: 0_LRU_3. +Bit 2: 1_LRU_2. +Bit 1: 1_LRU_3. +Bit 0: 2_LRU_3. + [5:0] + read-only + + + + + CM0_STATUS + CM0+ interface status + 0x460 + 32 + read-write + 0x0 + 0x3 + + + MAIN_INTERNAL_ERR + Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ (or debug access via SYS_AP/CM0_AP) access. + +SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. + +Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. + [0:0] + read-write + + + WORK_INTERNAL_ERR + See CM0_STATUS.MAIN_INTERNAL_ERROR. + [1:1] + read-write + + + + + CM7_0_STATUS + CM7 #0 interface status + 0x4E0 + 32 + read-write + 0x0 + 0x3 + + + MAIN_INTERNAL_ERR + Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM7_0 (or debug access via SYS_AP/CM7_0_AP) access. + +SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. + +Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. + [0:0] + read-write + + + WORK_INTERNAL_ERR + See CM7_0_STATUS.MAIN_INTERNAL_ERROR. + [1:1] + read-write + + + + + CM7_1_STATUS + CM7 #1 interface status + 0x560 + 32 + read-write + 0x0 + 0x3 + + + MAIN_INTERNAL_ERR + Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM7_1 (or debug access via SYS_AP/CM7_1_AP) access. + +SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. + +Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT. + [0:0] + read-write + + + WORK_INTERNAL_ERR + See CM7_1_STATUS.MAIN_INTERNAL_ERROR. + [1:1] + read-write + + + + + CRYPTO_BUFF_CTL + Cryptography buffer control + 0x580 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + Prefetch enable: +0: Disabled. +1: Enabled. + [30:30] + read-write + + + + + DW0_BUFF_CTL + Datawire 0 buffer control + 0x600 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + DW1_BUFF_CTL + Datawire 1 buffer control + 0x680 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + DMAC_BUFF_CTL + DMA controller buffer control + 0x700 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + SLOW0_MS_BUFF_CTL + Slow external master 0 buffer control + 0x780 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + SLOW1_MS_BUFF_CTL + Slow external master 1 buffer control + 0x800 + 32 + read-write + 0x40000000 + 0x40000000 + + + PREF_EN + See CRYPTO_BUFF_CTL. + [30:30] + read-write + + + + + FM_CTL_ECT + Flash Macro Registers + 0x0000F000 + + FM_CTL + Flash Macro Control + 0x0 + 32 + read-write + 0x0 + 0x8000001F + + + FM_MODE + Flash macro mode selection: +d0: Read/Idle - Normal mode, read array enabled +d1: Not Used - the 1st analog POR is done by enable/enable_hv +d2 - POR FUR Download - Downloads critical Flash initialization data from OTP (BG, rd, redu, etc....) +d3 - POR IRAM MMR Download - Downloads from OTP region the MMR / IRAM into to the 8051 RDL shadows +d4 - POR SW Download - Downloads from OTP region the SW code into to the 8051 MCU SRAM +d5 - POR Code_Work Prepare - Loads the Code and Work Flash MG's to be ready for user mode operation +d6 - Not Used +d7 - Program 32b (WORK) - Used as program confirm command for 32 (Work) bits program +d8 - Program 64b (CODE) - Used as program confirm command for 64 (Code) bits program +d9 - Program 256b (CODE) - Used as program confirm command for 256 (Code) bits program +d10: Program Page (CODE) - Used as program confirm command for page program for Code flash +d11: Not Used +d12 - Sector Erase - Erase for all kinds of sectors (Code/Work/SMS) +d13 - Blank check Entry (UBC) +d14 - Blank Check Read 32bit (WORK) - Blank check mode +d15 - Blank check Exit +d16 - Not Used +d17 - Erase Suspend - Suspend command to the Erase operation +d18 - Erase Resume - Resume command to Erase suspended operation +d19 - Not Used +d20- Not Used +d21- Not Used +d22- Not Used +d23- Not Used +d24- Not Used +d25- Not Used +d26- Not Used +d27- Not Used +d28- Not Used +d29- Not Used +d30: Not Used +d31: Not Used + [4:0] + read-write + + + EMB_START + '0': not active +'1': starts the actual embedded operation + [31:31] + read-write + + + + + FM_CODE_MARGIN + Flash Macro Margin Mode on Code Flash + 0x4 + 32 + read-write + 0x3943 + 0xE000FFFF + + + MARGIN_DCS_TRIM + see above table to set the DCS reference current value to be used during Margin mode. (default set to 5uS = 0x143) which gives a Margin to the Erase side. 7uA would probably be used for Margin to the PGM side + [8:0] + read-write + + + MARGIN_DCS_TRIM_EN + 0: internal device defaults used from Margin reads reference current +1: MARGIN_DCS_TRIM configuration is used during Margin read + [9:9] + read-write + + + MARGIN_RDREG_TRIM + rdreg_c trim to be used in Margin mode if enabled by MARGIN_MODE_RDREG_CHNG_EN + [15:10] + read-write + + + MARGIN_PGM_ERS_B + 0: ERS Margin is checked +1: PGM Margin is checked + [29:29] + read-write + + + MARGIN_MODE_RDREG_CHNG_EN + when set will also use the MARGIN_RDREG_TRIM from above. Default is not to use + [30:30] + read-write + + + MARGIN_MODE_EN + when set puts the s40ect Flash IP In Margin mode + [31:31] + read-write + + + + + FM_ADDR + Flash Macro Address + 0x8 + 32 + write-only + 0x0 + 0xFFFFFFFF + + + FM_ADDR + Code or Work Flash Address to be used during write operations (PGM/ERS) + [31:0] + write-only + + + + + INTR + Interrupt + 0x20 + 32 + read-write + 0x0 + 0x1 + + + INTR + Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit. + [0:0] + read-write + + + + + INTR_SET + Interrupt Set + 0x24 + 32 + read-write + 0x0 + 0x1 + + + INTR_SET + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [0:0] + read-write + + + + + INTR_MASK + Interrupt Mask + 0x28 + 32 + read-write + 0x0 + 0x1 + + + INTR_MASK + Mask for corresponding field in the INTR register + [0:0] + read-write + + + + + INTR_MASKED + Interrupt Masked + 0x2C + 32 + read-only + 0x0 + 0x1 + + + INTR_MASKED + Logical and of corresponding request and mask fields. + [0:0] + read-only + + + + + ECC_OVERRIDE + ECC Data In override information and control bits + 0x30 + 32 + write-only + 0x0 + 0xC00000FF + + + ECC_OVERRIDE_SYNDROME + The override syndrome itself to be used in case one of the enables are set. It will take [7:0] in the case of Code flash and [6:0] in the case of work flash, to bypass the internal generated syndrome + [7:0] + write-only + + + ECC_OVERRIDE_WORK + 0: no override. Using internal ECC engine to calculate the ECC of the Work Flash + [30:30] + write-only + + + ECC_OVERRIDE_CODE + 0: no override. Using internal ECC engine to calculate the ECC of the Code Flash + [31:31] + write-only + + + + + FM_DATA + Flash macro data_in[31 to 0] both Code and Work Flash + 0x40 + 32 + write-only + 0x0 + 0xFFFFFFFF + + + FM_DATA + Pgm command data in going to the internal write buffer (WBUF). + [31:0] + write-only + + + + + BOOKMARK + Bookmark register - keeps the current FW HV seq + 0x64 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + BOOKMARK + Used by FW. Keeps the Current HV cycle sequence + [31:0] + read-write + + + + + MAIN_FLASH_SAFETY + Main (Code) Flash Security enable + 0x400 + 32 + read-write + 0x0 + 0x1 + + + MAINFLASHWRITEENABLE + '0': Main Flash embedded operations are blocked +'1': Main Flash embedded operations are enabled + [0:0] + read-write + + + + + STATUS + Status read from Flash Macro + 0x404 + 32 + read-only + 0x80000000 + 0xF800007F + + + PGM_CODE + Indicates if active PGM operation to the Code flash is taking place +0: not running +1: running + [0:0] + read-only + + + PGM_WORK + Indicates if active PGM operation to the Work flash is taking place +0: not running +1: running + [1:1] + read-only + + + ERASE_CODE + Indicates if active Erase operation to the Code flash is taking place +0: not running +1: running + [2:2] + read-only + + + ERASE_WORK + Indicates if active Erase operation to the Work flash is taking place +0: not running +1: running + [3:3] + read-only + + + ERS_SUSPEND + Indicates if Erase operation (Code/Work) is currently being suspended +0: not suspended +1: suspended + [4:4] + read-only + + + BLANK_CHECK_WORK + Indicates if Blank Check mode is currently running on the work flash +0: not running +1: running + [5:5] + read-only + + + BLANK_CHCEK_PASS + Indicates the Blank check command result is PASS (Blank) +0: Not Blank +1: Blank (PASS) + [6:6] + read-only + + + POR_1B_ECC_CORRECTED + Indicates internal ECC found 1b error while downloading info in POR from NVM to VM and fixed it. +Valid after 2nd, 3rd and 4th POR phases (FUR, IREM & MMR, SW DOWNLOAD). If Set it is not cleaned till additional POR (rst_hf_ac_t) +0: No error +1: 1b ECC Error corrected in POR + [27:27] + read-only + + + POR_2B_ECC_ERROR + Indicates an internal ECC error of 2b while downloading info in POR from NVM to VM. +Valid after 2nd, 3rd and 4th POR phases (FUR, IREM & MMR, SW DOWNLOAD). If Set it is not cleaned till additional POR (rst_hf_ac_t) +0: No error +1: ECC 2b Error in POR + [28:28] + read-only + + + NATIVE_POR + Indicates a Native Flash state (UV) or sorted one. +Valid only after 2nd phase of POR (FUR DOWNLOAD). +Comment: not a retained flop, therefore reset (rst_hf_act_n) puts it back to 0. If Set it is not cleaned till additional POR (rst_hf_ac_t) +0: SORTED DEVICE (Non - Native) +1: NATIVE + [29:29] + read-only + + + HANG + After embedded operation (pgm/erase) this flag will tell if it was successful or failed +0: PASS +1: FAIL + [30:30] + read-only + + + BUSY + Whenever the device is in embedded mode the RDY goes low. Should be the same as c_interrupt pin of the IP (but inverted) +1: busy in embedded +0: rdy (high also in erase suspend) + [31:31] + read-only + + + + + WORK_FLASH_SAFETY + Work Flash Security enable + 0x500 + 32 + read-write + 0x0 + 0x1 + + + WORKFLASHWRITEENABLE + 0: Work Flash embedded operations are blocked +1: Work Flash embedded operations are enabled + [0:0] + read-write + + + + + + + + SRSS + SRSS Core Registers (ver3) + 0x40260000 + + 0 + 65536 + registers + + + + PWR_LVD_STATUS + High Voltage / Low Voltage Detector (HVLVD) Status Register + 0x40 + 32 + read-only + 0x0 + 0x1 + + + HVLVD1_OUT + HVLVD1 output. +0: below voltage threshold +1: above voltage threshold + [0:0] + read-only + + + + + PWR_LVD_STATUS2 + High Voltage / Low Voltage Detector (HVLVD) Status Register #2 + 0x44 + 32 + read-only + 0x0 + 0x1 + + + HVLVD2_OUT + HVLVD2 output. +0: below voltage threshold +1: above voltage threshold + [0:0] + read-only + + + + + 16 + 4 + CLK_DSI_SELECT[%s] + Clock DSI Select Register + 0x100 + 32 + read-write + 0x0 + 0x1F + + + DSI_MUX + Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH<i> using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or as reference inputs for the FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. + [4:0] + read-write + + + DSI_OUT0 + DSI0 - dsi_out[0] + 0 + + + DSI_OUT1 + DSI1 - dsi_out[1] + 1 + + + DSI_OUT2 + DSI2 - dsi_out[2] + 2 + + + DSI_OUT3 + DSI3 - dsi_out[3] + 3 + + + DSI_OUT4 + DSI4 - dsi_out[4] + 4 + + + DSI_OUT5 + DSI5 - dsi_out[5] + 5 + + + DSI_OUT6 + DSI6 - dsi_out[6] + 6 + + + DSI_OUT7 + DSI7 - dsi_out[7] + 7 + + + DSI_OUT8 + DSI8 - dsi_out[8] + 8 + + + DSI_OUT9 + DSI9 - dsi_out[9] + 9 + + + DSI_OUT10 + DSI10 - dsi_out[10] + 10 + + + DSI_OUT11 + DSI11 - dsi_out[11] + 11 + + + DSI_OUT12 + DSI12 - dsi_out[12] + 12 + + + DSI_OUT13 + DSI13 - dsi_out[13] + 13 + + + DSI_OUT14 + DSI14 - dsi_out[14] + 14 + + + DSI_OUT15 + DSI15 - dsi_out[15] + 15 + + + ILO0 + ILO0 - Internal Low-speed Oscillator #0 + 16 + + + WCO + WCO - Watch-Crystal Oscillator + 17 + + + ALTLF + ALTLF - Alternate Low-Frequency Clock + 18 + + + PILO + PILO - Precision Internal Low-speed Oscillator + 19 + + + ILO1 + ILO1 - Internal Low-speed Oscillator #1, if present. + 20 + + + + + + + CLK_OUTPUT_FAST + Fast Clock Output Select Register + 0x140 + 32 + read-write + 0x0 + 0xFFF0FFF + + + FAST_SEL0 + Select signal for fast clock output #0 + [3:0] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0. + 0 + + + ECO + External Crystal Oscillator (ECO) + 1 + + + EXTCLK + External clock input (EXTCLK) + 2 + + + ALTHF + Alternate High-Frequency (ALTHF) clock input to SRSS + 3 + + + TIMERCLK + Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. + 4 + + + PATH_SEL0 + Selects the clock path chosen by PATH_SEL0 field + 5 + + + HFCLK_SEL0 + Selects the output of the HFCLK_SEL0 mux + 6 + + + SLOW_SEL0 + Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0 + 7 + + + + + PATH_SEL0 + Selects a clock path to use in fast clock output #0 logic. +0: FLL output +1-15: PLL output on path1-path15 (if available) + [7:4] + read-write + + + HFCLK_SEL0 + Selects a HFCLK tree for use in fast clock output #0 + [11:8] + read-write + + + FAST_SEL1 + Select signal for fast clock output #1 + [19:16] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1. + 0 + + + ECO + External Crystal Oscillator (ECO) + 1 + + + EXTCLK + External clock input (EXTCLK) + 2 + + + ALTHF + Alternate High-Frequency (ALTHF) clock input to SRSS + 3 + + + TIMERCLK + Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. + 4 + + + PATH_SEL1 + Selects the clock path chosen by PATH_SEL1 field + 5 + + + HFCLK_SEL1 + Selects the output of the HFCLK_SEL1 mux + 6 + + + SLOW_SEL1 + Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1 + 7 + + + + + PATH_SEL1 + Selects a clock path to use in fast clock output #1 logic. +0: FLL output +1-15: PLL output on path1-path15 (if available) + [23:20] + read-write + + + HFCLK_SEL1 + Selects a HFCLK tree for use in fast clock output #1 logic + [27:24] + read-write + + + + + CLK_OUTPUT_SLOW + Slow Clock Output Select Register + 0x144 + 32 + read-write + 0x0 + 0xFF + + + SLOW_SEL0 + Select signal for slow clock output #0 + [3:0] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. + 0 + + + ILO0 + Internal Low Speed Oscillator (ILO0) + 1 + + + WCO + Watch-Crystal Oscillator (WCO) + 2 + + + BAK + Root of the Backup domain clock tree (BAK) + 3 + + + ALTLF + Alternate low-frequency clock input to SRSS (ALTLF) + 4 + + + LFCLK + Root of the low-speed clock tree (LFCLK) + 5 + + + IMO + Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 6 + + + SLPCTRL + Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 7 + + + PILO + Precision Internal Low Speed Oscillator (PILO) + 8 + + + ILO1 + Internal Low Speed Oscillator (ILO1), if present on the product. + 9 + + + ECO_PRESCALER + ECO Prescaler (ECO_PRESCALER) + 10 + + + LPECO + LPECO + 11 + + + LPECO_PRESCALER + LPECO Prescaler (LPECO_PRESCALER) + 12 + + + + + SLOW_SEL1 + Select signal for slow clock output #1 + [7:4] + read-write + + + NC + Disabled - output is 0. For power savings, clocks are blocked before entering any muxes. + 0 + + + ILO0 + Internal Low Speed Oscillator (ILO) + 1 + + + WCO + Watch-Crystal Oscillator (WCO) + 2 + + + BAK + Root of the Backup domain clock tree (BAK) + 3 + + + ALTLF + Alternate low-frequency clock input to SRSS (ALTLF) + 4 + + + LFCLK + Root of the low-speed clock tree (LFCLK) + 5 + + + IMO + Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 6 + + + SLPCTRL + Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit. + 7 + + + PILO + Precision Internal Low Speed Oscillator (PILO) + 8 + + + ILO1 + Internal Low Speed Oscillator (ILO1), if present on the product. + 9 + + + ECO_PRESCALER + ECO Prescaler (ECO_PRESCALER) + 10 + + + LPECO + LPECO + 11 + + + LPECO_PRESCALER + LPECO Prescaler (LPECO_PRESCALER) + 12 + + + + + + + CLK_CAL_CNT1 + Clock Calibration Counter 1 + 0x148 + 32 + read-write + 0x80000000 + 0x80FFFFFF + + + CAL_COUNTER1 + Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done. Do not write this field unless CAL_COUNTER_DONE==1. Both clocks must be running or the measurement will not complete. A stalled counter can be recovered by selecting valid clocks, waiting until the measurement completes, and discarding the first result. + [23:0] + read-write + + + CAL_COUNTER_DONE + Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up + [31:31] + read-only + + + + + CLK_CAL_CNT2 + Clock Calibration Counter 2 + 0x14C + 32 + read-only + 0x0 + 0xFFFFFF + + + CAL_COUNTER2 + Up-counter clocked on fast clock output #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER) + [23:0] + read-only + + + + + SRSS_INTR + SRSS Interrupt Register + 0x200 + 32 + read-write + 0x0 + 0x26 + + + HVLVD1 + Interrupt for low voltage detector HVLVD1 + [1:1] + read-write + + + HVLVD2 + Interrupt for low voltage detector HVLVD2 + [2:2] + read-write + + + CLK_CAL + Clock calibration counter is done. This field is reset during DEEPSLEEP mode. + [5:5] + read-write + + + + + SRSS_INTR_SET + SRSS Interrupt Set Register + 0x204 + 32 + read-write + 0x0 + 0x26 + + + HVLVD1 + Set interrupt for low voltage detector HVLVD1 + [1:1] + read-write + + + HVLVD2 + Set interrupt for low voltage detector HVLVD2 + [2:2] + read-write + + + CLK_CAL + Set interrupt for clock calibration counter done. This field is reset during DEEPSLEEP mode. + [5:5] + read-write + + + + + SRSS_INTR_MASK + SRSS Interrupt Mask Register + 0x208 + 32 + read-write + 0x0 + 0x26 + + + HVLVD1 + Mask for low voltage detector HVLVD1 + [1:1] + read-write + + + HVLVD2 + Mask for low voltage detector HVLVD2 + [2:2] + read-write + + + CLK_CAL + Mask for clock calibration done + [5:5] + read-write + + + + + SRSS_INTR_MASKED + SRSS Interrupt Masked Register + 0x20C + 32 + read-only + 0x0 + 0x26 + + + HVLVD1 + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + HVLVD2 + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + CLK_CAL + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + + + PWR_CTL + Power Mode Control + 0x1000 + 32 + read-only + 0x0 + 0x33 + + + POWER_MODE + Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon. + [1:0] + read-only + + + RESET + System is resetting. + 0 + + + ACTIVE + At least one CPU is running. + 1 + + + SLEEP + No CPUs are running. Peripherals may be running. + 2 + + + DEEPSLEEP + Main high-frequency clock is off; low speed clocks are available. Communication interface clocks may be present. + 3 + + + + + DEBUG_SESSION + Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1) + [4:4] + read-only + + + NO_SESSION + No debug session active + 0 + + + SESSION_ACTIVE + Debug session is active. Power modes behave differently to keep the debug session active. + 1 + + + + + LPM_READY + Indicates whether certain low power functions are ready. The low current circuits take longer to startup after XRES, HIBERNATE wakeup, or supply supervision reset wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless of this bit. +0: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready. If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP. When low power circuits are ready, device will automatically enter the originally requested mode. +1: Normal operation. DEEPSLEEP and low power circuits operate as requested in other registers. + [5:5] + read-only + + + + + PWR_CTL2 + Power Mode Control 2 + 0x1004 + 32 + read-write + 0x0 + 0x9F731117 + + + LINREG_DIS + Explicitly disable the linear Core Regulator. Write zero for Traveo II devices. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. +0: Linear Core Regulator is not explicitly disabled. Hardware disables it automatically for internal sequences, including for DEEPSLEEP, HIBERNATE, and XRES low power modes. +1: Linear Core Regulator is explicitly disabled. Only use this for special cases when another source supplies vccd during ACTIVE and SLEEP modes. This setting is only legal when another source supplies vccd, but there is no special hardware protection for this case. + [0:0] + read-write + + + LINREG_OK + Status of the linear Core Regulator. + [1:1] + read-only + + + LINREG_LPMODE + Control the power mode of the Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. +0: Linear Regulator operates in normal mode. Internal current consumption is 50uA and load current capability is 50mA to 300mA, depending on the number of regulator modules present in the product. +1: Linear Regulator operates in low power mode. Internal current consumption is 5uA and load current capability is 25mA. Firmware must ensure the current is kept within the limit. + [2:2] + read-write + + + DPSLP_REG_DIS + Explicity disable the DeepSleep regulator, including circuits shared with the Active Regulator. This register must not be set except as part of a Cypress-provided sequence or API, such as the PMIC case described below. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. If the DeepSleep regulator is disabled, it is not supported to enable it again later by clearing this bit. +0: DeepSleep Regulator is not explicitly disabled. This is the normal setting, and hardware automatically controls the DeepSleep regulator for most sequences, including for HIBERNATE and XRES low power modes. This setting must be used if the Active Linear Regulator is used, because some circuitry is shared. +1: DeepSleep Regulator is explicitly disabled. Only use this for special cases when another source supplies vccdpslp during DEEPSLEEP mode and there is no future intention to use the Active Regulator for ACTIVE/SLEEP modes. For example, this setting is used as part of a Cypress-provided handover sequence to a PMIC that operates in ACTIVE, SLEEP, and DEEPSLEEP and disables both the Active Linear Regulator and DeepSleep Regulator. + [4:4] + read-write + + + RET_REG_DIS + Explicitly disable the Retention regulator. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. +0: Retention Regulator is not explicitly disabled. Hardware disables it automatically for internal sequences, including for HIBERNATE and XRES low power modes. Hardware keeps the Retention Regulator enabled during ACTIVE/SLEEP modes, so it is ready to enter DEEPSLEEP at any time. +1: Retention Regulator is explicitly disabled. Only use this for special cases when another source supplies vccret during DEEPSLEEP mode. This setting is only legal when another source supplies vccret, but there is no special hardware protection for this case. + [8:8] + read-write + + + NWELL_REG_DIS + Explicitly disable the Nwell regulator. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. +0: Nwell Regulator is on. Hardware disables it automatically for internal sequences, including for HIBERNATE and XRES low power modes. Hardware keeps the Nwell Regulator enabled during ACTIVE/SLEEP modes, so it is ready to enter DEEPSLEEP at any time. +1: Nwell Regulator is explicitly disabled. Only use this for special cases when another source supplies vnwell during DEEPSLEEP mode. This setting is only legal when another source supplies vnwell, but there is no special hardware protection for this case. + [12:12] + read-write + + + REFV_DIS + N/A + [16:16] + read-write + + + REFV_OK + Indicates that the normal mode of the voltage reference is ready. + [17:17] + read-only + + + REFVBUF_DIS + Disable the voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS that use the buffer. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. + [20:20] + read-write + + + REFVBUF_OK + Indicates that the voltage reference buffer is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting REFVBUF_DIS=1. + [21:21] + read-only + + + REFVBUF_LPMODE + Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. +0: Voltage Reference Buffer operates in normal mode. They work for vddd ramp rates of 100mV/us or less. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. +1: Voltage Reference Buffer operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. + [22:22] + read-write + + + REFI_DIS + N/A + [24:24] + read-write + + + REFI_OK + Indicates that the current reference is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting REFI_DIS=1. + [25:25] + read-only + + + REFI_LPMODE + Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. +0: Current reference generator operates in normal mode. It works for vddd ramp rates of 100mV/us or less. +1: Current reference generator operates in low power mode. Response time is reduced to save current, and it works for vddd ramp rates of 10mV/us or less. + [26:26] + read-write + + + PORBOD_LPMODE + Control the power mode of the POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. +0: POR/BOD circuits operate in normal mode. They work for vddd ramp rates of 100mV/us or less. +1: POR/BOD circuits operate in low power mode. Response time is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. + [27:27] + read-write + + + BGREF_LPMODE + Control the circuit-level power mode of the Bandgap Reference circuits. +0: Bandgap Reference circuits operate in higher current mode. +1: Bandgap Reference circuits operate in low power. Refer to documentation for restrictions. + +HT-variant: This register will not set unless CLK_ILO0_CONFIG.ILO0_ENABLE==1. When disabling low power operation, keep ILO0 enabled for at least 5 cycles after clearing this bit to allow for internal synchronization. + [28:28] + read-write + + + PLL_LS_BYPASS + Bypass level shifter inside the PLL. Unused, if no PLL is present in the product. +0: Do not bypass the level shifter. This setting is ok for all operational modes and vccd target voltage. +1: Bypass the level shifter. This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal. Otherwise, it can result in clock degradation and static current. + [31:31] + read-write + + + + + PWR_HIBERNATE + HIBERNATE Mode Register + 0x1008 + 32 + read-write + 0x0 + 0xCFFEFFFF + + + TOKEN + Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register. + [7:0] + read-write + + + UNLOCK + This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description. + [15:8] + read-write + + + FREEZE + Firmware sets this bit to freeze the configuration, mode and state of all GPIOs and SIOs in the system. When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command. This occurs even in the illegal condition where UNLOCK is not set. If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write. Supply supervision is disabled during HIBERNATE mode. HIBERNATE peripherals ignore resets (excluding XRES) while FREEZE==1. + [17:17] + read-write + + + MASK_HIBALARM + When set, HIBERNATE will wakeup for a RTC interrupt + [18:18] + read-write + + + MASK_HIBWDT + When set, HIBERNATE will wakeup for WDT interrupt + [19:19] + read-write + + + POLARITY_HIBPIN + Each bit sets the active polarity of the corresponding wakeup pin. +0: Pin input of 0 will wakeup the part from HIBERNATE +1: Pin input of 1 will wakeup the part from HIBERNATE + [23:20] + read-write + + + MASK_HIBPIN + When set, HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting. Each bit corresponds to one of the wakeup pins. + [27:24] + read-write + + + HIBERNATE_DISABLE + Hibernate disable bit. +0: Normal operation, HIBERNATE works as described +1: Further writes to this register are ignored +Note: This bit is a write-once bit until the next reset. Avoid changing any other bits in this register while disabling HIBERNATE mode. Also, it is recommended to clear the UNLOCK code, if it was previously written.. + [30:30] + read-write + + + HIBERNATE + Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event. Both UNLOCK and FREEZE must have been set correctly in a previous write operations. Otherwise, it will not enter HIBERNATE. External supplies must have been stable for 250us before entering HIBERNATE mode. + [31:31] + read-write + + + + + PWR_BUCK_CTL + Buck Control Register + 0x1010 + 32 + read-write + 0x5 + 0xC0000007 + + + BUCK_OUT1_SEL + Voltage output selection for vccbuck1 output. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. +0: 0.85V +1: 0.875V +2: 0.90V +3: 0.95V +4: 1.05V +5: 1.10V +6: 1.15V +7: 1.20V + [2:0] + read-write + + + BUCK_EN + Master enable for buck converter. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. + [30:30] + read-write + + + BUCK_OUT1_EN + Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. The TRM specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1. + [31:31] + read-write + + + + + PWR_BUCK_CTL2 + Buck Control Register 2 + 0x1014 + 32 + read-write + 0x0 + 0xC0000007 + + + BUCK_OUT2_SEL + Voltage output selection for vccbuck2 output. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. +0: 1.15V +1: 1.20V +2: 1.25V +3: 1.30V +4: 1.35V +5: 1.40V +6: 1.45V +7: 1.50V + [2:0] + read-write + + + BUCK_OUT2_HW_SEL + Hardware control for vccbuck2 output. When this bit is set, the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the product has supporting hardware, it can directly control the enable signal for vccbuck2. The same charging time in BUCK_OUT2_EN applies. + [30:30] + read-write + + + BUCK_OUT2_EN + Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. + [31:31] + read-write + + + + + PWR_SSV_CTL + Supply Supervision Control Register + 0x1018 + 32 + read-write + 0x8080808 + 0x9D909D9 + + + BODVDDD_VSEL + Selects the voltage threshold for BOD on vddd. The BOD does not reliably monitor the supply during the transition. +0: vddd<2.7V +1: vddd<3.0V + [0:0] + read-write + + + BODVDDD_ENABLE + Enable for BOD on vddd. This cannot be disabled during normal operation. + [3:3] + read-write + + + BODVDDA_VSEL + Selects the voltage threshold for BOD on vdda. Ensure BODVDDA_ENABLE==0 before changing this setting to prevent false triggers. +0: vdda<2.7V +1: vdda<3.0V + [4:4] + read-write + + + BODVDDA_ACTION + Action taken when the BOD on vdda triggers. + [7:6] + read-write + + + NOTHING + No action + 0 + + + FAULT + Generate a fault + 1 + + + RESET + Reset the chip + 2 + + + + + BODVDDA_ENABLE + Enable for BOD on vdda. BODVDDA_ACTION will be triggered when the BOD is disabled. If no action is desired when disabling, firmware must first write BODVDDA_ACTION=NOTHING in a separate write cycle. + [8:8] + read-write + + + BODVCCD_ENABLE + Enable for BOD on vccd. This cannot be disabled during normal operation. + [11:11] + read-write + + + OVDVDDD_VSEL + Selects the voltage threshold for OVD on vddd. The OVD does not reliably monitor the supply during the transition. +0: vddd>5.5V +1: vddd>5.0V + [16:16] + read-write + + + OVDVDDD_ENABLE + Enable for OVD on vddd. This cannot be disabled during normal operation. + [19:19] + read-write + + + OVDVDDA_VSEL + Selects the voltage threshold for OVD on vdda. Ensure OVDVDDA_ENABLE==0 before changing this setting to prevent false triggers +0: vddd>5.5V +1: vddd>5.0V + [20:20] + read-write + + + OVDVDDA_ACTION + Action taken when the OVD on vdda triggers. + [23:22] + read-write + + + NOTHING + No action + 0 + + + FAULT + Generate a fault + 1 + + + RESET + Reset the chip + 2 + + + + + OVDVDDA_ENABLE + Enable for OVD on vdda. + [24:24] + read-write + + + OVDVCCD_ENABLE + Enable for OVD on vccd. This cannot be disabled during normal operation. + [27:27] + read-write + + + + + PWR_SSV_STATUS + Supply Supervision Status Register + 0x101C + 32 + read-only + 0x30505 + 0x30707 + + + BODVDDD_OK + BOD indicates vddd is ok. This will always read 1, because a detected brownout will reset the chip. + [0:0] + read-only + + + BODVDDA_OK + BOD indicates vdda is ok. + [1:1] + read-only + + + BODVCCD_OK + BOD indicates vccd is ok. This will always read 1, because a detected brownout will reset the chip. + [2:2] + read-only + + + OVDVDDD_OK + OVD indicates vddd is ok. This will always read 1, because a detected over-voltage condition will reset the chip. + [8:8] + read-only + + + OVDVDDA_OK + OVD indicates vdda is ok. + [9:9] + read-only + + + OVDVCCD_OK + OVD indicates vccd is ok. This will always read 1, because a detected over-over-voltage condition will reset the chip. + [10:10] + read-only + + + OCD_ACT_LINREG_OK + OCD indicates the current drawn from the linear Active Regulator is ok. This will always read 1, because a detected over-current condition will reset the chip. + [16:16] + read-only + + + OCD_DPSLP_REG_OK + OCD indicates the current drawn from the linear DeepSleep Regulator is ok. This will always read 1, because a detected over-current condition will reset the chip. + [17:17] + read-only + + + + + PWR_LVD_CTL + High Voltage / Low Voltage Detector (HVLVD) Configuration Register + 0x1020 + 32 + read-write + 0x0 + 0x7DFFF + + + HVLVD1_TRIPSEL + Threshold selection for HVLVD1. Disable the detector (HVLVD1_EN=0) before changing the threshold. +0: rise=1.225V (nom), fall=1.2V (nom) +1: rise=1.425V (nom), fall=1.4V (nom) +2: rise=1.625V (nom), fall=1.6V (nom) +3: rise=1.825V (nom), fall=1.8V (nom) +4: rise=2.025V (nom), fall=2V (nom) +5: rise=2.125V (nom), fall=2.1V (nom) +6: rise=2.225V (nom), fall=2.2V (nom) +7: rise=2.325V (nom), fall=2.3V (nom) +8: rise=2.425V (nom), fall=2.4V (nom) +9: rise=2.525V (nom), fall=2.5V (nom) +10: rise=2.625V (nom), fall=2.6V (nom) +11: rise=2.725V (nom), fall=2.7V (nom) +12: rise=2.825V (nom), fall=2.8V (nom) +13: rise=2.925V (nom), fall=2.9V (nom) +14: rise=3.025V (nom), fall=3.0V (nom) +15: rise=3.125V (nom), fall=3.1V (nom) + [3:0] + read-write + + + HVLVD1_SRCSEL + Source selection for HVLVD1 + [6:4] + read-write + + + VDDD + Select VDDD + 0 + + + AMUXBUSA + Select AMUXBUSA (VDDD branch) + 1 + + + RSVD + N/A + 2 + + + VDDIO + N/A + 3 + + + AMUXBUSB + Select AMUXBUSB (VDDD branch) + 4 + + + + + HVLVD1_EN + Enable HVLVD1 voltage monitor. HVLVD1 does not function during DEEPSLEEP, but it automatically returns to its configured setting after DEEPSLEEP wakeup. Do not change other HVLVD1 settings when enabled. + [7:7] + read-write + + + HVLVD1_TRIPSEL_HT + N/A + [12:8] + read-write + + + HVLVD1_DPSLP_EN_HT + Keep HVLVD1 voltage monitor enabled during DEEPSLEEP mode. This field is only used when HVLVD1_EN_HT==1. + [14:14] + read-write + + + HVLVD1_EN_HT + Enable HVLVD1 voltage monitor. This detector monitors vddd only. Do not change other HVLVD1 settings when enabled. + [15:15] + read-write + + + HVLVD1_EDGE_SEL + Sets which edge(s) will trigger an action when the threshold is crossed. + [17:16] + read-write + + + DISABLE + Disabled + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + HVLVD1_ACTION + Action taken when the threshold is crossed in the programmed directions(s) + [18:18] + read-write + + + INTERRUPT + Generate an interrupt + 0 + + + FAULT + Generate a fault + 1 + + + + + + + PWR_LVD_CTL2 + High Voltage / Low Voltage Detector (HVLVD) Configuration Register #2 + 0x1024 + 32 + read-write + 0x0 + 0x7DF00 + + + HVLVD2_TRIPSEL_HT + N/A + [12:8] + read-write + + + HVLVD2_DPSLP_EN_HT + Keep HVLVD2 voltage monitor enabled during DEEPSLEEP mode. This field is only used when HVLVD1_EN_HT==1. + [14:14] + read-write + + + HVLVD2_EN_HT + Enable HVLVD2 voltage monitor. This detector monitors vddd only. Do not change other HVLVD2 settings when enabled. + [15:15] + read-write + + + HVLVD2_EDGE_SEL + Sets which edge(s) will trigger an action when the threshold is crossed. + [17:16] + read-write + + + DISABLE + Disabled + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + HVLVD2_ACTION + Action taken when the threshold is crossed in the programmed directions(s) + [18:18] + read-write + + + INTERRUPT + Generate an interrupt + 0 + + + FAULT + Generate a fault + 1 + + + + + + + PWR_REGHC_CTL + REGHC Control Register + 0x1028 + 32 + read-write + 0x40000104 + 0xFFFF7DFD + + + REGHC_MODE + REGHC control mode: +0: external transistor connected, +1: external PMIC connected + [0:0] + read-write + + + REGHC_PMIC_DRV_VOUT + Setting for DRV_VOUT pin for PMIC mode. See REGHC_VADJ for calculation of vadj. +2'b00: DRV_VOUT=vccd*0.9/vadj; +2'b01: DRV_VOUT=vccd*0.8/vadj; +2'b10: DRV_VOUT=vccd*0.6/vadj; +2'b11: DRV_VOUT=vccd + [3:2] + read-write + + + REGHC_VADJ + Regulator output trim according to the formula vadj=(1.020V + REGHC_VADJ*0.005V) plus an offset described below. For example, 0x1A=>1.15V (nominal). + +For transistor mode, REGHC will dynamically adjust DRV_VOUT so the supply targets the vadj voltage. Adjust for die to die variation by adding the signed offset value in SFLASH SRSS_PWR_OFFSET.REGHC_TRANS_VADJ_OFFSET. +Note: SRSS_PWR_OFFSET.REGHC_TRANS_VADJ_OFFSET value is calculated using the default value of the REGHC_VADJ: 0x10 (1.1V) and applies to the full range of REGHC target voltages. + +For PMIC mode, adjust for die to die variation by adding the signed offset value in SFLASH SRSS_PWR_OFFSET.PMIC_VADJ_OFFSET to the nominal calculated code. For PMIC mode, also see REGHC_PMIC_DRV_VOUT. + [8:4] + read-write + + + REGHC_PMIC_USE_LINREG + For REGHC external PMIC mode, controls whether hardware sequencer keeps the internal Active Linear Regulator enabled to improve supply supervision of vccd. When using this feature, if the PMIC fails to keep vccd above the internal regulator target, then the internal regulator will attempt to recover vccd. If the regulator current is too high, the regulator triggers an over-current detector (OCD) reset. +0: Internal Active Linear Regulator disabled after PMIC enabled. OCD is disabled.; +1: Internal Active Linear Regulator kept enabled. See datasheet for minimum PMIC vccd input to prevent OCD. + [10:10] + read-write + + + REGHC_PMIC_USE_RADJ + Controls whether hardware sequencer enables reset voltage adjustment circuit when enabling a PMIC. + [11:11] + read-write + + + REGHC_PMIC_RADJ + Reset voltage adjustment for PMIC as a factor (Vfbk/Vref) where Vfbk is the feedback voltage and Vref is the PMIC internal reference. The reset voltage adjustment circuit is enabled by the hardware sequencer if REGHC_PMIC_USE_RADJ=1. PMIC have Vref of 0.8V or 0.9V, and the resulting reset voltage (Vreset) are precalculated in the table below: +3'b000: Vfbk/Vref=1.0000, Vreset=.800V@(Vref=0.8V), .900V@(Vref=0.9V); +3'b001: Vfbk/Vref=1.0556, Vreset=.844V@(Vref=0.8V), .950V@(Vref=0.9V); +3'b010: Vfbk/Vref=1.1111, Vreset=.889V@(Vref=0.8V), 1.000V@(Vref=0.9V); +3'b011: Vfbk/Vref=1.1250, Vreset=.900V@(Vref=0.8V), 1.013V@(Vref=0.9V); +3'b100: Vfbk/Vref=1.1667, Vreset=.933V@(Vref=0.8V), 1.050V@(Vref=0.9V); +3'b101: Vfbk/Vref=1.1875, Vreset=.950V@(Vref=0.8V), 1.069V@(Vref=0.9V); +3'b110: Vfbk/Vref=1.2500, Vreset=1.000V@(Vref=0.8V), 1.125V@(Vref=0.9V); +3'b111: Vfbk/Vref=1.3125, Vreset=1.050V@(Vref=0.8V), 1.181V@(Vref=0.9V); + [14:12] + read-write + + + REGHC_PMIC_CTL_OUTEN + Output enable for PMIC enable pin. Set this bit high to enable the driver on this pin. + [16:16] + read-write + + + REGHC_PMIC_CTL_POLARITY + Polarity used to enable the PMIC. The sequencer uses REGHC_PMIC_CTL_POLARITY to enable the PMIC, and it uses the complement to disable the PMIC. + [17:17] + read-write + + + REGHC_PMIC_STATUS_INEN + Input buffer enable for PMIC status input. Set this bit high to enable the input receiver. + [18:18] + read-write + + + REGHC_PMIC_STATUS_POLARITY + The polarity used to trigger a reset action based on the PMIC status input. The reset system triggers a reset when the unmasked PMIC status matches this value. + [19:19] + read-write + + + REGHC_PMIC_STATUS_WAIT + Wait count in 4us steps after PMIC status ok. This is used by the hardware sequencer to allow additional settling time before disabling the internal regulator. The LSB is 32 IMO periods which results in a nominal LSB step of 4us. + [29:20] + read-write + + + REGHC_TRANS_USE_OCD + N/A + [30:30] + read-write + + + REGHC_CONFIGURED + Indicates the REGHC has been configured. This is used to know if REGHC should be enabled in response to a debug power up request. It is recommended to not change REGHC settings after REGHC_CONFIGURED is set high, because it can cause failure if REGHC is enabled or transitioning. + [31:31] + read-write + + + + + PWR_REGHC_STATUS + REGHC Status Register + 0x102C + 32 + read-only + 0x0 + 0x80001307 + + + REGHC_ENABLED + Indicates the state of the REGHC enable/disable sequencer. This bit is only valid when REGHC_SEQ_BUSY==0. +0: REGHC sequencer indicates REGHC is disabled. +1: REGHC sequencer indicates REGHC is enabled. + [0:0] + read-only + + + REGHC_OCD_OK + Indicates the over-current detector is operating and the current drawn from REGHC is within limits. OCD is only a choice for transistor mode, and it is disabled for PMIC mode. +0: Current measurement exceeds limit or detector is OFF, +1: Current measurement within limit + [1:1] + read-only + + + REGHC_CKT_OK + Indicates the REGHC circuit is enabled and operating. It does not indicate that the voltage and current are within required limits for robust operation. +0: REGHC circuit is not ready. This can occur if the REGHC circuit is disabled or if it was recently enabled. +1: REGHC circuit is enabled and operating. + [2:2] + read-only + + + REGHC_UV_OUT + N/A + [8:8] + read-only + + + REGHC_OV_OUT + N/A + [9:9] + read-only + + + REGHC_PMIC_STATUS_OK + Indicates the PMIC status is ok. This includes polarity adjustment according to REGHC_PMIC_STATUS_POLARITY. +0: PMIC status is not ok or PMIC input buffer is disabled (REGHC_PMIC_STATUS_INEN==0); +1: PMIC status input buffer is enabled and indicates ok + [12:12] + read-only + + + REGHC_SEQ_BUSY + Indicates the REGHC enable/disable sequencer is busy transitioning to/from REGHC. +0: Sequencer is not busy; +1: Sequencer is busy either enabling or disabling REGHC. + [31:31] + read-only + + + + + PWR_REGHC_CTL2 + REGHC Control Register 2 + 0x1030 + 32 + read-write + 0x0 + 0x800000FF + + + REGHC_PMIC_STATUS_TIMEOUT + Timeout while waiting for REGHC_PMIC_STATUS_OK==1 when switching to PMIC. +0: disables timeout. +>0: enables timeout of REGHC_PMIC_STATUS_TIMEOUT*128us (nominal, clocked by IMO). Timeout expiration triggers reset. + [7:0] + read-write + + + REGHC_EN + Enable REGHC. This bit will not set if REGHC_CONFIGURED==0. Use PWR_REGHC_STATUS.ENABLED to know the actual status of REGHC. It will differ from this bit in the following cases: +A) Do not enter DEEPSLEEP while the sequencer is busy (see PWR_REGHC_STATUS.REGHC_SEQ_BUSY). The hardware sequencer disables REGHC during DEEPSLEEP entry and enables it upon wakeup. +B) The debugger requests the chip remain powered up. Hardware prevents REGHC from disabling when this bit is cleared. Hardware does not automatically enable REGHC in response to debugger power up request. If this bit is low when the debugger deasserts the power up request, the hardware sequencer will disable REGHC. + [31:31] + read-write + + + + + PWR_REGHC_CTL4 + REGHC Control Register 4 + 0x1038 + 32 + read-write + 0x0 + 0xC0000000 + + + REGHC_PMIC_VADJ_DIS + When operating in PMIC mode, disables the VADJ circuitry. This can be used to decrease current consumption if the entire feedback network is outside the device. +0: Device generates VADJ when PMIC is enabled. This allows the feedback loop to compensate for voltage drops in the PCB and package. +1: Device does not generate VADJ, and it must not be part of the PMIC feedback loop. This reduces current by turning off the internal resistor divider that generates VADJ. This setting is ineffective when REGHC_PMIC_RADJ_EN==1, and VADJ is generated in that case when PMIC is enabled. + [30:30] + read-write + + + REGHC_PMIC_DPSLP + When operating in PMIC mode, configures PMIC behavior during DEEPSLEEP. +0: Device operates from internal regulators during DEEPSLEEP. If PMIC is enabled at the beginning of the DEEPSLEEP transition, hardware changes to the internal regulators and disables the PMIC. +1: DEEPSLEEP transition does not change PMIC enable. + [31:31] + read-write + + + + + 16 + 4 + PWR_HIB_DATA[%s] + HIBERNATE Data Register + 0x1040 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HIB_DATA + Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. + [31:0] + read-write + + + + + PWR_PMIC_CTL + PMIC Control Register + 0x10C0 + 32 + read-write + 0x104 + 0xBFFF85FC + + + PMIC_VREF + PMIC reference voltage setting. This selects the scaling factor used to generate the output voltage (vout) given the feedback voltage (vfb) for the chosen PMIC. For a PMIC that compares vfb to an internal reference voltage (vref) according to the formula vout=vref/vfb, select that vref below. For a PMIC that contains an internal resistor divider and expects an unscaled feedback voltage, use the 'No scaling' choice. +2'b00: Scale for vref=0.9V, use PMIC_VADJ to set the vccd target; +2'b01: Scale for vref=0.8V, use PMIC_VADJ to set the vccd target; +2'b10: Scale for vref=0.6V, use PMIC_VADJ to set the vccd target; +2'b11: No scaling, PMIC_VADJ has no effect + [3:2] + read-write + + + PMIC_VADJ + Voltage adjustment output setting. The lookup table in this field requires the proper setting in PMIC_VREF for the chosen PMIC. This field has no effect when PMIC_VREF selects no scaling. The feedback tap point is at a vccd pad inside the chip, so the voltage may be a little higher at the PMIC output. Adjust for die to die variation by adding the signed offset value in SFLASH SRSS_PWR_OFFSET.PMIC_VADJ_OFFSET to desired code in this lookup table: +0x03: 1.040V, 0x04: 1.049V, +0x05: 1.057V, 0x06: 1.066V, +0x07: 1.074V, 0x08: 1.083V, +0x09: 1.091V, 0x0A: 1.099V, +0x0B: 1.108V, 0x0C: 1.116V, +0x0D: 1.125V, 0x0E: 1.133V, +0x0F: 1.142V, 0x10: 1.150V, +0x11: 1.158V, 0x12: 1.167V, +0x13: 1.175V, 0x14: 1.184V, +0x15: 1.192V, 0x16: 1.201V, +0x17: 1.209V, 0x18: 1.218V, +0x19: 1.226V, 0x1A: 1.234V, +0x1B: 1.243V, 0x1C: 1.251V, +others: Illegal. Behavior is undefined. + [8:4] + read-write + + + PMIC_USE_LINREG + Controls whether hardware sequencer keeps the internal Active Linear Regulator enabled to improve supply supervision of vccd. When using this feature, if the PMIC fails to keep vccd above the internal regulator target, then the internal regulator will attempt to recover vccd. If the regulator current is too high, the regulator triggers an over-current detector (OCD) reset. +0: Internal Active Linear Regulator disabled after PMIC enabled. OCD is disabled.; +1: Internal Active Linear Regulator kept enabled. See datasheet for minimum PMIC vccd input to prevent OCD. + [10:10] + read-write + + + PMIC_VADJ_BUF_EN + Analog buffer enable on voltage adjust output. Write this bit depending on the type of PMIC connected: +0: Bypass buffer. This connects the resistor divider directly to the output pin. Use this setting for a PMIC with a high-impedance feedback input, such as those that support a resistor divider on the PCB. This setting can also be used with a low-impedance PMIC with PMIC_VREF=2'b11 (no scaling). +1: Use analog buffer. This enables an analog buffer between the resistor divider output and the pin. The buffer can drive a resistor divider on the PCB that feeds into the PMIC feedback input. This allows targeting a different PMIC reference voltage from PMIC_VREF choices, while still supporting voltage adjustment using the internal divider. + [15:15] + read-write + + + PMIC_CTL_OUTEN + Output enable for PMIC enable pin. Set this bit high to enable the driver on this pin. + [16:16] + read-write + + + PMIC_CTL_POLARITY + Polarity used to enable the PMIC. The sequencer uses PMIC_CTL_POLARITY to enable the PMIC, and it uses the complement to disable the PMIC. + [17:17] + read-write + + + PMIC_STATUS_INEN + Input buffer enable for PMIC status input. Set this bit high to enable the input receiver. + [18:18] + read-write + + + PMIC_STATUS_POLARITY + The polarity used to trigger a reset action based on the PMIC status input. The reset system triggers a reset when the unmasked PMIC status matches this value. + [19:19] + read-write + + + PMIC_STATUS_WAIT + Wait count in 4us steps after PMIC status ok. This is used by the hardware sequencer to allow additional settling time before disabling the internal regulator. The LSB is 32 IMO periods which results in a nominal LSB step of 4us. + [29:20] + read-write + + + PMIC_CONFIGURED + Indicates the PMIC has been configured. This is used to know if PMIC should be enabled in response to a debug power up request. Do not change PMIC settings after this bit is set high. + [31:31] + read-write + + + + + PWR_PMIC_STATUS + PMIC Status Register + 0x10C4 + 32 + read-only + 0x0 + 0x80001001 + + + PMIC_ENABLED + Indicates the state of the PMIC enable/disable sequencer. This bit is only valid when PMIC_SEQ_BUSY==0. +0: PMIC sequencer indicates PMIC is disabled. +1: PMIC sequencer indicates PMIC is enabled. + [0:0] + read-only + + + PMIC_STATUS_OK + Indicates the PMIC status is ok. This includes polarity adjustment according to PMIC_STATUS_POLARITY. +0: PMIC status is not ok or PMIC input buffer is disabled (PMIC_STATUS_INEN==0); +1: PMIC status input buffer is enabled and indicates ok + [12:12] + read-only + + + PMIC_SEQ_BUSY + Indicates the PMIC enable/disable sequencer is busy transitioning to/from PMIC. +0: Sequencer is not busy; +1: Sequencer is busy either enabling or disabling PMIC. + [31:31] + read-only + + + + + PWR_PMIC_CTL2 + PMIC Control Register 2 + 0x10C8 + 32 + read-write + 0x0 + 0x800000FF + + + PMIC_STATUS_TIMEOUT + Timeout while waiting for PMIC_STATUS_OK==1 when switching to PMIC. +0: disables timeout. Do not change this register after setting PWR_PMIC_CTL.PMIC_CONFIGURED. +>0: enables timeout of PMIC_STATUS_TIMEOUT*128us (nominal, clocked by IMO). Timeout expiration triggers reset. + [7:0] + read-write + + + PMIC_EN + Enable PMIC. This bit will not set if PMIC_CONFIGURED==0. Use PWR_PMIC_STATUS.ENABLED to know the actual status of PMIC. It will differ from this bit in the following cases: +A) Do not enter DEEPSLEEP while the sequencer is busy (see PWR_PMIC_STATUS.PMIC_SEQ_BUSY). The hardware sequencer disables PMIC during DEEPSLEEP entry and enables it upon wakeup. +B) The debugger requests the chip remain powered up. Hardware prevents PMIC from disabling when this bit is cleared. Hardware does not automatically enable PMIC in response to debugger power up request. If this bit is low when the debugger deasserts the power up request, the hardware sequencer will disable PMIC. + [31:31] + read-write + + + + + PWR_PMIC_CTL4 + PMIC Control Register 4 + 0x10D0 + 32 + read-write + 0x0 + 0xC0000000 + + + PMIC_VADJ_DIS + Disables the VADJ circuitry. This can be used to decrease current consumption if the entire feedback network is outside the device. +0: Device generates VADJ when PMIC is enabled. This allows the feedback loop to compensate for voltage drops in the PCB and package. +1: Device does not generate VADJ, and it must not be part of the PMIC feedback loop. This reduces current by turning off the internal resistor divider that generates VADJ. + [30:30] + read-write + + + PMIC_DPSLP + Configures PMIC behavior during DEEPSLEEP. +0: Device operates from internal regulators during DEEPSLEEP. If PMIC is enabled at the beginning of the DEEPSLEEP transition, hardware changes to the internal regulators and disables the PMIC. +1: DEEPSLEEP transition does not change PMIC enable. + [31:31] + read-write + + + + + 16 + 4 + CLK_PATH_SELECT[%s] + Clock Path Select Register + 0x1200 + 32 + read-write + 0x0 + 0x7 + + + PATH_MUX + Selects a source for clock PATH<i>. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. It takes four cycles of the originally selected clock to switch away from it. Do not disable the original clock during this time. + [2:0] + read-write + + + IMO + IMO - Internal R/C Oscillator + 0 + + + EXTCLK + EXTCLK - External Clock Pin + 1 + + + ECO + ECO - External-Crystal Oscillator + 2 + + + ALTHF + ALTHF - Alternate High-Frequency clock input (product-specific clock) + 3 + + + DSI_MUX + DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior. + 4 + + + LPECO + LPECO - Low-Power External-Crystal Oscillator + 5 + + + + + + + 16 + 4 + CLK_ROOT_SELECT[%s] + Clock Root Select Register + 0x1240 + 32 + read-write + 0x0 + 0x8000013F + + + ROOT_MUX + Selects a clock path as the root of HFCLK<k> and for SRSS DSI input <k>. Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. It takes four cycles of the originally selected clock to switch away from it. Do not disable the original clock during this time. + [3:0] + read-write + + + PATH0 + Select PATH0 (can be configured for FLL) + 0 + + + PATH1 + Select PATH1 (can be configured for PLL0, if available in the product) + 1 + + + PATH2 + Select PATH2 (can be configured for PLL1, if available in the product) + 2 + + + PATH3 + Select PATH3 (can be configured for PLL2, if available in the product) + 3 + + + PATH4 + Select PATH4 (can be configured for PLL3, if available in the product) + 4 + + + PATH5 + Select PATH5 (can be configured for PLL4, if available in the product) + 5 + + + PATH6 + Select PATH6 (can be configured for PLL5, if available in the product) + 6 + + + PATH7 + Select PATH7 (can be configured for PLL6, if available in the product) + 7 + + + PATH8 + Select PATH8 (can be configured for PLL7, if available in the product) + 8 + + + PATH9 + Select PATH9 (can be configured for PLL8, if available in the product) + 9 + + + PATH10 + Select PATH10 (can be configured for PLL9, if available in the product) + 10 + + + PATH11 + Select PATH11 (can be configured for PLL10, if available in the product) + 11 + + + PATH12 + Select PATH12 (can be configured for PLL11, if available in the product) + 12 + + + PATH13 + Select PATH13 (can be configured for PLL12, if available in the product) + 13 + + + PATH14 + Select PATH14 (can be configured for PLL13, if available in the product) + 14 + + + PATH15 + Select PATH15 (can be configured for PLL14, if available in the product) + 15 + + + + + ROOT_DIV + Selects predivider value for this clock root and DSI input. This divider is after DIRECT_MUX. For products with DSI, the output of this mux is routed to DSI for use as a signal. For products with clock supervision, the output of this mux is the monitored clock for CSV_HF<k>. + [5:4] + read-write + + + NO_DIV + Transparent mode, feed through selected clock source w/o dividing. + 0 + + + DIV_BY_2 + Divide selected clock source by 2 + 1 + + + DIV_BY_4 + Divide selected clock source by 4 + 2 + + + DIV_BY_8 + Divide selected clock source by 8 + 3 + + + + + DIRECT_MUX + Direct selection mux that allows IMO to bypass most of the clock mux structure. For products with multiple regulators, this mux can be used to reduce current without requiring significant reconfiguration of the clocking network. The default value of HFCLK<0>==ROOT_MUX, and the default value for other clock trees is product-specific. + [8:8] + read-write + + + IMO + Select IMO + 0 + + + ROOT_MUX + Select ROOT_MUX selection + 1 + + + + + ENABLE + Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. + [31:31] + read-write + + + + + CSV_HF + Clock Supervisor (CSV) registers for Root clocks + CSV_HF + 0x00001400 + + 8 + 16 + CSV[%s] + Active domain Clock Supervisor (CSV) registers + CSV_HF_CSV + 0x00000000 + + REF_CTL + Clock Supervision Reference Control + 0x0 + 32 + read-write + 0x0 + 0xC000FFFF + + + STARTUP + Startup delay time -1 (in reference clock cycles), after enable or DeepSleep wakeup, from reference clock start to monitored clock start. +At a minimum (both clocks running): STARTUP >= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency) +On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added. + [15:0] + read-write + + + CSV_ACTION + Specifies the action taken when an anomaly is detected on the monitored clock. CSV in DeepSleep domain always do a Fault report (which also wakes up the system). + [30:30] + read-write + + + FAULT + Do a Fault report. + 0 + + + RESET + Cause a power reset. This should only be used for clk_hf0. + 1 + + + + + CSV_EN + Enables clock supervision, both frequency and loss. +CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes. When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup. +CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode. It must be reconfigured after Hibernate wakeup. + +A CSV error detection is reported to the Fault structure, or instead it can generate a power reset. + [31:31] + read-write + + + + + REF_LIMIT + Clock Supervision Reference Limits + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + LOWER + Cycle time lower limit. Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected. +LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER. + [15:0] + read-write + + + UPPER + Cycle time upper limit. Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected. + [31:16] + read-write + + + + + MON_CTL + Clock Supervision Monitor Control + 0x8 + 32 + read-write + 0x0 + 0xFFFF + + + PERIOD + Period time. Set the Period -1, in monitored clock cycles, before the next monitored clock event happens. +PERIOD <= (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency) +In case the clocks are asynchronous: PERIOD <= UPPER / FREQ_RATIO -1 +Additionally margin must be added for accuracy of both clocks. + [15:0] + read-write + + + + + + + CLK_SELECT + Clock selection register + 0x1500 + 32 + read-write + 0x0 + 0xFF07 + + + LFCLK_SEL + Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. It takes four cycles of the originally selected clock to switch away from it. Do not disable the original clock during this time. + [2:0] + read-write + + + ILO0 + ILO0 - Internal Low-speed Oscillator #0. + 0 + + + WCO + WCO - Watch-Crystal Oscillator. Requires Backup domain to be present and properly configured (including external watch crystal, if used). + 1 + + + ALTLF + ALTLF - Alternate Low-Frequency Clock. Capability is product-specific + 2 + + + PILO + PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes. Does not work in HIBERNATE mode. + 3 + + + ILO1 + ILO1 - Internal Low-speed Oscillator #1, if present. + 4 + + + ECO_PRESCALER + ECO_PRESCALER - External-Crystal Oscillator after prescaling, if present. Does not work in DEEPSLEEP or HIBERNATE modes. Intended for applications that operate in ACTIVE/SLEEP modes only. This option is only valid when ECO is present in the product. + 5 + + + LPECO_PRESCALER + LPECO_PRESCALER - Low-Power External-Crystal Oscillator after prescaling, if present. This choice works in ACTIVE/SLEEP/DEEPSLEEP modes. This option is only valid when LPECO is present in the product. + 6 + + + + + PUMP_SEL + N/A + [11:8] + read-write + + + PUMP_DIV + N/A + [14:12] + read-write + + + NO_DIV + N/A + 0 + + + DIV_BY_2 + N/A + 1 + + + DIV_BY_4 + N/A + 2 + + + DIV_BY_8 + N/A + 3 + + + DIV_BY_16 + N/A + 4 + + + + + PUMP_ENABLE + N/A + [15:15] + read-write + + + + + CLK_ILO0_CONFIG + ILO0 Configuration + 0x1508 + 32 + read-write + 0x80000000 + 0xC0000001 + + + ILO0_BACKUP + This register indicates that ILO0 should stay enabled during XRES and HIBERNATE modes. If backup voltage domain is implemented on the product, this bit also indicates if ILO0 should stay enabled through power-related resets on other supplies, e.g.. BOD on VDDD/VCCD. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. This register is reset when the backup logic resets. +0: ILO0 turns off during XRES, HIBERNATE, and power-related resets. ILO0 configuration and trims are reset by these events. +1: ILO0 stays enabled, as described above. ILO0 configuration and trims are not reset by these events. + [0:0] + read-write + + + ILO0_MON_ENABLE + N/A + [30:30] + read-write + + + ENABLE + Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. + +HT-variant: This register will not clear unless PWR_CTL2.BGREF_LPMODE==0. After enabling, the first ILO0 cycle occurs within 12us and is +/-10 percent accuracy. Thereafter, ILO0 is +/-5 percent accurate. + [31:31] + read-write + + + + + CLK_ILO1_CONFIG + ILO1 Configuration + 0x150C + 32 + read-write + 0x0 + 0xC0000000 + + + ILO1_MON_ENABLE + N/A + [30:30] + read-write + + + ENABLE + Master enable for ILO1. + +HT-variant: After enabling, the first ILO1 cycle occurs within 12us and is +/-10 percent accuracy. Thereafter, ILO1 is +/-5 percent accurate. + [31:31] + read-write + + + + + CLK_IMO_CONFIG + IMO Configuration + 0x1518 + 32 + read-write + 0x80000000 + 0x80000000 + + + ENABLE + Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during DEEPSLEEP, HIBERNATE, and XRES. + [31:31] + read-write + + + + + CLK_ECO_CONFIG + ECO Configuration Register + 0x151C + 32 + read-write + 0x2 + 0x98000002 + + + AGC_EN + Automatic Gain Control (AGC) enable. When set, the oscillation amplitude is controlled to the level selected by CLK_ECO_CONFIG2.ATRIM. When low, the amplitude is not explicitly controlled and can be as high as the vddd supply. WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal. + [1:1] + read-write + + + ECO_DIV_DISABLE + ECO prescaler disable command (mutually exclusive with ECO_DIV_ENABLE). SW sets this field to '1' and HW sets this field to '0'. + +HW sets ECO_DIV_DISABLE field to '0' immediately and HW sets CLK_ECO_PRESCALE.ECO_DIV_EN field to '0' immediately. + [27:27] + read-write + + + ECO_DIV_ENABLE + ECO prescaler enable command (mutually exclusive with ECO_DIV_DISABLE). ECO Prescaler only works in ACTIVE and SLEEP modes. SW sets this field to '1' to enable the divider and HW sets this field to '0' to indicate that divider enabling has completed. When the divider is enabled, its integer and fractional counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: +0: Disable the divider using the ECO_DIV_DISABLE field. +1: Configure CLK_ECO_PRESCALE registers. +2: Enable the divider using the ECO_DIV_ENABLE field. + +HW sets the ECO_DIV_ENABLE field to '0' when the enabling is performed and HW set CLK_ECO_PRESCALER.ENABLED to '1' when the enabling is performed. + [28:28] + read-write + + + ECO_EN + Master enable for ECO oscillator. Configure the settings in CLK_ECO_CONFIG2 to work with the selected crystal, before enabling ECO. + [31:31] + read-write + + + + + CLK_ECO_PRESCALE + ECO Prescaler Configuration Register + 0x1520 + 32 + read-write + 0x0 + 0x3FFFF01 + + + ECO_DIV_ENABLED + ECO prescaler enabled. HW sets this field to '1' as a result of an CLK_ECO_CONFIG.ECO_DIV_ENABLE command. HW sets this field to '0' as a result on a CLK_ECO_CONFIG.ECO_DIV_DISABLE command. + [0:0] + read-only + + + ECO_FRAC_DIV + 8-bit fractional value, sufficient to get prescaler output within the +/-65ppm calibration range. Do not change this setting when ECO Prescaler is enabled. + [15:8] + read-write + + + ECO_INT_DIV + 10-bit integer value allows for ECO frequencies up to 33.55MHz. Subtract one from the desired divide value when writing this field. For example, to divide by 1, write ECO_INT_DIV=0. Do not change this setting when ECO Prescaler is enabled. + [25:16] + read-write + + + + + CLK_ECO_STATUS + ECO Status Register + 0x1524 + 32 + read-only + 0x0 + 0x3 + + + ECO_OK + Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec. + [0:0] + read-only + + + ECO_READY + Indicates the ECO internal oscillator circuit has had enough time to fully stabilize. This is the output of a counter since ECO was enabled, and it does not check the ECO output. It is recommended to also confirm ECO_OK==1. + [1:1] + read-only + + + + + CLK_PILO_CONFIG + Precision ILO Configuration Register + 0x1528 + 32 + read-write + 0x80 + 0xE00003FF + + + PILO_FFREQ + Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz. + [9:0] + read-write + + + PILO_CLK_EN + Enable the PILO clock output. See PILO_EN field for required sequencing. + [29:29] + read-write + + + PILO_RESET_N + Reset the PILO. See PILO_EN field for required sequencing. + [30:30] + read-write + + + PILO_EN + Enable PILO. When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle. + [31:31] + read-write + + + + + CLK_FLL_CONFIG + FLL Configuration Register + 0x1530 + 32 + read-write + 0x1000000 + 0x8103FFFF + + + FLL_MULT + Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref). + +Ffll = (FLL_MULT) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1) + [17:0] + read-write + + + FLL_OUTPUT_DIV + Control bits for Output divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. +0: no division +1: divide by 2 + [24:24] + read-write + + + FLL_ENABLE + Master enable for FLL. The FLL requires firmware sequencing when enabling and disabling. Hardware handles sequencing automatically when entering/exiting DEEPSLEEP. + +To enable the FLL, use the following sequence: +1) Configure FLL and CCO settings. Do not modify CLK_FLL_CONFIG3.BYPASS_SEL (must be AUTO) or CLK_FLL_CONFIG.FLL_ENABLE (must be 0). +2) Enable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=1 +3) Wait until CLK_FLL_STATUS.CCO_READY==1. +4) Ensure the reference clock has stabilized. +5) Write FLL_ENABLE=1. +6) Optionally wait until CLK_FLL_STATUS.LOCKED==1. The hardware automatically changes to the FLL output when LOCKED==1. + +To disable the FLL, use the following sequence: +1) Write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF. +2) Read CLK_FLL_CONFIG3.BYPASS_SEL to ensure the write completes (read is not optional). +3) Wait at least ten cycles of either FLL reference clock or FLL output clock, whichever is slower. It is recommended to use a HW counter (e.g. clock calibration counter, event generator) running on the slower clock. +4) Disable FLL with FLL_ENABLE=0. +5) Disable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=0. +6) Write CLK_FLL_CONFIG3.BYPASS_SEL=AUTO. +7) Read CLK_FLL_CONFIG3.BYPASS_SEL to ensure the write completes (read is not optional). +8) Wait three cycles of FLL reference clock. It is recommended to use a HW counter (e.g. clock calibration counter, event generator) running on the reference clock. + +0: Block is powered off +1: Block is powered on + [31:31] + read-write + + + + + CLK_FLL_CONFIG2 + FLL Configuration Register 2 + 0x1534 + 32 + read-write + 0x20001 + 0xFFFF1FFF + + + FLL_REF_DIV + Control bits for reference divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. +0: illegal (undefined behavior) +1: divide by 1 +... +8191: divide by 8191 + [12:0] + read-write + + + LOCK_TOL + Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or allow less accuracy. The tolerance is the allowed difference between the count value for the ideal formula and the measured value. +0: tolerate error of 1 count value +1: tolerate error of 2 count values +... +255: tolerate error of 256 count values + [23:16] + read-write + + + UPDATE_TOL + Update tolerance sets the error threshold for when the FLL will update the CCO frequency settings. The update tolerance is the allowed difference between the count value for the ideal formula and the measured value. UPDATE_TOL should be less than LOCK_TOL. + [31:24] + read-write + + + + + CLK_FLL_CONFIG3 + FLL Configuration Register 3 + 0x1538 + 32 + read-write + 0x2800 + 0x301FFFFF + + + FLL_LF_IGAIN + FLL Loop Filter Gain Setting #1. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. +0: 1/256 +1: 1/128 +2: 1/64 +3: 1/32 +4: 1/16 +5: 1/8 +6: 1/4 +7: 1/2 +8: 1.0 +9: 2.0 +10: 4.0 +11: 8.0 +>=12: illegal + [3:0] + read-write + + + FLL_LF_PGAIN + FLL Loop Filter Gain Setting #2. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. +0: 1/256 +1: 1/128 +2: 1/64 +3: 1/32 +4: 1/16 +5: 1/8 +6: 1/4 +7: 1/2 +8: 1.0 +9: 2.0 +10: 4.0 +11: 8.0 +>=12: illegal + [7:4] + read-write + + + SETTLING_COUNT + Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case. +0: no settling time +1: wait one reference clock cycle +... +8191: wait 8191 reference clock cycles + [20:8] + read-write + + + BYPASS_SEL + Bypass mux located just after FLL output. This register can be written while the FLL is enabled. When changing BYPASS_SEL, do not turn off the reference clock or CCO clock for five cycles (whichever is slower). In case of disabling FLL(FLL_ENABLE=0), additional five cycles are required. Refer to FLL disable sequence for more details in CLK_FLL_CONFIG->FLL_ENABLE. Whenever BYPASS_SEL is changed, it is required to read CLK_FLL_CONFIG3 to ensure the change takes effect. + [29:28] + read-write + + + AUTO + Automatic using lock indicator. When unlocked, automatically selects FLL reference input (bypass mode). When locked, automatically selects FLL output. This can allow some processing to occur while the FLL is locking, such as after DEEPSLEEP wakeup. It is incompatible with clock supervision, because the frequency changes based on the lock signal. + 0 + + + LOCKED_OR_NOTHING + Similar to AUTO, except the clock is gated off when unlocked. This is compatible with clock supervision, because the supervisors allow no clock during startup (until a timeout occurs), and the clock targets the proper frequency whenever it is running. + 1 + + + FLL_REF + Select FLL reference input (bypass mode). Ignores lock indicator + 2 + + + FLL_OUT + Select FLL output. Ignores lock indicator. + 3 + + + + + + + CLK_FLL_CONFIG4 + FLL Configuration Register 4 + 0x153C + 32 + read-write + 0xFF + 0xC1FF07FF + + + CCO_LIMIT + Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support) + [7:0] + read-write + + + CCO_RANGE + Frequency range of CCO + [10:8] + read-write + + + RANGE0 + Target frequency is in range [48, 64) MHz + 0 + + + RANGE1 + Target frequency is in range [64, 85) MHz + 1 + + + RANGE2 + Target frequency is in range [85, 113) MHz + 2 + + + RANGE3 + Target frequency is in range [113, 150) MHz + 3 + + + RANGE4 + Target frequency is in range [150, 200] MHz + 4 + + + + + CCO_FREQ + CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range. + [24:16] + read-write + + + CCO_HW_UPDATE_DIS + Disable CCO frequency update by FLL hardware +0: Hardware update of CCO settings is allowed. Use this setting for normal FLL operation. +1: Hardware update of CCO settings is disabled. Use this setting for open-loop FLL operation. + [30:30] + read-write + + + CCO_ENABLE + Enable the CCO. It is required to enable the CCO before using the FLL. +0: Block is powered off +1: Block is powered on + [31:31] + read-write + + + + + CLK_FLL_STATUS + FLL Status Register + 0x1540 + 32 + read-write + 0x0 + 0x7 + + + LOCKED + FLL Lock Indicator + [0:0] + read-only + + + UNLOCK_OCCURRED + This bit sets whenever the FLL is enabled and goes out of lock. This bit stays set until cleared by firmware. + [1:1] + read-write + + + CCO_READY + This indicates that the CCO is internally settled and ready to use. + [2:2] + read-only + + + + + CLK_ECO_CONFIG2 + ECO Configuration Register 2 + 0x1544 + 32 + read-write + 0x3 + 0x7FF7 + + + WDTRIM + Watch Dog Trim. Sets the minimum oscillation amplitude (Vp) for the crystal drive level. The minimum amplitude detector output is readable in CLK_ECO_STATUS.ECO_OK. +0x0: Vp > 0.05V +0x1: Vp > 0.10V +0x2: Vp > 0.15V +0x3: Vp > 0.20V +0x4: Vp > 0.25V +0x5: Vp > 0.30V +0x6: Vp > 0.35V +0x7: Vp > 0.40V + [2:0] + read-write + + + ATRIM + Amplitude trim. Sets maximum oscillation amplitude (Vp) to set the crystal drive level when ECO_CONFIG.AGC_EN=1. When AGC_EN=0, most values of this register are unused, except as noted. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal. +0x0: Vp < 0.35V +0x1: Vp < 0.40V +0x2: Vp < 0.45V +0x3: Vp < 0.50V +0x4: Vp < 0.55V +0x5: Vp < 0.60V +0x6: Vp < 0.65V +0x7: Vp < 0.70V +0x8: Vp < 0.75V +0x9: Vp < 0.80V +0xA: Vp < 0.85V +0xB: Vp < 0.90V +0xC: Vp < 0.95V +0xD: Vp < 1.00V +0xE: Vp < 1.05V +0xF: Vp < 1.10V when AGC_EN=1. When AGC_EN=0, this setting enables maximum swing between vddd and vssd. + [7:4] + read-write + + + FTRIM + Filter Trim - 3rd harmonic oscillation + [9:8] + read-write + + + RTRIM + Feedback resistor Trim + [11:10] + read-write + + + GTRIM + Gain Trim - Startup time. + [14:12] + read-write + + + + + 15 + 4 + CLK_PLL_CONFIG[%s] + PLL Configuration Register + 0x1600 + 32 + read-write + 0x20116 + 0xBE1F1F7F + + + FEEDBACK_DIV + Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0-21: illegal (undefined behavior) +22: divide by 22 +... +112: divide by 112 +>112: illegal (undefined behavior) + [6:0] + read-write + + + REFERENCE_DIV + Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0: illegal (undefined behavior) +1: divide by 1 +... +20: divide by 20 +others: illegal (undefined behavior) + [12:8] + read-write + + + OUTPUT_DIV + Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0: illegal (undefined behavior) +1: illegal (undefined behavior) +2: divide by 2. Suitable for direct usage as HFCLK source. +... +16: divide by 16. Suitable for direct usage as HFCLK source. +>16: illegal (undefined behavior) + [20:16] + read-write + + + LOCK_DELAY + N/A + [26:25] + read-write + + + PLL_LF_MODE + VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. +0: VCO frequency is [200MHz, 400MHz] +1: VCO frequency is [170MHz, 200MHz) + [27:27] + read-write + + + BYPASS_SEL + Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. When changing BYPASS_SEL, do not turn off the reference clock or PLL clock for five cycles (whichever is slower). + [29:28] + read-write + + + AUTO + Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. If ENABLE=0, automatically selects PLL reference input. + 0 + + + LOCKED_OR_NOTHING + Similar to AUTO, except the clock is gated off when unlocked. This is compatible with clock supervision, because the supervisors allow no clock during startup (until a timeout occurs), and the clock targets the proper frequency whenever it is running. If ENABLE=0, no clock is output. + 1 + + + PLL_REF + Select PLL reference input (bypass mode). Ignores lock indicator + 2 + + + PLL_OUT + Select PLL output. Ignores lock indicator. If ENABLE=0, no clock is output. + 3 + + + + + ENABLE + Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. + +Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) + +0: Block is disabled. When the PLL disables, hardware controls the bypass mux as described in BYPASS_SEL, before disabling the PLL circuit. +1: Block is enabled + [31:31] + read-write + + + + + 15 + 4 + CLK_PLL_STATUS[%s] + PLL Status Register + 0x1640 + 32 + read-write + 0x0 + 0x3 + + + LOCKED + PLL Lock Indicator + [0:0] + read-only + + + UNLOCK_OCCURRED + This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. + [1:1] + read-write + + + + + CSV_REF_SEL + Select CSV Reference clock for Active domain + 0x1700 + 32 + read-write + 0x0 + 0x7 + + + REF_MUX + Selects a source for clock clk_ref_hf. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. It takes four cycles of the originally selected clock to switch away from it. Do not disable the original clock during this time. + [2:0] + read-write + + + IMO + IMO - Internal R/C Oscillator + 0 + + + EXTCLK + EXTCLK - External Clock Pin + 1 + + + ECO + ECO - External-Crystal Oscillator + 2 + + + ALTHF + ALTHF - Alternate High-Frequency clock input (product-specific clock) + 3 + + + + + + + CSV_REF + CSV registers for the CSV Reference clock + CSV_REF + 0x00001710 + + CSV + Active domain Clock Supervisor (CSV) registers for CSV Reference clock + CSV_REF_CSV + 0x00000000 + + REF_CTL + Clock Supervision Reference Control + 0x0 + 32 + read-write + 0x0 + 0xC000FFFF + + + STARTUP + Startup delay time -1 (in reference clock cycles), after enable or DeepSleep wakeup, from reference clock start to monitored clock start. +At a minimum (both clocks running): STARTUP >= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency) +On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added. + [15:0] + read-write + + + CSV_ACTION + Specifies the action taken when an anomaly is detected on the monitored clock. CSV in DeepSleep domain always do a Fault report (which also wakes up the system). + [30:30] + read-write + + + FAULT + Do a Fault report. + 0 + + + RESET + Cause a power reset. This should only be used for clk_hf0. + 1 + + + + + CSV_EN + Enables clock supervision, both frequency and loss. +CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes. When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup. +CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode. It must be reconfigured after Hibernate wakeup. + +A CSV error detection is reported to the Fault structure, or instead it can generate a power reset. + [31:31] + read-write + + + + + REF_LIMIT + Clock Supervision Reference Limits + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + LOWER + Cycle time lower limit. Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected. +LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER. + [15:0] + read-write + + + UPPER + Cycle time upper limit. Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected. + [31:16] + read-write + + + + + MON_CTL + Clock Supervision Monitor Control + 0x8 + 32 + read-write + 0x0 + 0xFFFF + + + PERIOD + Period time. Set the Period -1, in monitored clock cycles, before the next monitored clock event happens. +PERIOD <= (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency) +In case the clocks are asynchronous: PERIOD <= UPPER / FREQ_RATIO -1 +Additionally margin must be added for accuracy of both clocks. + [15:0] + read-write + + + + + + + CSV_LF + CSV registers for LF clock + CSV_LF + 0x00001720 + + CSV + LF clock Clock Supervisor registers + CSV_LF_CSV + 0x00000000 + + REF_CTL + Clock Supervision Reference Control + 0x0 + 32 + read-write + 0x0 + 0x800000FF + + + STARTUP + Startup delay time -1 (in reference clock cycles), after enable, from reference clock start to monitored clock start. +At a minimum (both clocks running): STARTUP >= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency) +On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added. + [7:0] + read-write + + + CSV_EN + Enables clock supervision, both frequency and loss. +CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes. When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup. +CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode. It must be reconfigured after Hibernate wakeup. +CSV in Backup domain: Clock supervision operates during Hibernate mode, can be configured to wake from Hibernate, and continues operating during reboot. + +A CSV error detection is reported to the Fault structure. + [31:31] + read-write + + + + + REF_LIMIT + Clock Supervision Reference Limits + 0x4 + 32 + read-write + 0x0 + 0xFF00FF + + + LOWER + Cycle time lower limit. Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected. +LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER. + [7:0] + read-write + + + UPPER + Cycle time upper limit. Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected. + [23:16] + read-write + + + + + MON_CTL + Clock Supervision Monitor Control + 0x8 + 32 + read-write + 0x0 + 0xFF + + + PERIOD + Period time. Set the Period -1, in monitored clock cycles, before the next monitored clock event happens. +PERIOD <= (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency) +In case the clocks are asynchronous: PERIOD <= UPPER / FREQ_RATIO -1 +Additionally margin must be added for accuracy of both clocks. + [7:0] + read-write + + + + + + + CSV_ILO + CSV registers for HVILO clock + CSV_ILO + 0x00001730 + + CSV + ILO0 clock DeepSleep domain Clock Supervisor registers + CSV_ILO_CSV + 0x00000000 + + REF_CTL + Clock Supervision Reference Control + 0x0 + 32 + read-write + 0x0 + 0x800000FF + + + STARTUP + Startup delay time -1 (in reference clock cycles), after enable, from reference clock start to monitored clock start. +At a minimum (both clocks running): STARTUP >= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency) +On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added. + [7:0] + read-write + + + CSV_EN + Enables clock supervision, both frequency and loss. +CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes. When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup. +CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode. It must be reconfigured after Hibernate wakeup. +CSV in Backup domain: Clock supervision operates during Hibernate mode, can be configured to wake from Hibernate, and continues operating during reboot. + +A CSV error detection is reported to the Fault structure. + [31:31] + read-write + + + + + REF_LIMIT + Clock Supervision Reference Limits + 0x4 + 32 + read-write + 0x0 + 0xFF00FF + + + LOWER + Cycle time lower limit. Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected. +LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER. + [7:0] + read-write + + + UPPER + Cycle time upper limit. Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected. + [23:16] + read-write + + + + + MON_CTL + Clock Supervision Monitor Control + 0x8 + 32 + read-write + 0x0 + 0xFF + + + PERIOD + Period time. Set the Period -1, in monitored clock cycles, before the next monitored clock event happens. +PERIOD <= (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency) +In case the clocks are asynchronous: PERIOD <= UPPER / FREQ_RATIO -1 +Additionally margin must be added for accuracy of both clocks. + [7:0] + read-write + + + + + + + RES_CAUSE + Reset Cause Observation Register + 0x1800 + 32 + read-write + 0x40000000 + 0x77FF01FF + + + RESET_WDT + A basic WatchDog Timer (WDT) reset has occurred since last power cycle. ULP products: This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). + +For products that support high-voltage cause detection, this bit blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits. + [0:0] + read-write + + + RESET_ACT_FAULT + Fault logging system requested a reset from its Active logic. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). + [1:1] + read-write + + + RESET_DPSLP_FAULT + Fault logging system requested a reset from its DeepSleep logic. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). + [2:2] + read-write + + + RESET_TC_DBGRESET + Test controller or debugger asserted reset. Only resets debug domain. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). + [3:3] + read-write + + + RESET_SOFT + A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). + [4:4] + read-write + + + RESET_MCWDT0 + Multi-Counter Watchdog timer reset #0. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). + [5:5] + read-write + + + RESET_MCWDT1 + Multi-Counter Watchdog timer reset #1. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). + [6:6] + read-write + + + RESET_MCWDT2 + Multi-Counter Watchdog timer reset #2. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). + [7:7] + read-write + + + RESET_MCWDT3 + Multi-Counter Watchdog timer reset #3. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). + [8:8] + read-write + + + RESET_XRES + External XRES pin was asserted. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits. + [16:16] + read-write + + + RESET_BODVDDD + External VDDD supply crossed brown-out limit. Note that this cause will only be observable as long as the VDDD supply does not go below the POR (power on reset) detection limit. Below this limit it is not possible to reliably retain information in the device. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. + [17:17] + read-write + + + RESET_BODVDDA + External VDDA supply crossed the brown-out limit. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. + [18:18] + read-write + + + RESET_BODVCCD + Internal VCCD core supply crossed the brown-out limit. Note that this detector will detect gross issues with the internal core supply, but may not catch all brown-out conditions. Functional and timing supervision (CSV, WDT) is provided to create fully failsafe internal crash detection. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. + [19:19] + read-write + + + RESET_OVDVDDD + Overvoltage detection on the external VDDD supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. + [20:20] + read-write + + + RESET_OVDVDDA + Overvoltage detection on the external VDDA supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. + [21:21] + read-write + + + RESET_OVDVCCD + Overvoltage detection on the internal core VCCD supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. + [22:22] + read-write + + + RESET_OCD_ACT_LINREG + Overcurrent detection on the internal VCCD supply when supplied by the ACTIVE power mode linear regulator. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. + [23:23] + read-write + + + RESET_OCD_DPSLP_LINREG + Overcurrent detection on the internal VCCD supply when supplied by the DEEPSLEEP power mode linear regulator. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. + [24:24] + read-write + + + RESET_OCD_REGHC + Overcurrent detection from REGHC (if present). If REGHC is not present, hardware will never set this bit. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. + [25:25] + read-write + + + RESET_PMIC + PMIC status triggered a reset. If PMIC control is not present, hardware will never set this bit. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. + [26:26] + read-write + + + RESET_PXRES + PXRES triggered. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits. + [28:28] + read-write + + + RESET_STRUCT_XRES + Structural reset was asserted. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits. + [29:29] + read-write + + + RESET_PORVDDD + Indicator that a POR occurred. This is a high-voltage cause bit, and hardware clears the other bits when this one is set. It does not block further recording of other high-voltage causes. + [30:30] + read-write + + + + + RES_CAUSE2 + Reset Cause Observation Register 2 + 0x1804 + 32 + read-write + 0x0 + 0x1FFFF + + + RESET_CSV_HF + Clock supervision logic requested a reset due to loss or frequency violation of a high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero. + [15:0] + read-write + + + RESET_CSV_REF + Clock supervision logic requested a reset due to loss or frequency violation of the reference clock source that is used to monitor the other HF clock sources. + [16:16] + read-write + + + + + 2 + 16 + CLK_PLL400M[%s] + 400MHz PLL Configuration Register + CLK_PLL400M + 0x00001900 + + CONFIG + 400MHz PLL Configuration Register + 0x0 + 32 + read-write + 0x20116 + 0xB61F1FFF + + + FEEDBACK_DIV + Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0-15: illegal (undefined behavior) +16: divide by 16 +... +200: divide by 200 +>200: illegal (undefined behavior) + +When using fractional mode, the jitter specs are met over the restricted range of 27 to 47, inclusive. + [7:0] + read-write + + + REFERENCE_DIV + Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0: illegal (undefined behavior) +1: divide by 1 +... +16: divide by 16 +others: illegal (undefined behavior) + +When using fractional mode, the jitter specs are met over the restricted range of 1 to 4, inclusive. + [12:8] + read-write + + + OUTPUT_DIV + Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. +0: illegal (undefined behavior) +1: illegal (undefined behavior) +2: divide by 2. Suitable for direct usage as HFCLK source. +... +16: divide by 16. Suitable for direct usage as HFCLK source. +>16: illegal (undefined behavior) + [20:16] + read-write + + + LOCK_DELAY + N/A + [26:25] + read-write + + + BYPASS_SEL + Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. When changing BYPASS_SEL, do not turn off the reference clock or PLL clock for five cycles (whichever is slower). + [29:28] + read-write + + + AUTO + Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output. If ENABLE=0, automatically selects PLL reference input. + 0 + + + LOCKED_OR_NOTHING + Similar to AUTO, except the clock is gated off when unlocked. This is compatible with clock supervision, because the supervisors allow no clock during startup (until a timeout occurs), and the clock targets the proper frequency whenever it is running. If ENABLE=0, no clock is output. + 1 + + + PLL_REF + Select PLL reference input (bypass mode). Ignores lock indicator + 2 + + + PLL_OUT + Select PLL output. Ignores lock indicator. If ENABLE=0, no clock is output. + 3 + + + + + ENABLE + Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. + +fOUT = (FEEDBACK_DIV + FRAC_EN*FRAC_DIV/2^24) * (fREF / REFERENCE_DIV) / (OUTPUT_DIV) + +0: Block is disabled. When the PLL disables, hardware controls the bypass mux as described in BYPASS_SEL, before disabling the PLL circuit. +1: Block is enabled + [31:31] + read-write + + + + + CONFIG2 + 400MHz PLL Configuration Register 2 + 0x4 + 32 + read-write + 0x0 + 0xF0FFFFFF + + + FRAC_DIV + Control bits for fractional divider. This value is interpreted as a fraction of the PFD frequency, i.e. fPFD * (FRAC_DIV/2^24). This field can be dynamically updated within the 1000ppm control limit. It takes up to 115 AHB cycles to transfer the setting to the PLL, and writes that occur faster may be silently ignored and require the application to write again after the previous update has finished. Reading the register returns the accepted value. The PLL will start targeting the new value, but it may take significant time (milliseconds) to stabilize at the new average value. Do not change the FRAC_DIV setting while the PLL is initially locking. + [23:0] + read-write + + + FRAC_DITHER_EN + N/A + [30:28] + read-write + + + FRAC_EN + Enables fractional division mode. When using fractional division mode, see CLK_PLL400M_CONFIG.LOCK_DELAY for an additional configuration requirement. + [31:31] + read-write + + + + + CONFIG3 + 400MHz PLL Configuration Register 3 + 0x8 + 32 + read-write + 0x0 + 0x910703FF + + + SSCG_DEPTH + N/A + [9:0] + read-write + + + SSCG_RATE + N/A + [18:16] + read-write + + + SSCG_DITHER_EN + N/A + [24:24] + read-write + + + SSCG_MODE + N/A + [28:28] + read-write + + + SSCG_EN + Enables spreading mode. When using spreading, see CLK_PLL400M_CONFIG.LOCK_DELAY for an additional configuration requirement. + [31:31] + read-write + + + + + STATUS + 400MHz PLL Status Register + 0xC + 32 + read-write + 0x0 + 0x3 + + + LOCKED + PLL Lock Indicator + [0:0] + read-only + + + UNLOCK_OCCURRED + This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware. + [1:1] + read-write + + + + + + CLK_TRIM_ILO0_CTL + ILO0 Trim Register + 0x3014 + 32 + read-write + 0x52C + 0xF3F + + + ILO0_FTRIM + ILO0 frequency trims. LSB step size is 1.5 percent (typical) of the frequency. + [5:0] + read-write + + + ILO0_MONTRIM + ILO0 internal monitor trim. + [11:8] + read-write + + + + + PWR_TRIM_PWRSYS_CTL + Power System Trim Register + 0x3108 + 32 + read-write + 0x17 + 0x1F + + + ACT_REG_TRIM + Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. The nominal output voltage is vccd=812.5mV + ACT_REG_TRIM*12.5mV. The actual output voltage will vary depending on conditions and load. The following settings are explicitly shown for convenience, and other values may be calculated using the formula: +5'h07: 900mV (nominal) +5'h17: 1100mV (nominal) + [4:0] + read-write + + + ACT_REG_BOOST + Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that. This may allow a reduction in the internal operating current of the regulator. The regulator internal operating current depends on the boost setting: +2'b00: 50uA +2'b01: 100uA +2'b10: 150uA +2'b11: 200uA + +The allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer). The defaults are set assuming the application consumes the maximum allowed by the chip. +50mA chip: 2'b00 (default); +100mA chip: 2'b00 (default); +150mA chip: 50..100mA app => 2'b00, 150mA app => 2'b01 (default); +200mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200mA app => 2'b10 (default); +250mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10 (default); +300mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10, 300mA app => 2'b11 (default); + +This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset. + [31:30] + read-write + + + + + CLK_TRIM_PILO_CTL + PILO Trim Register + 0x3114 + 32 + read-write + 0x108500F + 0x7DFF703F + + + PILO_CFREQ + Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. The nominal step size of the LSB is 1kHz. + [5:0] + read-write + + + PILO_OSC_TRIM + Trim for current in oscillator block. + [14:12] + read-write + + + PILO_COMP_TRIM + Trim for comparator bias current. + [17:16] + read-write + + + PILO_NBIAS_TRIM + Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier + [19:18] + read-write + + + PILO_RES_TRIM + Trim for beta-multiplier branch current + [24:20] + read-write + + + PILO_ISLOPE_TRIM + Trim for beta-multiplier current slope + [27:26] + read-write + + + PILO_VTDIFF_TRIM + Trim for VT-DIFF output (internal power supply) + [30:28] + read-write + + + + + CLK_TRIM_PILO_CTL2 + PILO Trim Register 2 + 0x3118 + 32 + read-write + 0xDA10E0 + 0xFF1FFF + + + PILO_VREF_TRIM + Trim for voltage reference + [7:0] + read-write + + + PILO_IREFBM_TRIM + Trim for beta-multiplier current reference + [12:8] + read-write + + + PILO_IREF_TRIM + Trim for current reference + [23:16] + read-write + + + + + CLK_TRIM_PILO_CTL3 + PILO Trim Register 3 + 0x311C + 32 + read-write + 0x4800 + 0xFFFF + + + PILO_ENGOPT + Engineering options for PILO circuits +0: Short vdda to vpwr +1: Beta:mult current change +2: Iref generation Ptat current addition +3: Disable current path in secondary Beta:mult startup circuit +4: Double oscillator current +5: Switch between deep:sub:threshold and sub:threshold stacks in Vref generation block +6: Spare +7: Ptat component increase in Iref +8: vpwr_rc and vpwr_dig_rc shorting testmode +9: Switch b/w psub connection for cascode nfet for vref generation +10: Switch between sub:threshold and deep:sub:threshold stacks in comparator. +15-11: Frequency fine trim. See AKK-444 for an overview of the trim strategy. + [15:0] + read-write + + + + + CLK_TRIM_ILO1_CTL + ILO1 Trim Register + 0x3220 + 32 + read-write + 0x52C + 0xF3F + + + ILO1_FTRIM + ILO1 frequency trims. LSB step size is 1.5 percent (typical) of the frequency. + [5:0] + read-write + + + ILO1_MONTRIM + ILO1 internal monitor trim. + [11:8] + read-write + + + + + 3 + 256 + MCWDT[%s] + Multi-Counter Watchdog Timer + MCWDT + 0x00008000 + + 2 + 32 + CTR[%s] + MCWDT Configuration for Subcounter 0 and 1 + MCWDT_CTR + 0x00000000 + + CTL + MCWDT Subcounter Control Register + 0x0 + 32 + read-write + 0x0 + 0x80000001 + + + ENABLED + Indicates actual state of this subcounter. May lag ENABLE by up to two clk_lf cycles. + [0:0] + read-only + + + ENABLE + Enable subcounter. May take up to 2 clk_lf cycles to take effect. When ENABLE changes from 1->0, the counter is cleared. +0: Counter is disabled (not clocked) +1: Counter is enabled (counting up) + [31:31] + read-write + + + + + LOWER_LIMIT + MCWDT Subcounter Lower Limit Register + 0x4 + 32 + read-write + 0x0 + 0xFFFF + + + LOWER_LIMIT + Lower limit for this MCWDT subcounter. See LOWER_ACTION. + [15:0] + read-write + + + + + UPPER_LIMIT + MCWDT Subcounter Upper Limit Register + 0x8 + 32 + read-write + 0x0 + 0xFFFF + + + UPPER_LIMIT + Upper limit for this MCWDT subcounter. See UPPER_ACTION. + [15:0] + read-write + + + + + WARN_LIMIT + MCWDT Subcounter Warn Limit Register + 0xC + 32 + read-write + 0x0 + 0xFFFF + + + WARN_LIMIT + Warn limit for this MCWDT subcounter. See WARN_ACTION. + [15:0] + read-write + + + + + CONFIG + MCWDT Subcounter Configuration Register + 0x10 + 32 + read-write + 0x0 + 0xD0001133 + + + LOWER_ACTION + Action taken if this watchdog is serviced before LOWER_LIMIT is reached. LOWER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected and/or when the corresponding processor is in SLEEPDEEP. + [1:0] + read-write + + + NOTHING + Do nothing + 0 + + + FAULT + Trigger a fault. It can take up to 3 clk_lf cycles for the fault to be transferred to the fault manager. +For LOWER_LIMIT >= 1: The action is triggered on same edge when it meets this condition. +For LOWER_LIMIT == 0: No action is triggered. + 1 + + + FAULT_THEN_RESET + Trigger a fault. Further, trigger a system-wide reset if the fault is not serviced and the watchdog is not cleared within 6 clk_lf cycles. It can take up to 3 clk_lf cycles for the fault to be transferred to the fault manager, which gives at least 3 clk_lf cycles for software to respond. +For LOWER_LIMIT >= 1: The action is triggered on same edge when it meets this condition. +For LOWER_LIMIT == 0: No action is triggered. + 2 + + + + + UPPER_ACTION + Action taken if this watchdog is not serviced before UPPER_LIMIT is reached. The counter stops counting when UPPER_LIMIT is reached, regardless of UPPER_ACTION setting. UPPER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected. + [5:4] + read-write + + + NOTHING + Do nothing + 0 + + + FAULT + Trigger a fault. +For UPPER_LIMIT >= 2: The action is triggered on same edge when it meets this condition. +For UPPER_LIMIT < 2: The action may take up to one extra clk_lf cycle to trigger. + 1 + + + FAULT_THEN_RESET + Trigger a fault. Further, trigger a system-wide reset if the fault is not serviced and the watchdog is not cleared within 6 clk_lf cycles. It can take up to 3 clk_lf cycles for the fault to be transferred to the fault manager, which gives at least 3 clk_lf cycles for software to respond. +For UPPER_LIMIT >= 2: The action is triggered on same edge when it meets this condition. +For UPPER_LIMIT < 2: The action may take up to one extra clk_lf cycle to trigger. + 2 + + + + + WARN_ACTION + Action taken when the count value reaches WARN_LIMIT. The minimum setting to achieve a periodic interrupt is WARN_LIMIT==1. A setting of zero will trigger once but not periodically. +For WARN_LIMIT >= 2: The action is triggered on same edge when it meets this condition. +For WARN_LIMIT == [0,1] : The action may take up to one extra clk_lf cycle to trigger. + [8:8] + read-write + + + NOTHING + Do nothing + 0 + + + INT + Trigger an interrupt. + 1 + + + + + AUTO_SERVICE + Automatically service when the count value reaches WARN_LIMIT. This allows creation of a periodic interrupt if this counter is not needed as a watchdog. This field is ignored when LOWER_ACTION<>NOTHING or when UPPER_ACTION<>NOTHING. + [12:12] + read-write + + + DEBUG_TRIGGER_EN + Enables the trigger input for this MCWDT to pause the counter during debug mode. To pause at a breakpoint while debugging, configure the trigger matrix to connect the related CPU halted signal to the trigger input for this MCWDT, and then set this bit. It takes up to two clk_lf cycles for the trigger signal to be processed. Triggers that are less than two clk_lf cycles may be missed. Synchronization errors can accumulate each time it is halted. +0: Pauses the counter whenever a debug probe is connected. +1: Pauses the counter whenever a debug probe is connected and the trigger input is high. + [28:28] + read-write + + + SLEEPDEEP_PAUSE + Pauses/runs this counter when the corresponding processor is in SLEEPDEEP. Note it may take up to two clk_lf cycles for the counter to pause and up to two clk_lf cycles for it to unpause, due to internal synchronization. After wakeup, the LOWER_ACTION is ignored until after the first service. This prevents an unintentional trigger of the LOWER_ACTION before the firmware realigns the servicing period. After the first service, LOWER_ACTION behaves as configured. +0: Counter runs normally regardless of processor mode. +1: Counter pauses when corresponding processor is in SLEEPDEEP. + [30:30] + read-write + + + DEBUG_RUN + Pauses/runs this counter while a debugger is connected. Other behaviors are unchanged during debugging, including service, configuration updates and enable/disable. Note it may take up to two clk_lf cycles for the counter to pause, due to internal synchronization. + +When (DEBUG_RUN==1 or DEBUG_TRIGGER_EN==0) and the debugger is connected for at least two clk_lf cycles, the LOWER_ACTION is ignored until after the first service after the debugger is disconnected. After the debugger is disconnected, the LOWER_ACTION is ignored until after the first service. This prevents an unintentional trigger of the LOWER_ACTION before the firmware realigns the servicing period. After the first service, LOWER_ACTION behaves as configured. If the debugger is disconnected before two clk_lf cycles, the LOWER_ACTION may or may not be ignored. + +0: When debugger connected, counter pauses incrementing as configured in DEBUG_TRIGGER_EN. +1: When debugger connected, counter increments normally, but reset generation is blocked. To block LOWER_ACTION fault generation, write DEBUG_TRIGGER_EN==0. + [31:31] + read-write + + + + + CNT + MCWDT Subcounter Count Register + 0x14 + 32 + read-write + 0x0 + 0xFFFF + + + CNT + Current value of subcounter for this MCWDT. This field may lag the actual count value by up to one clk_lf cycle, due to internal synchronization. When this subcounter is disabled and unlocked, the count value can be written for verification and debugging purposes. Software writes are always ignored when the subcounter is enabled.This register retains information during DeepSleep mode if SLEEPDEEP_PAUSE == 1. + [15:0] + read-write + + + + + + CPU_SELECT + MCWDT CPU selection register + 0x40 + 32 + read-write + 0x0 + 0x3 + + + CPU_SEL + Assigns this MCWDT to a CPU. This selects which CPU SLEEPDEEP signal is used for SLEEPDEEP_PAUSE. + [1:0] + read-write + + + + + CTR2_CTL + MCWDT Subcounter 2 Control register + 0x80 + 32 + read-write + 0x0 + 0x80000001 + + + ENABLED + Indicates actual state of this subcounter. May lag ENABLE by up to two clk_lf cycles. + [0:0] + read-only + + + ENABLE + Enable subcounter. May take up to 2 clk_lf cycles to take effect. When ENABLE changes from 1->0, the counter is cleared. +0: Counter is disabled (not clocked) +1: Counter is enabled (counting up) + [31:31] + read-write + + + + + CTR2_CONFIG + MCWDT Subcounter 2 Configuration register + 0x84 + 32 + read-write + 0x0 + 0xD01F0001 + + + ACTION + Action taken when the specified BIT toggles. +Action will be triggered on the same edge where BITS to observe toggle. + [0:0] + read-write + + + NOTHING + Do nothing + 0 + + + INT + Trigger an interrupt + 1 + + + + + BITS + Bit to observe for a toggle: +0: Do ACTION after CNT[0] toggles (i.e. every tick) +. +31: Do ACTION after CNT[31] toggles (i.e. every 2^31 ticks) + [20:16] + read-write + + + DEBUG_TRIGGER_EN + Enables the trigger input for this MCWDT to pause the counter during debug mode. To pause at a breakpoint while debugging, configure the trigger matrix to connect the related CPU halted signal to the trigger input for this MCWDT, and then set this bit. It takes up to two clk_lf cycles for the trigger signal to be processed. Triggers that are less than two clk_lf cycles may be missed. Synchronization errors can accumulate each time it is halted. +0: Pauses the counter whenever a debug probe is connected. +1: Pauses the counter whenever a debug probe is connected and the trigger input is high. + [28:28] + read-write + + + SLEEPDEEP_PAUSE + Pauses/runs this counter when the corresponding processor is in SLEEPDEEP. Note it may take up to two clk_lf cycles for the counter to pause and up to two clk_lf cycles for it to unpause, due to internal synchronization. +0: Counter runs normally regardless of processor mode. +1: Counter pauses when corresponding processor is in SLEEPDEEP. + [30:30] + read-write + + + DEBUG_RUN + Pauses/runs this counter while a debugger is connected. Other behaviors are unchanged during debugging, including service, configuration updates and enable/disable. Note it may take up to two clk_lf cycles for the counter to pause and another two cycles to unpause, due to internal synchronization. +0: When debugger connected, counter pauses incrementing as configured in DEBUG_TRIGGER_EN. +1: When debugger connected, counter increments normally, but reset generation is blocked. + [31:31] + read-write + + + + + CTR2_CNT + MCWDT Subcounter 2 Count Register + 0x88 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CNT2 + Current value of subcounter 2 for this MCWDT. This field may lag the actual count value by up to one clk_lf cycle, due to internal synchronization. When this subcounter is disabled and unlocked, the count value can be written for verification and debugging purposes. Software writes are always ignored when the subcounter is enabled. This register retains information during DeepSleep mode if SLEEPDEEP_PAUSE == 1. + [31:0] + read-write + + + + + LOCK + MCWDT Lock Register + 0x90 + 32 + read-write + 0x0 + 0x3 + + + MCWDT_LOCK + Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. +Note that this field is 2 bits to force multiple writes only. Each MCWDT has a separate local lock. + [1:0] + read-write + + + NO_CHG + No effect + 0 + + + CLR0 + Clears bit 0 + 1 + + + CLR1 + Clears bit 1 + 2 + + + SET01 + Sets both bits 0 and 1 + 3 + + + + + + + SERVICE + MCWDT Service Register + 0x94 + 32 + read-write + 0x0 + 0x3 + + + CTR0_SERVICE + Services subcounter 0. This resets the count value for subcounter 0 to zero. This may take up to three clk_lf cycles to take effect. Hardware clears this bit, after necessary synchronization. To ensure a pending CTR0_SERVICE write is reflected, firmware should wait until this bit reads low before attempting to write CTR0_SERVICE=1. If subcounter 0 is disabled, CTR0_SERVICE will not trigger a LOWER_ACTION and will not clear a preloaded count value. + [0:0] + read-write + + + CTR1_SERVICE + Services subcounter 1. This resets the count value for subcounter 1 to zero. This may take up to three clk_lf cycles to take effect. Hardware clears this bit, after necessary synchronization. To ensure a pending CTR1_SERVICE write is reflected, firmware should wait until this bit reads low before attempting to write CTR1_SERVICE=1. If subcounter 1 is disabled, CTR1_SERVICE will not trigger a LOWER_ACTION and will not clear a preloaded count value. + [1:1] + read-write + + + + + INTR + MCWDT Interrupt Register + 0xA0 + 32 + read-write + 0x0 + 0x7 + + + CTR0_INT + MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. + [0:0] + read-write + + + CTR1_INT + MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. + [1:1] + read-write + + + CTR2_INT + MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. + [2:2] + read-write + + + + + INTR_SET + MCWDT Interrupt Set Register + 0xA4 + 32 + read-write + 0x0 + 0x7 + + + CTR0_INT + Set interrupt for MCWDT_INT0 + [0:0] + read-write + + + CTR1_INT + Set interrupt for MCWDT_INT1 + [1:1] + read-write + + + CTR2_INT + Set interrupt for MCWDT_INT2 + [2:2] + read-write + + + + + INTR_MASK + MCWDT Interrupt Mask Register + 0xA8 + 32 + read-write + 0x0 + 0x7 + + + CTR0_INT + Interrupt Mask for sub-counter 0 for warning interrupt. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1. + [0:0] + read-write + + + CTR1_INT + Interrupt Mask for sub-counter 1 for warning interrupt. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1. + [1:1] + read-write + + + CTR2_INT + Interrupt Mask for sub-counter 2. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1. + [2:2] + read-write + + + + + INTR_MASKED + MCWDT Interrupt Masked Register + 0xAC + 32 + read-only + 0x0 + 0x7 + + + CTR0_INT + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + CTR1_INT + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + CTR2_INT + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + + + + WDT + Watchdog Timer + WDT + 0x0000C000 + + CTL + WDT Control Register + 0x0 + 32 + read-write + 0x80000001 + 0x80000001 + + + ENABLED + Indicates actual state of watchdog. May lag ENABLE by up to three clk_ilo0 cycles. + [0:0] + read-only + + + ENABLE + Enable watchdog. May take up to three clk_ilo0 cycles to take effect. When ENABLE changes from 1->0, the counter is cleared. Do not enter DEEPSLEEP or HIBERNATE mode if ENABLE<>ENABLED. This can be done by waiting until ENABLE==ENABLED whenever ENABLE is changed. +0: Counter is disabled (not clocked). +1: Counter is enabled (counting up) + [31:31] + read-write + + + + + LOWER_LIMIT + WDT Lower Limit Register + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + LOWER_LIMIT + Lower limit for watchdog. See LOWER_ACTION. + [31:0] + read-write + + + + + UPPER_LIMIT + WDT Upper Limit Register + 0x8 + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + UPPER_LIMIT + Upper limit for watchdog. See UPPER_ACTION. + [31:0] + read-write + + + + + WARN_LIMIT + WDT Warn Limit Register + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WARN_LIMIT + Warn limit for watchdog. See WARN_ACTION. + [31:0] + read-write + + + + + CONFIG + WDT Configuration Register + 0x10 + 32 + read-write + 0x10 + 0xF0001111 + + + LOWER_ACTION + Action taken if this watchdog is serviced before LOWER_LIMIT is reached. LOWER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected and/or when the chip is in DEEPSLEEP/HIBERNATE modes. +For LOWER_LIMIT >= 1: The action is triggered on same edge when it meets this condition. +For LOWER_LIMIT == 0: No action is triggered. + [0:0] + read-write + + + NOTHING + Do nothing + 0 + + + RESET + Trigger a reset. + 1 + + + + + UPPER_ACTION + Action taken if this watchdog is not serviced before UPPER_LIMIT is reached. The counter stops counting when UPPER_LIMIT is reached, regardless of UPPER_ACTION setting. UPPER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected. +For UPPER_LIMIT >= 2: The action is triggered on same edge when it meets this condition. +For UPPER_LIMIT < 2: The action may take up to one extra clk_ilo0 cycle to trigger. + [4:4] + read-write + + + NOTHING + Do nothing + 0 + + + RESET + Trigger a reset. + 1 + + + + + WARN_ACTION + Action taken when the count value reaches WARN_LIMIT. The minimum setting to achieve a periodic interrupt is WARN_LIMIT==1. A setting of zero will trigger once but not periodically. +For WARN_LIMIT >= 2: The action is triggered on same edge when it meets this condition. +For WARN_LIMIT < 2 : The action may take up to one extra clk_ilo0 cycle to trigger. + [8:8] + read-write + + + NOTHING + Do nothing + 0 + + + INT + Trigger an interrupt. + 1 + + + + + AUTO_SERVICE + Automatically service when the count value reaches WARN_LIMIT. This allows creation of a periodic interrupt if this counter is not needed as a watchdog. This field is ignored when LOWER_ACTION<>NOTHING or when UPPER_ACTION<>NOTHING. + [12:12] + read-write + + + DEBUG_TRIGGER_EN + Enables the trigger input for WDT to pause the counter during debug mode. To pause at a breakpoint while debugging, configure the trigger matrix to connect the related CPU halted signal to the trigger input for this WDT, and then set this bit. It takes up to two clk_ilo0 cycles for the trigger signal to be processed. Triggers that are less than two clk_ilo0 cycles may be missed. Synchronization error can accumulate each time it is halted. +0: Pauses the counter whenever a debug probe is connected. +1: Pauses the counter whenever a debug probe is connected and the trigger input is high. + [28:28] + read-write + + + DPSLP_PAUSE + Pauses/runs this counter when the system is in DEEPSLEEP. Note it may take up to two clk_ilo0 cycles for the counter to pause, due to internal synchronization. During DEEPSLEEP wakeup, the pause request is removed when clk_hf0 starts clocking, and then it may take up to two clk_ilo0 cycles for the counter to start. After wakeup, the LOWER_ACTION is ignored until after the first service. This prevents an unintentional trigger of the LOWER_ACTION before the firmware realigns the servicing period. After the first service, LOWER_ACTION behaves as configured. +0: Counter behaves normally during DEEPSLEEP. +1: Counter pauses during DEEPSLEEP. + [29:29] + read-write + + + HIB_PAUSE + Pauses/runs this counter when the system is in HIBERNATE. Note it may take up to two clk_ilo0 cycles for the counter to pause, due to internal synchronization. After wakeup, the LOWER_ACTION is ignored until after the first service. This prevents an unintentional trigger of the LOWER_ACTION before the firmware realigns the servicing period. After the first service, LOWER_ACTION behaves as configured. +0: Counter behaves normally during HIBERNATE. +1: Counter pauses during HIBERNATE. + [30:30] + read-write + + + DEBUG_RUN + Pauses/runs this counter while a debugger is connected. Other behaviors are unchanged during debugging, including service, configuration updates and enable/disable. Note it may take up to two clk_ilo0 cycles for the counter to pause and another two cycles to unpause, due to internal synchronization. If the debugger is connected for at least two clk_ilo0 cycles, the LOWER_ACTION is ignored until after the first service after the debugger is disconnected. This prevents an unintentional trigger of the LOWER_ACTION before the firmware realigns the servicing period. After the first service, LOWER_ACTION behaves as configured. If the debugger is disconnected before two clk_ilo0 cycles, the LOWER_ACTION may or may not be ignored. +0: When debugger connected, counter pauses incrementing as configured in DEBUG_TRIGGER_EN. +1: When debugger connected, counter increments normally, but reset generation is blocked. + [31:31] + read-write + + + + + CNT + WDT Count Register + 0x14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CNT + Current value of subcounter for this WDT. This field may lag the actual count value by up to one clk_ilo0 cycle, due to internal synchronization. When this subcounter is disabled and unlocked, the count value can be written for verification and debugging purposes. Software writes are always ignored when the subcounter is enabled. This register retains information during DeepSleep or Hiberbate mode if DPSLP_PAUSE == 1 or HIB_PAUSE == 1. + [31:0] + read-write + + + + + LOCK + WDT Lock register + 0x40 + 32 + read-write + 0x3 + 0x3 + + + WDT_LOCK + Prohibits writing control and configuration registers related to this WDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. +Note that this field is 2 bits to force multiple writes only. This register also locks the clk_ilo0 settings. + [1:0] + read-write + + + NO_CHG + No effect + 0 + + + CLR0 + Clears bit 0 + 1 + + + CLR1 + Clears bit 1 + 2 + + + SET01 + Sets both bits 0 and 1 + 3 + + + + + + + SERVICE + WDT Service register + 0x44 + 32 + read-write + 0x0 + 0x1 + + + SERVICE + Services the watchdog. This resets the count value to zero. This may take up to three clk_ilo0 cycle to take effect. Hardware clears this bit, after necessary synchronization. To ensure a pending SERVICE write is reflected, firmware should wait until this bit reads low before attempting to write SERVICE=1. If WDT is disabled, SERVICE will not trigger a LOWER_ACTION and will not clear a preloaded count value. + [0:0] + read-write + + + + + INTR + WDT Interrupt Register + 0x50 + 32 + read-write + 0x0 + 0x1 + + + WDT + WDT Interrupt Request. This bit is set as configured by WDT action and limits. Due to internal synchronization, it takes up to 8 SYSCLK cycles to update after a W1C or reading this register and during this time AHB bus is stalled. + [0:0] + read-write + + + + + INTR_SET + WDT Interrupt Set Register + 0x54 + 32 + read-write + 0x0 + 0x1 + + + WDT + Set interrupt. +Due to internal synchronization, it takes up to 8 SYSCLK cycles to update after a W1S or reading from this register and during this time AHB bus is stalled. + [0:0] + read-write + + + + + INTR_MASK + WDT Interrupt Mask Register + 0x58 + 32 + read-write + 0x0 + 0x1 + + + WDT + Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU. + [0:0] + read-write + + + + + INTR_MASKED + WDT Interrupt Masked Register + 0x5C + 32 + read-only + 0x0 + 0x1 + + + WDT + Logical and of corresponding request and mask bits. +Due to internal synchronization, it takes up to 8 SYSCLK cycles to read from this register. During this time AHB bus is stalled. + [0:0] + read-only + + + + + + + + BACKUP + SRSS Backup Domain (ver3) + 0x40270000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0xFF0F3308 + + + WCO_EN + Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes. +After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs. Follow the procedure in BACKUP_RTC_RW to access this bit. + [3:3] + read-write + + + CLK_SEL + Clock select for RTC clock + [9:8] + read-write + + + WCO + Watch-crystal oscillator input, available in Active, DeepSleep, Hibernate, and XRES. + 0 + + + ALTBAK + This allows to use the LFCLK selection as an alternate backup domain clock. Note that LFCLK is only available in Active and DeepSleep power modes. +Note that LFCLK clock glitches can propagate into the backup logic when the clock is stopped. For this reason, if the WCO or ILO is intended as the clock source then choose it directly instead of routing through LFCLK. + 1 + + + ILO + Internal Low frequency Oscillator, available in Active, DeepSleep, Hibernate, and XRES. +For Hibernate operation CLK_ILO_CONFIG. ILO_BACKUP must be set. If there are multiple ILO, this is ILO0. + 2 + + + LPECO_PRESCALER + Low-power external crystal oscillator prescaler output, available in Active, DeepSleep, Hibernate, and XRES. + 3 + + + + + PRESCALER + N/A + [13:12] + read-write + + + WCO_BYPASS + Configures the WCO for different board-level connections to the WCO pins. For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below. Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1. +0: Watch crystal. Connect a 32.768 kHz watch crystal between WCO input and output pins. +1: Clock signal, either a square wave or sine wave. See PRESCALER field for connection information. + [16:16] + read-write + + + VDDBAK_CTL + Controls the behavior of the switch that generates vddbak from vbackup or vddd. +0: automatically select vddd if its brownout detector says it is valid. If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup. +1,2,3: force vddbak and vmax to select vbackup, regardless of its voltage. + [18:17] + read-write + + + VBACKUP_MEAS + Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled to 10 percent of vbackup, so it is within the supply range of the ADC. + [19:19] + read-write + + + EN_CHARGE_KEY + When set to 3C, the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY. + [31:24] + read-write + + + + + RTC_RW + RTC Read Write register + 0x8 + 32 + read-write + 0x0 + 0x3 + + + READ + Read bit +When this bit is set the RTC registers will be copied to user registers and frozen so that a coherent RTC value can safely be read. The RTC will keep on running. +Do not set the read bit if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Write bit is set. Do not set the Read bit at the same time that the Write bit is cleared. + [0:0] + read-write + + + WRITE + Write bit +Only when this bit is set can the RTC registers be written to (otherwise writes are ignored). This bit cannot be set if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Read bit is set or getting set. +The user writes to the RTC user registers, when the Write bit is cleared by the user then the user registers content is copied to the actual RTC registers. +Only user RTC registers that were written to will get copied, others will not be affected. +When the SECONDS field is updated then TICKS will also be reset (WDT is not affected). +When the Write bit is cleared by a reset (brown out/DeepSleep) then the RTC update will be ignored/lost. +Do not set the Write bit if the RTC if the RTC is still busy with a previous update (see RTC_BUSY). Do not set the Write bit at the same time that the Read bit is cleared. + [1:1] + read-write + + + + + CAL_CTL + Oscillator calibration for absolute frequency + 0xC + 32 + read-write + 0x0 + 0xB000007F + + + CALIB_VAL + Calibration value for absolute frequency (at a fixed temperature). Each step causes 128 ticks to be added or removed each hour. Effectively that means that each step is 1.085ppm (= 128/(60*60*32,768)). +Positive values 0x01-0x3c (1..60) add pulses, negative values remove pulses, thus giving a range of +/-65.1 ppm (limited by 60 minutes per hour, not the range of this field) + +Calibration is performed hourly, starting at 59 minutes and 59 seconds, and applied as 64 ticks every 30 seconds until there have been 2*CALIB_VAL adjustments. + [5:0] + read-write + + + CALIB_SIGN + Calibration sign: +0= Negative sign: remove pulses (it takes more clock ticks to count one second) +1= Positive sign: add pulses (it takes less clock ticks to count one second) + [6:6] + read-write + + + CAL_SEL + Select calibration wave output signal + [29:28] + read-write + + + CAL512 + 512Hz wave, not affected by calibration setting (not supported for 50/60Hz input clock: CTL.PRESCALER!=0) + 0 + + + RSVD + N/A + 1 + + + CAL2 + 2Hz wave, includes the effect of the calibration setting, (not supported for 50/60Hz input clock: CTL.PRESCALER!=0) + 2 + + + CAL1 + 1Hz wave, includes the effect of the calibration setting (supported for all input clocks) + 3 + + + + + CAL_OUT + Output enable for wave signal for calibration and allow CALIB_VAL to be written. + [31:31] + read-write + + + + + STATUS + Status + 0x10 + 32 + read-only + 0x0 + 0x5 + + + RTC_BUSY + Pending RTC write + [0:0] + read-only + + + WCO_OK + Indicates that output has transitioned. + [2:2] + read-only + + + + + RTC_TIME + Calendar Seconds, Minutes, Hours, Day of Week + 0x14 + 32 + read-write + 0x1000000 + 0x75F3F3F + + + RTC_SEC + Calendar seconds, 0-59 + [5:0] + read-write + + + RTC_MIN + Calendar minutes, 0-59 + [13:8] + read-write + + + RTC_HOUR + Calendar hours, value depending on 12/24HR mode +0=24HR: [20:16]=0-23 +1=12HR: [20]:0=AM, 1=PM, [19:16]=1-12 + [20:16] + read-write + + + CTRL_12HR + Select 12/24HR mode: 1=12HR, 0=24HR + [22:22] + read-write + + + RTC_DAY + Calendar Day of the week, 1-7 +It is up to the user to define the meaning of the values, but 1=Monday is recommended + [26:24] + read-write + + + + + RTC_DATE + Calendar Day of Month, Month, Year + 0x18 + 32 + read-write + 0x101 + 0x7F0F1F + + + RTC_DATE + Calendar Day of the Month, 1-31 +Automatic Leap Year Correction + [4:0] + read-write + + + RTC_MON + Calendar Month, 1-12 + [11:8] + read-write + + + RTC_YEAR + Calendar year, 0-99 + [22:16] + read-write + + + + + ALM1_TIME + Alarm 1 Seconds, Minute, Hours, Day of Week + 0x1C + 32 + read-write + 0x1000000 + 0x879FBFBF + + + ALM_SEC + Alarm seconds, 0-59 + [5:0] + read-write + + + ALM_SEC_EN + Alarm second enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MIN + Alarm minutes, 0-59 + [13:8] + read-write + + + ALM_MIN_EN + Alarm minutes enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_HOUR + Alarm hours, value depending on 12/24HR mode +24HR: [4:0]=0-23 +12HR: [4]:0=AM, 1=PM, [3:0]=1-12 + [20:16] + read-write + + + ALM_HOUR_EN + Alarm hour enable: 0=ignore, 1=match + [23:23] + read-write + + + ALM_DAY + Alarm Day of the week, 1-7 +It is up to the user to define the meaning of the values, but 1=Monday is recommended + [26:24] + read-write + + + ALM_DAY_EN + Alarm Day of the Week enable: 0=ignore, 1=match + [31:31] + read-write + + + + + ALM1_DATE + Alarm 1 Day of Month, Month + 0x20 + 32 + read-write + 0x101 + 0x80008F9F + + + ALM_DATE + Alarm Day of the Month, 1-31 +Leap Year corrected + [4:0] + read-write + + + ALM_DATE_EN + Alarm Day of the Month enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MON + Alarm Month, 1-12 + [11:8] + read-write + + + ALM_MON_EN + Alarm Month enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_EN + Master enable for alarm 1. +0: Alarm 1 is disabled. Fields for date and time are ignored. +1: Alarm 1 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second. + [31:31] + read-write + + + + + ALM2_TIME + Alarm 2 Seconds, Minute, Hours, Day of Week + 0x24 + 32 + read-write + 0x1000000 + 0x879FBFBF + + + ALM_SEC + Alarm seconds, 0-59 + [5:0] + read-write + + + ALM_SEC_EN + Alarm second enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MIN + Alarm minutes, 0-59 + [13:8] + read-write + + + ALM_MIN_EN + Alarm minutes enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_HOUR + Alarm hours, value depending on 12/24HR mode +24HR: [4:0]=0-23 +12HR: [4]:0=AM, 1=PM, [3:0]=1-12 + [20:16] + read-write + + + ALM_HOUR_EN + Alarm hour enable: 0=ignore, 1=match + [23:23] + read-write + + + ALM_DAY + Alarm Day of the week, 1-7 +It is up to the user to define the meaning of the values, but 1=Monday is recommended + [26:24] + read-write + + + ALM_DAY_EN + Alarm Day of the Week enable: 0=ignore, 1=match + [31:31] + read-write + + + + + ALM2_DATE + Alarm 2 Day of Month, Month + 0x28 + 32 + read-write + 0x101 + 0x80008F9F + + + ALM_DATE + Alarm Day of the Month, 1-31 +Leap Year corrected + [4:0] + read-write + + + ALM_DATE_EN + Alarm Day of the Month enable: 0=ignore, 1=match + [7:7] + read-write + + + ALM_MON + Alarm Month, 1-12 + [11:8] + read-write + + + ALM_MON_EN + Alarm Month enable: 0=ignore, 1=match + [15:15] + read-write + + + ALM_EN + Master enable for alarm 2. +0: Alarm 2 is disabled. Fields for date and time are ignored. +1: Alarm 2 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second. + [31:31] + read-write + + + + + INTR + Interrupt request register + 0x2C + 32 + read-write + 0x0 + 0x7 + + + ALARM1 + Alarm 1 Interrupt + [0:0] + read-write + + + ALARM2 + Alarm 2 Interrupt + [1:1] + read-write + + + CENTURY + Century overflow interrupt + [2:2] + read-write + + + + + INTR_SET + Interrupt set request register + 0x30 + 32 + read-write + 0x0 + 0x7 + + + ALARM1 + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + ALARM2 + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + CENTURY + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x34 + 32 + read-write + 0x0 + 0x7 + + + ALARM1 + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + ALARM2 + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + CENTURY + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + + + INTR_MASKED + Interrupt masked request register + 0x38 + 32 + read-only + 0x0 + 0x7 + + + ALARM1 + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + ALARM2 + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + CENTURY + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + + + PMIC_CTL + PMIC control register + 0x44 + 32 + read-write + 0xA0000000 + 0xE001FF00 + + + UNLOCK + This byte must be set to 0x3A for PMIC to be disabled. When the UNLOCK code is not present: writes to PMIC_EN field are ignored and the hardware ignores the value in PMIC_EN. Do not change PMIC_EN in the same write cycle as setting/clearing the UNLOCK code; do these in separate write cycles. + [15:8] + read-write + + + POLARITY + N/A + [16:16] + read-write + + + PMIC_EN_OUTEN + Output enable for the output driver in the PMIC_EN pad. +0: Output pad is tristate for PMIC_EN pin. This can allow this pin to be used for another purpose. Tristate condition is kept only if the UNLOCK key (0x3A) is present +1: Output pad is enabled for PMIC_EN pin. + [29:29] + read-write + + + PMIC_ALWAYSEN + Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware. +0: Normal operation, PMIC_EN and PMIC_OUTEN work as described +1: PMIC_EN and PMIC_OUTEN are ignored and the output pad is forced enabled. +Note: This bit is a write-once bit until the next backup reset. + [30:30] + read-write + + + PMIC_EN + Enable for external PMIC that supplies vddd (if present). This bit will only clear if UNLOCK was written correctly in a previous write operation and PMIC_ALWAYSEN=0. When PMIC_EN=0, the system functions normally until vddd is no longer present (OFF w/Backup mode). Firmware can set this bit, if it does so before vddd is actually removed. This bit is also set by any RTC alarm or PMIC pin wakeup event regardless of UNLOCK setting. + [31:31] + read-write + + + + + RESET + Backup reset register + 0x48 + 32 + read-write + 0x0 + 0x80000000 + + + RESET + Writing 1 to this register resets the backup logic. Hardware clears it when the reset is complete. After setting this register, firmware should confirm it reads as 0 before attempting to write other backup registers. + [31:31] + read-write + + + + + LPECO_CTL + Low-power external crystal oscillator control + 0x80 + 32 + read-write + 0x40000000 + 0xD0001130 + + + LPECO_CRANGE + Specifies the load capacitance of the chosen crystal. +2'b00: load is in range [5pF, 10pF], +2'b01: load is in range (10pF, 15pF], +2'b10: load is in range (15pF, 20pF], +2'b11: load is in range (20pF, 25pF] + [5:4] + read-write + + + LPECO_FRANGE + Specifies the crystal frequency range. +0: Crystal frequency is in range [4, 6) MHz +1: Crystal frequency is in range [6, 8] MHz. Use this setting for 6 MHz. + [8:8] + read-write + + + LPECO_AMP_SEL + Selects the oscillation amplitude. WARNING: the crystal can be permanently damaged by selecting an amplitude that exceeds the crystal limits. +0: maximum amplitude is 1.35V. This is the lowest power setting. +1: maximum amplitude is 1.8V. This is the lowest jitter setting. + [12:12] + read-write + + + LPECO_DIV_ENABLE + LPECO prescaler enable. Do not set this to '1' when LPECO_EN==0. SW sets this field to '1' to enable the divider and HW sets this field to '0' to indicate that divider enabling has completed. When the divider is enabled, its integer and fractional counters are initialized to '0'. + +HW sets the LPECO_DIV_ENABLE field to '0' when the enabling is performed and HW set CLK_LPECO_PRESCALER.ENABLED to '1' when the enabling is performed. + [28:28] + read-write + + + LPECO_AMPDET_EN + Minimum amplitude detector enable/disable. Ignored when LPECO_EN==0. +0: Initially enabled, and then automatically disabled when amplitude detector detects sufficient amplitude. +1: Keep minimum amplitude detector enabled as long as LPECO is enabled. + [30:30] + read-write + + + LPECO_EN + Master enable for LPECO oscillator. This also disables the LPECO prescaler. + [31:31] + read-write + + + + + LPECO_PRESCALE + Low-power external crystal oscillator prescaler + 0x84 + 32 + read-write + 0x0 + 0x3FFFF01 + + + LPECO_DIV_ENABLED + LPECO prescaler enabled. HW sets this field to '1' as a result of an BACKUP_LPECO_CTL.LPECO_DIV_ENABLE. HW sets this field to '0' as a result of writing CLK_LPECO_CONFIG.LPECO_EN==0. This field does not update unless LPECO clock is toggling. + [0:0] + read-only + + + LPECO_FRAC_DIV + Fractional value, sufficient to get prescaler output within the +/-65ppm calibration range. Do not change this setting when LPECO Prescaler is enabled. + [15:8] + read-write + + + LPECO_INT_DIV + Integer divide value allows for LPECO frequencies up to 8MHz to generate 32768 Hz. Subtract one from the desired divide value when writing this field. For example, to divide by 1, write LPECO_INT_DIV=0. Do not change this setting when LPECO Prescaler is enabled. + [25:16] + read-write + + + + + LPECO_STATUS + Low-power external crystal oscillator status + 0x88 + 32 + read-only + 0x0 + 0x3 + + + LPECO_AMPDET_OK + Indicates sufficient oscillation amplitude reported by LPECO amplitude detector. This field will read as zero when the amplitude detector is off (see LPECO_CTL.LPECO_AMPDET_EN). + [0:0] + read-only + + + LPECO_READY + Indicates the LPECO has had enough time to start. This field is driven by a stabilization counter clocked by IMO. + [1:1] + read-only + + + + + 64 + 4 + BREG[%s] + Backup register region + 0x1000 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + BREG + Backup memory that contains application-specific data. Memory is retained on vbackup supply. + [31:0] + read-write + + + + + + + DW0 + Datawire Controller + DW + 0x40280000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x1 + 0x80000003 + + + ECC_EN + Enable ECC checking: +'0': Disabled. +'1': Enabled. + [0:0] + read-write + + + ECC_INJ_EN + Enable parity injection for SRAM. +When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM. + [1:1] + read-write + + + ENABLED + IP enable: +'0': Disabled. Disabling the IP activates the IP's Active logic reset: Active logic and non-retention MMIO registers are reset (retention MMIO registers are not affected). +'1': Enabled. + [31:31] + read-write + + + + + STATUS + Status + 0x4 + 32 + read-only + 0x0 + 0xF0000000 + + + P + Active channel, user/privileged access control: +'0': user mode. +'1': privileged mode. + [0:0] + read-only + + + NS + Active channel, secure/non-secure access control: +'0': secure. +'1': non-secure. + [1:1] + read-only + + + B + Active channel, non-bufferable/bufferable access control: +'0': non-bufferable +'1': bufferable. + [2:2] + read-only + + + PC + Active channel protection context. + [7:4] + read-only + + + PRIO + Active channel priority. + [9:8] + read-only + + + PREEMPTABLE + Active channel preemptable. + [11:11] + read-only + + + CH_IDX + Active channel index. + [24:16] + read-only + + + STATE + State of the DW controller. +'0': Default/inactive state. +'1': Loading descriptor. +'2': Loading data element from source location. +'3': Storing data element to destination location. +'4': CRC functionality (only used for CRC transfer descriptor type). +'5': Update of active control information (e.g. source and destination addresses) and wait for trigger de-activation. +'6': Error. + [30:28] + read-only + + + ACTIVE + Active channel present: +'0': No. +'1': Yes. + [31:31] + read-only + + + + + ACT_DESCR_CTL + Active descriptor control + 0x20 + 32 + read-only + 0x0 + 0x0 + + + DATA + N/A + [31:0] + read-only + + + + + ACT_DESCR_SRC + Active descriptor source + 0x24 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_SRC of the currently active descriptor. + +Base address of source location. + [31:0] + read-only + + + + + ACT_DESCR_DST + Active descriptor destination + 0x28 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_DST of the currently active descriptor. + +Base address of destination location. + +Note: For a CRC transfer descriptor, this field should be programmed with the address of the CRC_LFSR_CTL register. The calculated CRC LFSR state is written to this address (through the CRYPTO AHB-Lite master interface) when the input trigger is processed. The write transfer will be submitted to the CPUSS and PERI protection schemes. + [31:0] + read-only + + + + + ACT_DESCR_X_CTL + Active descriptor X loop control + 0x30 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_X_CTL of the currently active descriptor. + +[11:0] SRC_X_INCR +Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures. + +[23:12] DST_X_INCR +Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures. + +Note: this field is not used for CRC transfer descriptors and must be set to '0'. + +[31:24] X_COUNT +Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations. + +For a single transfer descriptor type, descriptor will not have X_CTL. + [31:0] + read-only + + + + + ACT_DESCR_Y_CTL + Active descriptor Y loop control + 0x34 + 32 + read-only + 0x0 + 0x0 + + + DATA + Copy of DESCR_Y_CTL of the currently active descriptor. + +[11:0] SRC_Y_INCR +Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. + +[23:12] DST_Y_INCR +Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. + +[31:24] Y_COUNT +Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations. + +For single, 1D and CRC transfer descriptor types, descriptor will not have Y_CTL. + [31:0] + read-only + + + + + ACT_DESCR_NEXT_PTR + Active descriptor next pointer + 0x38 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Copy of DESCR_NEXT_PTR of the currently active descriptor. + +[31:2] ADDR +Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list. + [31:2] + read-only + + + + + ACT_SRC + Active source + 0x40 + 32 + read-only + 0x0 + 0x0 + + + SRC_ADDR + Current address of source location. + [31:0] + read-only + + + + + ACT_DST + Active destination + 0x44 + 32 + read-only + 0x0 + 0x0 + + + DST_ADDR + Current address of destination location. + [31:0] + read-only + + + + + ECC_CTL + ECC control + 0x80 + 32 + read-write + 0x0 + 0xFE0003FF + + + WORD_ADDR + Specifies the word address where an error will be injected. +- On a write transfer to this SRAM word address and when CTL.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. + [9:0] + read-write + + + PARITY + ECC parity to use for ECC error injection at address WORD_ADDR. + [31:25] + read-write + + + + + CRC_CTL + CRC control + 0x100 + 32 + read-write + 0x0 + 0x101 + + + DATA_REVERSE + Specifies the bit order in which a data Byte is processed (reversal is performed after XORing): +'0': Most significant bit (bit 1) first. +'1': Least significant bit (bit 0) first. + [0:0] + read-write + + + REM_REVERSE + Specifies whether the remainder is bit reversed (reversal is performed after XORing): +'0': No. +'1': Yes. + [8:8] + read-write + + + + + CRC_DATA_CTL + CRC data control + 0x110 + 32 + read-write + 0x0 + 0xFF + + + DATA_XOR + Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal. + [7:0] + read-write + + + + + CRC_POL_CTL + CRC polynomial control + 0x120 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + POLYNOMIAL + CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials: +- CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1). +- CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions). +- CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions). + [31:0] + read-write + + + + + CRC_LFSR_CTL + CRC LFSR control + 0x130 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + LFSR32 + State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value. + +The seed value should be aligned such that the more significant bits (bit 31 and down) contain the seed value and the less significant bits (bit 0 and up) contain padding '0's. + +Note that SW can write this field. This functionality can be used prevent information leakage (through either CRC_LFSR_CTL or CRC_REM_RESULT). + [31:0] + read-write + + + + + CRC_REM_CTL + CRC remainder control + 0x140 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + REM_XOR + Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal. + [31:0] + read-write + + + + + CRC_REM_RESULT + CRC remainder result + 0x148 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REM + Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE: +'0': the more significant bits (bit 31 and down) contain the remainder. +'1': the less significant bits (bit 0 and up) contain the remainder. + +Note: This field is combinatorially derived from CRC_LFSR_CTL.LFSR32, CRC_CTL.REM_REVERSE and CRC_REM_CTL.REM_XOR. + [31:0] + read-only + + + + + 100 + 64 + CH_STRUCT[%s] + DW channel structure + 0x00008000 + + CH_CTL + Channel control + 0x0 + 32 + read-write + 0x0 + 0x80000300 + + + P + User/privileged access control: +'0': user mode. +'1': privileged mode. + +This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). + +All transactions for this channel use the P field for the user/privileged access control ('hprot[1]'). + [0:0] + read-write + + + NS + Secure/on-secure access control: +'0': secure. +'1': non-secure. + +This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). + +All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]'). + [1:1] + read-write + + + B + Non-bufferable/bufferable access control: +'0': non-bufferable. +'1': bufferable. + +This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. + +All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]'). + [2:2] + read-write + + + PC + Protection context. + +This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). + +All transactions for this channel uses the PC field for the protection context. + [7:4] + read-write + + + PRIO + Channel priority: +'0': highest priority. +'1' +'2' +'3': lowest priority. + +Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, round robin arbitration is applied. Round robin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group). + [9:8] + read-write + + + PREEMPTABLE + Specifies if the channel is preemptable. +'0': Not preemptable. +'1': Preemptable. This field allows higher priority pending channels (from a higher priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated. + [11:11] + read-write + + + ENABLED + Channel enable: +'0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). +'1': Enabled. + +SW sets this field to '1' to enable a specific channel. + +HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE). + [31:31] + read-write + + + + + CH_STATUS + Channel status + 0x4 + 32 + read-only + 0x0 + 0x80000000 + + + INTR_CAUSE + Specifies the source of the interrupt cause: +'0': No interrupt generated +'1': Interrupt based on transfer complettion configuration based on INTR_TYPE +'2': Source transfer bus error +'3': Destination transfer bus error +'4': Source address misalignment +'5': Destination address misalignment +'6': Current descriptor pointer is null +'7': Active channel is disabled +'8': Descriptor bus error +'9'-'15': Not used. + +For error related interrupt causes (INTR_CAUSE is '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0'). + [3:0] + read-only + + + PENDING + Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s)). + [31:31] + read-only + + + + + CH_IDX + Channel current indices + 0x8 + 32 + read-write + 0x0 + 0x0 + + + X_IDX + Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + +Note: SW should set this field to '0' when it updates CH_CURR_PTR. + [7:0] + read-write + + + Y_IDX + Specifies the Y loop index, with X_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + +Note: SW should set this field to '0' when it updates CH_CURR_PTR. + [15:8] + read-write + + + + + CH_CURR_PTR + Channel current descriptor pointer + 0xC + 32 + read-write + 0x0 + 0x0 + + + ADDR + Address of current descriptor. When this field is '0', there is no valid descriptor. + +Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + +Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'. + [31:2] + read-write + + + + + INTR + Interrupt + 0x10 + 32 + read-write + 0x0 + 0x1 + + + CH + Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit. + [0:0] + read-write + + + + + INTR_SET + Interrupt set + 0x14 + 32 + read-write + 0x0 + 0x1 + + + CH + Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect). + [0:0] + read-write + + + + + INTR_MASK + Interrupt mask + 0x18 + 32 + read-write + 0x0 + 0x1 + + + CH + Mask for corresponding field in INTR register. + [0:0] + read-write + + + + + INTR_MASKED + Interrupt masked + 0x1C + 32 + read-only + 0x0 + 0x1 + + + CH + Logical and of corresponding INTR and INTR_MASK fields. + [0:0] + read-only + + + + + SRAM_DATA0 + SRAM data 0 + 0x20 + 32 + read-write + 0x0 + 0x0 + + + DATA + N/A + [31:0] + read-write + + + + + SRAM_DATA1 + SRAM data 1 + 0x24 + 32 + read-write + 0x0 + 0x0 + + + DATA + N/A + [31:0] + read-write + + + + + TR_CMD + Channel software trigger + 0x28 + 32 + read-write + 0x0 + 0x1 + + + ACTIVATE + Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0. + [0:0] + read-write + + + + + + + + DW1 + 0x40290000 + + + DMAC + DMAC + 0x402A0000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLED + IP enable: +'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. +'1': Enabled. + [31:31] + read-write + + + DISABLED + N/A + 0 + + + ENABLED + N/A + 1 + + + + + + + ACTIVE + Active channels + 0x8 + 32 + read-only + 0x0 + 0xFF + + + ACTIVE + Specifies active channels; i.e. enabled channels whose trigger got activated. + [7:0] + read-only + + + + + 8 + 256 + CH[%s] + DMA controller channel + 0x00001000 + + CTL + Channel control + 0x0 + 32 + read-write + 0x2 + 0x800003F7 + + + P + User/privileged access control: +'0': user mode. +'1': privileged mode. + +This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. + +All transactions for this channel use the P field for the user/privileged access control ('hprot[1]'). + [0:0] + read-write + + + NS + Secure/on-secure access control: +'0': secure. +'1': non-secure. + +This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data. + +All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]'). + [1:1] + read-write + + + B + Non-bufferable/bufferable access control: +'0': non-bufferable. +'1': bufferable. + +This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. + +All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]'). + [2:2] + read-write + + + PC + Protection context. + +This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data. + +All transactions for this channel uses the PC field for the protection context. + [7:4] + read-write + + + PRIO + Channel priority: +'0': highest priority. +'1' +'2' +'3': lowest priority. + +Channels with the same priority constitute a priority group and within this priority group, the following 'roundrobin' arbitration is applied. +A 'round' consists of a contiguous sequence of channel activations, within this priority group, without any repetition. Within a round, higher priority is given to the lower channel indices. The notion of a round guarantees that within a group, higher channel indices do not yield to lower indices indefinitely. + [9:8] + read-write + + + ENABLED + Channel enable: +'0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). +'1': Enabled. + +SW sets this field to '1' to enable a specific channel. + +HW sets this field to '0' when an error interrupt cause is activated. + [31:31] + read-write + + + + + IDX + Channel current indices + 0x10 + 32 + read-only + 0x0 + 0x0 + + + X + Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it loads a descriptor. + [15:0] + read-only + + + Y + Specifies the Y loop index, with Y_COUNT taken from the current descriptor. + +Note: HW sets this field to '0' when it loads a descriptor.. + [31:16] + read-only + + + + + SRC + Channel current source address + 0x14 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Current address of source location. + [31:0] + read-only + + + + + DST + Channel current destination address + 0x18 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Current address of destination location. + [31:0] + read-only + + + + + CURR + Channel current descriptor pointer + 0x20 + 32 + read-write + 0x0 + 0x0 + + + PTR + Address of current descriptor. When this field is '0', there is no valid descriptor. + +Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. + [31:2] + read-write + + + + + TR_CMD + Channle software trigger + 0x28 + 32 + read-write + 0x0 + 0x1 + + + ACTIVATE + Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0. + [0:0] + read-write + + + + + DESCR_STATUS + Channel descriptor status + 0x40 + 32 + read-only + 0x0 + 0x80000000 + + + VALID + Indicates whether the descriptor information present in DESCR_CTL, DESCR_SRC, DESCR_DST, DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE, DESCR_Y_INCR, DESCR_NEXT status registers is valid or not. + [31:31] + read-only + + + + + DESCR_CTL + Channel descriptor control + 0x60 + 32 + read-only + 0x0 + 0x0 + + + WAIT_FOR_DEACT + Specifies whether the controller should wait for the input trigger to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller with the agent that generated the trigger. This field is ONLY used at the completion of the transfer as specified by TR_IN. E.g., a TX FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the controller AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW controller performance. +'0': Do not wait for trigger de-activation (for pulse sensitive triggers). +'1': Wait for up to 4 cycles. +'2': Wait for up to 16 cycles. +'3': Wait indefinitely. This option may result in controller lockup if the trigger is not de-activated. + [1:0] + read-only + + + INTR_TYPE + Specifies when a completion interrupt is generated (CH_STATUS.INTR_CAUSE is set to COMPLETION): +'0': An interrupt is generated after a single transfer. +'1': An interrupt is generated after a single 1D transfer or a memory copy transfer +- If the descriptor type is 'single', the interrupt is generated after a single transfer. +- If the descriptor type is '1D' or '2D', the interrupt is generated after the execution of a 1D transfer. +- If the descriptor type is 'memory copy', the interrupt is generated after the execution of a memory copy transfer. +- If the descriptor type is 'scatter' the interrupt is generated after the execution of a scatter transfer. +'2': An interrupt is generated after the execution of the current descriptor (independent of the value of DESCR_NEXT_PTR.ADDR of the current descriptor). +'3': An interrupt is generated after the execution of the current descriptor and the current descriptor's DESCR_NEXT_PTR.ADDR is '0'. + [3:2] + read-only + + + TR_OUT_TYPE + Specifies when an output trigger is generated: +'0': An output trigger is generated after a single transfer. +'1': An output trigger is generated after a single 1D transfer or a memory copy transfer. +- If the descriptor type is 'single', the output trigger is generated after a single transfer. +- If the descriptor type is '1D' or '2D', the output trigger is generated after the execution of a 1D transfer. +- If the descriptor type is 'memory copy', the output trigger is generated after the execution of a memory copy transfer. +- If the descriptor type is 'scatter', the output trigger is generated after the execution of a scatter transfer. +'2': An output trigger is generated after the execution of the current descriptor. +'3': An output trigger is generated after the execution of a descriptor list: after the execution of the current descriptor AND the current descriptor's DESCR_NEXT_PTR.ADDR is '0'. + [5:4] + read-only + + + TR_IN_TYPE + Specifies the input trigger type (not to be confused with the descriptor type): +'0': A trigger results in the execution of a single transfer. The descriptor type can be single, 1D or 2D. +'1': A trigger results in the execution of a single 1D transfer. +- If the descriptor type is 'single', the trigger results in the execution of a single transfer. +- If the descriptor type is '1D' or '2D', the trigger results in the execution of a 1D transfer. +- If the descriptor type is 'memory copy', the trigger results in the execution of a memory copy transfer. +- If the descriptor type is 'scatter', the trigger results in the execution of an scatter transfer. +'2': A trigger results in the execution of the current descriptor. +'3': A trigger results in the execution of the current descriptor and continues (without requiring another input trigger) with the execution of the next descriptor using the next descriptor's information. + [7:6] + read-only + + + DATA_PREFETCH + Source data prefetch: +'0': No source data prefetch. Source data transfers are only initiated AFTER the input trigger is activated. +'1': Source data prefetch. Source data transfers are initiated as soon as the channel is enabled, the current descriptor pointer is NOT '0' and there is space available in the channel's data FIFO. When the input trigger is activated, the trigger can initiate destination data transfers with data that is already in the channel's data FIFO. This effectively shortens the initial delay of the data transfer. + +Note: data prefetch should be used with care, to ensure that data coherency is guaranteed and that prefetches do not cause undesired side effects. + [8:8] + read-only + + + DATA_SIZE + Specifies the data element size: +'0': Byte (8 bits). +'1': Halfword (16 bits). +'2': Word (32 bits). +DATA_SIZE, SRC_TRANSFER_SIZE and DST_TRANSFER_SIZE together determine how data elements are transferred. The following are the 9 legal settings: +- DATA is 8 bit, SRC is 8 bit, DST is 8 bit. +- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 8 bit. +- DATA is 8 bit, SRC is 8 bit, DST is 32 bit (higher 24 bits are made '0'). +- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 32 bit (higher 24 bits are made '0'). +- DATA is 16 bit, SRC is 16 bit, DST is 16 bit. +- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 16 bit. +- DATA is 16 bit, SRC is 16 bit, DST is 32 bit (higher 16 bits are made '0'). +- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 32 bit (higher 16 bits are made '0'). +- DATA is 32 bit, SRC is 32 bit, DST is 32 bit. + +Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '2' for a 'initialization' descriptor type. + [17:16] + read-only + + + CH_DISABLE + Specifies whether the channel is disabled or not after completion of the current descriptor (independent of the value of the DESCR_NEXT_PTR value): +'0': Channel is not disabled. +'1': Channel is disabled. + [24:24] + read-only + + + SRC_TRANSFER_SIZE + Specifies the bus transfer size to the source location: +'0': As specified by DATA_SIZE. +'1': Word (32 bits). +Distinguishing bus transfer size from data element size allows for source components with data elements that are smaller than their 32-bit bus interface width. E.g., an ADC source has a 32-bit bus transfer size, but only provides a 16-bit data element. + +Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type. + [26:26] + read-only + + + DST_TRANSFER_SIZE + Specifies the bus transfer size to the destination location: +'0': As specified by DATA_SIZE. +'1': Word (32 bits). +Distinguishing bus transfer size from data element size allows for destination components with data elements that are smaller than their 32-bit bus interface width. E.g., a DAC destination has a 32-bit bus transfer size, but only requires a 16-bit data element. + +Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type. + [27:27] + read-only + + + DESCR_TYPE + Specifies the descriptor type (not to be confused with the trigger type): +'0': Single transfer. +The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are NOT present. The DESCR_NEXT_PTR is at offset 0x0c. +'1': 1D transfer. +The DESCR_X_SIZE and DESCR_X_INCR registers are present, the DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A 1D transfer consists out of DESCR_X_SIZE.X_COUNT+1 single transfers. The DESCR_NEXT_PTR is at offset 0x14. +'2': 2D transfer. +The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are present. A 2D transfer consists of (DESCR_X_SIZE.X_COUNT+1)*(DESCR_Y_SIZE.Y_COUNT+1) single transfers. The DESCR_NEXT_PTR is at offset 0x1c. +'3': Memory copy. +The DESCR_X_SIZE register is present, the DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A memory copy transfer copies DESCR_X_SIZE.X_COUNT+1 Bytes and may use Byte, halfword and word transfers. The DESCR_NEXT_PTR is at offset 0x10. +'4': Scatter transfer. The DESCR_X_SIZE register is present, the DESCR_DST, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. +'5'-'7': Undefined. + +After the execution of the current descriptor, the DESCR_NEXT_PTR address is copied to the channel's CH_CURR_PTR address and CH_STATUS.X_IDX and CH_STATUS.Y_IDX are set to '0'. + [30:28] + read-only + + + + + DESCR_SRC + Channel descriptor source + 0x64 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Base address of source location. + [31:0] + read-only + + + + + DESCR_DST + Channel descriptor destination + 0x68 + 32 + read-only + 0x0 + 0x0 + + + ADDR + Base address of destination location. + [31:0] + read-only + + + + + DESCR_X_SIZE + Channel descriptor X size + 0x6C + 32 + read-only + 0x0 + 0x0 + + + X_COUNT + Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations. + +For the 'memory copy' descriptor type, (X_COUNT + 1) is the number of transferred Bytes. For the 'scatter' descriptor type, ceiling(X_COUNT/2) is the number of (address, write data) initialization pairs processed. + [15:0] + read-only + + + + + DESCR_X_INCR + Channel descriptor X increment + 0x70 + 32 + read-only + 0x0 + 0x0 + + + SRC_X + Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures. + [15:0] + read-only + + + DST_X + Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures. + [31:16] + read-only + + + + + DESCR_Y_SIZE + Channel descriptor Y size + 0x74 + 32 + read-only + 0x0 + 0x0 + + + Y_COUNT + Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations. + [15:0] + read-only + + + + + DESCR_Y_INCR + Channel descriptor Y increment + 0x78 + 32 + read-only + 0x0 + 0x0 + + + SRC_Y + Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767]. + [15:0] + read-only + + + DST_Y + Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767]. + [31:16] + read-only + + + + + DESCR_NEXT + Channel descriptor next pointer + 0x7C + 32 + read-only + 0x0 + 0x0 + + + PTR + Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list. + [31:2] + read-only + + + + + INTR + Interrupt + 0x80 + 32 + read-write + 0x0 + 0xFF + + + COMPLETION + Activated (set to '1') on completion of data transfer(s) as specified by the descriptor's CH_DESCR_CTL.INTR_TYPE. + [0:0] + read-write + + + SRC_BUS_ERROR + Activated (set to '1') on a bus error for a load from the source. + [1:1] + read-write + + + DST_BUS_ERROR + Activated (set to '1') on a bus error for a store to the destination. + [2:2] + read-write + + + SRC_MISAL + Activated (set to '1') on a misalignment of the source address. + [3:3] + read-write + + + DST_MISAL + Activated (set to '1') on a misalignment of the destination address. + [4:4] + read-write + + + CURR_PTR_NULL + Activated (set to '1') when the channel is enabled (CH_CTL.ENABLED is '1') and CH_CURR_PTR is '0'. + [5:5] + read-write + + + ACTIVE_CH_DISABLED + Activated (set to '1') if the channel is disabled by SW (accidentally/incorrectly) when the data transfer engine is busy. + [6:6] + read-write + + + DESCR_BUS_ERROR + Activated (set to '1') on a bus error for a load of the descriptor. + [7:7] + read-write + + + + + INTR_SET + Interrupt set + 0x84 + 32 + read-write + 0x0 + 0xFF + + + COMPLETION + Write this field with '1' to set INTR.COMPLETION field to '1' (a write of '0' has no effect). + [0:0] + read-write + + + SRC_BUS_ERROR + Write this field with '1' to set INTR.SRC_BUS_ERROR field to '1' (a write of '0' has no effect). + [1:1] + read-write + + + DST_BUS_ERROR + Write this field with '1' to set INTR.DST_BUS_ERROR field to '1' (a write of '0' has no effect). + [2:2] + read-write + + + SRC_MISAL + Write this field with '1' to set INTR.SRC_MISAL field to '1' (a write of '0' has no effect). + [3:3] + read-write + + + DST_MISAL + Write this field with '1' to set INTR.DST_MISAL field to '1' (a write of '0' has no effect). + [4:4] + read-write + + + CURR_PTR_NULL + Write this field with '1' to set INTR.CURR_PTR_NULL field to '1' (a write of '0' has no effect). + [5:5] + read-write + + + ACTIVE_CH_DISABLED + Write this field with '1' to set INTR.ACT_CH_DISABLED field to '1' (a write of '0' has no effect). + [6:6] + read-write + + + DESCR_BUS_ERROR + Write this field with '1' to set INTR.DESCR_BUS_ERROR field to '1' (a write of '0' has no effect). + [7:7] + read-write + + + + + INTR_MASK + Interrupt mask + 0x88 + 32 + read-write + 0x0 + 0xFF + + + COMPLETION + Mask for INTR.COMPLETION interrupt. + [0:0] + read-write + + + SRC_BUS_ERROR + Mask for INTR.SRC_BUS_ERROR interrupt. + [1:1] + read-write + + + DST_BUS_ERROR + Mask for INTR.DST_BUS_ERROR interrupt. + [2:2] + read-write + + + SRC_MISAL + Mask for INTR.SRC_MISAL interrupt. + [3:3] + read-write + + + DST_MISAL + Mask for INTR.DST_MISAL interrupt. + [4:4] + read-write + + + CURR_PTR_NULL + Mask for INTR.CURR_PTR_NULL interrupt. + [5:5] + read-write + + + ACTIVE_CH_DISABLED + Mask for INTR.ACTIVE_CH_DISABLED interrupt. + [6:6] + read-write + + + DESCR_BUS_ERROR + Mask for INTR.DESCR_BUS_ERROR interrupt. + [7:7] + read-write + + + + + INTR_MASKED + Interrupt masked + 0x8C + 32 + read-only + 0x0 + 0xFF + + + COMPLETION + Logical and of corresponding INTR.COMPLETION and INTR_MASK.COMPLETION fields. + [0:0] + read-only + + + SRC_BUS_ERROR + Logical and of corresponding INTR.SRC_BUS_ERROR and INTR_MASK.SRC_BUS_ERROR fields. + [1:1] + read-only + + + DST_BUS_ERROR + Logical and of corresponding INTR.DST_BUS_ERROR and INTR_MASK.DST_BUS_ERROR fields. + [2:2] + read-only + + + SRC_MISAL + Logical and of corresponding INTR.SRC_MISAL and INTR_MASK.SRC_MISAL fields. + [3:3] + read-only + + + DST_MISAL + Logical and of corresponding INTR.DST_MISAL and INTR_MASK.DST_MISAL fields. + [4:4] + read-only + + + CURR_PTR_NULL + Logical and of corresponding INTR.CURR_PTR_NULL and INTR_MASK.CURR_PTR_NULL fields. + [5:5] + read-only + + + ACTIVE_CH_DISABLED + Logical and of corresponding INTR.ACTIVE_CH_DISABLED and INTR_MASK.ACTIVE_CH_DISABLED fields. + [6:6] + read-only + + + DESCR_BUS_ERROR + Logical and of corresponding INTR.DESCR_BUS_ERROR and INTR_MASK.DESCR_BUS_ERROR fields. + [7:7] + read-only + + + + + + + + EFUSE + EFUSE MXS40 registers + 0x402C0000 + + 0 + 512 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLED + IP enable: +'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. +'1': Enabled. + [31:31] + read-write + + + + + TEST + Test + 0x4 + 32 + read-write + 0x1 + 0x3 + + + MARG_READ + Margin Read + [1:0] + read-write + + + LOWR + Low Resistance: -50 percent from nominal + 0 + + + DEFAULTR + Nominal resistance (Default read condition) + 1 + + + HIGHR + High Resistance: +50 percent from nominal + 2 + + + HIGHERR + Higher Resistance: +100 percent from nominal + 3 + + + + + + + CMD + Command + 0x10 + 32 + read-write + 0x1 + 0x800F1F71 + + + BIT_DATA + Bit data. This field specifies the bit value that is to be programmed into the eFUSE macro array. The address of the bit is specified by the BIT_ADDR, BYTE_ADDR, and MACRO_ADDR fields. This bit is a don't care for the MXS40 Macro. + [0:0] + read-write + + + BIT_ADDR + Bit address. This field specifies a bit within a Byte. + [6:4] + read-write + + + BYTE_ADDR + Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B). + [12:8] + read-write + + + MACRO_ADDR + Macro address. This field specifies an eFUSE macro. + [19:16] + read-write + + + START + FW sets this field to '1' to start a program operation. HW sets this field to '0' to indicate that the operation has completed. + +Note: it is good practice to verify the result of a program operation by reading back a programmed eFUSE memory location. Programming can only change an eFUSE memory bit from '0' to '1'; i.e. a programming operation is a 'one-off' operation for each eFUSE memory bit: once a bit is changed to '1', it can NEVER be changed back to '0' as a hardware fuse is blown. + +Programming a memory bit to '1' requires blowing a fuse and requires an eFUSE macro operation. Therefore, this programmiong operation takes time (as specified by the SEQ_PROGRAM_CTL reguisters). Programming amemory bit to '0' does not require an eFUSE macro operation (it is the default eFUSE macro state). Therefore, this programming operation is almost instantaneous. + +Note: during a program operation, a read operation can not be performed. An AHB-Lite read transfer to the eFUSE memory during a program operation results in an AHB-Lite bus error. + [31:31] + read-write + + + + + SEQ_DEFAULT + Sequencer Default value + 0x20 + 32 + read-write + 0x1D0000 + 0x7F0000 + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + + + SEQ_READ_CTL_0 + Sequencer read control 0 + 0x40 + 32 + read-write + 0x80560001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_1 + Sequencer read control 1 + 0x44 + 32 + read-write + 0x540004 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_2 + Sequencer read control 2 + 0x48 + 32 + read-write + 0x560001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_3 + Sequencer read control 3 + 0x4C + 32 + read-write + 0x540003 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_4 + Sequencer read control 4 + 0x50 + 32 + read-write + 0x80150001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_READ_CTL_5 + Sequencer read control 5 + 0x54 + 32 + read-write + 0x310004 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_f + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_0 + Sequencer program control 0 + 0x60 + 32 + read-write + 0x200001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_1 + Sequencer program control 1 + 0x64 + 32 + read-write + 0x220020 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_2 + Sequencer program control 2 + 0x68 + 32 + read-write + 0x200001 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_3 + Sequencer program control 3 + 0x6C + 32 + read-write + 0x310005 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_4 + Sequencer program control 4 + 0x70 + 32 + read-write + 0x80350006 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + SEQ_PROGRAM_CTL_5 + Sequencer program control 5 + 0x74 + 32 + read-write + 0x803D0019 + 0x807F03FF + + + CYCLES + Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles. + [9:0] + read-write + + + STROBE_A + Specifies value of eFUSE control signal strobe_a + [16:16] + read-write + + + STROBE_B + Specifies value of eFUSEcontrol signal strobe_b + [17:17] + read-write + + + STROBE_C + Specifies value of eFUSE control signal strobe_c + [18:18] + read-write + + + STROBE_D + Specifies value of eFUSE control signal strobe_d + [19:19] + read-write + + + STROBE_E + Specifies value of eFUSE control signal strobe_e + [20:20] + read-write + + + STROBE_F + Specifies value of eFUSE control signal strobe_f + [21:21] + read-write + + + STROBE_G + Specifies value of eFUSE control signal strobe_g + [22:22] + read-write + + + DONE + When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0. + [31:31] + read-write + + + + + + + HSIOM + High Speed IO Matrix (HSIOM) + 0x40300000 + + 0 + 16384 + registers + + + + 33 + 16 + PRT[%s] + HSIOM port registers + 0x00000000 + + PORT_SEL0 + Port selection 0 + 0x0 + 32 + read-write + 0x0 + 0x1F1F1F1F + + + IO0_SEL + Selects the peripheral connections of Pin 0. Note that available connectivity options vary depending on the device, port and the pin. See the device Datasheet for a list of peripheral connections available at each pin. + [4:0] + read-write + + + GPIO + GPIO controls 'out' + 0 + + + GPIO_DSI + GPIO controls 'out', DSI controls 'output enable' + 1 + + + DSI_DSI + DSI controls 'out' and 'output enable' + 2 + + + DSI_GPIO + DSI controls 'out', GPIO controls 'output enable' + 3 + + + AMUXA + Analog mux bus A + 4 + + + AMUXB + Analog mux bus B + 5 + + + AMUXA_DSI + Analog mux bus A, DSI control + 6 + + + AMUXB_DSI + Analog mux bus B, DSI control + 7 + + + ACT_0 + Active functionality 0 + 8 + + + ACT_1 + Active functionality 1 + 9 + + + ACT_2 + Active functionality 2 + 10 + + + ACT_3 + Active functionality 3 + 11 + + + DS_0 + DeepSleep functionality 0 + 12 + + + DS_1 + DeepSleep functionality 1 + 13 + + + DS_2 + DeepSleep functionality 2 + 14 + + + DS_3 + DeepSleep functionality 3 + 15 + + + ACT_4 + Active functionality 4 + 16 + + + ACT_5 + Active functionality 5 + 17 + + + ACT_6 + Active functionality 6 + 18 + + + ACT_7 + Active functionality 7 + 19 + + + ACT_8 + Active functionality 8 + 20 + + + ACT_9 + Active functionality 9 + 21 + + + ACT_10 + Active functionality 10 + 22 + + + ACT_11 + Active functionality 11 + 23 + + + ACT_12 + Active functionality 12 + 24 + + + ACT_13 + Active functionality 13 + 25 + + + ACT_14 + Active functionality 14 + 26 + + + ACT_15 + Active functionality 15 + 27 + + + DS_4 + DeepSleep functionality 4 + 28 + + + DS_5 + DeepSleep functionality 5 + 29 + + + DS_6 + DeepSleep functionality 6 + 30 + + + DS_7 + DeepSleep functionality 7 + 31 + + + + + IO1_SEL + Selects the peripheral connections of Pin 1. + [12:8] + read-write + + + IO2_SEL + Selects the peripheral connections of Pin 2. + [20:16] + read-write + + + IO3_SEL + Selects the peripheral connections of Pin 3. + [28:24] + read-write + + + + + PORT_SEL1 + Port selection 1 + 0x4 + 32 + read-write + 0x0 + 0x1F1F1F1F + + + IO4_SEL + Selects the peripheral connections of Pin 4. See PORT_SEL0 for connection details. + [4:0] + read-write + + + IO5_SEL + Selects the peripheral connections of Pin 4. + [12:8] + read-write + + + IO6_SEL + Selects the peripheral connections of Pin 5. + [20:16] + read-write + + + IO7_SEL + Selects the peripheral connections of Pin 6. + [28:24] + read-write + + + + + + 64 + 4 + AMUX_SPLIT_CTL[%s] + AMUX splitter cell control + 0x2000 + 32 + read-write + 0x0 + 0x77 + + + SWITCH_AA_SL + T-switch control for Left AMUXBUSA switch: +'0': switch open. +'1': switch closed. + [0:0] + read-write + + + SWITCH_AA_SR + T-switch control for Right AMUXBUSA switch: +'0': switch open. +'1': switch closed. + [1:1] + read-write + + + SWITCH_AA_S0 + T-switch control for AMUXBUSA vssa/ground switch: +'0': switch open. +'1': switch closed. + [2:2] + read-write + + + SWITCH_BB_SL + T-switch control for Left AMUXBUSB switch. + [4:4] + read-write + + + SWITCH_BB_SR + T-switch control for Right AMUXBUSB switch. + [5:5] + read-write + + + SWITCH_BB_S0 + T-switch control for AMUXBUSB vssa/ground switch. + [6:6] + read-write + + + + + MONITOR_CTL_0 + Power/Ground Monitor cell control 0 + 0x2200 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MONITOR_EN + control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: +'0': switch open. +'1': switch closed. + [31:0] + read-write + + + + + MONITOR_CTL_1 + Power/Ground Monitor cell control 1 + 0x2204 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MONITOR_EN + control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: +'0': switch open. +'1': switch closed. + [31:0] + read-write + + + + + MONITOR_CTL_2 + Power/Ground Monitor cell control 2 + 0x2208 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MONITOR_EN + control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: +'0': switch open. +'1': switch closed. + [31:0] + read-write + + + + + MONITOR_CTL_3 + Power/Ground Monitor cell control 3 + 0x220C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MONITOR_EN + control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed: +'0': switch open. +'1': switch closed. + [31:0] + read-write + + + + + ALT_JTAG_EN + Alternate JTAG IF selection register + 0x2240 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLE + Provides the selection for alternate JTAG IF connectivity. +0: Primary JTAG interface is selected +1: Secondary (alternate) JTAG interface is selected. + +This connectivity works ONLY in ACTIVE mode. + [31:31] + read-write + + + + + + + GPIO + GPIO port control/configuration + 0x40310000 + + 0 + 65536 + registers + + + + 33 + 128 + PRT[%s] + GPIO port registers + 0x00000000 + + OUT + Port output data register + 0x0 + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO output data for pin 0 +'0': Output state set to '0' +'1': Output state set to '1' + [0:0] + read-write + + + OUT1 + IO output data for pin 1 + [1:1] + read-write + + + OUT2 + IO output data for pin 2 + [2:2] + read-write + + + OUT3 + IO output data for pin 3 + [3:3] + read-write + + + OUT4 + IO output data for pin 4 + [4:4] + read-write + + + OUT5 + IO output data for pin 5 + [5:5] + read-write + + + OUT6 + IO output data for pin 6 + [6:6] + read-write + + + OUT7 + IO output data for pin 7 + [7:7] + read-write + + + + + OUT_CLR + Port output data clear register + 0x4 + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO clear output for pin 0: +'0': Output state not affected. +'1': Output state set to '0'. + [0:0] + read-write + + + OUT1 + IO clear output for pin 1 + [1:1] + read-write + + + OUT2 + IO clear output for pin 2 + [2:2] + read-write + + + OUT3 + IO clear output for pin 3 + [3:3] + read-write + + + OUT4 + IO clear output for pin 4 + [4:4] + read-write + + + OUT5 + IO clear output for pin 5 + [5:5] + read-write + + + OUT6 + IO clear output for pin 6 + [6:6] + read-write + + + OUT7 + IO clear output for pin 7 + [7:7] + read-write + + + + + OUT_SET + Port output data set register + 0x8 + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO set output for pin 0: +'0': Output state not affected. +'1': Output state set to '1'. + [0:0] + read-write + + + OUT1 + IO set output for pin 1 + [1:1] + read-write + + + OUT2 + IO set output for pin 2 + [2:2] + read-write + + + OUT3 + IO set output for pin 3 + [3:3] + read-write + + + OUT4 + IO set output for pin 4 + [4:4] + read-write + + + OUT5 + IO set output for pin 5 + [5:5] + read-write + + + OUT6 + IO set output for pin 6 + [6:6] + read-write + + + OUT7 + IO set output for pin 7 + [7:7] + read-write + + + + + OUT_INV + Port output data invert register + 0xC + 32 + read-write + 0x0 + 0xFF + + + OUT0 + IO invert output for pin 0: +'0': Output state not affected. +'1': Output state inverted ('0' => '1', '1' => '0'). + [0:0] + read-write + + + OUT1 + IO invert output for pin 1 + [1:1] + read-write + + + OUT2 + IO invert output for pin 2 + [2:2] + read-write + + + OUT3 + IO invert output for pin 3 + [3:3] + read-write + + + OUT4 + IO invert output for pin 4 + [4:4] + read-write + + + OUT5 + IO invert output for pin 5 + [5:5] + read-write + + + OUT6 + IO invert output for pin 6 + [6:6] + read-write + + + OUT7 + IO invert output for pin 7 + [7:7] + read-write + + + + + IN + Port input state register + 0x10 + 32 + read-only + 0x0 + 0x1FF + + + IN0 + IO pin state for pin 0 +'0': Low logic level present on pin. +'1': High logic level present on pin. +On reset assertion , IN register will get reset. The Pad value takes 2 clock cycles to be reflected into IN Register. It's value then depends on the external pin value. + [0:0] + read-only + + + IN1 + IO pin state for pin 1 + [1:1] + read-only + + + IN2 + IO pin state for pin 2 + [2:2] + read-only + + + IN3 + IO pin state for pin 3 + [3:3] + read-only + + + IN4 + IO pin state for pin 4 + [4:4] + read-only + + + IN5 + IO pin state for pin 5 + [5:5] + read-only + + + IN6 + IO pin state for pin 6 + [6:6] + read-only + + + IN7 + IO pin state for pin 7 + [7:7] + read-only + + + FLT_IN + Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register. + [8:8] + read-only + + + + + INTR + Port interrupt status register + 0x14 + 32 + read-write + 0x0 + 0x1FF01FF + + + EDGE0 + Edge detect for IO pin 0 +'0': No edge was detected on pin. +'1': An edge was detected on pin. + [0:0] + read-write + + + EDGE1 + Edge detect for IO pin 1 + [1:1] + read-write + + + EDGE2 + Edge detect for IO pin 2 + [2:2] + read-write + + + EDGE3 + Edge detect for IO pin 3 + [3:3] + read-write + + + EDGE4 + Edge detect for IO pin 4 + [4:4] + read-write + + + EDGE5 + Edge detect for IO pin 5 + [5:5] + read-write + + + EDGE6 + Edge detect for IO pin 6 + [6:6] + read-write + + + EDGE7 + Edge detect for IO pin 7 + [7:7] + read-write + + + FLT_EDGE + Edge detected on filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-write + + + IN_IN0 + IO pin state for pin 0 + [16:16] + read-only + + + IN_IN1 + IO pin state for pin 1 + [17:17] + read-only + + + IN_IN2 + IO pin state for pin 2 + [18:18] + read-only + + + IN_IN3 + IO pin state for pin 3 + [19:19] + read-only + + + IN_IN4 + IO pin state for pin 4 + [20:20] + read-only + + + IN_IN5 + IO pin state for pin 5 + [21:21] + read-only + + + IN_IN6 + IO pin state for pin 6 + [22:22] + read-only + + + IN_IN7 + IO pin state for pin 7 + [23:23] + read-only + + + FLT_IN_IN + Filtered pin state for pin selected by INTR_CFG.FLT_SEL + [24:24] + read-only + + + + + INTR_MASK + Port interrupt mask register + 0x18 + 32 + read-write + 0x0 + 0x1FF + + + EDGE0 + Masks edge interrupt on IO pin 0 +'0': Pin interrupt forwarding disabled +'1': Pin interrupt forwarding enabled + [0:0] + read-write + + + EDGE1 + Masks edge interrupt on IO pin 1 + [1:1] + read-write + + + EDGE2 + Masks edge interrupt on IO pin 2 + [2:2] + read-write + + + EDGE3 + Masks edge interrupt on IO pin 3 + [3:3] + read-write + + + EDGE4 + Masks edge interrupt on IO pin 4 + [4:4] + read-write + + + EDGE5 + Masks edge interrupt on IO pin 5 + [5:5] + read-write + + + EDGE6 + Masks edge interrupt on IO pin 6 + [6:6] + read-write + + + EDGE7 + Masks edge interrupt on IO pin 7 + [7:7] + read-write + + + FLT_EDGE + Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-write + + + + + INTR_MASKED + Port interrupt masked status register + 0x1C + 32 + read-only + 0x0 + 0x1FF + + + EDGE0 + Edge detected AND masked on IO pin 0 +'0': Interrupt was not forwarded to CPU +'1': Interrupt occurred and was forwarded to CPU + [0:0] + read-only + + + EDGE1 + Edge detected and masked on IO pin 1 + [1:1] + read-only + + + EDGE2 + Edge detected and masked on IO pin 2 + [2:2] + read-only + + + EDGE3 + Edge detected and masked on IO pin 3 + [3:3] + read-only + + + EDGE4 + Edge detected and masked on IO pin 4 + [4:4] + read-only + + + EDGE5 + Edge detected and masked on IO pin 5 + [5:5] + read-only + + + EDGE6 + Edge detected and masked on IO pin 6 + [6:6] + read-only + + + EDGE7 + Edge detected and masked on IO pin 7 + [7:7] + read-only + + + FLT_EDGE + Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-only + + + + + INTR_SET + Port interrupt set register + 0x20 + 32 + read-write + 0x0 + 0x1FF + + + EDGE0 + Sets edge detect interrupt for IO pin 0 +'0': Interrupt state not affected +'1': Interrupt set + [0:0] + read-write + + + EDGE1 + Sets edge detect interrupt for IO pin 1 + [1:1] + read-write + + + EDGE2 + Sets edge detect interrupt for IO pin 2 + [2:2] + read-write + + + EDGE3 + Sets edge detect interrupt for IO pin 3 + [3:3] + read-write + + + EDGE4 + Sets edge detect interrupt for IO pin 4 + [4:4] + read-write + + + EDGE5 + Sets edge detect interrupt for IO pin 5 + [5:5] + read-write + + + EDGE6 + Sets edge detect interrupt for IO pin 6 + [6:6] + read-write + + + EDGE7 + Sets edge detect interrupt for IO pin 7 + [7:7] + read-write + + + FLT_EDGE + Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL + [8:8] + read-write + + + + + INTR_CFG + Port interrupt configuration register + 0x40 + 32 + read-write + 0x0 + 0x1FFFFF + + + EDGE0_SEL + Sets which edge will trigger an IRQ for IO pin 0 + [1:0] + read-write + + + DISABLE + Disabled + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + EDGE1_SEL + Sets which edge will trigger an IRQ for IO pin 1 + [3:2] + read-write + + + EDGE2_SEL + Sets which edge will trigger an IRQ for IO pin 2 + [5:4] + read-write + + + EDGE3_SEL + Sets which edge will trigger an IRQ for IO pin 3 + [7:6] + read-write + + + EDGE4_SEL + Sets which edge will trigger an IRQ for IO pin 4 + [9:8] + read-write + + + EDGE5_SEL + Sets which edge will trigger an IRQ for IO pin 5 + [11:10] + read-write + + + EDGE6_SEL + Sets which edge will trigger an IRQ for IO pin 6 + [13:12] + read-write + + + EDGE7_SEL + Sets which edge will trigger an IRQ for IO pin 7 + [15:14] + read-write + + + FLT_EDGE_SEL + Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL + [17:16] + read-write + + + DISABLE + Disabled + 0 + + + RISING + Rising edge + 1 + + + FALLING + Falling edge + 2 + + + BOTH + Both rising and falling edges + 3 + + + + + FLT_SEL + Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt. + [20:18] + read-write + + + + + CFG + Port configuration register + 0x44 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DRIVE_MODE0 + The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. +Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. +Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). +Note: D_OUT, D_OUT_EN are pins of GPIO cell. + [2:0] + read-write + + + HIGHZ + Output buffer is off creating a high impedance input +D_OUT = '0': High Impedance +D_OUT = '1': High Impedance + 0 + + + RSVD + N/A + 1 + + + PULLUP + Resistive pull up + 2 + + + PULLDOWN + Resistive pull down + 3 + + + OD_DRIVESLOW + Open drain, drives low + 4 + + + OD_DRIVESHIGH + Open drain, drives high + 5 + + + STRONG + Strong D_OUTput buffer + 6 + + + PULLUP_DOWN + Pull up or pull down + 7 + + + + + IN_EN0 + Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. +'0': Input buffer disabled +'1': Input buffer enabled + [3:3] + read-write + + + DRIVE_MODE1 + The GPIO drive mode for IO pin 1. Resistive pull-up and pull-down is selected in the drive mode. +Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. +Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). +Note: D_OUT, D_OUT_EN are pins of GPIO cell. + [6:4] + read-write + + + HIGHZ + Output buffer is off creating a high impedance input +D_OUT = '0': High Impedance +D_OUT = '1': High Impedance + 0 + + + RSVD + N/A + 1 + + + PULLUP + Resistive pull up + 2 + + + PULLDOWN + Resistive pull down + 3 + + + OD_DRIVESLOW + Open drain, drives low + 4 + + + OD_DRIVESHIGH + Open drain, drives high + 5 + + + STRONG + Strong D_OUTput buffer + 6 + + + PULLUP_DOWN + Pull up or pull down + 7 + + + + + IN_EN1 + Enables the input buffer for IO pin 1 + [7:7] + read-write + + + DRIVE_MODE2 + The GPIO drive mode for IO pin 2. Resistive pull-up and pull-down is selected in the drive mode. +Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. +Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). +Note: D_OUT, D_OUT_EN are pins of GPIO cell. + [10:8] + read-write + + + HIGHZ + Output buffer is off creating a high impedance input +D_OUT = '0': High Impedance +D_OUT = '1': High Impedance + 0 + + + RSVD + N/A + 1 + + + PULLUP + Resistive pull up + 2 + + + PULLDOWN + Resistive pull down + 3 + + + OD_DRIVESLOW + Open drain, drives low + 4 + + + OD_DRIVESHIGH + Open drain, drives high + 5 + + + STRONG + Strong D_OUTput buffer + 6 + + + PULLUP_DOWN + Pull up or pull down + 7 + + + + + IN_EN2 + Enables the input buffer for IO pin 2 + [11:11] + read-write + + + DRIVE_MODE3 + The GPIO drive mode for IO pin 3. Resistive pull-up and pull-down is selected in the drive mode. +Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. +Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). +Note: D_OUT, D_OUT_EN are pins of GPIO cell. + [14:12] + read-write + + + HIGHZ + Output buffer is off creating a high impedance input +D_OUT = '0': High Impedance +D_OUT = '1': High Impedance + 0 + + + RSVD + N/A + 1 + + + PULLUP + Resistive pull up + 2 + + + PULLDOWN + Resistive pull down + 3 + + + OD_DRIVESLOW + Open drain, drives low + 4 + + + OD_DRIVESHIGH + Open drain, drives high + 5 + + + STRONG + Strong D_OUTput buffer + 6 + + + PULLUP_DOWN + Pull up or pull down + 7 + + + + + IN_EN3 + Enables the input buffer for IO pin 3 + [15:15] + read-write + + + DRIVE_MODE4 + The GPIO drive mode for IO pin 4. Resistive pull-up and pull-down is selected in the drive mode. +Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. +Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). +Note: D_OUT, D_OUT_EN are pins of GPIO cell. + [18:16] + read-write + + + HIGHZ + Output buffer is off creating a high impedance input +D_OUT = '0': High Impedance +D_OUT = '1': High Impedance + 0 + + + RSVD + N/A + 1 + + + PULLUP + Resistive pull up + 2 + + + PULLDOWN + Resistive pull down + 3 + + + OD_DRIVESLOW + Open drain, drives low + 4 + + + OD_DRIVESHIGH + Open drain, drives high + 5 + + + STRONG + Strong D_OUTput buffer + 6 + + + PULLUP_DOWN + Pull up or pull down + 7 + + + + + IN_EN4 + Enables the input buffer for IO pin 4 + [19:19] + read-write + + + DRIVE_MODE5 + The GPIO drive mode for IO pin 5. Resistive pull-up and pull-down is selected in the drive mode. +Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. +Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). +Note: D_OUT, D_OUT_EN are pins of GPIO cell. + [22:20] + read-write + + + HIGHZ + Output buffer is off creating a high impedance input +D_OUT = '0': High Impedance +D_OUT = '1': High Impedance + 0 + + + RSVD + N/A + 1 + + + PULLUP + Resistive pull up + 2 + + + PULLDOWN + Resistive pull down + 3 + + + OD_DRIVESLOW + Open drain, drives low + 4 + + + OD_DRIVESHIGH + Open drain, drives high + 5 + + + STRONG + Strong D_OUTput buffer + 6 + + + PULLUP_DOWN + Pull up or pull down + 7 + + + + + IN_EN5 + Enables the input buffer for IO pin 5 + [23:23] + read-write + + + DRIVE_MODE6 + The GPIO drive mode for IO pin 6. Resistive pull-up and pull-down is selected in the drive mode. +Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. +Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). +Note: D_OUT, D_OUT_EN are pins of GPIO cell. + [26:24] + read-write + + + HIGHZ + Output buffer is off creating a high impedance input +D_OUT = '0': High Impedance +D_OUT = '1': High Impedance + 0 + + + RSVD + N/A + 1 + + + PULLUP + Resistive pull up + 2 + + + PULLDOWN + Resistive pull down + 3 + + + OD_DRIVESLOW + Open drain, drives low + 4 + + + OD_DRIVESHIGH + Open drain, drives high + 5 + + + STRONG + Strong D_OUTput buffer + 6 + + + PULLUP_DOWN + Pull up or pull down + 7 + + + + + IN_EN6 + Enables the input buffer for IO pin 6 + [27:27] + read-write + + + DRIVE_MODE7 + The GPIO drive mode for IO pin 7. Resistive pull-up and pull-down is selected in the drive mode. +Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. +Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). +Note: D_OUT, D_OUT_EN are pins of GPIO cell. + [30:28] + read-write + + + HIGHZ + Output buffer is off creating a high impedance input +D_OUT = '0': High Impedance +D_OUT = '1': High Impedance + 0 + + + RSVD + N/A + 1 + + + PULLUP + Resistive pull up + 2 + + + PULLDOWN + Resistive pull down + 3 + + + OD_DRIVESLOW + Open drain, drives low + 4 + + + OD_DRIVESHIGH + Open drain, drives high + 5 + + + STRONG + Strong D_OUTput buffer + 6 + + + PULLUP_DOWN + Pull up or pull down + 7 + + + + + IN_EN7 + Enables the input buffer for IO pin 7 + [31:31] + read-write + + + + + CFG_IN + Port input buffer configuration register + 0x48 + 32 + read-write + 0x0 + 0xFF + + + VTRIP_SEL0_0 + Configures the pin 0 input buffer mode (trip points and hysteresis) + [0:0] + read-write + + + CMOS + PSoC6:: Input buffer compatible with CMOS and I2C interfaces +Traveo II: full encoding is shown in CFG_IN_AUTOLVL.VTRIP_SEL0_1 + 0 + + + TTL + PSoC6:: Input buffer compatible with TTL and MediaLB interfaces +Traveo II: full encoding is shown in CFG_IN_AUTOLVL.VTRIP_SEL0_1 + 1 + + + + + VTRIP_SEL1_0 + Configures the pin 1 input buffer mode (trip points and hysteresis) + [1:1] + read-write + + + VTRIP_SEL2_0 + Configures the pin 2 input buffer mode (trip points and hysteresis) + [2:2] + read-write + + + VTRIP_SEL3_0 + Configures the pin 3 input buffer mode (trip points and hysteresis) + [3:3] + read-write + + + VTRIP_SEL4_0 + Configures the pin 4 input buffer mode (trip points and hysteresis) + [4:4] + read-write + + + VTRIP_SEL5_0 + Configures the pin 5 input buffer mode (trip points and hysteresis) + [5:5] + read-write + + + VTRIP_SEL6_0 + Configures the pin 6 input buffer mode (trip points and hysteresis) + [6:6] + read-write + + + VTRIP_SEL7_0 + Configures the pin 7 input buffer mode (trip points and hysteresis) + [7:7] + read-write + + + + + CFG_OUT + Port output buffer configuration register + 0x4C + 32 + read-write + 0x0 + 0xFFFF00FF + + + SLOW0 + Enables slow slew rate for IO pin 0 +'0': Fast slew rate +'1': Slow slew rate + [0:0] + read-write + + + SLOW1 + Enables slow slew rate for IO pin 1 + [1:1] + read-write + + + SLOW2 + Enables slow slew rate for IO pin 2 + [2:2] + read-write + + + SLOW3 + Enables slow slew rate for IO pin 3 + [3:3] + read-write + + + SLOW4 + Enables slow slew rate for IO pin 4 + [4:4] + read-write + + + SLOW5 + Enables slow slew rate for IO pin 5 + [5:5] + read-write + + + SLOW6 + Enables slow slew rate for IO pin 6 + [6:6] + read-write + + + SLOW7 + Enables slow slew rate for IO pin 7 + [7:7] + read-write + + + DRIVE_SEL0 + Sets the GPIO drive strength for IO pin 0 + [17:16] + read-write + + + DRIVE_SEL_ZERO + Please refer to architecture TRM section I/O System + 0 + + + DRIVE_SEL_ONE + Please refer to architecture TRM section I/O System + 1 + + + DRIVE_SEL_TWO + Please refer to architecture TRM section I/O System + 2 + + + DRIVE_SEL_THREE + Please refer to architecture TRM section I/O System + 3 + + + + + DRIVE_SEL1 + Sets the GPIO drive strength for IO pin 1 + [19:18] + read-write + + + DRIVE_SEL2 + Sets the GPIO drive strength for IO pin 2 + [21:20] + read-write + + + DRIVE_SEL3 + Sets the GPIO drive strength for IO pin 3 + [23:22] + read-write + + + DRIVE_SEL4 + Sets the GPIO drive strength for IO pin 4 + [25:24] + read-write + + + DRIVE_SEL5 + Sets the GPIO drive strength for IO pin 5 + [27:26] + read-write + + + DRIVE_SEL6 + Sets the GPIO drive strength for IO pin 6 + [29:28] + read-write + + + DRIVE_SEL7 + Sets the GPIO drive strength for IO pin 7 + [31:30] + read-write + + + + + CFG_SIO + Port SIO configuration register + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VREG_EN01 + The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used. + [0:0] + read-write + + + IBUF_SEL01 + N/A + [1:1] + read-write + + + VTRIP_SEL01 + N/A + [2:2] + read-write + + + VREF_SEL01 + N/A + [4:3] + read-write + + + VOH_SEL01 + Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'): +0: input buffer functions as a CMOS input buffer. +1: input buffer functions as a LVTTL input buffer. +In differential input buffer mode (IBUF01_SEL = '1'): VTRIP_SEL=0: a) VREF_SEL=00, VOH_SEL=X -> Trip point=50 percent of vddio +b) VREF_SEL=01, VOH_SEL=000 -> Trip point=Vohref (buffered) +c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. +d) VREF_SEL=10/11, VOH_SEL=000 -> Trip point=Amuxbus_a/b (buffered) +e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. VTRIP_SEL=1: a) VREF_SEL=00, VOH_SEL=X -> Trip point=40 percent of vddio +b) VREF_SEL=01, VOH_SEL=000 -> Trip point=0.5*Vohref +c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip point=0.5*Amuxbus_a/b (buffered) +e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. + [7:5] + read-write + + + VREG_EN23 + N/A + [8:8] + read-write + + + IBUF_SEL23 + N/A + [9:9] + read-write + + + VTRIP_SEL23 + N/A + [10:10] + read-write + + + VREF_SEL23 + N/A + [12:11] + read-write + + + VOH_SEL23 + N/A + [15:13] + read-write + + + VREG_EN45 + N/A + [16:16] + read-write + + + IBUF_SEL45 + N/A + [17:17] + read-write + + + VTRIP_SEL45 + N/A + [18:18] + read-write + + + VREF_SEL45 + N/A + [20:19] + read-write + + + VOH_SEL45 + N/A + [23:21] + read-write + + + VREG_EN67 + N/A + [24:24] + read-write + + + IBUF_SEL67 + N/A + [25:25] + read-write + + + VTRIP_SEL67 + N/A + [26:26] + read-write + + + VREF_SEL67 + N/A + [28:27] + read-write + + + VOH_SEL67 + N/A + [31:29] + read-write + + + + + CFG_IN_AUTOLVL + Port input buffer AUTOLVL configuration register + 0x58 + 32 + read-write + 0x0 + 0xFF + + + VTRIP_SEL0_1 + Configures the input buffer mode (trip points and hysteresis) for GPIO upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. This field is used along with CFG_IN.VTRIP_SEL0_0 field as below: +{CFG_IN_AUTOLVL.VTRIP_SEL0_1,CFG_IN.VTRIP_SEL0_0}: +0,0: CMOS +0,1: TTL +1,0: input buffer is compatible with automotive. +1,1: input buffer is compatible with automotive. + [0:0] + read-write + + + CMOS_OR_TTL + Input buffer compatible with CMOS/TTL interfaces as described in CFG_IN.VTRIP_SEL0_0. + 0 + + + AUTO + Input buffer compatible with AUTO (elevated Vil) interfaces when used along with CFG_IN.VTRIP_SEL0_0. + 1 + + + + + VTRIP_SEL1_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [1:1] + read-write + + + VTRIP_SEL2_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [2:2] + read-write + + + VTRIP_SEL3_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [3:3] + read-write + + + VTRIP_SEL4_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [4:4] + read-write + + + VTRIP_SEL5_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [5:5] + read-write + + + VTRIP_SEL6_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [6:6] + read-write + + + VTRIP_SEL7_1 + Input buffer compatible with automotive (elevated Vil) interfaces. + [7:7] + read-write + + + + + + INTR_CAUSE0 + Interrupt port cause register 0 + 0x4000 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PRT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + INTR_CAUSE1 + Interrupt port cause register 1 + 0x4004 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + INTR_CAUSE2 + Interrupt port cause register 2 + 0x4008 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + INTR_CAUSE3 + Interrupt port cause register 3 + 0x400C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PORT_INT + Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. +'0': Port has no pending interrupt +'1': Port has pending interrupt + [31:0] + read-only + + + + + VDD_ACTIVE + Extern power supply detection register + 0x4010 + 32 + read-only + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Indicates presence or absence of VDDIO supplies (i.e. other than VDDD, VDDA) on the device (supplies are numbered 0..n-1). Note that VDDIO supplies have basic (crude) supply detectors only. If separate, robust, brown-out detection is desired on IO supplies, on-chip or off-chip analog resources need to provide it. For these bits to work reliable, the supply must be within valid spec range (per datasheet) or held at ground. Any in-between voltage has an undefined result. +'0': Supply is not present +'1': Supply is present + +When multiple VDDIO supplies are present, they will be assigned in alphanumeric ascending order to these bits during implementation. +For example 'vddusb, vddio_0, vddio_a, vbackup, vddio_r, vddio_1' are present then they will be assigned to these bits as below: +0: vbackup, +1: vddio_0, +2: vddio_1, +3: vddio_a, +4: vddio_r, +5: vddusb' + [15:0] + read-only + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-only + + + VDDD_ACTIVE + This bit indicates presence of the VDDD supply. This bit will always read-back 1. The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in certain test-modes to observe the brown-out detector status.) + [31:31] + read-only + + + + + VDD_INTR + Supply detection interrupt register + 0x4014 + 32 + read-write + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Supply state change detected. +'0': No change to supply detected +'1': Change to supply detected + [15:0] + read-write + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-write + + + VDDD_ACTIVE + The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'. + [31:31] + read-write + + + + + VDD_INTR_MASK + Supply detection interrupt mask register + 0x4018 + 32 + read-write + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Masks supply interrupt on VDDIO. +'0': VDDIO interrupt forwarding disabled +'1': VDDIO interrupt forwarding enabled + [15:0] + read-write + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-write + + + VDDD_ACTIVE + Same as VDDIO_ACTIVE for the digital supply VDDD. + [31:31] + read-write + + + + + VDD_INTR_MASKED + Supply detection interrupt masked register + 0x401C + 32 + read-only + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Supply transition detected AND masked +'0': Interrupt was not forwarded to CPU +'1': Interrupt occurred and was forwarded to CPU + [15:0] + read-only + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-only + + + VDDD_ACTIVE + Same as VDDIO_ACTIVE for the digital supply VDDD. + [31:31] + read-only + + + + + VDD_INTR_SET + Supply detection interrupt set register + 0x4020 + 32 + read-write + 0x0 + 0xC000FFFF + + + VDDIO_ACTIVE + Sets supply interrupt. +'0': Interrupt state not affected +'1': Interrupt set + [15:0] + read-write + + + VDDA_ACTIVE + Same as VDDIO_ACTIVE for the analog supply VDDA. + [30:30] + read-write + + + VDDD_ACTIVE + Same as VDDIO_ACTIVE for the digital supply VDDD. + [31:31] + read-write + + + + + + + SMARTIO + Programmable IO configuration + 0x40320000 + + 0 + 65536 + registers + + + + 18 + 256 + PRT[%s] + Programmable IO port registers + 0x00000000 + + CTL + Control register + 0x0 + 32 + read-write + 0x2001400 + 0x82001F00 + + + BYPASS + Bypass of the programmable IO, one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1', this field is used. When ENABLED is '0', this field is NOT used and SMARTIO fabric is always bypassed. +'0': No bypass (programmable SMARTIO fabric is exposed). +'1': Bypass (programmable SMARTIOIO fabric is hidden). + [7:0] + read-write + + + CLOCK_SRC + Clock ('clk_fabric') and reset ('rst_fabric_n') source selection: +'0': io_data_in[0]/'1'. +... +'7': io_data_in[7]/'1'. +'8': chip_data[0]/'1'. +... +'15': chip_data[7]/'1'. +'16': clk_smartio/rst_sys_act_n. Used for both Active functionality synchronous logic on 'clk_smartio'. This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. +'17': clk_smartio/rst_sys_dpslp_n. Used for both DeepSleep functionality synchronous logic on 'clk_smartio' (note that 'clk_smartio' is NOT available in DeepSleep and Hibernate power modes). This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. +'18': Same as '17'. Note that the M0S8 SMARTIO version used the Hibernate reset for this value, but the MXS40 SMARTIO version does not support Hibernate functionality. +'19': clk_lf/rst_lf_dpslp_n (note that 'clk_lf' is available in DeepSleep power mode). This selection is intended for synchronous operation on'clk_lf'. Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to other 'clk_lf' clocked elements. +'20'-'30': Clock source is constant '0'. Any of these clock sources should be selected when the IP is disabled to ensure low power consumption. +'31': asynchronous mode/'1'. Select this when clockless operation is configured. + +NOTE: Two positive edges of the selected clock are required for the block to be enabled (to deactivate reset). In asynchronous (clockless) mode clk_sys is used to enable the block, but is not available for clocking. + [12:8] + read-write + + + HLD_OVR + IO cell hold override functionality. In DeepSleep power mode, the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep output functionality on these IO pads. This field is used to control the hold override functionality from the SMARTIO: +'0': The HSIOM controls the IO cell hold override functionality ('hsiom_hld_ovr'). +'1': The SMARTIO controls the IO cel hold override functionality: +- In bypass mode (ENABLED is '0' or BYPASS[i] is '1'), the HSIOM control is used. +- In NON bypass mode (ENABLED is '1' and BYPASS[i] is '0'), the SMARTIO sets hold override to 'pwr_hld_ovr_hib' to enable SMARTIO functionality in DeepSleep power mode (but disables it in Hibernate or Stop power mode). + [24:24] + read-write + + + PIPELINE_EN + Enable for pipeline register: +'0': Disabled (register is bypassed). +'1': Enabled. + [25:25] + read-write + + + ENABLED + Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured: +'0': Disabled (signals are bypassed; behavior as if BYPASS is 0xFF). When disabled, the fabric (data unit and LUTs) reset is activated. + +If the IP is disabled: +- The PIPELINE_EN register field should be set to '1', to ensure low power consumption by preventing combinatorial loops. +- The CLOCK_SRC register field should be set to '20'-'30' (clock is constant '0'), to ensure low power consumption. + +'1': Enabled. Once enabled, it takes 3 'clk_fabric' clock cycles till the fabric reset is de-activated and the fabric becomes fully functional. This ensures that the IO pins' input synchronizer states are flushed when the fabric is fully functional. + [31:31] + read-write + + + + + SYNC_CTL + Synchronization control register + 0x10 + 32 + read-write + 0x0 + 0x0 + + + IO_SYNC_EN + Synchronization of the IO pin input signals to 'clk_fabric', one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i. +'0': No synchronization. +'1': Synchronization. + [7:0] + read-write + + + CHIP_SYNC_EN + Synchronization of the chip input signals to 'clk_fabric', one bit for each input: CHIP_SYNC_EN[i] is for input i. +'0': No synchronization. +'1': Synchronization. + [15:8] + read-write + + + + + 8 + 4 + LUT_SEL[%s] + LUT component input selection + 0x20 + 32 + read-write + 0x0 + 0x0 + + + LUT_TR0_SEL + LUT input signal 'tr0_in' source selection: +'0': Data unit output. +'1': LUT 1 output. +'2': LUT 2 output. +'3': LUT 3 output. +'4': LUT 4 output. +'5': LUT 5 output. +'6': LUT 6 output. +'7': LUT 7 output. +'8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). +'9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). +'10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). +'11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). +'12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). +'13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). +'14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). +'15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). + [3:0] + read-write + + + LUT_TR1_SEL + LUT input signal 'tr1_in' source selection: +'0': LUT 0 output. +'1': LUT 1 output. +'2': LUT 2 output. +'3': LUT 3 output. +'4': LUT 4 output. +'5': LUT 5 output. +'6': LUT 6 output. +'7': LUT 7 output. +'8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). +'9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). +'10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). +'11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). +'12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). +'13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). +'14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). +'15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). + [11:8] + read-write + + + LUT_TR2_SEL + LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL. + [19:16] + read-write + + + + + 8 + 4 + LUT_CTL[%s] + LUT component control register + 0x40 + 32 + read-write + 0x0 + 0x0 + + + LUT + LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg). + [7:0] + read-write + + + LUT_OPC + LUT opcode specifies the LUT operation: +'0': Combinatoral output, no feedback. + tr_out = LUT[{tr2_in, tr1_in, tr0_in}]. +'1': Combinatorial output, feedback. + tr_out = LUT[{lut_reg, tr1_in, tr0_in}]. +On clock: + lut_reg <= tr_in2. +'2': Sequential output, no feedback. + temp = LUT[{tr2_in, tr1_in, tr0_in}]. + tr_out = lut_reg. +On clock: + lut_reg <= temp. +'3': Register with asynchronous set and reset. + tr_out = lut_reg. + enable = (tr2_in ^ LUT[4]) | LUT[5]. + set = enable & (tr1_in ^ LUT[2]) & LUT[3]. + clr = enable & (tr0_in ^ LUT[0]) & LUT[1]. +Asynchronously (no clock required): + lut_reg <= if (clr) '0' else if (set) '1' + [9:8] + read-write + + + + + DU_SEL + Data unit component input selection + 0xC0 + 32 + read-write + 0x0 + 0x0 + + + DU_TR0_SEL + Data unit input signal 'tr0_in' source selection: +'0': Constant '0'. +'1': Constant '1'. +'2': Data unit output. +'10-3': LUT 7 - 0 outputs. +Otherwise: Undefined. + [3:0] + read-write + + + DU_TR1_SEL + Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL. + [11:8] + read-write + + + DU_TR2_SEL + Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL. + [19:16] + read-write + + + DU_DATA0_SEL + Data unit input data 'data0_in' source selection: +'0': Constant '0'. +'1': chip_data[7:0]. +'2': io_data_in[7:0]. +'3': DATA.DATA MMIO register field. + [25:24] + read-write + + + DU_DATA1_SEL + Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL. + [29:28] + read-write + + + + + DU_CTL + Data unit component control register + 0xC4 + 32 + read-write + 0x0 + 0x0 + + + DU_SIZE + Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g., if DU_SIZE is 7, the width is 8 bits. + [2:0] + read-write + + + DU_OPC + Data unit opcode specifies the data unit operation: +'1': INCR +'2': DECR +'3': INCR_WRAP +'4': DECR_WRAP +'5': INCR_DECR +'6': INCR_DECR_WRAP +'7': ROR +'8': SHR +'9': AND_OR +'10': SHR_MAJ3 +'11': SHR_EQL. +Otherwise: Undefined. + [11:8] + read-write + + + + + DATA + Data register + 0xF0 + 32 + read-write + 0x0 + 0x0 + + + DATA + Data unit input data source. + [7:0] + read-write + + + + + + + + EVTGEN0 + Event generator + EVTGEN + 0x403F0000 + + 0 + 4096 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLED + IP enable: +'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. +'1': Enabled. + [31:31] + read-write + + + DISABLED + N/A + 0 + + + ENABLED + N/A + 1 + + + + + + + COMP0_STATUS + Comparator structures comparator 0 status + 0x4 + 32 + read-only + 0x0 + 0xFFFF + + + COMP0_OUT + Active comparator 'comp0_out[]' outputs. + [15:0] + read-only + + + + + COMP1_STATUS + Comparator structures comparator 1 status + 0x8 + 32 + read-only + 0x0 + 0xFFFF + + + COMP1_OUT + DeepSleep comparator 'comp1_out_lf[]' outputs (synchronized from clk_lf to the IP clock). + [15:0] + read-only + + + + + COUNTER_STATUS + Counter status + 0x10 + 32 + read-only + 0x0 + 0x80000000 + + + VALID + Active counter validity: +'0': Invalid. +'1': Valid. + +The COUNTER register field INT32 is only valid when VALID is '1'. + +The COUNTER_STATUS and COUNTER registers are non-retention registers; i.e. the COUNTER_STATUS and COUNTER registers are reset during DeepSleep power mode. After entering the Active power mode, the Active counter is initialized with the DeepSleep counter. This initialization may take up to 1 clk_lf cycle. + [31:31] + read-only + + + + + COUNTER + Counter + 0x14 + 32 + read-only + 0x0 + 0x0 + + + INT32 + Active counter 'counter_int[31:0]' on clk_ref_div. + [31:0] + read-only + + + + + RATIO_CTL + Ratio control + 0x20 + 32 + read-write + 0x0 + 0xC0070000 + + + DYNAMIC_MODE + Weighted average calculation (only used when DYNAMIC is '1'): +'0': new RATIO value = (RATIO + measurement + 1) / 2. +'1': new RATIO value = (3*RATIO + measurement + 2) / 4. +'2': new RATIO value = (7*RATIO + measurement + 4) / 8. +'3': new RATIO value = (15*RATIO + measurement + 8) / 16. +'4': new RATIO value = (31*RATIO + measurement + 16) / 32. +'5': new RATIO value = (63*RATIO + measurement + 32) / 64. +'6': new RATIO value = (127*RATIO + measurement + 64) / 128. +'7': new RATIO value = (255*RATIO + measurement + 128) / 256. + +Note: 'measurement' (integer component only) is defined as: 256 * 'number of measured clk_ref_div cycles per clk_lf cycle'. The RATIO value (integer and fractional component) is defined as: 256*RATIO.INT16 + RATIO.FRAC8 (RATIO.INT16 = RATIO >> 8 and RATIO.FRAC8 = RATIO percent 256). + [18:16] + read-write + + + DYNAMIC + Specifies if RATIO_CTL.VALID and RATIO are under SW or HW control: +'0': SW control. +'1: HW control. Auto calibration is used to derive the RATIO value. HW measures the number of clk_ref_div cycles per clk_lf cycle. This measurement is combined with the current ratio value to calculate a new ratio value. + [30:30] + read-write + + + VALID + Ratio value valid: +'0': Invalid. +'1': Valid. + +The RATIO register fields INT16 and FRAC8 are only valid when VALID is '1'. + [31:31] + read-write + + + + + RATIO + Ratio + 0x24 + 32 + read-write + 0x0 + 0x0 + + + FRAC8 + Fractional component of ratio value. + [15:8] + read-write + + + INT16 + Integer component of ratio value. + [31:16] + read-write + + + + + REF_CLOCK_CTL + Reference clock control + 0x30 + 32 + read-write + 0x0 + 0xFF + + + INT_DIV + Divider control for clk_ref_div: +'0': Divide by 1. +... +'255': Divide by '256'. + +Fclk_ref_div = Fclk_ref / (INT_DIV + 1) + [7:0] + read-write + + + + + INTR + Interrupt + 0x700 + 32 + read-write + 0x0 + 0xFFFF + + + COMP0 + This interrupt cause field is activated (HW sets the field to '1') when a comparator 0 event is generated (Active counter 'counter_int[31:0]' becomes greater or equal to COMP0.INT[31:0]). + [15:0] + read-write + + + + + INTR_SET + Interrupt set + 0x704 + 32 + read-write + 0x0 + 0xFFFF + + + COMP0 + SW writes a '1' to this field to set the corresponding field in the INTR register. + [15:0] + read-write + + + + + INTR_MASK + Interrupt mask + 0x708 + 32 + read-write + 0x0 + 0xFFFF + + + COMP0 + Mask bit for corresponding field in the INTR register. + [15:0] + read-write + + + + + INTR_MASKED + Interrupt masked + 0x70C + 32 + read-only + 0x0 + 0xFFFF + + + COMP0 + Logical and of corresponding INTR and INTR_MASK fields. + [15:0] + read-only + + + + + INTR_DPSLP + DeepSleep interrupt + 0x710 + 32 + read-write + 0x0 + 0xFFFF + + + COMP1 + This interrupt cause field is activated (HW sets the field to '1') when a comparator 1 event is generated (DeepSleep counter 'counter_int_lf[31:0]' becomes greater or equal to COMP1.INT[31:0]). + [15:0] + read-write + + + + + INTR_DPSLP_SET + DeepSleep interrupt set + 0x714 + 32 + read-write + 0x0 + 0xFFFF + + + COMP1 + SW writes a '1' to this field to set the corresponding field in the INTR register. + [15:0] + read-write + + + + + INTR_DPSLP_MASK + DeepSleep interrupt mask + 0x718 + 32 + read-write + 0x0 + 0xFFFF + + + COMP1 + Mask bit for corresponding field in the INTR register. + [15:0] + read-write + + + + + INTR_DPSLP_MASKED + DeepSleep interrupt masked + 0x71C + 32 + read-only + 0x0 + 0xFFFF + + + COMP1 + Logical and of corresponding INTR and INTR_MASK fields. + [15:0] + read-only + + + + + 16 + 32 + COMP_STRUCT[%s] + Comparator structure + 0x00000800 + + COMP_CTL + Comparator control + 0x0 + 32 + read-write + 0x0 + 0x80010003 + + + COMP0_EN + Active comparator (COMP0) enable: +'0': Disabled. The comparator output 'comp0_out' is '0'. +'1': Enabled. + [0:0] + read-write + + + COMP1_EN + DeepSleep comparator (COMP1) enable: +'0': Disabled. The comparator output 'comp1_out_lf' is '0'. +'1': Enabled. + [1:1] + read-write + + + TR_OUT_EDGE + Specifies the 'tr_out' output trigger: +'0': The trigger is a level sensitive trigger. The Active comparator output ('comp0_out') is reflected on 'tr_out'. +'1': The trigger is an edge sensitive trigger. Activation of the Active comparator output (rising edge on 'comp0_out') results in a two cycle '1'/high pulse on 'tr_out'. + [16:16] + read-write + + + ENABLED + Comparator structure enable: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + COMP0 + Comparator 0 (Active functionality) + 0x4 + 32 + read-write + 0x0 + 0x0 + + + INT32 + This value is a 32-bit unsigned integer in the range [0, 2^32-1]. The comparator 'comp0_out' output is activated when the Active counter 'counter_int[31:0]' becomes greater or equal to COMP0. + +Note: SW must ensure that COMP_CTL.COMP_EN[0] is '0' when COMP0 is written. + [31:0] + read-write + + + + + COMP1 + Comparator 1 (DeepSleep functionality) + 0x8 + 32 + read-write + 0x0 + 0x0 + + + INT32 + This value is a 32-bit unsigned integer in the range [0, 2^32-1]. The comparator 'comp1_out_lf' output is activated when the DeepSleep counter 'counter_int_lf[31:0]' becomes greater or equal to COMP1. + +Note: SW must ensure that COMP_CTL.COMP_EN[1] is '0' when COMP1 is written. + [31:0] + read-write + + + + + + + + SMIF0 + Serial Memory Interface + SMIF + 0x40420000 + + 0 + 65536 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x503400 + 0x81F77FF1 + + + XIP_MODE + Mode of operation. + +Note: this field should only be changed when the IP is disabled or when STATUS.BUSY is '0' and SW should not be executing from the XIP interface or MMIO interface. + [0:0] + read-write + + + MMIO_MODE + '0': MMIO mode. Individual MMIO accesses to TX and RX FIFOs are used to generate a sequence of SPI transfers. This mode of operation allows for large flexibility in terms of the SPI transfers that can be generated. + 0 + + + XIP_MODE + '1': XIP mode. eXecute-In-Place mode: incoming read and write transfers over the AHB-Lite bus infrastructure are automatically translated in SPI transfers to read data from and write data to a device. This mode of operation allow for efficient device read and write operations. This mode is only supported in SPI_MODE. + 1 + + + + + CLOCK_IF_TX_SEL + Specifies device interface transmitter clock options. +'0': SDR. Memory interface clock 'spihb_clk_out' is divided (by 2) interface clock 'clk_if', memory interface data signals are driven by divided (by 2) interface clock 'clk_if' with different phase than 'spihb_clk_out'. +Results in driving memory interface data signals at falling 'spihb_clk_out' edge. +'1': DDR. Memory interface clock 'spihb_clk_out' is divided (by 2) inverted interface clock 'clk_if_inv', memory interface data signals are driven with interface clock 'clk_if'. +Results in driving memory interface data signals 90 degrees before rising and falling 'spihb_clk_out' edge. + [4:4] + read-write + + + DELAY_LINE_SEL + Specifies the delay line used for RX data capturing with +- output / feedback clock based capturing (when CLOCK_IF_RX_SEL = [0..3] and DELAY_TAP_ENABLED = 1) +- internal clock based capturing (when CLOCK_IF_RX_SEL = [4..5], INT_CLOCK_CAPTURE_PRESENT = 1 and DELAY_TAP_ENABLED = 1) +- RWDS based capturing (when CLOCK_IF_RX_SEL = [6..7]) + [7:5] + read-write + + + DELAY_TAP_ENABLED + Delay Line Tap Enable. +'0': Disabled. The delay line tap selections specified in registers DELAY_TAP_SEL or INT_CLOCK_DELAY_TAP_SEL0/1 are not used. The read data is directly captured by the RX data FIFO capture clock as specified by CLOCK_IF_RX_SEL and INT_CLOCK_CAPTURE_CYCLE. +'1': Enabled. The delay line tap selections specified in registers DELAY_TAP_SEL or INT_CLOCK_DELAY_TAP_SEL0/1 are used. Note that in RWDS based capture scheme (CLOCK_IF_RX_SEL = [6..7]), DELAY_TAP_ENABLED must be set to '1' as the RWDS based capture scheme requires to use the delay line. +If the output / feedback clock based capture scheme (CLOCK_IF_RX_SEL = [0..3]) or the RWDS based capture scheme (CLOCK_IF_RX_SEL = [6..7]) is selected then the register DELAY_TAP_SEL is used to select the capture clock. If the internal clock based capture scheme (CLOCK_IF_RX_SEL = [4..5] and INT_CLOCK_CAPTURE_PRESENT = 1) is selected then the registers INT_CLOCK_DELAY_TAP_SEL0/1 are used to select the capture clock per data bit line (read data is captured by the capture logic and afterwards transferred to the RX data FIFO). + [8:8] + read-write + + + INT_CLOCK_DL_ENABLED + Data Learning Enable for internal RX clock based on Data Learning Pattern. Only applies when CLOCK_IF_RX_SEL = [4..5] for selecting the internal clock based capture scheme and when DELAY_TAP_ENABLED = 1. +'0': Disabled. The delay line tap selections specified in registers INT_CLOCK_DELAY_TAP_SEL0/1 are not modified by HW. +'1': Enabled. The delay linle tap selections specified in registers INT_CLOCK_DELAY_TAP_SEL0/1 are modified by HW based on the data learning pattern. From all capture clock delay line taps producing a match between the expected data learning pattern in register DLP and the captured data learning pattern from the memory device the middle one is selected. + [9:9] + read-write + + + INT_CLOCK_CAPTURE_CYCLE + N/A + [11:10] + read-write + + + CLOCK_IF_RX_SEL + Specifies device interface receiver clock 'clk_if_rx' source. MISO data is captured on the rising edge of 'clk_if_rx' in SDR mode and on both edges of 'clk_if_rx' in DDR mode. +'0': 'spi_clk_out' (output clock) for SDR capturing with output clock +'1': !'spi_clk_out' (output clock) for DDR or SDR capturing with inverted output clock +'2': 'spi_clk_in' (feedback clock) for SDR capturing with feedback clock +'3': !'spi_clk_in' (feedback clock) for DDR or SDR capturing with inverted feedback clock +'4': 'clk_if_tx' (internal clock) for DDR or SDR capturing with internal clock +'5': 'clk_if_tx_inv' (internal clock) for DDR or SDR capturing with inverted internal clock +'6': 'sphb_rwds_inv' (RWDS / DQS strobe signal driven by memory device) for DDR capturing with RWDS / DQS in Hyperbus / Octal SPI mode or for SDR capturing with falling RWDS / DQS edge in Octal SPI mode +'7': 'sphb_rwds' (RWDS / DQS strobe signal driven by memory device) for SDR capturing with rising RWDS / DQS edge in Octal SPI mode + [14:12] + read-write + + + DESELECT_DELAY + Specifies the minimum duration of SPI deselection ('spi_select_out[]' is high/'1') in between SPI transfers: +'0': 1 memory interface clock cycle. +'1': 2 memory interface clock cycles. +'2': 3 memory interface clock cycles. +'3': 4 memory interface clock cycles. +'4': 5 memory interface clock cycles. +'5': 6 memory interface clock cycles. +'6': 7 memory interface clock cycles. +'7': 8 memory interface clock cycles. + +During SPI deselection, 'spi_select_out[]' are '1'/inactive, 'spi_data_out[]' are '1' and 'spi_clk_out' is '0'/inactive. + [18:16] + read-write + + + SELECT_SETUP_DELAY + Specifies the duration between 'spi_select_out[]' becomes low/'0') to 1st 'spi_clk_out' edge: +'0': 0 memory interface clock cycles + min. duration (see below). +'1': 1 memory interface clock cycle + min. duration (see below). +'2': 2 memory interface clock cycles + min. duration (see below). +'3': 3 memory interface clock cycles + min. duration (see below). + +In addition to the number of cycles selected here there is a min. duration of: +- 1 memory interface clock cycle (= 2 clk_if cycle) for SDR timing (CLOCK_IF_TX_SEL = 0) +- 1/4 memory interface clock cycle (= 1/2 clk_if cycle) for DDR timing (CLOCK_IF_TX_SEL = 1) + [21:20] + read-write + + + SELECT_HOLD_DELAY + Specifies the duration between last 'spi_clk_out' edge to 'spi_select_out[]' becomes high/'1'): +'0': 0 memory interface clock cycles + min. duration (see below). +'1': 1 memory interface clock cycle + min. duration (see below). +'2': 2 memory interface clock cycles + min. duration (see below). +'3': 3 memory interface clock cycles + min. duration (see below). + +In addition to the number of cycles selected here there is a min. duration of: +- 1/2 memory interface clock cycle (= 1 clk_if cycles) for SDR timing (CLOCK_IF_TX_SEL = 0) +- 1/4 memory interface clock cycle (= 1/2 clk_if cycle) for DDR timing (CLOCK_IF_TX_SEL = 1) + [23:22] + read-write + + + BLOCK + Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or to a full TX format/data FIFO. Note: the FIFOs can only be accessed in MMIO_MODE. + +This field is not used for test controller accesses. + [24:24] + read-write + + + BUS_ERROR + 0': Generate an AHB-Lite bus error. This option is useful when SW decides to use polling on STATUS.TR_BUSY to determine if a interface transfer is no longer busy (transfer is completed). This option adds SW complexity, but limits the number of AHB-Lite wait states (and limits ISR latency). + 0 + + + WAIT_STATES + 1': Introduce wait states. This setting potentially locks up the AHB-Lite infrastructure and may increase the CPU interrupt latency.This option is useful when SW performs TX/RX data FIFO accesses immediately after a command is setup using the TX format FIFO. This option has low SW complexity, but may result in a significant number of AHB-Lite wait states (and may increase ISR latency). + 1 + + + + + ENABLED + IP enable: +'0': Disabled. All non-retention registers are reset to their default value when the IP is disabled. When the IP is disabled, the XIP accesses produce AHB-Lite bus errors. +'1': Enabled. + +Notes: +- Before disabling the IP, SW should ensure that the IP is NOT busy (STATUS.BUSY is '0'), otherwise illegal interface transfers may occur. +- After CTL.ENABLED is set to 1 it takes up to 20 clk_if cycles until the memory interface registers are realeased from reset. + [31:31] + read-write + + + DISABLED + N/A + 0 + + + ENABLED + N/A + 1 + + + + + + + STATUS + Status + 0x4 + 32 + read-only + 0x0 + 0x80000000 + + + BUSY + AHB Cache, AXI interface, cryptography, XIP, device interface or any other logic busy in the IP: +'0': not busy +'1': busy +When BUSY is '0', the IP can be safely disabled without: +- the potential loss of transient write data. +- the potential risk of aborting an inflight SPI device interface transfer. +When BUSY is '0', the mode of operation (XIP_MODE or MMIO_MODE) can be safely changed. + [31:31] + read-only + + + + + INT_CLOCK_DELAY_TAP_SEL0 + Internal Clocking Delay Tap Select Register 0 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA_BIT0 + Delay line tap selection for data bit 0. +A value of 0 selects the receive capture clock source specified by CTL.CLOCK_IF_RX_SEL. All other values select a tap of the clock delay line. When the data learning pattern is enabled this value is set by HW. + [7:0] + read-write + + + DATA_BIT1 + Delay line tap selection for data bit 1. +See DATA_BIT0. + [15:8] + read-write + + + DATA_BIT2 + Delay line tap selection for data bit 2. +See DATA_BIT0. + [23:16] + read-write + + + DATA_BIT3 + Delay line tap selection for data bit 3. +See DATA_BIT0. + [31:24] + read-write + + + + + INT_CLOCK_DELAY_TAP_SEL1 + Internal Clocking Delay Tap Select Register 1 + 0x14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA_BIT4 + Delay line tap selection for data bit 4. +See DATA_BIT0. + [7:0] + read-write + + + DATA_BIT5 + Delay line tap selection for data bit 5. +See DATA_BIT0. + [15:8] + read-write + + + DATA_BIT6 + Delay line tap selection for data bit 6. +See DATA_BIT0. + [23:16] + read-write + + + DATA_BIT7 + Delay line tap selection for data bit 7. +See DATA_BIT0. + [31:24] + read-write + + + + + DLP + Data Learning Pattern + 0x18 + 32 + read-write + 0x0 + 0xFF + + + DLP + Data Learning Pattern + [7:0] + read-write + + + + + DL_STATUS0 + Data Learning Status Register 0 + 0x20 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA_BIT0 + Number of delay line taps for data bit 0 with correctly captured DLP in last read transaction. Legal range: [0, 255]. + [7:0] + read-only + + + DATA_BIT1 + Number of delay line taps for data bit 1 with correctly captured DLP in last read transaction. Legal range: [0, 255]. + [15:8] + read-only + + + DATA_BIT2 + Number of delay line taps for data bit 2 with correctly captured DLP in last read transaction. Legal range: [0, 255]. + [23:16] + read-only + + + DATA_BIT3 + Number of delay line taps for data bit 3 with correctly captured DLP in last read transaction. Legal range: [0, 255]. + [31:24] + read-only + + + + + DL_STATUS1 + Data Learning Status Register 1 + 0x24 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA_BIT4 + Number of delay line taps for data bit 4 with correctly captured DLP in last read transaction. Legal range: [0, 255]. + [7:0] + read-only + + + DATA_BIT5 + Number of delay line taps for data bit 5 with correctly captured DLP in last read transaction. Legal range: [0, 255]. + [15:8] + read-only + + + DATA_BIT6 + Number of delay line taps for data bit 6 with correctly captured DLP in last read transaction. Legal range: [0, 255]. + [23:16] + read-only + + + DATA_BIT7 + Number of delay line taps for data bit 7 with correctly captured DLP in last read transaction. Legal range: [0, 255]. + [31:24] + read-only + + + + + DELAY_TAP_SEL + Delay Tap Select Register + 0x30 + 32 + read-write + 0x1 + 0xFF + + + SEL + Delay line tap selection in output / feedback clock based capture scheme (CLOCK_IF_RX_SEL = [0..3]) and RWDS capture scheme (CLOCK_IF_RX_SEL = [6..7]). This is used to shift the strobe signal into the data eye. + +Note: DELAY_TAP_SEL must not be changed while STATUS.BUSY=1. + [7:0] + read-write + + + + + TX_CMD_FIFO_STATUS + Transmitter command FIFO status + 0x44 + 32 + read-only + 0x0 + 0xF + + + USED4 + Number of entries that are used in the TX command FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8]. + [3:0] + read-only + + + + + TX_CMD_FIFO_WR + Transmitter command FIFO write + 0x50 + 32 + write-only + 0x0 + 0x7FFFFFF + + + DATA27 + N/A + [26:0] + write-only + + + + + TX_DATA_FIFO_CTL + Transmitter data FIFO control + 0x80 + 32 + read-write + 0x0 + 0x7 + + + TX_TRIGGER_LEVEL + Determines when the TX data FIFO 'tr_tx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): +- Trigger is active when TX_DATA_FIFO_STATUS.USED <= TRIGGER_LEVEL. + [2:0] + read-write + + + + + TX_DATA_FIFO_STATUS + Transmitter data FIFO status + 0x84 + 32 + read-only + 0x0 + 0xF + + + USED4 + Number of entries that are used in the TX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8]. + [3:0] + read-only + + + + + TX_DATA_FIFO_WR1 + Transmitter data FIFO write + 0x90 + 32 + write-only + 0x0 + 0xFF + + + DATA0 + TX data (written to TX data FIFO). + [7:0] + write-only + + + + + TX_DATA_FIFO_WR2 + Transmitter data FIFO write + 0x94 + 32 + write-only + 0x0 + 0xFFFF + + + DATA0 + TX data (written to TX data FIFO, first byte). + [7:0] + write-only + + + DATA1 + TX data (written to TX data FIFO, second byte). + [15:8] + write-only + + + + + TX_DATA_FIFO_WR4 + Transmitter data FIFO write + 0x98 + 32 + write-only + 0x0 + 0xFFFFFFFF + + + DATA0 + TX data (written to TX data FIFO, first byte). + [7:0] + write-only + + + DATA1 + TX data (written to TX data FIFO, second byte). + [15:8] + write-only + + + DATA2 + TX data (written to TX data FIFO, third byte). + [23:16] + write-only + + + DATA3 + TX data (written to TX data FIFO, fourth byte). + [31:24] + write-only + + + + + TX_DATA_FIFO_WR1ODD + Transmitter data FIFO write + 0x9C + 32 + write-only + 0x0 + 0xFF + + + DATA0 + TX data (written to TX data FIFO). + [7:0] + write-only + + + + + RX_DATA_MMIO_FIFO_CTL + Receiver data MMIO FIFO control + 0xC0 + 32 + read-write + 0x0 + 0x7 + + + RX_TRIGGER_LEVEL + Determines when RX data FIFO 'tr_rx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): +- Trigger is active when RX_DATA_MMIO_FIFO_STATUS.USED > TRIGGER_LEVEL. + [2:0] + read-write + + + + + RX_DATA_MMIO_FIFO_STATUS + Receiver data MMIO FIFO status + 0xC4 + 32 + read-only + 0x0 + 0xF + + + USED4 + Number of entries that are used in the RX data MMIO FIFO (only available in MMIO_MODE). Legal range: [0, 8]. + [3:0] + read-only + + + + + RX_DATA_FIFO_STATUS + Receiver data FIFO status + 0xC8 + 32 + read-only + 0x0 + 0x11F + + + USED5 + Number of entries that are used in the RX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 16]. + [4:0] + read-only + + + RX_SR_USED + Data available in RX Shift Register, i.e. completely read from RX data FIFO (availabe in both XIP_MODE and MMIO_MODE). + [8:8] + read-only + + + + + RX_DATA_MMIO_FIFO_RD1 + Receiver data MMIO FIFO read + 0xD0 + 32 + read-only + 0x0 + 0xFF + + + DATA0 + RX data (read from RX data FIFO). + [7:0] + read-only + + + + + RX_DATA_MMIO_FIFO_RD2 + Receiver data MMIO FIFO read + 0xD4 + 32 + read-only + 0x0 + 0xFFFF + + + DATA0 + RX data (read from RX data FIFO, first byte). + [7:0] + read-only + + + DATA1 + RX data (read from RX data FIFO, second byte). + [15:8] + read-only + + + + + RX_DATA_MMIO_FIFO_RD4 + Receiver data MMIO FIFO read + 0xD8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA0 + RX data (read from RX data FIFO, first byte). + [7:0] + read-only + + + DATA1 + RX data (read from RX data FIFO, second byte). + [15:8] + read-only + + + DATA2 + RX data (read from RX data FIFO, third byte). + [23:16] + read-only + + + DATA3 + RX data (read from RX data FIFO, fourth byte). + [31:24] + read-only + + + + + RX_DATA_MMIO_FIFO_RD1_SILENT + Receiver data MMIO FIFO silent read + 0xE0 + 32 + read-only + 0x0 + 0xFF + + + DATA0 + RX data (read from RX data FIFO). + [7:0] + read-only + + + + + SLOW_CA_CTL + Slow cache control + 0x100 + 32 + read-write + 0xC0000000 + 0xC3030000 + + + WAY + this is for debug purpose only, and should be hidden to customers in technical document + [17:16] + read-write + + + SET_ADDR + this is for debug purpose only, and should be hidden to customers in technical document + [25:24] + read-write + + + PREF_EN + N/A + [30:30] + read-write + + + ENABLED + N/A + [31:31] + read-write + + + + + SLOW_CA_CMD + Slow cache command + 0x108 + 32 + read-write + 0x0 + 0x1 + + + INV + Cache and prefetch buffer invalidation. +SW writes a '1' to clear the cache and prefetch buffer. The cache's LRU structure is also reset to its default state. +Note, +A write access will invalidate the prefetch buffer automatically in hardware. +A write access should invalidate both fast and slow caches, by firmware. +Note, firmware should invalidate the cache and prefetch buffer only when STATUS.BUSY is '0'. + [0:0] + read-write + + + + + FAST_CA_CTL + Fast cache control + 0x180 + 32 + read-write + 0xC0000000 + 0xC3030000 + + + WAY + this is for debug purpose only, and should be hidden to customers in technical document + [17:16] + read-write + + + SET_ADDR + this is for debug purpose only, and should be hidden to customers in technical document + [25:24] + read-write + + + PREF_EN + N/A + [30:30] + read-write + + + ENABLED + N/A + [31:31] + read-write + + + + + FAST_CA_CMD + Fast cache command + 0x188 + 32 + read-write + 0x0 + 0x1 + + + INV + See SLOW_CA_CMD.INV. + [0:0] + read-write + + + + + CRYPTO_CMD + Cryptography Command + 0x200 + 32 + read-write + 0x0 + 0x1 + + + START + SW sets this field to '1' to start a AES-128 forward block cipher operation (on the address in CRYPTO_ADDR). HW sets this field to '0' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRYPTO_RESULT0, ..., CRYPTO_RESULT3. + +The operation takes roughly 13 clk_mem clock cycles. + +Note: An operation can only be started in MMIO_MODE. + [0:0] + read-write + + + + + CRYPTO_INPUT0 + Cryptography input 0 + 0x220 + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[31:0] = CRYPTO_INPUT0.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_INPUT1 + Cryptography input 1 + 0x224 + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[63:32] = CRYPTO_INPUT1.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_INPUT2 + Cryptography input 2 + 0x228 + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[95:64] = CRYPTO_INPUT2.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_INPUT3 + Cryptography input 3 + 0x22C + 32 + read-write + 0x0 + 0x0 + + + INPUT + Four Bytes of the plaintext PT[127:96] = CRYPTO_INPUT3.INPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_KEY0 + Cryptography key 0 + 0x240 + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[31:0] = CRYPTO_KEY0.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_KEY1 + Cryptography key 1 + 0x244 + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[63:32] = CRYPTO_KEY1.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_KEY2 + Cryptography key 2 + 0x248 + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[95:64] = CRYPTO_KEY2.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_KEY3 + Cryptography key 3 + 0x24C + 32 + write-only + 0x0 + 0x0 + + + KEY + Four Bytes of the key KEY[127:96] = CRYPTO_KEY3.KEY[31:0]. + [31:0] + write-only + + + + + CRYPTO_OUTPUT0 + Cryptography output 0 + 0x260 + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[31:0] = CRYPTO_OUTPUT0.OUTPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_OUTPUT1 + Cryptography output 1 + 0x264 + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[63:32] = CRYPTO_OUTPUT1.OUTPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_OUTPUT2 + Cryptography output 2 + 0x268 + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[95:64] = CRYPTO_OUTPUT2.OUTPUT[31:0]. + [31:0] + read-write + + + + + CRYPTO_OUTPUT3 + Cryptography output 3 + 0x26C + 32 + read-write + 0x0 + 0x0 + + + OUTPUT + Four Bytes of the ciphertext CT[127:96] = CRYPTO_OUTPUT3.OUTPUT[31:0]. + [31:0] + read-write + + + + + CRC_CMD + CRC Command + 0x300 + 32 + read-write + 0x0 + 0x3 + + + START + SW sets this field to '1' to start a CRC calculation over the 64 CRC input bits provided in CRC_INPUT0 and CRC_INPUT1, using 0xFF as CRC feedback. HW sets this field to '0' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRC_OUTPUT. + +A CRC calculation over 64 bits is done by writing the 64 input bits to CRC_INPUT0/1, performing a START command and reading the CRC result from CRC_OUTPUT. + +Note: An operation can only be started in MMIO_MODE. + [0:0] + read-write + + + CONTINUE + SW sets this field to '1' to continue a CRC calculation over the 64 CRC input bits provided in CRC_INPUT0 and CRC_INPUT1, using the current CRC output in CRC_OUTPUT as CRC feedback. HW sets this field to '0' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRC_OUTPUT. + +This command is used to perform a CRC calculation over more than 64 intput bits. For example a CRC calculation over 128 bits is done by writing the first 64 input bits to CRC_INPUT0/1, performing a START command, writing the second 64 input bits to CRC_INPUT0/1, performing a CONTINUE command and reading the CRC result from CRC_OUTPUT. For a CRC calculation of even more input bits the CONTINUE command has to be used multiple times. + +Note: An operation can only be started in MMIO_MODE. + [1:1] + read-write + + + + + CRC_INPUT0 + CRC input 0 + 0x320 + 32 + read-write + 0x0 + 0x0 + + + INPUT + Lower 32 input bits to the CRC engine. + [31:0] + read-write + + + + + CRC_INPUT1 + CRC input 1 + 0x324 + 32 + read-write + 0x0 + 0x0 + + + INPUT + Higher 32 input bits to the CRC engine. + [31:0] + read-write + + + + + CRC_OUTPUT + CRC output + 0x340 + 32 + read-only + 0xFF + 0xFF + + + CRC_OUTPUT + CRC engine output. + [7:0] + read-only + + + + + INTR + Interrupt register + 0x7C0 + 32 + read-write + 0x0 + 0x3113F + + + TR_TX_REQ + Activated in MMIO mode, when a TX data FIFO trigger 'tr_tx_req' is activated. + [0:0] + read-write + + + TR_RX_REQ + Activated in MMIO mode, when a RX data FIFO trigger 'tr_rx_req' is activated. + [1:1] + read-write + + + XIP_ALIGNMENT_ERROR + Activated in XIP mode, when: +- a write transfer is requested +and +- Dual-Quad SPI mode (selected device's ADDR_CTL.DIV2 is '1') is selected or +- Octal SPI DDR mode (selected device's DATA_CTL.DDR_MODE = '1' and DATA_CTL.WIDTH = '3') or Hyperbus mode (selected device's ADDR_CTL.SIZE3 = '7') is selected without memory write byte masking (selected device's WR_DUMMY_CTL.RWDS_EN = '0') +and +- the AHB-Lite / AXI bus transfer address is not a multiple of '2' or +- the requested AHB-Lite / AXI bus transfer size is NOT a multiple of '2'. + +Additionally, it is activated in XIP mode when the selected memory device does not support write byte masking (WR_DUMMY_CTL.RWDS_EN=0) and an AXI transfer occurs with not all of the AXI write strobes ('wstrb') enabled according to the transfer size ('assize'). + +Note: In dual-quad SPI mode (ADDR_CTL.DIV is '1'), each memory device contributes a 4-bit nibble for read data or write data. Write accesses are only possible if the request address is a multiple of 2 and the number of requested Bytes is a multiple of 2. Octal SPI DDR mode or Hyperbus mode are 16-bit word based protocols, writing single bytes is only possible when write byte masking is supported (via RWDS). Read accesses are always possible by extending the transfer size and / or aligning the address as needed and discarding the non-relevant byte(s). + [2:2] + read-write + + + TX_CMD_FIFO_OVERFLOW + Activated in MMIO mode, on an AHB-Lite write transfer to the TX command FIFO (TX_CMD_FIFO_WR) with not enough free entries available. + [3:3] + read-write + + + TX_DATA_FIFO_OVERFLOW + Activated in MMIO mode, on an AHB-Lite write transfer to the TX data FIFO (TX_DATA_FIFO_WR1, TX_DATA_FIFO_WR2, TX_DATA_FIFO_WR4) with not enough free entries available. + [4:4] + read-write + + + RX_DATA_MMIO_FIFO_UNDERFLOW + Activated in MMIO mode, on an AHB-Lite read transfer from the RX data MMIO FIFO (RX_DATA_MMIO_FIFO_RD1, RX_DATA_MMIO_FIFO_RD2, RX_DATA_MMIO_FIFO_RD4) with not enough entries available. Only activated for NON test bus controller transfers. + [5:5] + read-write + + + DL_FAIL + Data Learning Failed (no DLP match found on at least one of the input data lines when CTL.INT_CLOCK_DL_ENABLED = 1). + [8:8] + read-write + + + DL_WARNING + Data Learning Warning (for at least one input data line only 1 or 2 delay line taps resulted in a correct DLP capturing when CTL.INT_CLOCK_DL_ENABLED = 1). + [12:12] + read-write + + + CRC_ERROR + CRC Error. A read transfer data CRC check failed. + [16:16] + read-write + + + FS_STATUS_ERROR + Functional Safety Status Error. A read transfer Functional Safety Status check failed (see definition in DEVICE_ver2.RD_CRC_CTL.STATUS_CHECK_MASK and DEVICE_ver2.RD_CRC_CTL.STATUS_CHECK_MASK_POL). + [17:17] + read-write + + + + + INTR_SET + Interrupt set register + 0x7C4 + 32 + read-write + 0x0 + 0x3113F + + + TR_TX_REQ + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + TR_RX_REQ + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + XIP_ALIGNMENT_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + TX_CMD_FIFO_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + TX_DATA_FIFO_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + RX_DATA_MMIO_FIFO_UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + DL_FAIL + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + DL_WARNING + Write with '1' to set corresponding bit in interrupt request register. + [12:12] + read-write + + + CRC_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [16:16] + read-write + + + FS_STATUS_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [17:17] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x7C8 + 32 + read-write + 0x0 + 0x3113F + + + TR_TX_REQ + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + TR_RX_REQ + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + XIP_ALIGNMENT_ERROR + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + TX_CMD_FIFO_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + TX_DATA_FIFO_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + RX_DATA_MMIO_FIFO_UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + DL_FAIL + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + DL_WARNING + Mask bit for corresponding bit in interrupt request register. + [12:12] + read-write + + + CRC_ERROR + Mask bit for corresponding bit in interrupt request register. + [16:16] + read-write + + + FS_STATUS_ERROR + Mask bit for corresponding bit in interrupt request register. + [17:17] + read-write + + + + + INTR_MASKED + Interrupt masked register + 0x7CC + 32 + read-only + 0x0 + 0x3113F + + + TR_TX_REQ + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + TR_RX_REQ + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + XIP_ALIGNMENT_ERROR + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + TX_CMD_FIFO_OVERFLOW + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + TX_DATA_FIFO_OVERFLOW + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + RX_DATA_MMIO_FIFO_UNDERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + DL_FAIL + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + DL_WARNING + Logical and of corresponding request and mask bits. + [12:12] + read-only + + + CRC_ERROR + Logical and of corresponding request and mask bits. + [16:16] + read-only + + + FS_STATUS_ERROR + Logical and of corresponding request and mask bits. + [17:17] + read-only + + + + + 2 + 128 + DEVICE[%s] + Device (only used in XIP mode) + 0x00000800 + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0xFFFFF311 + + + WR_EN + Write enable: +'0': write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error. +'1': write transfers are allowed to this device. + [0:0] + read-write + + + CRYPTO_EN + Cryptography on read/write accesses: +'0': disabled. +'1': enabled. + [4:4] + read-write + + + DATA_SEL + Specifies the connection of the IP's data lines (spi_data[0], ..., spi_data[7]) to the device's data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7): +'0': spi_data[0] = IO0, spi_data[1] = IO1, ..., spi_data[7] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode. +'1': spi_data[2] = IO0, spi_data[3] = IO1. This value is only allowed for single and dual SPI modes. +'2': spi_data[4] = IO0, spi_data[5] = IO1, ..., spi_data[7] = IO3. This value is only allowed for single, dual, quad and dual quad SPI modes. In dual quad SPI mode, this value must be used for the second device. +'3': spi_data[6] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes. + [9:8] + read-write + + + MERGE_TIMEOUT + Continuous transfer merge timeout in clk_mem cycles. This limits the standby time of the memory interface, i.e. the time the memory device is selected but no data is transferred. +The counting of the merge timeout period is done in the XIP block using clk_mem cycles. It starts when the last TX or RX byte is transferred to or from the data FIFOs. +After this period the memory device is deselected. A later transfer, even from a continuous address, starts with the overhead phases (command, address, mode, dummy cycles). + [14:12] + read-write + + + _1_cycle + Timeout after 1 clk_mem cycle. +That means transfers will only be merged if the continuous transfer request is already available when the previous transfer is finished. + 0 + + + _16_cycles + Timeout after 2^4 = 16 clk_mem cycles. +At a clk_mem frequency of 200MHz this means 80ns. + 1 + + + _256_cycles + Timeout after 2^8 = 256 clk_mem cycles. +At a clk_mem frequency of 200MHz this means ~1.3us. + 2 + + + _4096_cycles + Timeout after 2^12 = 4096 clk_mem cycles. +At a clk_mem frequency of 200MHz this means ~20us. + 3 + + + _65536_cycles + Timeout after 2^16 = 65536 clk_mem cycles. +At a clk_mem frequency of 200MHz this means ~330us. + 4 + + + RSVD5 + N/A + 5 + + + RSVD6 + N/A + 6 + + + RSVD7 + N/A + 7 + + + + + MERGE_EN + Continous transfer merge enable: +'0': Disabled. No merging of transfers is done. Longest possible memory transfer is 16 Byte. +'1': Enabled. Merging of continous transfers is done. This skips the overhead (command, address, mode, dummy cycles) for a continuous (linear sequential) transfer. + [15:15] + read-write + + + TOTAL_TIMEOUT + Total transfer timeout in clk_mem cycles. +The counting of the total timout period is done in the XIP block using clk_mem cycles. It starts when the first command of a new (not merged) transaction is transferred to the TX command FIFO causing the interface logic to select the memory. +After this period the memory device is deselected. + +This feature is needed for RAM devices requiring refresh cycles. The value needs to be derived from the RAMs maximum transaction length time (tCMS) minus the time of transferring 2x16byte data block (data granularity of the XIP ports is 16byte, 1 16byte block transfer outstanding, another available for merging). If the result in negative, MERGE_EN must be set to '0'. + +Example: RAM device tCMS = 4us, interface clock frequency = 100MHz: total transfer timeout is 4us - 2x16x10ns = 3680ns. +With clk_mem frequency of 200MHz the TOTAL_TIMEOUT value is 3680/5 = 736. + +Note: In the unlikely case that the total transfer timeout is used (usually for RAM devices) while the page boundary crossing latency generation is enabled via RD_BOUND_CTL.PRESENT (usually for FLASH devices) the additional time needs to taken into account. + [29:16] + read-write + + + TOTAL_TIMEOUT_EN + Total transfer timeout enable. +'0': Disabled. There is no limit for the total transfer time. The continuous transfer merge timeout for limiting the idle time of the memory interface still applies. +'1': Enabled. The maximum total transfer time is limited by field TOTAL_TIMEOUT. + [30:30] + read-write + + + ENABLED + Device enable: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + ADDR + Device region base address + 0x8 + 32 + read-write + 0x0 + 0x0 + + + ADDR + Specifies the base address of the device region. If the device region is 2^m Bytes, ADDR MUST be a multiple of 2^m. + +In dual quad SPI data transfer, the two devices should have the same ADDR and MASK register settings. The device control information (ADDR_CTL, RD_CMD_CTL, etc.) are provided by the MMIO control registers of the device with the lowest index. + +The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24]. + [31:8] + read-write + + + + + MASK + Device region mask + 0xC + 32 + read-write + 0x0 + 0x0 + + + MASK + Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] & MASK[31:8]) == ADDR.ADDR[31:8]. + +The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff. + +Note: a transfer request that is not in any device region results in an AHB-Lite bus error. + [31:8] + read-write + + + + + ADDR_CTL + Address control + 0x20 + 32 + read-write + 0x0 + 0x107 + + + SIZE3 + N/A + [2:0] + read-write + + + DIV2 + Specifies if the AHB-Lite bus transfer address is divided by 2 or not: +'0': No divide by 2. +'1': Divide by 2. + +This functionality is used for read and write operation in XIP, dual quad SPI mode; i.e. this DIV2 must be set to '1' in dual quad SPI mode. +If DIV2 is set to '1', the memory does not support write masking (WR_DUMMY_CTL.RWDS_EN = '0'), and in this configuration a write transfer is requested and the write transfer request address is NOT a multiple of 2 or the requested number of Bytes to be written is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated. + [8:8] + read-write + + + + + RD_STATUS + Read status + 0x30 + 32 + read-only + 0x0 + 0xFF + + + FS_STATUS + Provides the Functional Safety Status Register of the memory received with the last read transfer. + [7:0] + read-only + + + + + RD_CMD_CTL + Read command control + 0x40 + 32 + read-write + 0x0 + 0xC007FFFF + + + CODE + Command byte code. + [7:0] + read-write + + + CODEH + Command high byte code. +This field specifies the most significant command byte, sent before the least significant command byte (CODE). It is only used when PRESENT2 = '2'. + [15:8] + read-write + + + WIDTH + Width of data transfer: +'0': 1 bit/cycle (single data transfer). +'1': 2 bits/cycle (dual data transfer). +'2': 4 bits/cycle (quad data transfer). +'3': 8 bits/cycle (octal data transfer). + [17:16] + read-write + + + DDR_MODE + Mode of transfer rate: +'0': SDR mode +'1': DDR mode + [18:18] + read-write + + + PRESENT2 + Presence of command field: +'0': not present +'1': present (1 Byte) +'2': present (2 Byte for OPI) + +Note: For octal data transfer with DDR mode (WIDTH='3' and DDR_MODE='1') either the HB protocol needs to be selected (by ADDR_CTL.SIZE3='7') or this field needs to be set to PRESENT2='2'. + [31:30] + read-write + + + + + RD_ADDR_CTL + Read address control + 0x44 + 32 + read-write + 0x0 + 0x70000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + DDR_MODE + Mode of transfer rate. + [18:18] + read-write + + + + + RD_MODE_CTL + Read mode control + 0x48 + 32 + read-write + 0x0 + 0xC007FFFF + + + CODE + Mode byte code. +Note: If a mode field is present (PRESENT='1') for octal data transfer with DDR mode (WIDTH='3' and DDR_MODE='1') the CODE is sent twice. + [7:0] + read-write + + + CODEH + Mode high byte code. +This field specifies the most significant mode byte, sent before the least significant mode byte (CODE). It is only used when PRESENT2 = '2'. + [15:8] + read-write + + + WIDTH + Width of transfer. + [17:16] + read-write + + + DDR_MODE + Mode of transfer rate. + [18:18] + read-write + + + PRESENT2 + Presence of mode field: +'0': not present +'1': present (1 Byte) +'2': present (2 Byte for OPI) + +Note: For octal data transfer with DDR mode (WIDTH='3' and DDR_MODE='1') this field needs to be set to PRESENT2='2' to generate a mode field (or to PRESENT2='0'). + [31:30] + read-write + + + + + RD_DUMMY_CTL + Read dummy control + 0x4C + 32 + read-write + 0x0 + 0xC000001F + + + SIZE5 + Number of dummy cycles (minus 1): +'0': 1 cycles +... +'31': 32 cycles. + +Note: this field specifies dummy cycles, not dummy Bytes! + [4:0] + read-write + + + PRESENT2 + Presence of dummy cycles: +'0': not present +'1': present +'2': present - Dummy cycles are doubled when RWDS refresh indicator is high during CA cycle. (HyperRAM variable latency mode) + +Notes: +- If CLOCK_IF_TX_SEL = '0' for transmitting command, address and mode fields in SDR mode (driving data between falling edges of spihb_clk_out) and the memory is driving read data in DDR mode (based on memory type and transmitted command), then there must be at least 1 latency / dummy cycle specified (RD_DUMMY_CTL.PRESENT2 > 0') to prevent controller and memory driving data signals at the same time. +The same is true for the theoretical (practically irrelevant case) of transmitting at least one of the command, address and mode fields in DDR mode but receiving data from the memory in SDR mode. + +- When using the RWDS / DQS based capturing scheme (CTL.CLK_IF_RX_SEL=[6,7]), then there is a minimum number of latency / dummy cycles required (RD_DUMMY_CTL.PRESENT2 > 0). For the Hyperbus protocol (DDR_CTL.SIZE3=7) at least 1 latency / dummy cycle has to be specified, for SPI with DQS capturing at least 2 latency / dummy cycles need to be selected (RD_DUMMY_CTL.SIZE5 > 0, exception see following note). + +- In case of falling edge RWDS / DQS capturing (CTL.CLOCK_IF_RX_SEL = '6') and SDR mode, SW should reduce the number of dummy cycles by 1 compared to the latency cycles required by the memory device. + +- For Hyperbus, set RD DUMMY_CTL.SIZE5=initial latency cycles-2 + [31:30] + read-write + + + + + RD_DATA_CTL + Read data control + 0x50 + 32 + read-write + 0x0 + 0x70000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + DDR_MODE + Mode of transfer rate. + [18:18] + read-write + + + + + RD_CRC_CTL + Read Bus CRC control + 0x54 + 32 + read-write + 0xFF00 + 0xDFFFFFFF + + + STATUS_CHECK_MASK + Specifies which of the Functional Safety Status field bits are checked. There is 1 mask bit for each Functional Safety Status bit. +'0': The associated Functional Safety Status bit is not checked. +'1': The associated Functional Safety Status bit is checked. If the received Funciontal Safety Status bit = Functional Safety Status Error Polarity (STATUS_ERROR_POLARITY), then a Functional Safety Status error interrupt and a XIP bus error response is generated. + [7:0] + read-write + + + STATUS_ERROR_POL + Specifies the polarity of the Functional Safety Status field bits. There is 1 polarity bit for each Functional Safety Status bit. +'0': The associated Functional Safety Status bit is active-low. +'1': The associated Functional Safety Status bit is active-high. + [15:8] + read-write + + + DATA_CRC_INPUT_SIZE + Number of input data bytes for CRC generation (minus 1), i.e. number of data bytes over which the data CRC field is generated (minus 1): +'0': 1 byte +... +'255': 256 bytes. + +Note: For octal data transfer with DDR mode (RD_DATA_CTL.WIDTH='3' and RD_DATA_CTL.DDR_MODE='1') the number of bytes for CRC generation must be even (i.e. DATA_CRC_INPUT_SIZE must be odd). + [23:16] + read-write + + + CMD_ADDR_CRC_WIDTH + Width of command / address CRC field. + [25:24] + read-write + + + CMD_ADDR_CRC_DDR_MODE + Mode of transfer rate of command / address CRC field. + [26:26] + read-write + + + CMD_ADDR_CRC_INPUT + Specifies which fields are included in the command / address CRC generation. +'0': The command / address CRC field is generated over the address and (if present) mode fields only. +'1': The command / address CRC field is generated over the command, address and (if present) mode fields. + [27:27] + read-write + + + DATA_CRC_CHECK + N/A + [28:28] + read-write + + + CMD_ADDR_CRC_PRESENT + Presence of command / address CRC field: +'0': not present +'1': present + +Note: For octal data transfer with DDR mode (RD_CRC_CTL.WIDTH='3' and RD_CRC_CTL.DDR_MODE='1') the command / address CRC byte is sent twice, otherwise the command / address CRC byte is only sent once. + [30:30] + read-write + + + DATA_CRC_PRESENT + Presence of data CRC field: +'0': not present +'1': present + +Note: Width and data transfer mode (SDR or DDR) of read data CRC fields are the same as for the associated read data fields, i.e. are specified by RD_DATA_CTL.WIDTH and RD_DATA_CTL.DDR_MODE. + [31:31] + read-write + + + + + RD_BOUND_CTL + Read boundary control + 0x58 + 32 + read-write + 0x100000 + 0x9033001F + + + SIZE5 + Number of base latency cycles (minus 1) used for calculating the number of fist page boundary crossing latency cycles: +'0': base_latency = 1 cycles +... +'31': base_latency = 32 cycles. + +The actual latency cycles when crossing the first page boundary depend on the start address of the transaction and is calculated as follows: +if ((page_size - base_latency) < Start_Addr & (sub_page_size - 1)) + { ((Start_Addr & (sub_page_size - 1)) - page_size + base_latency) } +else + { 0 } + [4:0] + read-write + + + SUB_PAGE_SIZE + Specifies the size of a memory sub page 'sub_page_size'. +'0': sub_page_size = 8 words = 16 bytes (default). +'1': sub_page_size = 16 words = 32 bytes. +'2': sub_page_size = 32 words = 64 bytes. +'3': sub_page_size = 64 words = 128 bytes. + [17:16] + read-write + + + SUB_PAGE_NR + Specifies the number of sub pages per page. +'0': 1 sub pages per page, i.e. page_size = sub_page_size +'1': 2 sub pages per page, i.e. page_size = 2 x sub_page_size +'2': 4 sub pages per page, i.e. page_size = 4 x sub_page_size +'3': 8 sub pages per page, i.e. page_size = 8 x sub_page_size + [21:20] + read-write + + + SUBSEQ_BOUND_EN + Enable subsequent page boundary latency cycles. +'0': Disabled. +The page crossing latency cycles are only generated when crossing the first page boundary (i.e. the first time when the SUB_PAGE_NRth sub page boundary is crossed, e.g. with 2 sub pages per page when the 2nd sub page boundary is crossed). +'1': Enabled. +The page crossing latency cycles are generated when crossing the first and subsequent page boundaries (i.e. every time when a SUB_PAGE_NRth sub page boundary is crossed, e.g. with 2 sub pages per page when the 2nd, 4th, 6th, ... sub page boundary is crossed). + +Note: This only applies when the number of base latency cycles (SIZE5+1) is greater than the size of a page (base_latency > page_size). + [28:28] + read-write + + + PRESENT + Presence of first page boundary latency cycles: +'0': not present +'1': present + [31:31] + read-write + + + + + WR_CMD_CTL + Write command control + 0x60 + 32 + read-write + 0x0 + 0xC007FFFF + + + CODE + Command byte code. + [7:0] + read-write + + + CODEH + Command high byte code. +This field specifies the most significant command byte, sent before the least significant command byte (CODE). It is only used when PRESENT2 = '2'. + [15:8] + read-write + + + WIDTH + Width of transfer. + [17:16] + read-write + + + DDR_MODE + Mode of transfer rate. + [18:18] + read-write + + + PRESENT2 + Presence of command field: +'0': not present +'1': present (1 Byte) +'2': present (2 Byte for OPI) + +Note: For octal data transfer with DDR mode (WIDTH='3' and DDR_MODE='1') either the HB protocol needs to be selected (by ADDR_CTL.SIZE3='7') or this field needs to be set to PRESENT2='2'. + [31:30] + read-write + + + + + WR_ADDR_CTL + Write address control + 0x64 + 32 + read-write + 0x0 + 0x70000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + DDR_MODE + Mode of transfer rate. + [18:18] + read-write + + + + + WR_MODE_CTL + Write mode control + 0x68 + 32 + read-write + 0x0 + 0xC007FFFF + + + CODE + Mode byte code. + [7:0] + read-write + + + CODEH + Mode high byte code. +This field specifies the most significant mode byte, sent before the least significant mode byte (CODE). It is only used when PRESENT2 = '2'. + [15:8] + read-write + + + WIDTH + Width of transfer. + [17:16] + read-write + + + DDR_MODE + Mode of transfer rate. + [18:18] + read-write + + + PRESENT2 + Presence of mode field: +'0': not present +'1': present (1 Byte) +'2': present (2 Byte for OPI) + +Note: For octal data transfer with DDR mode (WIDTH='3' and DDR_MODE='1') this field needs to be set to PRESENT2='2' to generate a mode field (or to PRESENT2='0'). + [31:30] + read-write + + + + + WR_DUMMY_CTL + Write dummy control + 0x6C + 32 + read-write + 0x0 + 0xC002001F + + + SIZE5 + Number of dummy cycles (minus 1): +'0': 1 cycles +... +'31': 32 cycles. + [4:0] + read-write + + + RWDS_EN + Read-Write-Data-Strobe Enable. Specifies whether the RWDS output signal should be driven starting in the last dummy cycle until DESELECT. This is needed for write transactions with byte masking via RWDS (e.g. Hyperbus). +'0': do not drive RWDS output +'1': drive RWDS output starting in last dummy cycle until DESELECT + +Note: this field is located in the WR_DUMMY_CTL register (and not in the WR_DATA_CTL register) since the RWDS signal needs to be driven already in the last dummy cycle. + [17:17] + read-write + + + PRESENT2 + Presence of dummy cycles: +'0': not present +'1': present +'2': present - Dummy cycles are doubled when RWDS refresh indicator is high during CA cycle. (HyperRAM variable latency mode) + [31:30] + read-write + + + + + WR_DATA_CTL + Write data control + 0x70 + 32 + read-write + 0x0 + 0x70000 + + + WIDTH + Width of transfer. + [17:16] + read-write + + + DDR_MODE + Mode of transfer rate. + [18:18] + read-write + + + + + WR_CRC_CTL + Write Bus CRC control + 0x74 + 32 + read-write + 0x0 + 0xCFFF0000 + + + DATA_CRC_INPUT_SIZE + Number of input data bytes for CRC generation (minus 1), i.e. number of data bytes over which the data CRC field is generated (minus 1): +'0': 1 byte +... +'255': 256 bytes. + +Note: For octal data transfer with DDR mode (WR_DATA_CTL.WIDTH='3' and WR_DATA_CTL.DDR_MODE='1') the number of bytes for CRC generation must be even (i.e. DATA_CRC_INPUT_SIZE must be odd). + [23:16] + read-write + + + CMD_ADDR_CRC_WIDTH + Width of command / address CRC field. + [25:24] + read-write + + + CMD_ADDR_CRC_DDR_MODE + Mode of transfer rate of command / address CRC field. + [26:26] + read-write + + + CMD_ADDR_CRC_INPUT + Specifies which fields are included in the command / address CRC generation. +'0': The command / address CRC field is generated over the address and (if present) mode fields only. +'1': The command / address CRC field is generated over the command, address and (if present) mode fields. + [27:27] + read-write + + + CMD_ADDR_CRC_PRESENT + Presence of command / address CRC field: +'0': not present +'1': present + +Note: For octal data transfer with DDR mode (RD_CRC_CTL.WIDTH='3' and RD_CRC_CTL.DDR_MODE='1') the command / address CRC byte is sent twice, otherwise the command / address CRC byte is only sent once. + [30:30] + read-write + + + DATA_CRC_PRESENT + Presence of data CRC field: +'0': not present +'1': present + +Note: Width and data transfer mode (SDR or DDR) of read data CRC fields are the same as for the associated read data fields, i.e. are specified by RD_DATA_CTL.WIDTH and RD_DATA_CTL.DDR_MODE. + +Note: For octal data transfer with DDR mode (RD_DATA_CTL.WIDTH='3' and RD_DATA_CTL.DDR_MODE='1') the data CRC byte is sent twice, otherwise the data CRC byte is only sent once. + [31:31] + read-write + + + + + + + + SDHC0 + SD/eMMC Host Controller + SDHC + 0x40460000 + + 0 + 65536 + registers + + + + WRAP + MMIO at SDHC wrapper level + 0x00000000 + + CTL + Top level wrapper control + 0x0 + 32 + read-write + 0x0 + 0x80000000 + + + ENABLE + IP Enable: +0: IP disabled, RAM in DeepSleep, SDHC_CORE regs are inaccessible (any attempts to access will result in AHB Error responses), IP is NOT held in reset but the clocks are gated +1: IP enabled, normal operation + [31:31] + read-write + + + + + + CORE + MMIO for Synopsys Mobile Storage Host Controller IP + 0x00001000 + + SDMASA_R + SDMA System Address register + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + BLOCKCNT_SDMASA + 32-bit Block Count (SDMA System Address) +- SDMA System Address (Host Version 4 Enable = 0): This +register contains the system memory address for an +SDMA transfer in the 32-bit addressing mode. When the +Host Controller stops an SDMA transfer, this register +points to the system address of the next contiguous data +position. It can be accessed only if no transaction is +executing. Reading this register during data transfers may +return an invalid value. +- 32-bit Block Count (Host Version 4 Enable = 1): From the +Host Controller Version 4.10 specification, this register is +redefined as 32-bit Block Count. The Host Controller +decrements the block count of this register for every block +transfer and the data transfer stops when the count +reaches zero. This register must be accessed when no +transaction is executing. Reading this register during data +transfers may return invalid value. +Following are the values for BLOCKCNT_SDMASA: +- 0xFFFF_FFFF - 4G - 1 Block +- ...... +- 0x0000_0002 - 2 Blocks +- 0x0000_0001 - 1 Block +- 0x0000_0000 - Stop Count +Note: +- When Host Version 4 Enable = 0, SDMA uses this register as system address and hence Auto CMD23 cannot be used with SDMA since this register is assigned for Auto CMD23 as 32-bit Block Count register. +-When Host Version 4 Enable = 1, SDMA uses ADMA system address register and this register is reassigned to 32-bit Block Count. This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. SDMA may use Auto CMD23 if 32-bit Block Count register is used. + [31:0] + read-write + + + + + BLOCKSIZE_R + Block Size register + 0x4 + 16 + read-write + 0x0 + 0x7FFF + + + XFER_BLOCK_SIZE + Transfer Block Size +These bits specify the block size of data transfers. In case of +memory, it is set to 512 bytes. It can be accessed only if no +transaction is executing. Read operations during transfers +may return an invalid value, and write operations are +ignored. Following are the values for XFER_BLOCK_SIZE: +- 0x1: 1 byte +- 0x2: 2 bytes +- 0x3: 3 bytes +- ...... +- 0x1FF: 511 byte +- 0x200: 512 bytes +- ...... +- 0x800: 2048 bytes +Note: This register must be programmed with a non-zero +value for data transfer. + [11:0] + read-write + + + SDMA_BUF_BDARY + SDMA Buffer Boundary +These bits specify the size of contiguous buffer in system +memory. The SDMA transfer waits at every boundary +specified by these fields and the Host Controller generates +the DMA interrupt to request the Host Driver to update the +SDMA System Address register. +Values: +- 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary +- 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary +- 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary +- 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary +- 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary +- 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary +- 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary +- 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary + [14:12] + read-write + + + + + BLOCKCOUNT_R + 16-bit Block Count register + 0x6 + 16 + read-write + 0x0 + 0xFFFF + + + BLOCK_CNT + 16-bit Block Count +- If the Host Version 4 Enable bit is set 0 or the 16-bit Block +Count register is set to non-zero, the 16-bit Block Count +register is selected. +- If the Host Version 4 Enable bit is set 1 and the 16-bit +Block Count register is set to zero, the 32-bit Block Count +register is selected. +Following are the values for BLOCK_CNT: +- 0x0: Stop Count +- 0x1: 1 Block +- 0x2: 2 Blocks +- ... - ... +- 0xFFFF: 65535 Blocks +Note: For Host Version 4 Enable = 0, this register must be +set to 0000h before programming the 32-bit block count +register when Auto CMD23 is enabled for non-DMA and +ADMA modes. + [15:0] + read-write + + + + + ARGUMENT_R + Argument register + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ARGUMENT + Command Argument +These bits specify the SD/eMMC command argument that is +specified in bits 39-8 of the Command format. + [31:0] + read-write + + + + + XFER_MODE_R + Transfer Mode register + 0xC + 16 + read-write + 0x0 + 0x1FF + + + DMA_ENABLE + DMA Enable +This bit enables the DMA functionality. If this bit is set to 1, a +DMA operation begins when the Host Driver writes to the +Command register. You can select one of the DMA modes by +using DMA Select in the Host Control 1 register. +Values: +- 0x1 (ENABLED): DMA Data transfer +- 0x0 (DISABLED): No data transfer or Non-DMA data +transfer + [0:0] + read-write + + + BLOCK_COUNT_ENABLE + Block Count Enable +This bit is used to enable the Block Count register, which is +relevant for multiple block transfers. If this bit is set to 0, the +Block Count register is disabled, which is useful in executing +an infinite transfer. The Host Driver must set this bit to 0 +when ADMA is used. When 16-bit Block Count register is used, the Host Driver can set this bit to 0 in ADMA2 mode to enable larger data transfer than the maximum of 65535 block counts supported by the 16-bit Block Count register. + [1:1] + read-write + + + AUTO_CMD_ENABLE + Auto Command Enable +This field determines use of Auto Command functions. +Note: In SDIO, this field must be set as 00b (Auto Command +Disabled). +Values: +- 0x0 (AUTO_CMD_DISABLED): Auto Command Disabled +- 0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable +- 0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable +- 0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Select + [3:2] + read-write + + + DATA_XFER_DIR + Data Transfer Direction Select +This bit defines the direction of DAT line data transfers. This +bit is set to 1 by the Host Driver to transfer data from the +SD/eMMC card to the Host Controller and it is set to 0 for all +other commands. +Values: +- 0x1 (READ): Read (Card to Host) +- 0x0 (WRITE): Write (Host to Card) + [4:4] + read-write + + + MULTI_BLK_SEL + Multi/Single Block Select +This bit is set when issuing multiple-block transfer +commands using the DAT line. If this bit is set to 0, it is not +necessary to set the Block Count register. + [5:5] + read-write + + + RESP_TYPE + Response Type R1/R5 +This bit selects either R1 or R5 as a response type when the +Response Error Check is selected. +Error statuses checked in R1: +- OUT_OF_RANGE +- ADDRESS_ERROR +- BLOCK_LEN_ERROR +- WP_VIOLATION +- CARD_IS_LOCKED +- COM_CRC_ERROR +- CARD_ECC_FAILED +- CC_ERROR +- ERROR +Response Flags checked in R5: +- COM_CRC_ERROR +- ERROR +- FUNCTION_NUMBER +- OUT_OF_RANGE +Values: +- 0x0 (RESP_R1): R1 (Memory) +- 0x1 (RESP_R5): R5 (SDIO) + [6:6] + read-write + + + RESP_ERR_CHK_ENABLE + Response Error Check Enable +The Host Controller supports response check function to +avoid overhead of response error check by Host driver. +Response types of only R1 and R5 can be checked by the +Controller. If the Host Controller checks the response error, +set this bit to 1 and set Response Interrupt Disable to 1. If an +error is detected, the Response Error interrupt is generated +in the Error Interrupt Status register. +Note: +- Response error check must not be enabled for any +response type other than R1 and R5. +Values: +- 0x0 (DISABLED): Response Error Check is disabled +- 0x1 (ENABLED): Response Error Check is enabled + [7:7] + read-write + + + RESP_INT_DISABLE + Response Interrupt Disable +The Host Controller supports response check function to +avoid overhead of response error check by the Host driver. +Response types of only R1 and R5 can be checked by the +Controller. +If Host Driver checks the response error, set this bit to 0 and +wait for Command Complete Interrupt and then check the +response register. +If the Host Controller checks the response error, set this bit +to 1 and set the Response Error Check Enable bit to 1. The +Command Complete Interrupt is disabled by this bit +regardless of the Command Complete Signal Enable. +Values: +- 0x0 (ENABLED): Response Interrupt is enabled +- 0x1 (DISABLED): Response Interrupt is disabled + [8:8] + read-write + + + + + CMD_R + Command register + 0xE + 16 + read-write + 0x0 + 0x3FFF + + + RESP_TYPE_SELECT + Response Type Select +This bit indicates the type of response expected from the +card. +Values: +- 0x0 (NO_RESP): No Response +- 0x1 (RESP_LEN_136): Response Length 136 +- 0x2 (RESP_LEN_48): Response Length 48 +- 0x3 (RESP_LEN_48B): Response Length 48; Check +Busy after response + [1:0] + read-write + + + SUB_CMD_FLAG + Sub Command Flag +This bit distinguishes between a main command and a sub +command. +Values: +- 0x0 (MAIN): Main Command +- 0x1 (SUB): Sub Command + [2:2] + read-write + + + CMD_CRC_CHK_ENABLE + Command CRC Check Enable +This bit enables the Host Controller to check the CRC field in +the response. If an error is detected, it is reported as a +Command CRC error. +Note: +- CRC Check enable must be set to 0 for the command +with no response, R3 response, and R4 response. +Values: +- 0x0 (DISABLED): Disable +- 0x1 (ENABLED): Enable + [3:3] + read-write + + + CMD_IDX_CHK_ENABLE + Command Index Check Enable +This bit enables the Host Controller to check the index field in +the response to verify if it has the same value as the +command index. If the value is not the same, it is reported as +a Command Index error. +Note: +- Index Check enable must be set to 0 for the command +with no response, R2 response, R3 response and R4 +response. +Values: +- 0x0 (DISABLED): Disable +- 0x1 (ENABLED): Enable + [4:4] + read-write + + + DATA_PRESENT_SEL + Data Present Select +This bit is set to 1 to indicate that data is present and that the +data is transferred using the DAT line. This bit is set to 0 in +the following instances: +- Command using the CMD line +- Command with no data transfer but using busy signal on +the DAT[0] line +- Resume Command +Values: +- 0x0 (NO_DATA): No Data Present +- 0x1 (DATA): Data Present + [5:5] + read-write + + + CMD_TYPE + Command Type +These bits indicate the command type. +Note: While issuing Abort CMD using CMD12/CMD52 or +reset CMD using CMD0/CMD52, CMD_TYPE field shall be +set to 0x3. +Values: +- 0x3 (ABORT_CMD): Abort +- 0x2 (RESUME_CMD): Resume +- 0x1 (SUSPEND_CMD): Suspend +- 0x0 (NORMAL_CMD): Normal + [7:6] + read-write + + + CMD_INDEX + Command Index +These bits are set to the command number that is specified +in bits 45-40 of the Command Format. + [13:8] + read-write + + + + + RESP01_R + Response Register 0/1 + 0x10 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RESP01 + Command Response +These bits reflect 39-8 bits of SD/eMMC Response Field. +Note: For Auto CMD, the 32-bit response (bits 39-8 of the +Response Field) is updated in the RESP67_R register. + [31:0] + read-only + + + + + RESP23_R + Response Register 2/3 + 0x14 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RESP23 + Command Response +These bits reflect 71-40 bits of the SD/eMMC Response + [31:0] + read-only + + + + + RESP45_R + Response Register 4/5 + 0x18 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RESP45 + Command Response +These bits reflect 103-72 bits of the Response Field. + [31:0] + read-only + + + + + RESP67_R + Response Register 6/7 + 0x1C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RESP67 + Command Response +These bits reflect bits 135-104 of SD/EMMC Response +Field. +Note: For Auto CMD, this register also reflects the 32-bit +response (bits 39-8 of the Response Field). + [31:0] + read-only + + + + + BUF_DATA_R + Buffer Data Port Register + 0x20 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + BUF_DATA + Buffer Data +These bits enable access to the Host Controller packet +buffer. + [31:0] + read-write + + + + + PSTATE_REG + Present State Register + 0x24 + 32 + read-only + 0x0 + 0x1BFF0FF7 + + + CMD_INHIBIT + Command Inhibit (CMD) +This bit indicates the following : +- SD/eMMC mode: If this bit is set to 0, it indicates that the +CMD line is not in use and the Host controller can issue +an SD/eMMC command using the CMD line. This bit is +set when the command register is written. This bit is +cleared when the command response is received. This bit +is not cleared by the response of auto CMD12/23 but +cleared by the response of read/write command. +Values: +- 0x0 (READY): Host Controller is ready to issue a +command +- 0x1 (NOT_READY): Host Controller is not ready to issue +a command + [0:0] + read-only + + + CMD_INHIBIT_DAT + Command Inhibit (DAT) +This bit is applicable for SD/eMMC mode and is generated if +either DAT line active or Read transfer active is set to 1. If +this bit is set to 0, it indicates that the Host Controller can +issue subsequent SD/eMMC commands. +Values: +- 0x0 (READY): Can issue command which used DAT line +- 0x1 (NOT_READY): Cannot issue command which used +DAT line + [1:1] + read-only + + + DAT_LINE_ACTIVE + DAT Line Active (SD/eMMC Mode only) +This bit indicates whether one of the DAT lines on the +SD/eMMC bus is in use. +In the case of read transactions, this bit indicates whether a +read transfer is executing on the SD/eMMC bus. +In the case of write transactions, this bit indicates whether a +write transfer is executing on the SD/eMMC bus. +For a command with busy, this status indicates whether the +command executing busy is executing on an SD or eMMC +bus. +Values: +- 0x0 (INACTIVE): DAT Line Inactive +- 0x1 (ACTIVE): DAT Line Active + [2:2] + read-only + + + DAT_7_4 + DAT[7:4] Line Signal Level +This bit is used to check the DAT line level to recover from +errors and for debugging. These bits reflect the value of the +sd_dat_in (upper nibble) signal. + [7:4] + read-only + + + WR_XFER_ACTIVE + Write Transfer Active +This status indicates whether a write transfer is active for +SD/eMMC mode. +Values: +- 0x0 (INACTIVE): No valid data +- 0x1 (ACTIVE): Transferring data + [8:8] + read-only + + + RD_XFER_ACTIVE + Read Transfer Active +This bit indicates whether a read transfer is active for +SD/eMMC mode. +Values: +- 0x0 (INACTIVE): No valid data +- 0x1 (ACTIVE): Transferring data + [9:9] + read-only + + + BUF_WR_ENABLE + Buffer Write Enable +This bit is used for non-DMA transfers. This bit is set if space +is available for writing data. +Values: +- 0x0 (DISABLED): Write disable +- 0x1 (ENABLED): Write enable + [10:10] + read-only + + + BUF_RD_ENABLE + Buffer Read Enable +This bit is used for non-DMA transfers. This bit is set if valid +data exists in the Host buffer. +Values: +- 0x0 (DISABLED): Read disable +- 0x1 (ENABLED): Read enable + [11:11] + read-only + + + CARD_INSERTED + Card Inserted +This bit indicates whether a card has been inserted. The +Host Controller debounces this signal so that Host Driver +need not wait for it to stabilize. +Values: +- 0x0 (FALSE): Reset, Debouncing, or No card +- 0x1 (TRUE): Card Inserted + [16:16] + read-only + + + CARD_STABLE + Card Stable +This bit indicates the stability of the Card Detect Pin Level. A +card is not detected if this bit is set to 1 and the value of the +CARD_INSERTED bit is 0. +Values: +- 0x0 (FALSE): Reset or Debouncing +- 0x1 (TRUE): No Card or Inserted + [17:17] + read-only + + + CARD_DETECT_PIN_LEVEL + Card Detect Pin Level +This bit reflects the inverse synchronized value of the +card_detect_n signal. +Values: +- 0x0 (FALSE): No card present +- 0x1 (TRUE): Card Present + [18:18] + read-only + + + WR_PROTECT_SW_LVL + Write Protect Switch Pin Level +This bit is supported only for memory and combo cards. This +bit reflects the synchronized value of the card_write_prot +signal. +Values: +- 0x0 (FALSE): Write protected +- 0x1 (TRUE): Write enabled + [19:19] + read-only + + + DAT_3_0 + DAT[3:0] Line Signal Level +This bit is used to check the DAT line level to recover from +errors and for debugging. These bits reflect the value of the +sd_dat_in (lower nibble) signal. + [23:20] + read-only + + + CMD_LINE_LVL + Command-Line Signal Level +This bit is used to check the CMD line level to recover from +errors and for debugging. These bits reflect the value of the +sd_cmd_in signal. + [24:24] + read-only + + + HOST_REG_VOL + Host Regulator Voltage Stable +This bit is used to check whether the host regulator voltage is +stable for switching the voltage of UHS-I mode. This bit +reflects the synchronized value of the host_reg_vol_stable +signal. +Values: +- 0x0 (FALSE): Host Regulator Voltage is not stable +- 0x1 (TRUE): Host Regulator Voltage is stable + [25:25] + read-only + + + CMD_ISSU_ERR + Command Not Issued by Error +This bit is set if a command cannot be issued after setting +the command register due to an error except the Auto +CMD12 error. +Values: +- 0x0 (FALSE): No error for issuing a command +- 0x1 (TRUE): Command cannot be issued + [27:27] + read-only + + + SUB_CMD_STAT + Sub Command Status +This bit is used to distinguish between a main command and +a sub command status. +Values: +- 0x0 (FALSE): Main Command Status +- 0x1 (TRUE): Sub Command Status + [28:28] + read-only + + + + + HOST_CTRL1_R + Host Control 1 Register + 0x28 + 8 + read-write + 0x0 + 0xFF + + + LED_CTRL + LED Control +This bit is used to caution the user not to remove the card +while the SD card is being accessed. The value is reflected +on the led_ctrl ouput. +Values: +- 0x0 (OFF): LED off +- 0x1 (ON): LED on + [0:0] + read-write + + + DAT_XFER_WIDTH + Data Transfer Width +For SD/eMMC mode,this bit selects the data transfer width of +the Host Controller. The Host Driver sets it to match the data +width of the SD/eMMC card. +Values: +- 0x1 (FOUR_BIT): 4-bit mode +- 0x0 (ONE_BIT): 1-bit mode + [1:1] + read-write + + + HIGH_SPEED_EN + High Speed Enable (SD/eMMC Mode only) +Before setting this bit, the Host Driver checks the High Speed +Support in the Capabilities register. +Note: SDHC always outputs the sd_cmd_out and +sd_dat_out lines at the rising edge of card clock +irrespective of this bit. +Values: +- 0x1 (HIGH_SPEED): High Speed mode +- 0x0 (NORMAL_SPEED): Normal Speed mode + [2:2] + read-write + + + DMA_SEL + N/A + [4:3] + read-write + + + EXT_DAT_XFER + Extended Data Transfer Width +This bit controls 8-bit bus width mode of embedded device. +Values: +- 0x1 (EIGHT_BIT): 8-bit Bus Width +- 0x0 (DEFAULT): Bus Width is selected by the Data +Transfer Width + [5:5] + read-write + + + CARD_DETECT_TEST_LVL + Card Detect Test Level +This bit is enabled while the Card Detect Signal Selection is +set to 1 and it indicates whether a card inserted or not. +Values: +- 0x1 (CARD_INSERTED): Card Inserted +- 0x0 (No_CARD): No Card + [6:6] + read-write + + + CARD_DETECT_SIG_SEL + Card Detect Signal Selection +This bit selects a source for card detection. When the source +for the card detection is switched, the interrupt must be +disabled during the switching period. +Values: +- 0x1 (CARD_DT_TEST_LEVEL): Card Detect Test Level +is selected (for test purpose) +- 0x0 (card_detect_n): card_detect_n signal is +selected (for normal use) + [7:7] + read-write + + + + + PWR_CTRL_R + Power Control Register + 0x29 + 8 + read-write + 0x0 + 0xF + + + SD_BUS_PWR_VDD1 + SD Bus Power for VDD1 +This bit enables VDD1 power of the card. This setting is +available on the card_if_pwr_en output so that it +can be used to control the VDD1 power supply of the card. +Before setting this bit, the SD Host Driver sets the SD Bus +Voltage Select bit. If the Host Controller detects a No Card +state, this bit is cleared. +In SD mode, if this bit is cleared, the Host Controller stops +the SD Clock by clearing the SD_CLK_IN bit in the +CLK_CTRL_R register. +Values: +- 0x0 (OFF): Power off +- 0x1 (ON): Power on + [0:0] + read-write + + + SD_BUS_VOL_VDD1 + These bits are NON-operational (they can be written and read but they have no effect). In a generic HCI host these would select the card supply voltage. But, for the applications targeted for this block it is assumed that the card supply voltage is always fixed at the board level. If for some reason there is a variable power supply then that can be managed through normal GPIO programming separately. + [3:1] + read-write + + + + + BGAP_CTRL_R + Block Gap Control Register + 0x2A + 8 + read-write + 0x0 + 0xF + + + STOP_BG_REQ + Stop At Block Gap Request +This bit is used to stop executing read and write transactions +at the next block gap for non-DMA, SDMA, and ADMA +transfers. +Values: +- 0x0 (XFER): Transfer +- 0x1 (STOP): Stop + [0:0] + read-write + + + CONTINUE_REQ + Continue Request +This bit is used to restart the transaction, which was stopped +using the Stop At Block Gap Request. The Host Controller +automatically clears this bit when the transaction restarts. If +stop at block gap request is set to 1, any write to this bit is +ignored. +Values: +- 0x0 (NO_AFFECT): No Affect +- 0x1 (RESTART): Restart + [1:1] + read-write + + + RD_WAIT_CTRL + N/A + [2:2] + read-write + + + INT_AT_BGAP + Interrupt At Block Gap +This bit is valid only in the 4-bit mode of an SDIO card and is +used to select a sample point in the interrupt cycle. Setting to +1 enables interrupt detection at the block gap for a multiple +block transfer. +Values: +- 0x0 (DISABLE): Disabled +- 0x1 (ENABLE): Enabled + [3:3] + read-write + + + + + WUP_CTRL_R + Wakeup Control Register + 0x2B + 8 + read-write + 0x0 + 0x7 + + + WUP_CARD_INT + Wakeup Event Enable on SDIO Card Interrupt (through DAT[1]). +This bit enables wakeup event through an SDIO Card Interrupt +assertion in the Normal Interrupt Status register. This bit can +be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. +Values: +- 0x0 (DISABLED): Disable +- 0x1 (ENABLED): Enable + [0:0] + read-write + + + WUP_CARD_INSERT + Wakeup Event Enable on SD Card Insertion +This bit enables wakeup event through Card Insertion +assertion in the Normal Interrupt Status register. FN_WUS +(Wake Up Support) in CIS does not affect this bit. +Values: +- 0x0 (DISABLED): Disable +- 0x1 (ENABLED): Enable + [1:1] + read-write + + + WUP_CARD_REMOVAL + Wakeup Event Enable on SD Card Removal +This bit enables wakeup event through Card Removal +assertion in the Normal Interrupt Status register. For the +SDIO card, Wake Up Support (FN_WUS) in the Card +Information Structure (CIS) register does not affect this bit. +Values: +- 0x0 (DISABLED): Disable +- 0x1 (ENABLED): Enable + [2:2] + read-write + + + + + CLK_CTRL_R + Clock Control Register + 0x2C + 16 + read-write + 0x0 + 0xFFEF + + + INTERNAL_CLK_EN + Internal Clock Enable +This bit is set to 0 when the Host Driver is not using the Host +Controller or the Host Controller awaits a wakeup interrupt. +The Host Controller must stop its internal clock to enter a +very low power state. Certain registers are not accessible when this bit is off. So, to be safe turn it on for any register access. +Values: +- 0x0 (FALSE): Stop +- 0x1 (TRUE): Oscillate + [0:0] + read-write + + + INTERNAL_CLK_STABLE + Internal Clock Stable +This bit enables the Host Driver to check the clock stability +twice after the Internal Clock Enable bit is set and after the +PLL Enable bit is set. This bit reflects the synchronized +value of the Internal Clock Stable signal after the Internal Clock +Enable bit is set to 1 and also reflects the synchronized +value of the Card Clock Stable signal after the PLL Enable bit is +set to 1. +Values: +- 0x0 (FALSE): Not Ready +- 0x1 (TRUE): Ready + [1:1] + read-only + + + SD_CLK_EN + SD/eMMC Clock Enable +This bit stops the clk_card output when set to 0. The +SDCLK Frequency Select bit can be changed when +this bit is set to 0. +Values: +- 0x0 (FALSE): Disable providing clk_card +- 0x1 (TRUE): Enable providing clk_card + [2:2] + read-write + + + PLL_ENABLE + PLL Enable +This bit is used to activate the PLL (applicable when Host +Version 4 Enable = 1). +Values: +- 0x0 (FALSE): PLL is in low power mode +- 0x1 (TRUE): PLL is enabled + [3:3] + read-write + + + CLK_GEN_SELECT + Clock Generator Select +This bit is used to select the clock generator mode in +SDCLK Frequency Select. +Values: +- 0x0 (FALSE): Divided Clock Mode +- 0x1 (TRUE): Programmable Clock Mode + [5:5] + read-write + + + UPPER_FREQ_SEL + These bits specify the upper 2 bits of 10-bit SDCLK +Frequency Select control. + [7:6] + read-write + + + FREQ_SEL + SDCLK Frequency Select +These bits are used to select the frequency of the SDCLK +signal. +10-bit Divided Clock Mode: +- 0x3FF - 1/2046 Divided clock +- .......... +- N - 1/2N Divided Clock +- .......... +- 0x002 - 1/4 Divided Clock +- 0x001 - 1/2 Divided Clock +- 0x000 - Base clock (10MHz - 255 MHz) + [15:8] + read-write + + + + + TOUT_CTRL_R + Timeout Control Register + 0x2E + 8 + read-write + 0x0 + 0xF + + + TOUT_CNT + N/A + [3:0] + read-write + + + + + SW_RST_R + Software Reset Register + 0x2F + 8 + read-write + 0x0 + 0x7 + + + SW_RST_ALL + Software Reset For All +This reset affects the entire Host Controller except for the +card detection circuit. During its initialization, the Host Driver +sets this bit to 1 to reset the Host Controller. All registers are +reset except the capabilities register. If this bit is set to 1, the +Host Driver must issue reset command and reinitialize the +card. +Values: +- 0x0 (FALSE): Work +- 0x1 (TRUE): Reset + [0:0] + read-write + + + SW_RST_CMD + Software Reset For CMD line +This bit resets only a part of the command circuit to be able +to issue a command. This reset is effective only for a command +issuing circuit (including response error statuses related to +Command Inhibit (CMD) control) and does not affect the +data transfer circuit. Host Controller can continue data +transfer even after this reset is executed while handling +subcommand-response errors. +The following registers and bits are cleared by this bit: +- Present State register - Command Inhibit (CMD) bit +- Normal Interrupt Status register - Command Complete bit +- Error Interrupt Status - Response error statuses related +to Command Inhibit (CMD) bit +Values: +- 0x0 (FALSE): Work +- 0x1 (TRUE): Reset + [1:1] + read-write + + + SW_RST_DAT + Software Reset For DAT line +This bit is used in SD/eMMC mode and it resets only a part +of the data circuit and the DMA circuit is also reset. +The following registers and bits are cleared by this bit: +- Buffer Data Port register +- Buffer is cleared and initialized. +- Present state register +- Buffer Read Enable +- Buffer Write Enable +- Read Transfer Active +- Write Transfer Active +- DAT Line Active +- Command Inhibit (DAT) +- Block Gap Control register +- Continue Request +- Stop At Block Gap Request +- Normal Interrupt status register +- Buffer Read Ready +- Buffer Write Ready +- DMA Interrupt +- Block Gap Event +- Transfer Complete +Values: +- 0x0 (FALSE): Work +- 0x1 (TRUE): Reset + [2:2] + read-write + + + + + NORMAL_INT_STAT_R + Normal Interrupt Status Register + 0x30 + 16 + read-write + 0x0 + 0xE1FF + + + CMD_COMPLETE + Command Complete +In an SD/eMMC Mode, this bit is set when the end bit of a +response except for Auto CMD12 and Auto CMD23. +This interrupt is not generated when the Response Interrupt +Disable in Transfer Mode Register is set to 1. +Values: +- 0x0 (FALSE): No command complete +- 0x1 (TRUE): Command Complete + [0:0] + read-write + + + XFER_COMPLETE + Transfer Complete +This bit is set when a read/write transfer and a command +with status busy is completed. +Values: +- 0x0 (FALSE): Not complete +- 0x1 (TRUE): Command execution is completed + [1:1] + read-write + + + BGAP_EVENT + Block Gap Event +This bit is set when both read/write transaction is stopped at +block gap due to a Stop at Block Gap Request. +Values: +- 0x0 (FALSE): No Block Gap Event +- 0x1 (TRUE): Transaction stopped at block gap + [2:2] + read-write + + + DMA_INTERRUPT + DMA Interrupt +This bit is set if the Host Controller detects the SDMA Buffer +Boundary during transfer. In case of ADMA, by setting the Int +field in the descriptor table, the Host controller generates this +interrupt. This interrupt is not generated after a Transfer +Complete. +Values: +- 0x0 (FALSE): No DMA Interrupt +- 0x1 (TRUE): DMA Interrupt is generated + [3:3] + read-write + + + BUF_WR_READY + Buffer Write Ready +This bit is set if the Buffer Write Enable changes from 0 to 1. +Values: +- 0x0 (FALSE): Not ready to write buffer +- 0x1 (TRUE): Ready to write buffer + [4:4] + read-write + + + BUF_RD_READY + Buffer Read Ready +This bit is set if the Buffer Read Enable changes from 0 to 1. +Values: +- 0x0 (FALSE): Not ready to read buffer +- 0x1 (TRUE): Ready to read buffer + [5:5] + read-write + + + CARD_INSERTION + Card Insertion +This bit is set if the Card Inserted in the Present State +register changes from 0 to 1. +Values: +- 0x0 (FALSE): Card state stable or Debouncing +- 0x1 (TRUE): Card Inserted + [6:6] + read-write + + + CARD_REMOVAL + Card Removal +This bit is set if the Card Inserted in the Present State +register changes from 1 to 0. +Values: +- 0x0 (FALSE): Card state stable or Debouncing +- 0x1 (TRUE): Card Removed + [7:7] + read-write + + + CARD_INTERRUPT + Card Interrupt +This bit reflects the synchronized value of: +- DAT[1] Interrupt Input for SD Mode +Values: +- 0x0 (FALSE): No Card Interrupt +- 0x1 (TRUE): Generate Card Interrupt + [8:8] + read-only + + + FX_EVENT + FX Event +This status is set when R[14] of response register is set to 1 +and Response Type R1/R5 is set to 0 in Transfer Mode +register. This interrupt is used with response check function. +Values: +- 0x0 (FALSE): No Event +- 0x1 (TRUE): FX Event is detected + [13:13] + read-only + + + CQE_EVENT + Command Queuing Event +This status is set if Command Queuing/Crypto related event +has occurred in eMMC/SD mode. Read CQHCI's +CQIS/CRNQIS register for more details. In UHS-II Mode, +this bit is irrelevant. +Values: +- 0x0 (FALSE): No Event +- 0x1 (TRUE): Command Queuing Event is detected + [14:14] + read-write + + + ERR_INTERRUPT + Error Interrupt +If any of the bits in the Error Interrupt Status register are set, +then this bit is set. +Values: +- 0x0 (FALSE): No Error +- 0x1 (TRUE): Error + [15:15] + read-only + + + + + ERROR_INT_STAT_R + Error Interrupt Status Register + 0x32 + 16 + read-write + 0x0 + 0x1FFF + + + CMD_TOUT_ERR + Command Timeout Error +In SD/eMMC Mode,this bit is set only if no response is +returned within 64 SD clock cycles from the end bit of the +command. If the Host Controller detects a CMD line conflict, +along with Command CRC Error bit, this bit is set to 1, +without waiting for 64 SD/eMMC card clock cycles. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Time out + [0:0] + read-write + + + CMD_CRC_ERR + Command CRC Error +Command CRC Error is generated in SD/eMMC mode for +following two cases. +- If a response is returned and the Command Timeout +Error is set to 0 (indicating no timeout), this bit is set to 1 +when detecting a CRC error in the command response. +- The Host Controller detects a CMD line conflict by +monitoring the CMD line when a command is issued. If +the Host Controller drives the CMD line to 1 level, but +detects 0 level on the CMD line at the next SD clock +edge, then the Host Controller aborts the command (stop +driving CMD line) and set this bit to 1. The Command +Timeout Error is also set to 1 to distinguish a CMD line +conflict. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): CRC error generated + [1:1] + read-write + + + CMD_END_BIT_ERR + Command End Bit Error +This bit is set when detecting that the end bit of a command +response is 0 in SD/eMMC mode. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): End Bit error generated + [2:2] + read-write + + + CMD_IDX_ERR + Command Index Error +This bit is set if a Command Index error occurs in the +command respons in SD/eMMC mode. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [3:3] + read-write + + + DATA_TOUT_ERR + Data Timeout Error +This bit is set in SD/eMMC mode when detecting one of the +following timeout conditions: +- Busy timeout for R1b, R5b type +- Busy timeout after Write CRC status +- Write CRC Status timeout +- Read Data timeout +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Time out + [4:4] + read-write + + + DATA_CRC_ERR + Data CRC Error +This error occurs in SD/eMMC mode when detecting CRC +error when transferring read data which uses the DAT line, +when detecting the Write CRC status having a value of other +than 010 or when write CRC status timeout. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [5:5] + read-write + + + DATA_END_BIT_ERR + Data End Bit Error +This error occurs in SD/eMMC mode either when detecting 0 +at the end bit position of read data that uses the DAT line or +at the end bit position of the CRC status. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [6:6] + read-write + + + CUR_LMT_ERR + Current Limit Error +By setting the SD Bus Power bit in the Power Control +register, the Host Controller is requested to supply power for +the SD Bus. If the Host Controller supports the Current Limit +function, it can be protected from an illegal card by stopping +power supply to the card in which case this bit indicates a +failure status. A reading of 1 for this bit means that the Host +Controller is not supplying power to the SD card due to some +failure. A reading of 0 for this bit means that the Host +Controller is supplying power and no error has occurred. The +Host Controller may require some sampling time to detect +the current limit. DWC_mshc Host Controller does not +support this function, this bit is always set to 0. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Power Fail + [7:7] + read-write + + + AUTO_CMD_ERR + Auto CMD Error +This error status is used by Auto CMD12 and Auto CMD23 in +SD/eMMC mode. This bit is set when detecting that any of +the bits D00 to D05 in Auto CMD Error Status register has +changed from 0 to 1. D07 is effective in case of Auto CMD12. +Auto CMD Error Status register is valid while this bit is set to +1 and may be cleared by clearing of this bit. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [8:8] + read-write + + + ADMA_ERR + ADMA Error +This bit is set when the Host Controller detects error during +ADMA-based data transfer. The error could be due to +following reasons: +- Error response received from System bus (Master I/F) +- ADMA3,ADMA2 Descriptors invalid +- CQE Task or Transfer descriptors invalid +When the error occurs, the state of the ADMA is saved in the +ADMA Error Status register. +In eMMC CQE mode: +The Host Controller generates this Interrupt when it detects +an invalid descriptor data (Valid=0) at the ST_FDS state. +ADMA Error State in the ADMA Error Status indicates that +an error has occurred in ST_FDS state. The Host Driver may +find that Valid bit is not set at the error descriptor. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [9:9] + read-write + + + TUNING_ERR + N/A + [10:10] + read-write + + + RESP_ERR + Response Error +Host Controller Version 4.00 supports response error check +function to avoid overhead of response error check by Host +Driver during DMA execution. If Response Error Check +Enable is set to 1 in the Transfer Mode register, Host +Controller Checks R1 or R5 response. If an error is detected +in a response, this bit is set to 1.This is applicable in +SD/eMMC mode. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [11:11] + read-write + + + BOOT_ACK_ERR + Boot Acknowledgement Error +This bit is set when there is a timeout for boot +acknowledgement or when detecting boot ack status having +a value other than 010. This is applicable only when boot +acknowledgement is expected in eMMC mode. +In SD mode, this bit is irrelevant. +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [12:12] + read-write + + + + + NORMAL_INT_STAT_EN_R + Normal Interrupt Status Enable Register + 0x34 + 16 + read-write + 0x0 + 0x7FFF + + + CMD_COMPLETE_STAT_EN + Command Complete Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [0:0] + read-write + + + XFER_COMPLETE_STAT_EN + Transfer Complete Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [1:1] + read-write + + + BGAP_EVENT_STAT_EN + Block Gap Event Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [2:2] + read-write + + + DMA_INTERRUPT_STAT_EN + DMA Interrupt Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [3:3] + read-write + + + BUF_WR_READY_STAT_EN + Buffer Write Ready Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [4:4] + read-write + + + BUF_RD_READY_STAT_EN + Buffer Read Ready Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [5:5] + read-write + + + CARD_INSERTION_STAT_EN + Card Insertion Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [6:6] + read-write + + + CARD_REMOVAL_STAT_EN + Card Removal Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [7:7] + read-write + + + CARD_INTERRUPT_STAT_EN + Card Interrupt Status Enable +If this bit is set to 0, the Host Controller clears the interrupt +request to the System. The Card Interrupt detection is +stopped when this bit is cleared and restarted when this bit is +set to 1. The Host Driver may clear the Card Interrupt Status +Enable before servicing the Card Interrupt and may set this +bit again after all interrupt requests from the card are cleared +to prevent inadvertent interrupts. +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [8:8] + read-write + + + INT_A_STAT_EN + N/A + [9:9] + read-write + + + INT_B_STAT_EN + N/A + [10:10] + read-write + + + INT_C_STAT_EN + N/A + [11:11] + read-write + + + RE_TUNE_EVENT_STAT_EN + N/A + [12:12] + read-write + + + FX_EVENT_STAT_EN + FX Event Status Enable +This bit is added from Version 4.10. +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [13:13] + read-write + + + CQE_EVENT_STAT_EN + CQE Event Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [14:14] + read-write + + + + + ERROR_INT_STAT_EN_R + Error Interrupt Status Enable Register + 0x36 + 16 + read-write + 0x0 + 0xFFFF + + + CMD_TOUT_ERR_STAT_EN + Command Timeout Error Status Enable (SD/eMMC Mode +only). +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [0:0] + read-write + + + CMD_CRC_ERR_STAT_EN + ommand CRC Error Status Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [1:1] + read-write + + + CMD_END_BIT_ERR_STAT_EN + Command End Bit Error Status Enable (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [2:2] + read-write + + + CMD_IDX_ERR_STAT_EN + Command Index Error Status Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [3:3] + read-write + + + DATA_TOUT_ERR_STAT_EN + Data Timeout Error Status Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [4:4] + read-write + + + DATA_CRC_ERR_STAT_EN + Data CRC Error Status Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [5:5] + read-write + + + DATA_END_BIT_ERR_STAT_EN + Data End Bit Error Status Enable (SD/eMMC Mode only). +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [6:6] + read-write + + + CUR_LMT_ERR_STAT_EN + Current Limit Error Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [7:7] + read-write + + + AUTO_CMD_ERR_STAT_EN + Auto CMD Error Status Enable (SD/eMMC Mode only). +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [8:8] + read-write + + + ADMA_ERR_STAT_EN + ADMA Error Status Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [9:9] + read-write + + + TUNING_ERR_STAT_EN + Tuning Error Status Enable (UHS-I Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [10:10] + read-write + + + RESP_ERR_STAT_EN + Response Error Status Enable (SD Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [11:11] + read-write + + + BOOT_ACK_ERR_STAT_EN + Boot Acknowledgment Error (eMMC Mode only) +Setting this bit to 1 enables setting of Boot Acknowledgment +Error in Error Interrupt Status register +(ERROR_INT_STAT_R). +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [12:12] + read-write + + + VENDOR_ERR_STAT_EN1 + N/A + [13:13] + read-write + + + VENDOR_ERR_STAT_EN2 + N/A + [14:14] + read-write + + + VENDOR_ERR_STAT_EN3 + N/A + [15:15] + read-write + + + + + NORMAL_INT_SIGNAL_EN_R + Normal Interrupt Signal Enable Register + 0x38 + 16 + read-write + 0x0 + 0x7FFF + + + CMD_COMPLETE_SIGNAL_EN + Command Complete Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [0:0] + read-write + + + XFER_COMPLETE_SIGNAL_EN + Transfer Complete Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [1:1] + read-write + + + BGAP_EVENT_SIGNAL_EN + Block Gap Event Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [2:2] + read-write + + + DMA_INTERRUPT_SIGNAL_EN + DMA Interrupt Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [3:3] + read-write + + + BUF_WR_READY_SIGNAL_EN + Buffer Write Ready Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [4:4] + read-write + + + BUF_RD_READY_SIGNAL_EN + Buffer Read Ready Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [5:5] + read-write + + + CARD_INSERTION_SIGNAL_EN + Card Insertion Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [6:6] + read-write + + + CARD_REMOVAL_SIGNAL_EN + Card Removal Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [7:7] + read-write + + + CARD_INTERRUPT_SIGNAL_EN + Card Interrupt Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [8:8] + read-write + + + INT_A_SIGNAL_EN + N/A + [9:9] + read-write + + + INT_B_SIGNAL_EN + N/A + [10:10] + read-write + + + INT_C_SIGNAL_EN + N/A + [11:11] + read-write + + + RE_TUNE_EVENT_SIGNAL_EN + N/A + [12:12] + read-write + + + FX_EVENT_SIGNAL_EN + FX Event Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [13:13] + read-write + + + CQE_EVENT_SIGNAL_EN + Command Queuing Engine Event Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [14:14] + read-write + + + + + ERROR_INT_SIGNAL_EN_R + Error Interrupt Signal Enable Register + 0x3A + 16 + read-write + 0x0 + 0xFFFF + + + CMD_TOUT_ERR_SIGNAL_EN + Command Timeout Error Signal Enable (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [0:0] + read-write + + + CMD_CRC_ERR_SIGNAL_EN + Command CRC Error Signal Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [1:1] + read-write + + + CMD_END_BIT_ERR_SIGNAL_EN + Command End Bit Error Signal Enable (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [2:2] + read-write + + + CMD_IDX_ERR_SIGNAL_EN + Command Index Error Signal Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): No error +- 0x1 (TRUE): Error + [3:3] + read-write + + + DATA_TOUT_ERR_SIGNAL_EN + Data Timeout Error Signal Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [4:4] + read-write + + + DATA_CRC_ERR_SIGNAL_EN + Data CRC Error Signal Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [5:5] + read-write + + + DATA_END_BIT_ERR_SIGNAL_EN + Data End Bit Error Signal Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [6:6] + read-write + + + CUR_LMT_ERR_SIGNAL_EN + Current Limit Error Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [7:7] + read-write + + + AUTO_CMD_ERR_SIGNAL_EN + Auto CMD Error Signal Enable (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [8:8] + read-write + + + ADMA_ERR_SIGNAL_EN + ADMA Error Signal Enable +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [9:9] + read-write + + + TUNING_ERR_SIGNAL_EN + N/A + [10:10] + read-write + + + RESP_ERR_SIGNAL_EN + Response Error Signal Enable (SD Mode only) +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [11:11] + read-write + + + BOOT_ACK_ERR_SIGNAL_EN + Boot Acknowledgment Error (eMMC Mode only). +Setting this bit to 1 enables generating interrupt signal when +Boot Acknowledgement Error in Error Interrupt Status +register is set. +Values: +- 0x0 (FALSE): Masked +- 0x1 (TRUE): Enabled + [12:12] + read-write + + + VENDOR_ERR_SIGNAL_EN1 + N/A + [13:13] + read-write + + + VENDOR_ERR_SIGNAL_EN2 + N/A + [14:14] + read-write + + + VENDOR_ERR_SIGNAL_EN3 + N/A + [15:15] + read-write + + + + + AUTO_CMD_STAT_R + Auto CMD Status Register + 0x3C + 16 + read-only + 0x0 + 0xBF + + + AUTO_CMD12_NOT_EXEC + Auto CMD12 Not Executed +If multiple memory block data transfer is not started due to a +command error, this bit is not set because it is not necessary +to issue an Auto CMD12. Setting this bit to 1 means that the +Host Controller cannot issue Auto CMD12 to stop multiple +memory block data transfer, due to some error. If this bit is +set to 1, error status bits (D04-D01) is meaningless. +This bit is set to 0 when Auto CMD Error is generated by +Auto CMD23. +Values: +- 0x1 (TRUE): Not Executed +- 0x0 (FALSE): Executed + [0:0] + read-only + + + AUTO_CMD_TOUT_ERR + Auto CMD Timeout Error +This bit is set if no response is returned with 64 SDCLK +cycles from the end bit of the command. +If this bit is set to 1, error status bits (D04-D01) are +meaningless. +Values: +- 0x1 (TRUE): Time out +- 0x0 (FALSE): No Error + [1:1] + read-only + + + AUTO_CMD_CRC_ERR + Auto CMD CRC Error +This bit is set when detecting a CRC error in the command +response. +Values: +- 0x1 (TRUE): CRC Error Generated +- 0x0 (FALSE): No Error + [2:2] + read-only + + + AUTO_CMD_EBIT_ERR + Auto CMD End Bit Error +This bit is set when detecting that the end bit of command +response is 0. +Values: +- 0x1 (TRUE): End Bit Error Generated +- 0x0 (FALSE): No Error + [3:3] + read-only + + + AUTO_CMD_IDX_ERR + Auto CMD Index Error +This bit is set if the command index error occurs in response +to a command. +Values: +- 0x1 (TRUE): Error +- 0x0 (FALSE): No Error + [4:4] + read-only + + + AUTO_CMD_RESP_ERR + Auto CMD Response Error +This bit is set when Response Error Check Enable in the +Transfer Mode register is set to 1 and an error is detected in +R1 response of either Auto CMD12 or CMD13. This status is +ignored if any bit between D00 to D04 is set to 1. +Values: +- 0x1 (TRUE): Error +- 0x0 (FALSE): No Error + [5:5] + read-only + + + CMD_NOT_ISSUED_AUTO_CMD12 + Command Not Issued By Auto CMD12 Error +If this bit is set to 1, CMD_wo_DAT is not executed due to an +Auto CMD12 Error (D04-D01) in this register. +This bit is set to 0 when Auto CMD Error is generated by +Auto CMD23. +Values: +- 0x1 (TRUE): Not Issued +- 0x0 (FALSE): No Error + [7:7] + read-only + + + + + HOST_CTRL2_R + Host Control 2 Register + 0x3E + 16 + read-write + 0x0 + 0xFDFF + + + UHS_MODE_SEL + N/A + [2:0] + read-write + + + SIGNALING_EN + 1.8V Signaling Enable +This bit controls voltage regulator for I/O cell in SD UHS-I mode. Setting this bit from 0 to 1 starts changing the +signal voltage from 3.3V to 1.8V. Host Controller clears this +bit if switching to 1.8V signaling fails per protocol. The value is reflected on the io_volt_sel output which can then be used to change an external regulator to supply 1.8V instead of 3.3V on the VDDIO pin associated with the CLK/CMD/DAT signals. +Note: This bit must be set for all UHS-I speed modes +(SDR12/SDR25/SDR50/DDR50). +Values: +- 0x0 (V_3_3): 3.3V Signalling +- 0x1 (V_1_8): 1.8V Signalling + [3:3] + read-write + + + DRV_STRENGTH_SEL + Driver Strength Select +These bits are used to select the Host Controller output driver in +1.8V signaling UHS-I/eMMC speed modes. The value is reflected on the io_drive_strength[1:0] output. +- 0x0 (TYPEB): Driver TYPEB is selected +- 0x1 (TYPEA): Driver TYPEA is selected +- 0x2 (TYPEC): Driver TYPEC is selected +- 0x3 (TYPED): Driver TYPED is selected + [5:4] + read-write + + + EXEC_TUNING + N/A + [6:6] + read-write + + + SAMPLE_CLK_SEL + N/A + [7:7] + read-write + + + UHS2_IF_ENABLE + N/A + [8:8] + read-write + + + ADMA2_LEN_MODE + ADMA2 Length Mode +This bit selects ADMA2 Length mode to be either 16-bit or +26-bit. +Values: +- 0x0 (FALSE): 16-bit Data Length Mode +- 0x1 (TRUE): 26-bit Data Length Mode + [10:10] + read-write + + + CMD23_ENABLE + CMD23 Enable +If the card supports CMD23, this bit is set to 1. This bit is +used to select Auto CMD23 or Auto CMD12 for ADMA3 data +transfer. +Values: +- 0x0 (FALSE): Auto CMD23 is disabled +- 0x1 (TRUE): Auto CMD23 is enabled + [11:11] + read-write + + + HOST_VER4_ENABLE + Host Version 4 Enable +This bit selects either Version 3.00 compatible mode or +Version 4 mode. +Functions of following fields are modified for Host Version 4 +mode: +- SDMA Address: SDMA uses ADMA System Address +(05Fh-058h) instead of SDMA System Address register +(003h-000h) +- ADMA2/ADMA3 selection: ADMA3 is selected by DMA +select in Host Control 1 register +- 32-bit Block Count: SDMA System Address register +(003h-000h) is modified to 32-bit Block Count register +Note: It is recommended not to program ADMA3 Integrated +Descriptor Address registers and +Command Queuing registers (if applicable) while operating +in Host version less than 4 mode (Host Version 4 Enable = +0). +Values: +- 0x0 (FALSE): Version 3.00 compatible mode +- 0x1 (TRUE): Version 4 mode + [12:12] + read-write + + + ADDRESSING + N/A + [13:13] + read-write + + + ASYNC_INT_ENABLE + Asynchronous Interrupt Enable +This bit can be set if a card supports asynchronous +interrupts and Asynchronous Interrupt Support is set to 1 in +the Capabilities register. +Values: +- 0x0 (FALSE): Disabled +- 0x1 (TRUE): Enabled + [14:14] + read-write + + + PRESET_VAL_ENABLE + N/A + [15:15] + read-write + + + + + CAPABILITIES1_R + Capabilities 1 Register - 0 to 31 + 0x40 + 32 + read-only + 0x276C6481 + 0xFFEFFFBF + + + TOUT_CLK_FREQ + Timeout Clock Frequency +This bit shows the base clock frequency used to detect Data +Timeout Error. The Timeout Clock unit defines the unit of +timeout clock frequency. It can be KHz or MHz. +- 0x00 - Get information through another method +- 0x01 - 1KHz / 1MHz +- 0x02 - 2KHz / 2MHz +- 0x03 - 3KHz / 3MHz +- ........... +- 0x3F - 63KHz / 63MHz + [5:0] + read-only + + + TOUT_CLK_UNIT + Timeout Clock Unit +This bit shows the unit of base clock frequency used to +detect Data TImeout Error. +Values: +- 0x0 (KHZ): KHz +- 0x1 (MHZ): MHz + [7:7] + read-only + + + BASE_CLK_FREQ + Base Clock Frequency for SD clock +These bits indicate the base (maximum) clock frequency for +the SD Clock. The definition of these bits depend on the Host +Controller Version. +- 6-Bit Base Clock Frequency: This mode is supported by +the Host Controller version 1.00 and 2.00. The upper 2 +bits are not effective and are always 0. The unit values +are 1 MHz. The supported clock range is 10 MHz to 63 +MHz. +- 0x00 - Get information through another method +- 0x01 - 1 MHz +- 0x02 - 2 MHz +- ............. +- 0x3F - 63 MHz +- 0x40-0xFF - Not Supported +- 8-Bit Base Clock Frequency: This mode is supported by +the Host Controller version 3.00. The unit values are 1 +MHz. The supported clock range is 10 MHz to 255 MHz. +- 0x00 - Get information through another method +- 0x01 - 1 MHz +- 0x02 - 2 MHz +- ............ +- 0xFF - 255 MHz +If the frequency is 16.5 MHz, the larger value is set to +0001001b (17 MHz) because the Host Driver uses this value +to calculate the clock divider value and it does not exceed +the upper limit of the SD Clock frequency. If these bits are all +0, the Host system has to get information using a different +method. + [15:8] + read-only + + + MAX_BLK_LEN + N/A + [17:16] + read-only + + + EMBEDDED_8_BIT + 8-bit Support for Embedded Device +This bit indicates whether the Host Controller is capable of +using an 8-bit bus width mode. This bit is not effective when +the Slot Type is set to 10b. +Values: +- 0x0 (FALSE): 8-bit Bus Width not Supported +- 0x1 (TRUE): 8-bit Bus Width Supported + [18:18] + read-only + + + ADMA2_SUPPORT + ADMA2 Support +This bit indicates whether the Host Controller is capable of +using ADMA2. +Values: +- 0x0 (FALSE): ADMA2 not Supported +- 0x1 (TRUE): ADMA2 Supported + [19:19] + read-only + + + HIGH_SPEED_SUPPORT + High Speed Support +This bit indicates whether the Host Controller and the Host +System supports High Speed mode and they can supply the +SD Clock frequency from 25 MHz to 50 MHz. +Values: +- 0x0 (FALSE): High Speed not Supported +- 0x1 (TRUE): High Speed Supported + [21:21] + read-only + + + SDMA_SUPPORT + SDMA Support +This bit indicates whether the Host Controller is capable of +using SDMA to transfer data between the system memory +and the Host Controller directly. +Values: +- 0x0 (FALSE): SDMA not Supported +- 0x1 (TRUE): SDMA Supported + [22:22] + read-only + + + SUS_RES_SUPPORT + Suspense/Resume Support +This bit indicates whether the Host Controller supports +Suspend/Resume functionality. If this bit is 0, the Host Driver +does not issue either Suspend or Resume commands +because the Suspend and Resume mechanism is not +supported. +Values: +- 0x0 (FALSE): Not Supported +- 0x1 (TRUE): Supported + [23:23] + read-only + + + VOLT_33 + Voltage Support 3.3V +Values: +- 0x0 (FALSE): 3.3V Not Supported +- 0x1 (TRUE): 3.3V Supported + [24:24] + read-only + + + VOLT_30 + Voltage Support 3.0V +Values: +- 0x0 (FALSE): 3.0V Not Supported +- 0x1 (TRUE): 3.0V Supported + [25:25] + read-only + + + VOLT_18 + Voltage Support 1.8V +Values: +- 0x0 (FALSE): 1.8V Not Supported +- 0x1 (TRUE): 1.8V Supported + [26:26] + read-only + + + SYS_ADDR_64_V4 + 64-bit System Address Support for V4 +This bit sets the Host Controller to support 64-bit System +Addressing of V4 mode. When this bit is set to 1, full or part +of 64-bit address must be used to decode the Host Controller +Registers so that Host Controller Registers can be placed +above system memory area. 64-bit address decode of Host +Controller registers is effective regardless of setting to 64-bit +Addressing in Host Control 2. +If this bit is set to 1, 64-bit DMA Addressing for version 4 is +enabled by setting Host Version 4 Enable +(HOST_VER4_ENABLE = 1) and by setting 64-bit +Addressing (ADDRESSING =1) in the Host Control 2 +register. SDMA can be used and ADMA2 uses 128-bit +Descriptor. +Values: +- 0x0 (FALSE): 64-bit System Address for V4 is Not +Supported +- 0x1 (TRUE): 64-bit System Address for V4 is Supported + [27:27] + read-only + + + SYS_ADDR_64_V3 + 64-bit System Address Support for V3 +This bit sets the Host controller to support 64-bit System +Addressing of V3 mode. +SDMA cannot be used in 64-bit Addressing in Version 3 +Mode. +If this bit is set to 1, 64-bit ADMA2 with using 96-bit +Descriptor can be enabled by setting Host Version 4 Enable +(HOST_VER4_ENABLE = 0) and DMA select (DMA_SEL = +11b). +Values: +- 0x0 (FALSE): 64-bit System Address for V3 is Not +Supported +- 0x1 (TRUE): 64-bit System Address for V3 is Supported + [28:28] + read-only + + + ASYNC_INT_SUPPORT + Asynchronous Interrupt Support (SD Mode only) +Values: +- 0x0 (FALSE): Asynchronous Interrupt Not Supported +- 0x1 (TRUE): Asynchronous Interrupt Supported + [29:29] + read-only + + + SLOT_TYPE_R + Slot Type +These bits indicate usage of a slot by a specific Host +System. +Values: +- 0x0 (REMOVABLE_SLOT): Removable Card Slot +- 0x1 (EMBEDDED_SLOT): Embedded Slot for one Device +- 0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) +- 0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple +Embedded Devices + [31:30] + read-only + + + + + CAPABILITIES2_R + Capabilities Register - 32 to 63 + 0x44 + 32 + read-only + 0x8000077 + 0x18FFEF7F + + + SDR50_SUPPORT + SDR50 Support (UHS-I only) +Thsi bit indicates that SDR50 is supported. The bit 13 +(USE_TUNING_SDR50) indicates whether SDR50 requires +tuning or not. +Values: +- 0x0 (FALSE): SDR50 is not supported +- 0x1 (TRUE): SDR50 is supported + [0:0] + read-only + + + SDR104_SUPPORT + SDR104 Support (UHS-I only) +This bit mentions that SDR104 requires tuning. +Values: +- 0x0 (FALSE): SDR104 is not supported +- 0x1 (TRUE): SDR104 is supported (NOT ACTUALLY SUPPORTED) + [1:1] + read-only + + + DDR50_SUPPORT + DDR50 Support (UHS-I only) +Values: +- 0x0 (FALSE): DDR50 is not supported +- 0x1 (TRUE): DDR50 is supported + [2:2] + read-only + + + UHS2_SUPPORT + UHS-II Support (UHS-II only) +This bit indicates whether Host Controller supports UHS-II. +Values: +- 0x0 (FALSE): UHS-II is not supported +- 0x1 (TRUE): UHS-II is supported + [3:3] + read-only + + + DRV_TYPEA + Driver Type A Support (UHS-I only) +This bit indicates support of Driver Type A for 1.8 Signaling. +Values: +- 0x0 (FALSE): Driver Type A is not supported +- 0x1 (TRUE): Driver Type A is supported + [4:4] + read-only + + + DRV_TYPEC + Driver Type C Support (UHS-I only) +This bit indicates support of Driver Type C for 1.8 Signaling. +Values: +- 0x0 (FALSE): Driver Type C is not supported +- 0x1 (TRUE): Driver Type C is supported + [5:5] + read-only + + + DRV_TYPED + Driver Type D Support (UHS-I only) +This bit indicates support of Driver Type D for 1.8 Signaling. +Values: +- 0x0 (FALSE): Driver Type D is not supported +- 0x1 (TRUE): Driver Type D is supported + [6:6] + read-only + + + RETUNE_CNT + N/A + [11:8] + read-only + + + USE_TUNING_SDR50 + Use Tuning for SDR50 (UHS-I only) +Values: +- 0x0 (ZERO): SDR50 does not require tuning +- 0x1 (ONE): SDR50 requires tuning + [13:13] + read-only + + + RE_TUNING_MODES + N/A + [15:14] + read-only + + + CLK_MUL + Clock Multiplier +These bits indicate the clock multiplier of the programmable +clock generator. Setting these bits to 0 means that the Host +Controller does not support a programmable clock generator. +- 0x0: Clock Multiplier is not Supported +- 0x1: Clock Multiplier M = 2 +- 0x2: Clock Multiplier M = 3 +- ......... +- 0xFF: Clock Multiplier M = 256 + [23:16] + read-only + + + ADMA3_SUPPORT + ADMA3 Support +This bit indicates whether the Host Controller is capable of +using ADMA3. +Values: +- 0x0 (FALSE): ADMA3 not Supported +- 0x1 (TRUE): ADMA3 Supported + [27:27] + read-only + + + VDD2_18V_SUPPORT + 1.8V VDD2 Support +This bit indicates support of VDD2 for the Host System. +Values: +- 0x0 (FALSE): 1.8V VDD2 is not Supported +- 0x1 (TRUE): 1.8V VDD2 is Supported + [28:28] + read-only + + + + + CURR_CAPABILITIES1_R + Current Capabilities Register - 0 to 31 + 0x48 + 32 + read-only + 0x0 + 0xFFFFFF + + + MAX_CUR_33V + Maximum Current for 3.3V +This bit specifies the Maximum Current for 3.3V VDD1 power +supply for the card. +- 0: Get information through another method +- 1: 4mA +- 2: 8mA +- 3: 13mA +- ....... +- 255: 1020mA + [7:0] + read-only + + + MAX_CUR_30V + Maximum Current for 3.0V +This bit specifies the Maximum Current for 3.0V VDD1 power +supply for the card. +- 0: Get information through another method +- 1: 4mA +- 2: 8mA +- 3: 13mA +- ....... +- 255: 1020mA + [15:8] + read-only + + + MAX_CUR_18V + Maximum Current for 1.8V +This bit specifies the Maximum Current for 1.8V VDD1 power +supply for the card. +- 0: Get information through another method +- 1: 4mA +- 2: 8mA +- 3: 13mA +- ....... +- 255: 1020mA + [23:16] + read-only + + + + + CURR_CAPABILITIES2_R + Maximum Current Capabilities Register - 32 to 63 + 0x4C + 32 + read-only + 0x0 + 0xFF + + + MAX_CUR_VDD2_18V + Maximum Current for 1.8V VDD2 +This bit specifies the Maximum Current for 1.8V VDD2 power +supply for the UHS-II card. +- 0: Get information through another method +- 1: 4mA +- 2: 8mA +- 3: 13mA +- ....... +- 255: 1020mA + [7:0] + read-only + + + + + FORCE_AUTO_CMD_STAT_R + Force Event Register for Auto CMD Error Status register + 0x50 + 16 + write-only + 0x0 + 0xBF + + + FORCE_AUTO_CMD12_NOT_EXEC + Force Event for Auto CMD12 Not Executed +Values: +- 0x1 (TRUE): Auto CMD12 Not Executed Status is set +- 0x0 (FALSE): Not Affected + [0:0] + write-only + + + FORCE_AUTO_CMD_TOUT_ERR + Force Event for Auto CMD Timeout Error +Values: +- 0x1 (TRUE): Auto CMD Timeout Error Status is set +- 0x0 (FALSE): Not Affected + [1:1] + write-only + + + FORCE_AUTO_CMD_CRC_ERR + Force Event for Auto CMD CRC Error +Values: +- 0x1 (TRUE): Auto CMD CRC Error Status is set +- 0x0 (FALSE): Not Affected + [2:2] + write-only + + + FORCE_AUTO_CMD_EBIT_ERR + Force Event for Auto CMD End Bit Error +Values: +- 0x1 (TRUE): Auto CMD End Bit Error Status is set +- 0x0 (FALSE): Not Affected + [3:3] + write-only + + + FORCE_AUTO_CMD_IDX_ERR + Force Event for Auto CMD Index Error +Values: +- 0x1 (TRUE): Auto CMD Index Error Status is set +- 0x0 (FALSE): Not Affected + [4:4] + write-only + + + FORCE_AUTO_CMD_RESP_ERR + Force Event for Auto CMD Response Error +Values: +- 0x1 (TRUE): Auto CMD Response Error Status is set +- 0x0 (FALSE): Not Affected + [5:5] + write-only + + + FORCE_CMD_NOT_ISSUED_AUTO_CMD12 + Force Event for Command Not Issued By Auto CMD12 Error +Values: +- 0x1 (TRUE): Command Not Issued By Auto CMD12 Error +Status is set +- 0x0 (FALSE): Not Affected + [7:7] + write-only + + + + + FORCE_ERROR_INT_STAT_R + Force Event Register for Error Interrupt Status + 0x52 + 16 + read-write + 0x0 + 0xFFFF + + + FORCE_CMD_TOUT_ERR + Force Event for Command Timeout Error (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Command Timeout Error Status is set + [0:0] + read-write + + + FORCE_CMD_CRC_ERR + Force Event for Command CRC Error (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Command CRC Error Status is set + [1:1] + read-write + + + FORCE_CMD_END_BIT_ERR + Force Event for Command End Bit Error (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Command End Bit Error Status is set + [2:2] + read-write + + + FORCE_CMD_IDX_ERR + Force Event for Command Index Error (SD/eMMC Mode +only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Command Index Error Status is set + [3:3] + read-write + + + FORCE_DATA_TOUT_ERR + Force Event for Data Timeout Error (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Data Timeout Error Status is set + [4:4] + read-write + + + FORCE_DATA_CRC_ERR + Force Event for Data CRC Error (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Data CRC Error Status is set + [5:5] + read-write + + + FORCE_DATA_END_BIT_ERR + Force Event for Data End Bit Error (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Data End Bit Error Status is set + [6:6] + read-write + + + FORCE_CUR_LMT_ERR + Force Event for Current Limit Error +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Current Limit Error Status is set + [7:7] + read-write + + + FORCE_AUTO_CMD_ERR + Force Event for Auto CMD Error (SD/eMMC Mode only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Auto CMD Error Status is set + [8:8] + read-write + + + FORCE_ADMA_ERR + Force Event for ADMA Error +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): ADMA Error Status is set + [9:9] + read-write + + + FORCE_TUNING_ERR + Force Event for Tuning Error (UHS-I Mode only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Tuning Error Status is set + [10:10] + read-write + + + FORCE_RESP_ERR + Force Event for Response Error (SD Mode only) +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Response Error Status is set + [11:11] + read-write + + + FORCE_BOOT_ACK_ERR + Force Event for Boot Ack error +Values: +- 0x0 (FALSE): Not Affected +- 0x1 (TRUE): Boot ack Error Status is set + [12:12] + read-write + + + FORCE_VENDOR_ERR1 + N/A + [13:13] + read-write + + + FORCE_VENDOR_ERR2 + N/A + [14:14] + read-write + + + FORCE_VENDOR_ERR3 + N/A + [15:15] + read-write + + + + + ADMA_ERR_STAT_R + ADMA Error Status Register + 0x54 + 8 + read-only + 0x0 + 0x7 + + + ADMA_ERR_STATES + ADMA Error States +These bits indicate the state of ADMA when an error occurs +during ADMA data transfer. +Values: +- 0x0 (ST_STOP): Stop DMA - SYS_ADR register points to +a location next to the error descriptor +- 0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register +points to the error descriptor +- 0x2 (UNUSED): Never set this state +- 0x3 (ST_TFR): Transfer Data - SYS_ADR register points +to a location next to the error descriptor + [1:0] + read-only + + + ADMA_LEN_ERR + ADMA Length Mismatch Error States +This error occurs in the following instances: +- While the Block Count Enable is being set, the total data +length specified by the Descriptor table is different from +that specified by the Block Count and Block Length +- When the total data length cannot be divided by the block +length +Values: +- 0x0 (NO_ERR): No Error +- 0x1 (ERROR): Error + [2:2] + read-only + + + + + ADMA_SA_LOW_R + ADMA System Address Register - Low + 0x58 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADMA_SA_LOW + ADMA System Address +These bits indicate the lower 32 bits of the ADMA system +address. +- SDMA: If Host Version 4 Enable is set to 1, this register +stores the system address of the data location +- ADMA2: This register stores the byte address of the +executing command of the descriptor table +- ADMA3: This register is set by ADMA3. ADMA2 +increments the address of this register that points to the +next line, every time a Descriptor line is fetched. + [31:0] + read-write + + + + + ADMA_ID_LOW_R + ADMA3 Integrated Descriptor Address Register - Low + 0x78 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADMA_ID_LOW + ADMA Integrated Descriptor Address +These bits indicate the lower 32-bit of the ADMA Integrated +Descriptor address. The start address of Integrated +Descriptor is set to these register bits. The ADMA3 fetches +one Descriptor Address and increments these bits to indicate +the next Descriptor address. + [31:0] + read-write + + + + + HOST_CNTRL_VERS_R + Host Controller Version + 0xFE + 16 + read-only + 0x5 + 0xFFFF + + + SPEC_VERSION_NUM + N/A + [7:0] + read-only + + + VENDOR_VERSION_NUM + N/A + [15:8] + read-only + + + + + CQVER + Command Queuing Version register + 0x180 + 32 + read-only + 0x510 + 0xFFF + + + EMMC_VER_SUFFIX + This bit indicates the eMMC version suffix (2nd digit right of +decimal point) in BCD format. + [3:0] + read-only + + + EMMC_VER_MINOR + This bit indicates the eMMC minor version (1st digit right of +decimal point) in BCD format. + [7:4] + read-only + + + EMMC_VER_MAJOR + This bit indicates the eMMC major version (1st digit left of +decimal point) in BCD format. + [11:8] + read-only + + + + + CQCAP + Command Queuing Capabilities register + 0x184 + 32 + read-only + 0x30C8 + 0x1000F3FF + + + ITCFVAL + Internal Timer Clock Frequency Value (ITCFVAL) +This field scales the frequency of the timer clock provided by +ITCFMUL. The Final clock frequency of actual timer clock is +calculated as ITCFVAL* ITCFMUL. + [9:0] + read-only + + + ITCFMUL + N/A + [15:12] + read-only + + + CRYPTO_SUPPORT + Crypto Support +This bit indicates whether the Host Controller supports +cryptographic operations. +Values: +- 0x0 (FALSE): Crypto not Supported +- 0x1 (TRUE): Crypto Supported + [28:28] + read-only + + + + + CQCFG + Command Queuing Configuration register + 0x188 + 32 + read-write + 0x0 + 0x1103 + + + CQ_EN + Enable command queuing engine (CQE). +When CQE is disable, the software controls the eMMC bus +using the registers between the addresses 0x000 to 0x1FF. +Before the software writes to this bit, the software verifies +that the eMMC host controller is in idle state and there are no +ongoing commands or data transfers. When software wants +to exit command queuing mode, it clears all previous tasks (if +any) before setting this bit to 0. +Values: +- 0x1 (CQE_ENABLE): Enable command queuing +- 0x0 (CQE_DISABLE): Disable command queuing + [0:0] + read-write + + + CR_GENERAL_EN + N/A + [1:1] + read-write + + + TASK_DESC_SIZE + Bit Value Description +This bit indicates the size of task descriptor used in host +memory. This bit can only be configured when Command +Queuing Enable bit is 0 (command queuing is disabled). +Values: +- 0x1 (TASK_DESC_128b): Task descriptor size is 128 bits +- 0x0 (TASK_DESC_64b): Task descriptor size is 64 bits + [8:8] + read-write + + + DCMD_EN + This bit indicates to the hardware whether the Task +Descriptor in slot #31 of the TDL is a data transfer descriptor +or a direct-command descriptor. CQE uses this bit when a +task is issued in slot #31, to determine how to decode the +Task Descriptor. +Values: +- 0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot +#31 is a DCMD Task Descriptor +- 0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot +#31 is a data Transfer Task Descriptor + [12:12] + read-write + + + + + CQCTL + Command Queuing Control register + 0x18C + 32 + read-write + 0x0 + 0x101 + + + HALT + Halt request and resume +Values: +- 0x1 (HALT_CQE): Software writes 1 to this bit when it +wants to acquire software control over the eMMC bus and +to disable CQE from issuing command on the bus. +For example, issuing a Discard Task command +(CMDQ_TASK_MGMT). When the software writes 1, CQE +completes the ongoing task (if any in progress). After the +task is completed and the CQE is in idle state, CQE does not +issue new commands and indicates to the software by +setting this bit to 1. The software can poll on this bit until it is +set to 1 and only then send commands on the eMMC bus. +- 0x0 (RESUME_CQE): Software writes 0 to this bit to exit +from the halt state and resume CQE activity. + [0:0] + read-write + + + CLR_ALL_TASKS + Clear all tasks +This bit can only be written when the controller is halted. This +bit does not clear tasks in the device. The software has to +use the CMDQ_TASK_MGMT command to clear device's +queue. +Values: +- 0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the +controller +- 0x0 (NO_EFFECT): Programming 0 has no effect + [8:8] + read-write + + + + + CQIS + Command Queuing Interrupt Status register + 0x190 + 32 + read-write + 0x0 + 0x3F + + + HAC + Halt complete interrupt +This status bit is asserted (only if CQISE.HAC_STE=1) when +halt bit in the CQCTL register transitions from 0 to 1 +indicating that the host controller has completed its current +ongoing task and has entered halt state. A value of 1 clears +this status bit. +Values: +- 0x1 (SET): HAC Interrupt is set +- 0x0 (NOTSET): HAC Interrupt is not set + [0:0] + read-write + + + TCC + Task complete interrupt +This status bit is asserted (if CQISE.TCC_STE=1) when at +least one of the following conditions are met: +- A task is completed and the INT bit is set in its Task +Descriptor +- Interrupt caused by Interrupt Coalescing logic due to +timeout +- Interrupt Coalescing logic reached the configured +threshold +A value of 1 clears this status bit +Values: +- 0x1 (SET): TCC Interrupt is set +- 0x0 (NOTSET): TCC Interrupt is not set + [1:1] + read-write + + + RED + Response error detected interrupt +This status bit is asserted (if CQISE.RED_STE=1) when a +response is received with an error bit set in the device status +field. Configure the CQRMEM register to identify device +status bit fields that may trigger an interrupt and that are +masked. A value of 1 clears this status bit. +Values: +- 0x1 (SET): RED Interrupt is set +- 0x0 (NOTSET): RED Interrupt is not set + [2:2] + read-write + + + TCL + Task cleared interrupt +This status bit is asserted (if CQISE.TCL_STE=1) when a +task clear operation is completed by CQE. The completed +task clear operation is either an individual task clear (by +writing CQTCLR) or clearing of all tasks (by writing CQCTL). +A value of 1 clears this status bit. +Values: +- 0x1 (SET): TCL Interrupt is set +- 0x0 (NOTSET): TCL Interrupt is not set + [3:3] + read-write + + + GCE + N/A + [4:4] + read-write + + + ICCE + N/A + [5:5] + read-write + + + + + CQISE + Command Queuing Interrupt Status Enable register + 0x194 + 32 + read-write + 0x0 + 0x3F + + + HAC_STE + Halt complete interrupt status enable +Values: +- 0x1 (INT_STS_ENABLE): CQIS.HAC is set when its +interrupt condition is active +- 0x0 (INT_STS_DISABLE): CQIS.HAC is disabled + [0:0] + read-write + + + TCC_STE + Task complete interrupt status enable +Values: +- 0x1 (INT_STS_ENABLE): CQIS.TCC is set when its +interrupt condition is active +- 0x0 (INT_STS_DISABLE): CQIS.TCC is disabled + [1:1] + read-write + + + RED_STE + Response error detected interrupt status enable +Values: +- 0x1 (INT_STS_ENABLE): CQIS.RED is set when its +interrupt condition is active +- 0x0 (INT_STS_DISABLE): CQIS.RED is disabled + [2:2] + read-write + + + TCL_STE + Task cleared interrupt status enable +Values: +- 0x1 (INT_STS_ENABLE): CQIS.TCL is set when its +interrupt condition is active +- 0x0 (INT_STS_DISABLE): CQIS.TCL is disabled + [3:3] + read-write + + + GCE_STE + General Crypto Error interrupt status enable +Values: +- 0x1 (INT_STS_ENABLE): CQIS.GCE is set when its +interrupt condition is active +- 0x0 (INT_STS_DISABLE): CQIS.GCE is disabled + [4:4] + read-write + + + ICCE_STE + Invalid Crypto Configuration Error interrupt status enable +Values: +- 0x1 (INT_STS_ENABLE): CQIS.ICCE is set when its +interrupt condition is active +- 0x0 (INT_STS_DISABLE): CQIS.ICCE is disabled + [5:5] + read-write + + + + + CQISGE + Command Queuing Interrupt signal enable register + 0x198 + 32 + read-write + 0x0 + 0x3F + + + HAC_SGE + Halt complete interrupt signal enable +Values: +- 0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal +generation is active +- 0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal +generation is disabled + [0:0] + read-write + + + TCC_SGE + Task complete interrupt signal enable +Values: +- 0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal +generation is active +- 0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal +generation is disabled + [1:1] + read-write + + + RED_SGE + Response error detected interrupt signal enable +Values: +- 0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal +generation is active +- 0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal +generation is disabled + [2:2] + read-write + + + TCL_SGE + Task cleared interrupt signal enable +Values: +- 0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal +generation is active +- 0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal +generation is disabled + [3:3] + read-write + + + GCE_SGE + General Crypto Error interrupt signal enable +Values: +- 0x1 (INT_SIG_ENABLE): CQIS.GCE interrupt signal +generation is active +- 0x0 (INT_SIG_DISABLE): CQIS.GCE interrupt signal +generation is disabled + [4:4] + read-write + + + ICCE_SGE + Invalid Crypto Configuration Error interrupt signal enable +Values: +- 0x1 (INT_SIG_ENABLE): CQIS.ICCE interrupt signal +generation is active +- 0x0 (INT_SIG_DISABLE): CQIS.ICCE interrupt signal +generation is disabled + [5:5] + read-write + + + + + CQIC + Command Queuing Interrupt Coalescing register + 0x19C + 32 + read-write + 0x0 + 0x80119FFF + + + TOUT_VAL + Interrupt Coalescing Timeout Value +Software uses this field to configure the maximum time +allowed between the completion of a task on the bus and the +generation of an interrupt. +Timer Operation: The timer is reset by software during the +interrupt service routine. It starts running when the first data +transfer task with INT=0 is completed, after the timer was +reset. When the timer reaches the value configured in +ICTOVAL field, it generates an interrupt and stops. +The timer's unit is equal to 1024 clock periods of the clock +whose frequency is specified in the Internal Timer Clock +Frequency field CQCAP register. +- 0x0: Timer is disabled. Timeout-based interrupt is not +generated +- 0x1: Timeout on 01x1024 cycles of timer clock frequency +- 0x2: Timeout on 02x1024 cycles of timer clock frequency +- ........ +- 0x7f: Timeout on 127x1024 cycles of timer clock +frequency +In order to write to this field, the TOUT_VAL_WEN bit must +be set at the same write operation. + [6:0] + read-write + + + TOUT_VAL_WEN + When software writes 1 to this bit, the value TOUT_VAL is +updated with the contents written on the same cycle. +Values: +- 0x1 (WEN_SET): Sets TOUT_VAL_WEN +- 0x0 (WEN_CLR): clears TOUT_VAL_WEN + [7:7] + write-only + + + INTC_TH + Interrupt Coalescing Counter Threshold filed +Software uses this field to configure the number of task +completions (only tasks with INT=0 in the Task Descriptor), +which are required in order to generate an interrupt. +Counter Operation: As data transfer tasks with INT=0 +complete, they are counted by CQE. The counter is reset by +software during the interrupt service routine. The counter +stops counting when it reaches the value configured in +INTC_TH, and generates interrupt. +- 0x0: Interrupt coalescing feature disabled +- 0x1: Interrupt coalescing interrupt generated after 1 task +when INT=0 completes +- 0x2: Interrupt coalescing interrupt generated after 2 tasks +when INT=0 completes +- ........ +- 0x1f: Interrupt coalescing interrupt generated after 31 +tasks when INT=0 completes +To write to this field, the INTC_TH_WEN bit must be set +during the same write operation. + [12:8] + write-only + + + INTC_TH_WEN + Interrupt Coalescing Counter Threshold Write Enable +When software writes 1 to this bit, the value INTC_TH is +updated with the contents written on the same cycle. +Values: +- 0x1 (WEN_SET): Sets INTC_TH_WEN +- 0x0 (WEN_CLR): Clears INTC_TH_WEN + [15:15] + write-only + + + INTC_RST + Counter and Timer Reset +When host driver writes 1, the interrupt coalescing timer and +counter are reset. +Values: +- 0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer +and counter are reset +- 0x0 (NO_EFFECT): No Effect + [16:16] + write-only + + + INTC_STAT + Interrupt Coalescing Status Bit +This bit indicates to the software whether any tasks (with +INT=0) have completed and counted towards interrupt +coalescing (that is, this is set if and only if INTC counter > 0). +Values: +- 0x1 (INTC_ATLEAST1_COMP): At least one INT0 task +completion has been counted (INTC counter > 0) +- 0x0 (INTC_NO_TASK_COMP): INT0 Task completions +have not occurred since last counter reset (INTC counter +== 0) + [20:20] + read-only + + + INTC_EN + Interrupt Coalescing Enable Bit +Values: +- 0x1 (ENABLE_INT_COALESCING): Interrupt coalescing +mechanism is active. Interrupts are counted and timed, +and coalesced interrupts are generated +- 0x0 (DISABLE_INT_COALESCING): Interrupt coalescing +mechanism is disabled (Default). + [31:31] + read-write + + + + + CQTDLBA + Command Queuing Task Descriptor List Base Address register + 0x1A0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TDLBA + This register stores the LSB bits (31:0) of the byte address of +the head of the Task Descriptor List in system memory. +The size of the task descriptor list is 32 * (Task Descriptor +size + Transfer Descriptor size) as configured by the host +driver. This address is set on 1 KB boundary. The lower 10 +bits of this register are set to 0 by the software and are +ignored by CQE. + [31:0] + read-write + + + + + CQTDBR + Command Queuing DoorBell register + 0x1A8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DBR + The software configures TDLBA and TDLBAU, and enable +CQE in CQCFG before using this register. +Writing 1 to bit n of this register triggers CQE to start +processing the task encoded in slot n of the TDL. Writing 0 +by the software does not have any impact on the hardware, +and does not change the value of the register bit. +CQE always processes tasks according to the order +submitted to the list by CQTDBR write transactions. CQE +processes Data Transfer tasks by reading the Task +Descriptor and sending QUEUED_TASK_PARAMS (CMD44) +and QUEUED_TASK_ADDRESS (CMD45) commands to +the device. CQE processes DCMD tasks (in slot #31, when +enabled) by reading the Task Descriptor, and generating the +command encoded by its index and argument. +The corresponding bit is cleared to 0 by CQE in one of the +following events: +- A task execution is completed (with success or error). +- The task is cleared using CQTCLR register. +- All tasks are cleared using CQCTL register. +- CQE is disabled using CQCFG register. +Software may initiate multiple tasks at the same time (batch +submission) by writing 1 to multiple bits of this register in the +same transaction. In the case of batch submission, CQE +processes the tasks in order of the task index, starting with +the lowest index. If one or more tasks in the batch are +marked with QBR, the ordering of execution is based on said +processing order. + [31:0] + read-write + + + + + CQTCN + Command Queuing TaskClear Notification register + 0x1AC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TCN + Task Completion Notification +Each of the 32 bits are bit mapped to the 32 tasks. +- Bit-N(1): Task-N has completed execution (with success +or errors) +- Bit-N(0): Task-N has not completed, could be pending or +not submitted. +On task completion, software may read this register to know +tasks that have completed. After reading this register, +software may clear the relevant bit fields by writing 1 to the +corresponding bits. + [31:0] + read-write + + + + + CQDQS + Device queue status register + 0x1B0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DQS + Device Queue Status +Each of the 32 bits are bit mapped to the 32 tasks. +- Bit-N(1): Device has marked task N as ready for +execution +- Bit-N(0): Task-N is not ready for execution. This task +could be pending in device or not submitted. +Host controller updates this register with response of the +Device Queue Status command. + [31:0] + read-only + + + + + CQDPT + Device pending tasks register + 0x1B4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DPT + Device-Pending Tasks +Each of the 32 bits are bit mapped to the 32 tasks. +- Bit-N(1): Task-N has been successfully queued into the +device and is awaiting execution +- Bit-N(0): Task-N is not yet queued. +Bit n of this register is set if and only if +QUEUED_TASK_PARAMS (CMD44) and +QUEUED_TASK_ADDRESS (CMD45) were sent for this +specific task and if this task has not been executed. +The controller sets this bit after receiving a successful +response for CMD45. CQE clears this bit after the task has +completed execution. +Software reads this register in the task-discard procedure to +determine if the task is queued in the device. + [31:0] + read-only + + + + + CQTCLR + Command Queuing DoorBell register + 0x1B8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TCLR + Writing 1 to bit n of this register orders CQE to clear a task +that the software has previously issued. +This bit can only be written when CQE is in Halt state as +indicated in CQCFG register Halt bit. When software writes 1 +to a bit in this register, CQE updates the value to 1, and +starts clearing the data structures related to the task. CQE +clears the bit fields (sets a value of 0) in CQTCLR and in +CQTDBR once the clear operation is complete. Software +must poll on the CQTCLR until it is cleared to verify that a +clear operation was done. + [31:0] + read-write + + + + + CQSSC1 + CQ Send Status Configuration 1 register + 0x1C0 + 32 + read-write + 0x11000 + 0xFFFFF + + + SQSCMD_IDLE_TMR + This field configures the polling period to be used when +using periodic SEND_QUEUE_STATUS (CMD13) polling. +Periodic polling is used when tasks are pending in the +device, but no data transfer is in progress. When a +SEND_QUEUE_STATUS response indicates that no task is +ready for execution, CQE counts the configured time until it +issues the next SEND_QUEUE_STATUS. +Timer units are clock periods of the clock whose frequency is +specified in the Internal Timer Clock Frequency field CQCAP +register. The minimum value is 0001h (1 clock period) and +the maximum value is FFFFh (65535 clock periods). +For example, a CQCAP field value of 0 indicates a 19.2 MHz +clock frequency (period = 52.08 ns). If the setting in +CQSSC1.CIT is 1000h, the calculated polling period is +4096*52.08 ns= 213.33 ns. +Should be programmed only when CQCFG.CQ_EN is '0'. + [15:0] + read-write + + + SQSCMD_BLK_CNT + This field indicates when SQS CMD is sent while data +transfer is in progress. +A value of 'n' indicates that CQE sends status command on +the CMD line, during the transfer of data block BLOCK_CNTn, +on the data lines, where BLOCK_CNT is the number of +blocks in the current transaction. +- 0x0: SEND_QUEUE_STATUS (CMD13) command is not +sent during the transaction. Instead, it is sent only when +the data lines are idle. +- 0x1: SEND_QUEUE_STATUS command is to be sent +during the last block of the transaction. +- 0x2: SEND_QUEUE_STATUS command when last 2 +blocks are pending. +- 0x3: SEND_QUEUE_STATUS command when last 3 +blocks are pending. +- ........ +- 0xf: SEND_QUEUE_STATUS command when last 15 +blocks are pending. +Should be programmed only when CQCFG.CQ_EN is '0' + [19:16] + read-write + + + + + CQSSC2 + CQ Send Status Configuration 2 register + 0x1C4 + 32 + read-write + 0x0 + 0xFFFF + + + SQSCMD_RCA + This field provides CQE with the contents of the 16-bit RCA +field in SEND_QUEUE_STATUS (CMD13) command +argument. +CQE copies this field to bits 31:16 of the argument when +transmitting SEND_ QUEUE_STATUS (CMD13) command. + [15:0] + read-write + + + + + CQCRDCT + Command response for direct command register + 0x1C8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DCMD_RESP + This register contains the response of the command +generated by the last direct command (DCMD) task that was +sent. +Contents of this register are valid only after bit 31 of +CQTDBR register is cleared by the controller. + [31:0] + read-only + + + + + CQRMEM + Command response mode error mask register + 0x1D0 + 32 + read-write + 0xFDF9A080 + 0xFFFFFFFF + + + RESP_ERR_MASK + The bits of this field are bit mapped to the device response. +This bit is used as an interrupt mask on the device status +filed that is received in R1/R1b responses. +- 1: When a R1/R1b response is received, with a bit i in the +device status set, a RED interrupt is generated. +- 0: When a R1/R1b response is received, bit i in the device +status is ignored. +The reset value of this register is set to trigger an interrupt on +all 'Error' type bits in the device status. +Note: Responses to CMD13 (SQS) encode the QSR so that +they are ignored by this logic. + [31:0] + read-write + + + + + CQTERRI + CQ Task Error Information register + 0x1D4 + 32 + read-only + 0x0 + 0x9F3F9F3F + + + RESP_ERR_CMD_INDX + This field captures the index of the command that was +executed on the command line when the error occurred. + [5:0] + read-only + + + RESP_ERR_TASKID + This field captures the ID of the task which was executed on +the command line when the error occurred. + [12:8] + read-only + + + RESP_ERR_FIELDS_VALID + This bit is updated when an error is detected while a +command transaction was in progress. +Values: +- 0x1 (SET): Response-related error is detected. Check +contents of RESP_ERR_TASKID and +RESP_ERR_CMD_INDX fields +- 0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID +and RESP_ERR_CMD_INDX + [15:15] + read-only + + + TRANS_ERR_CMD_INDX + This field captures the index of the command that was +executed and whose data transfer has errors. + [21:16] + read-only + + + TRANS_ERR_TASKID + This field captures the ID of the task that was executed and +whose data transfer has errors. + [28:24] + read-only + + + TRANS_ERR_FIELDS_VALID + This bit is updated when an error is detected while a data +transfer transaction was in progress. +Values: +- 0x1 (SET): data transfer related error detected. Check +contents of TRANS_ERR_TASKID and +TRANS_ERR_CMD_INDX fields +- 0x0 (NOT_SET): Ignore contents of +TRANS_ERR_TASKID and TRANS_ERR_CMD_INDX + [31:31] + read-only + + + + + CQCRI + CQ Command response index + 0x1D8 + 32 + read-only + 0x0 + 0x3F + + + CMD_RESP_INDX + Last Command Response index +This field stores the index of the last received command +response. Controller updates the value every time a +command response is received. + [5:0] + read-only + + + + + CQCRA + CQ Command response argument register + 0x1DC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CMD_RESP_ARG + Last Command Response argument +This field stores the argument of the last received command +response. Controller updates the value every time a +command response is received. + [31:0] + read-only + + + + + MSHC_VER_ID_R + MSHC version + 0x500 + 32 + read-only + 0x3137302A + 0xFFFFFFFF + + + MSHC_VER_ID + Current release number +This field indicates the Synopsys DesignWare Cores +DWC_mshc/DWC_mshc_lite current release number that is +read by an application. +For example, release number '1.60a' is represented in +ASCII as 0x313630. Lower 8 bits read from this register can +be ignored by the application. +An application reading this register in conjunction with the +MSHC_VER_TYPE_R register, gathers details of the current +release. + [31:0] + read-only + + + + + MSHC_VER_TYPE_R + MSHC version type + 0x504 + 32 + read-only + 0x67612A2A + 0xFFFFFFFF + + + MSHC_VER_TYPE + Current release type +This field indicates the Synopsys DesignWare Cores +DWC_mshc/DWC_mshc_lite current release type that is +read by an application. +For example, release type is 'ga' is represented in ASCII as +0x6761. Lower 16 bits read from this register can be ignored +by the application. +An application reading this register in conjunction with the +MSHC_VER_ID_R register, gathers details of the current +release. + [31:0] + read-only + + + + + MSHC_CTRL_R + MSHC Control register + 0x508 + 8 + read-write + 0x1 + 0x11 + + + CMD_CONFLICT_CHECK + Command conflict check +This bit enables command conflict check. +Note: DWC_mshc controller monitors the CMD line +whenever a command is issued and checks whether the +value driven on sd_cmd_out matches the value on +sd_cmd_in at next subsequent edge of cclk_tx to determine +command conflict error. This bit is cleared only if the feed +back delay (including IO Pad delay) is more than +(t_card_clk_period - t_setup), where t_setup is the setup +time of a flop in DWC_mshc. The I/O pad delay is consistent +across CMD and DATA lines, and it is within the value: +(2*t_card_clk_period - t_setup) +Values: +- 0x0 (DISABLE_CMD_CONFLICT_CHK): Disable +command conflict check +- 0x1 (CMD_CONFLICT_CHK_LAT1): Check for command +conflict after 1 card clock cycle + [0:0] + read-write + + + SW_CG_DIS + Internal clock gating disable control +This bit must be used to disable IP's internal clock gating +when required. when disabled clocks are not gated. Clocks +to the core (except hclk) must be stopped when +programming this bit. +Values: +- 0x0 (ENABLE): Internal clock gates are active and clock +gating is controlled internally +- 0x1 (DISABLE): Internal clock gating is disabled, clocks +are not gated internally + [4:4] + read-write + + + + + MBIU_CTRL_R + MBIU Control register + 0x510 + 8 + read-write + 0x1 + 0xF + + + UNDEFL_INCR_EN + Undefined INCR Burst +Controls generation of undefined length INCR transfer on +Master interface. +Values: +- 0x0 (FALSE): Undefined INCR type burst is the least +preferred burst on AHB Master I/F +- 0x1 (TRUE): Undefined INCR type burst is the most +preferred burst on AHB Master I/F + [0:0] + read-write + + + BURST_INCR4_EN + INCR4 Burst +Controls generation of INCR4 transfers on Master interface. +Values: +- 0x0 (FALSE): AHB INCR4 burst type is not generated on +Master I/F +- 0x1 (TRUE): AHB INCR4 burst type can be generated on +Master I/F + [1:1] + read-write + + + BURST_INCR8_EN + INCR8 Burst +Controls generation of INCR8 transfers on Master interface. +Values: +- 0x0 (FALSE): AHB INCR8 burst type is not generated on +Master I/F +- 0x1 (TRUE): AHB INCR8 burst type can be generated on +Master I/F + [2:2] + read-write + + + BURST_INCR16_EN + INCR16 Burst +Controls generation of INCR16 transfers on Master +interface. +Values: +- 0x0 (FALSE): AHB INCR16 burst type is not generated on +Master I/F +- 0x1 (TRUE): AHB INCR16 burst type can be generated +on Master I/F + [3:3] + read-write + + + + + EMMC_CTRL_R + eMMC Control register + 0x52C + 16 + read-write + 0xC + 0x60F + + + CARD_IS_EMMC + eMMC Card present +This bit indicates the type of card connected. An application +program this bit based on the card connected to SDHC. +Values: +- 0x1 (EMMC_CARD): Card connected to SDHC is an +eMMC card +- 0x0 (NON_EMMC_CARD): Card connected to SDHC is +a non-eMMC card + [0:0] + read-write + + + DISABLE_DATA_CRC_CHK + Disable Data CRC Check +This bit controls masking of CRC16 error for Card Write in +eMMC mode. This is useful in bus testing (CMD19) for an +eMMC device. In bus testing, an eMMC card does not send +CRC status for a block, which may generate CRC error. This +CRC error can be masked using this bit during bus testing. +Values: +- 0x1 (DISABLE): DATA CRC check is disabled +- 0x0 (ENABLE): DATA CRC check is enabled + [1:1] + read-write + + + EMMC_RST_N + EMMC Device Reset signal control. +This register field controls the card_emmc_reset_n output of SDHC +Values: +- 0x1 (RST_DEASSERT): Reset to eMMC device is +deasserted +- 0x0 (RST_ASSERT): Reset to eMMC device asserted +(active low) + [2:2] + read-write + + + EMMC_RST_N_OE + Output Enable (OE) control for EMMC Device Reset signal (card_emmc_reset_n). +Values: +- 0x1 (ENABLE): OE for card_emmc_reset_n is 1 +- 0x0 (DISABLE): OE for card_emmc_reset_n is 0 + [3:3] + read-write + + + CQE_ALGO_SEL + Scheduler algorithm selected for execution +This bit selects the Algorithm used for selecting one of the +many ready tasks for execution. +Values: +- 0x0 (PRI_REORDER_PLUS_FCFS): Priority based +reordering with FCFS to resolve equal priority tasks +- 0x1 (FCFS_ONLY): First come First serve, in the order of +DBR rings + [9:9] + read-write + + + CQE_PREFETCH_DISABLE + Enable or Disable CQE's PREFETCH feature +This field allows Software to disable CQE's data prefetch +feature when set to 1. +Values: +- 0x0 (PREFETCH_ENABLE): CQE can Prefetch data for +sucessive WRITE transfers and pipeline sucessive READ +transfers +- 0x1 (PREFETCH_DISABLE): Prefetch for WRITE and +Pipeline for READ are disabled + [10:10] + read-write + + + + + BOOT_CTRL_R + eMMC Boot Control register + 0x52E + 16 + read-write + 0x0 + 0xF181 + + + MAN_BOOT_EN + Mandatory Boot Enable +This bit is used to initiate the mandatory boot operation. The +application sets this bit along with VALIDATE_BOOT bit. +Writing 0 is ignored. The SDHC clears this bit after the +boot transfer is completed or terminated. +Values: +- 0x1 (MAN_BOOT_EN): Mandatory boot enable +- 0x0 (MAN_BOOT_DIS): Mandatory boot disable + [0:0] + read-write + + + VALIDATE_BOOT + Validate Mandatory Boot Enable bit +This bit is used to validate the MAN_BOOT_EN bit. +Values: +- 0x1 (TRUE): Validate Mandatory boot enable bit +- 0x0 (FALSE): Ignore Mandatory boot Enable bit + [7:7] + write-only + + + BOOT_ACK_ENABLE + Boot Acknowledge Enable +When this bit set, SDHC checks for boot acknowledge +start pattern of 0-1-0 during boot operation. This bit is +applicable for both mandatory and alternate boot mode. +Values: +- 0x1 (TRUE): Boot Ack enable +- 0x0 (FALSE): Boot Ack disable + [8:8] + read-write + + + BOOT_TOUT_CNT + N/A + [15:12] + read-write + + + + + GP_IN_R + General Purpose Input register + 0x530 + 32 + read-only + 0x0 + 0x1 + + + GP_IN + It reflects the value of gp_in ports. +NOT USED - ALWAYS READS 0 + [0:0] + read-only + + + + + GP_OUT_R + General Purpose Output register + 0x534 + 32 + read-write + 0x0 + 0x3FF + + + CARD_DETECT_EN + 0: Force card_detect_n input to 0 +1: Normal card_detect_n operation allowing card detection from a device pin + [0:0] + read-write + + + CARD_MECH_WRITE_PROT_EN + card_mech_write_prot, despite its name, is an active low signal (per the SD Host Controller Standard spec it is officially called SDWP#). Consider that in the following: +0: Force card_mech_write_prot input to 0 internally; this forces write protection to be active +1: Allow card_mech_write_prot to work normally per the device's pin state + [1:1] + read-write + + + LED_CTRL_OE + Active high output enable for the LED output signal (led_ctrl) controlled through HOST_CTRL1_R.LED_CTRL: +0: disable OE associated with the led_ctrl output +1: enable OE associated with the led_ctrl output + [2:2] + read-write + + + CARD_CLOCK_OE + Active high output enable for the card clock output (clk_card) which is gated by CLK_CTRL_R.SD_CLK_EN: +0: disable OE to the clk_card output +1: enable OE to the clk_card output + [3:3] + read-write + + + CARD_IF_PWR_EN_OE + Active high output enable for the card interface power enable output (card_if_pwr_en) controlled through PWR_CTRL_R.SD_BUS_PWR_VDD1: +0: disable OE to the card_if_pwr_en output +1: enable OE to the card_if_pwr_en output + [4:4] + read-write + + + IO_VOLT_SEL_OE + Active high output enable for the IO voltage selection signal (io_volt_sel) controlled through HOST_CTRL_2.SIGNALING_EN: +0: disable OE to the io_volt_sel output +1: enable OE to the io_volt_sel output + [5:5] + read-write + + + CARD_CLOCK_OUT_DLY + N/A + [7:6] + read-write + + + CARD_CLOCK_IN_DLY + Delay CARD_CLOCK input internally to optimally sample CMD/DAT; set according to interface mode: +00: SD Default Speed, SD SDR12, eMMC Legacy +01: SD SDR25, SD SDR50 +10: SD High Speed, eMMC High Speed SDR +11: SD DDR50, eMMC DDR + [9:8] + read-write + + + + + + + + ETH0 + Ethernet Interface + ETH + 0x40480000 + + 0 + 65536 + registers + + + + CTL + MXETH Control Register + 0x0 + 32 + read-write + 0x0 + 0x8000FF07 + + + ETH_MODE + Set ethernet mode. The speed of 10M/100M/1G is selected by programming network_config after IP is enabled. +The field also specifies the clock source of internal tx_clk and rx_clk domain. + [1:0] + read-write + + + MII + MII mode (10/100MHz speed is determined by network_config[0]). + 0 + + + GMII + GMII mode (network_config[10] must be set to enable 1G operation). + 1 + + + RGMII + RGMII mode (10M/100M/1G speed is determined by network_config[10] and network_config[0]). + 2 + + + RMII + RMII mode (10M/100M speed is determined by network_config[0]). + 3 + + + + + REFCLK_SRC_SEL + Select the source for ref_clk. +0: Ref_clk comes from REF_CLK_IN input port (HSIO). +1: Ref_clk comes from REF_CLK_INT_IN input port (PLL). + [2:2] + read-write + + + REFCLK_DIV + Specify the ref_clk divider. Integer division by (1+REFCLK_DIV). Allows for integer divisions in the range [1, 256]. + [15:8] + read-write + + + ENABLED + MXETH enable: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + STATUS + MXETH Status Register + 0x4 + 32 + read-only + 0x0 + 0xFF01 + + + PFC_NEGOTIATE + Identifies that PFC priority based pause flow control +has been negotiated. +0 - No PFC priority based pause frames have yet +been received, flow control is being handled using +classic 802.3 pause frames. +1 - At least one PFC priority based pause frames +has been received. All subsequent 802.3 pause +frames will be dropped. + [0:0] + read-only + + + RX_PFC_PAUSED + Each bit corresponds to a priority indicated within the PFC priority based pause frame. +Each bit is set when a PFC priority based pause frame has been received, and the associated priority pause time quantum is non-zero. Each bit is cleared when the associated pause time identified by the received pause time quantum has elapsed. + [15:8] + read-only + + + + + NETWORK_CONTROL + The network control register contains general MAC control functions for both receiver and transmitter. + 0x1000 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + LOOPBACK + Loopback - controls the loopback output pin. + [0:0] + read-write + + + LOOPBACK_LOCAL + Loopback local - asserts the loopback_local signal to the system clock generator. Also connects txd to rxd, tx_en to rx_dv and forces full duplex mode. Bit 11 of the network configuration register must be set low to disable TBI mode when in internal loopback. rx_clk and tx_clk may malfunction as the GEM is switched into and out of internal loopback. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loopback. Local loopback functionality is optional and may not be supported by some instantiations of the GEM. + [1:1] + read-write + + + ENABLE_RECEIVE + Receive enable - when set, it enables the GEM to receive data. When reset frame reception will stop immediately and the receive pipeline will be cleared. The receive queue pointer register is unaffected. + [2:2] + read-write + + + ENABLE_TRANSMIT + Transmit enable - when set, it enables the GEM transmitter to send data. When reset transmission will stop immediately, the transmit pipeline and control registers will be cleared and the transmit queue pointer register will reset to point to the start of the transmit descriptor list. + [3:3] + read-write + + + MAN_PORT_EN + Management port enable - set to one to enable the management port. When zero forces mdio to high impedance state and mdc low. + [4:4] + read-write + + + CLEAR_ALL_STATS_REGS + Clear statistics registers - this bit is write only. Writing a one clears the statistics registers. Self clearing register. + [5:5] + write-only + + + INC_ALL_STATS_REGS + Incremental statistics registers - this bit is write only. Writing a one increments all the statistics registers by one for test purposes. Self clearing register. + [6:6] + write-only + + + STATS_WRITE_EN + Write enable for statistics registers - setting this bit to one means the statistics registers can be written for functional test purposes. + [7:7] + read-write + + + BACK_PRESSURE + Back pressure if set in 10M or 100M half duplex mode will force collisions on all received frames. Ignored in gigabit half duplex mode. + [8:8] + read-write + + + TX_START_PCLK + Start transmission - writing one to this bit starts transmission. + [9:9] + write-only + + + TX_HALT_PCLK + Transmit halt - writing one to this bit halts transmission as soon as any ongoing frame transmission ends. + [10:10] + write-only + + + TX_PAUSE_FRAME_REQ + Transmit pause frame - writing one to this bit causes a pause frame to be transmitted. Self clearing register. + [11:11] + write-only + + + TX_PAUSE_FRAME_ZERO + Transmit zero quantum pause frame - writing one to this bit causes a pause frame with zero quantum to be transmitted. + [12:12] + write-only + + + REMOVED_13 + Write ignore, read 0 + [13:13] + read-only + + + REMOVED_14 + Write ignore, read 0 + [14:14] + read-only + + + STORE_RX_TS + Store receive time stamp to memory. Setting this bit to one will cause the CRC of every received frame to be replaced with the value of the nanoseconds field of the 1588 timer that was captured as the receive frame passed the message time stamp point. Set to zero for normal operation. + [15:15] + read-write + + + PFC_ENABLE + Enable PFC Priority Based Pause Reception capabilities. Setting this bit will enable PFC negotiation and recognition of priority based pause frames. + [16:16] + read-write + + + TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME + Write a one to transmit PFC priority based pause frame. Takes the values stored in the Transmit PFC Pause Register. Self clearing register. + [17:17] + write-only + + + FLUSH_RX_PKT_PCLK + Flush the next packet from the external RX DPRAM. Writing one to this bit will only have an effect if the DMA is not currently writing a packet already stored in the DPRAM to memory. Self clearing register. + [18:18] + write-only + + + TX_LPI_EN + Enable LPI transmission when set LPI (low power idle) is immediately transmitted. LPI is transmitted even if bit 3 transmit enable is disabled. Setting this bit also sends a pause signal to the transmit datapath. + [19:19] + read-write + + + PTP_UNICAST_ENA + Enable detection of unicast PTP unicast frames. + [20:20] + read-write + + + ALT_SGMII_MODE + Alternative sgmii mode. If asserted with sgmii_mode in the network control register the ACK bit is driven before ability detect during transfer of status information from the PHY to the MAC. + [21:21] + read-write + + + STORE_UDP_OFFSET + N/A + [22:22] + read-write + + + EXT_TSU_PORT_ENABLE + Write ignore, read 0 + [23:23] + read-only + + + ONE_STEP_SYNC_MODE + 1588 One Step Sync Mode. Write 1 to enable. Replace timestamp field in the 1588 header for TX Sync Frames with current TSU timer value. + [24:24] + read-write + + + PFC_CTRL + 'Enable multiple PFC pause quantums, one per pause priority' + [25:25] + read-write + + + EXT_RXQ_SEL_EN + Enable external selection of receive queue. When this bit is high the ext_match1, ext_match2, ext_match3 and ext_match4 inputs will determine which receive queue a frame is routed to. This will be the case regardless of the state of the external address match +enable bit 9 of the network config register. Note that receive frames will be dropped unless they are matched by the internal frame filtering functionality. If the external address match enable bit 9 in the network config register is set frames may be matched by an +external address match filter as long as one of the ext_match1, ext_match2, ext_match3 and ext_match4 inputs is asserted early enough. When set ext_rxq_sel_en takes precedence over the existing screener functionality. This bit is only relevant if priority +queuing is configured. + [26:26] + read-write + + + OSS_CORRECTION_FIELD + 1588 One Step Correction Field Update. Set this bit +high to enable updating the correction field of PTP +1588 version 2 sync frames by adding current TSU +timer value. + [27:27] + read-write + + + SEL_MII_ON_RGMII + If the RGMII interface being used set this bit high to +configure the interface for MII operation. + [28:28] + read-write + + + TWO_PT_FIVE_GIG + 2.5G operation selected - setting this bit high drives +the speed_mode[3] top level output pin high and also +adjusts the link timer in the PCS auto-negotiation block +to ensure it delivers 10ms for 2500BASE-X and 1.6ms +in SGMII mode, and also ensures int_moderation +counts 800ns periods with the speeded up MAC +clocks. + [29:29] + read-write + + + IFG_EATS_QAV_CREDIT + Setting this bit high modifies the CBS algorithm so the +IFG/IPG associated with a transmit frame counts +towards its 802.1Qav credit. + [30:30] + read-write + + + EXT_RXQ_RSVD_31 + N/A + [31:31] + read-only + + + + + NETWORK_CONFIG + The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC. + 0x1004 + 32 + read-write + 0x2C0000 + 0xFFFFFFFF + + + SPEED + Speed - set to logic one to indicate 100Mbps operation, logic zero for 10Mbps. + [0:0] + read-write + + + FULL_DUPLEX + Full duplex - if set to logic one, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the half_duplex pin. + [1:1] + read-write + + + DISCARD_NON_VLAN_FRAMES + Discard non-VLAN frames - when set only VLAN tagged frames will be passed to the address matching logic. + [2:2] + read-write + + + JUMBO_FRAMES + Jumbo frames - set to one to enable jumbo frames up to `gem_jumbo_max_length bytes to be accepted. The default length is 10,240 bytes. + [3:3] + read-write + + + COPY_ALL_FRAMES + Copy all frames - when set to logic one, all valid frames will be accepted. + [4:4] + read-write + + + NO_BROADCAST + No broadcast - when set to logic one, frames addressed to the broadcast address of all ones will not be accepted. + [5:5] + read-write + + + MULTICAST_HASH_ENABLE + Multicast hash enable - when set, multicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register. + [6:6] + read-write + + + UNICAST_HASH_ENABLE + Unicast hash enable - when set, unicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register. + [7:7] + read-write + + + RECEIVE_1536_BYTE_FRAMES + Receive 1536 byte frames - setting this bit means the GEM will accept frames up to 1536 bytes in length. Normally the GEM would reject any frame above 1518 bytes. + [8:8] + read-write + + + EXTERNAL_ADDRESS_MATCH_ENABLE + External address match enable - when set the external address match interface can be used to copy frames to memory. + [9:9] + read-write + + + GIGABIT_MODE_ENABLE + Gigabit mode enable - setting this bit configures the GEM for 1000 Mbps operation. + 0: 10/100 operation using MII interface + 1: Gigabit operation using GMI interface + [10:10] + read-write + + + PCS_SELECT + PCS select - selects between MII/GMII and TBI + [11:11] + read-write + + + RETRY_TEST + Retry test - must be set to zero for normal operation. If set to one the backoff between collisions will always be one slot time. Setting this bit to one helps test the too many retries condition. Also used in the pause frame tests to reduce the pause counter's decrement time from 512 bit times, to every rx_clk cycle. + [12:12] + read-write + + + PAUSE_ENABLE + Pause enable - when set, transmission will pause if a non zero 802.3 classic pause frame is received and PFC has not been negotiated. + [13:13] + read-write + + + RECEIVE_BUFFER_OFFSET + Receive buffer offset - indicates the number of bytes by which the received data is offset from the start of the receive buffer. + [15:14] + read-write + + + LENGTH_FIELD_ERROR_FRAME_DISCARD + Length field error frame discard - setting this bit causes frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and 14 in a non-VLAN tagged frame) to be discarded. This only applies to frames with a length field less than 0x0600. + [16:16] + read-write + + + FCS_REMOVE + FCS remove - setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). The frame length indicated will be reduced by four bytes in this mode. + [17:17] + read-write + + + MDC_CLOCK_DIVISION + MDC clock division - set according to pclk speed. These three bits determine the number pclk will be divided by to generate MDC. For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations). The reset value for this can be changed by defining a new value for gem_mdc_clock_div in gem_defs.v + 000: divide pclk by 8 (pclk up to 20 MHz) + 001: divide pclk by 16 (pclk up to 40 MHz) + 010: divide pclk by 32 (pclk up to 80 MHz) + 011: divide pclk by 48 (pclk up to 120MHz) + 100: divide pclk by 64 (pclk up to 160 MHz) + 101: divide pclk by 96 (pclk up to 240 MHz) + 110: divide pclk by 128 (pclk up to 320 MHz) + 111: divide pclk by 224 (pclk up to 540 MHz). +Note. The reset value of this field is equal to the gem_mdc_clock_div define, which is user configurable. + [20:18] + read-write + + + DATA_BUS_WIDTH + Data bus width - set according to AMBA (AXI/AHB) or external FIFO data bus width. The reset value for this can be changed by defining a new value for gem_dma_bus_width_def in gem_defs. Only valid bus widths may be written if the system is configured to a maximum width less than 128-bits. + 00: 32 bit data bus width 01: 64 bit AMBA (AXI/AHB) data bus width + 10: 128 bit AMBA (AXI/AHB) data bus width + 11: 128 bit AMBA (AXI/AHB) data bus width. +Note. The reset value of this field is equal to the gem_dma_bus_width_def define, which is user configurable. +Note: +For AXI_MASTER_PRESENT=1, MXETH only supports 64b DMA data bus width, so must set it 1. +For AXI_MASTER_PRESENT=0, MXETH only supports 32b DMA data bus width, so must set it 0. + [22:21] + read-write + + + DISABLE_COPY_OF_PAUSE_FRAMES + Disable copy of pause frames - set to one to prevent pause frames being copied to memory. When set, neither control frames with type id 8808, nor pause frames with destination address 010000c28001 are copied to memory, this functionality was enhanced in release 1p09 (mxeth uses 1p09). Note that valid pause frames received will still increment pause statistics and pause the transmission of frames as required. + [23:23] + read-write + + + RECEIVE_CHECKSUM_OFFLOAD_ENABLE + Receive checksum offload enable - when set, the receive checksum engine is enabled. Frames with bad IP, TCP or UDP checksums are discarded. + [24:24] + read-write + + + EN_HALF_DUPLEX_RX + Enable frames to be received in half-duplex mode while transmitting. +Must set '0', MXETH only supports full-duplex mode. + [25:25] + read-write + + + IGNORE_RX_FCS + Ignore RX FCS - when set frames with FCS/CRC errors will not be rejected. FCS error statistics will still be collected for frames with bad FCS and FCS status will be recorded in frame's DMA descriptor. For normal operation this bit must be set to zero. + [26:26] + read-write + + + SGMII_MODE_ENABLE + SGMII mode enable - changes behaviour of the auto-negotiation advertisement and link partner ability registers to meet the requirements of SGMII and reduces the duration of the link timer from 10 ms to 1.6 ms. + [27:27] + read-write + + + IPG_STRETCH_ENABLE + IPG stretch enable - when set the transmit IPG can be increased above 96 bit times depending on the previous frame length using the IPG stretch register. + [28:28] + read-write + + + NSP_CHANGE + Receive bad preamble. When set frames with non-standard preamble are not rejected. + [29:29] + read-write + + + IGNORE_IPG_RX_ER + Ignore IPG rx_er. When set rx_er has no effect on the GEMs operation when rx_dv is low. Set this when using the RGMII wrapper in half-duplex mode. + [30:30] + read-write + + + RSVD_31 + N/A + [31:31] + read-write + + + + + NETWORK_STATUS + The network status register returns status information with respect to the PHY management interface. + 0x1008 + 32 + read-only + 0x6 + 0xFF + + + PCS_LINK_STATE + Returns status of PCS link state. If auto-negotiation is disabled this returns the synchronisation status. If auto-negotiation is enabled it is set in the LINK_OK state as long as a compatible duplex mode is resolved. + [0:0] + read-only + + + MDIO_IN + Returns status of the mdio_in pin. + [1:1] + read-only + + + MAN_DONE + The PHY management logic is idle (i.e. has completed). + [2:2] + read-only + + + MAC_FULL_DUPLEX + PCS auto-negotiation duplex resolution. Set to one if the resolution function determines that both devices are capable of full duplex operation. If zero half-duplex operation is possible as long as bit 0 (PCS link state) is also one. + [3:3] + read-only + + + REMOVED_5_4 + N/A + [5:4] + read-only + + + PFC_NEGOTIATE_PCLK + Set when PFC Priority Based Pause has been negotiated. + [6:6] + read-only + + + LPI_INDICATE_PCLK + LPI Indication - Low power idle has been detected on receive. This bit is set when LPI is detected and reset when normal idle is detected. An interrupt is generated when the state of this bit changes. + [7:7] + read-only + + + + + USER_IO_REGISTER + Not presents. Access to the register will return AHB error. + 0x100C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RSVD_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + DMA_CONFIG + DMA Configuration Register + 0x1010 + 32 + read-write + 0x180704 + 0x77FF3FFF + + + AMBA_BURST_LENGTH + Selects the burst length to use on the AMBA (AHB/AXI) when transferring frame data. Not used for DMA management operations and only used where space and data size allow and respecting AXI/AHB burst boundary rules. One-hot priority encoding enforced automatically on register writes as follows, where x represents don't care: + 1xxxx: Attempt to use bursts of up to 16. + 01xxx: Attempt to use bursts of up to 8. + 001xx: Attempt to use bursts of up to 4. + 0001x: Always use SINGLE bursts. + 00001: Always use SINGLE bursts. + 00000: Attempt to use bursts of up to 256. +Note: MXETH only supports burst length up to 16. + [4:0] + read-write + + + HDR_DATA_SPLITTING_EN + Enable header data Splitting. When set, receive frames will be forwarded to main memory using a minimum of two DMA data buffers. The first X data buffers will contain the frame header, consisting of the Ethernet,VLAN,(IPv4 or IPv6),(TCP or UDP). X= (frame header size divided by rx_buf_size as defined in bits 23:16 of this register). The last Y data buffers will contain the frame payload. Y= (frame payload size divided by rx_buf_size). Note that for non VLAN/IP/TCP/UDP frames, the header will always be 14 bytes. When this feature is disabled, the frame is forwarded to main memory in blocks of rx_buf_size. +Note: For AXI_MASTER_PRESENT=0 i.e. AHB master support, this feature cannot be set. + [5:5] + read-write + + + ENDIAN_SWAP_MANAGEMENT + endian swap mode enable for management descriptor accesses. When set, selects swapped endianism for AMBA (AXI/AHB) transfers. When clear, selects little endian mode. Note, the default value of this bit equals to `gem_endian_swap_def, which is design time configuration. + [6:6] + read-write + + + ENDIAN_SWAP_PACKET + endian swap mode enable for packet data accesses. When set, selects swapped endianism for AMBA (AXI/AHB) transfers. When clear, selects little endian mode. Note, the default value of this bit equals to `gem_endian_swap_def, which is design time configuration. + [7:7] + read-write + + + RX_PBUF_SIZE + N/A + [9:8] + read-write + + + TX_PBUF_SIZE + N/A + [10:10] + read-write + + + TX_PBUF_TCP_EN + N/A + [11:11] + read-write + + + INFINITE_LAST_DBUF_SIZE_EN + Forces the DMA to consider the data buffer pointed to by last descriptor in the descriptor list to be of infinite size. + [12:12] + read-write + + + CRC_ERROR_REPORT + When the bit is set, bit 16 of the receive buffer descriptor will represent FCS/CRC error (only if frames with FCS are copied to memory as enabled by bit 26 in the network config register). When this bit is clear, bit 16 of the receive buffer descriptor will represent the Canonical format indicator (CFI) bit as extracted from the receive frame (if the receive buffer descriptor is pointing to the last data buffer of the receive frame and the received frame was VLAN tagged). + [13:13] + read-write + + + RX_BUF_SIZE + DMA receive buffer size in external AMBA (AXI/AHB) system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes. + 0x01 corresponds to buffers of 64 bytes + 0x02 corresponds to 128 bytes etc. +For example: + 0x02: 128 byte. + 0x18: 1536 byte (1*max length frame/buffer) + 0xA0: 10240 byte (1*10K jumbo frame/buffer) +Note that this value should never be written as zero. +Note. The reset value of this field is equal to the gem_rx_buffer_length_def define, which is user configurable. + [23:16] + read-write + + + FORCE_DISCARD_ON_ERR + Auto Discard RX pkts during lack of resource. When set, the GEM DMA will automatically discard receive packets from the receiver packet buffer memory when no AMBA (AXI/AHB) resource is available. When low, then received packets will remain to be stored in the SRAM based packet buffer until AMBA (AXI/AHB) buffer resource next becomes available. A write to this bit is ignored if the DMA is not configured in the packet buffer full store and forward mode. + [24:24] + read-write + + + FORCE_MAX_AMBA_BURST_RX + Force max length bursts on RX. Force the RX DMA to always issue max length bursts on EOP(end of packet) or EOB(end of buffer)transfers, even if there is less than max burst real packet data required to write. Any extra bytes of pad data is set to 0x00. Does not apply on bursts that break 1k boundary rule. + [25:25] + read-write + + + FORCE_MAX_AMBA_BURST_TX + Force max length bursts on TX. Force the TX DMA to always issue max length bursts on EOP(end of packet) or EOB(end of buffer) transfers as defined by bits 4:0 of this register, even when there is less that max burst data bytes to read. Residual data read is ignored. Does not apply on bursts that break 1k boundary rule. + [26:26] + read-write + + + RX_BD_EXTENDED_MODE_EN + Enable RX extended BD mode. See RX BD control register definition for description of feature. + [28:28] + read-write + + + TX_BD_EXTENDED_MODE_EN + Enable TX extended BD mode. See TX BD control register definition for description of feature. + [29:29] + read-write + + + DMA_ADDR_BUS_WIDTH_1 + DMA address bus width. 0 = 32b, 1 = 64b. MXETH only supports 32b DMA address bus width, so must set it 0. + [30:30] + read-write + + + + + TRANSMIT_STATUS + This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register. + 0x1014 + 32 + read-write + 0x0 + 0x1FF + + + USED_BIT_READ + Used bit read - set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit. + [0:0] + read-write + + + COLLISION_OCCURRED + Collision occurred - set by the assertion of collision. Cleared by writing a one to this bit. When operating in 10/100 mode, this status indicates either a collision or a late collision. In gigabit mode, this status is not set for a late collision. + [1:1] + read-write + + + RETRY_LIMIT_EXCEEDED + Retry limit exceeded - cleared by writing a one to this bit. + [2:2] + read-write + + + TRANSMIT_GO + Transmit go - if high transmit is active. When using the exposed FIFO interface, this bit represents bit 3 of the network control register. When using the DMA interface this bit represents the tx_go variable as specified in the transmit buffer description. + [3:3] + read-only + + + AMBA_ERROR123 + Transmit frame corruption due to AMBA (AXI/AHB) errors. Set if an error occurs whilst midway through reading transmit frame from external memory including RRESP or BRESP errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted). Also set in DMA packet buffer mode if single frame is too large for configured packet buffer memory size. Cleared by writing a one to this bit. + [4:4] + read-write + + + TRANSMIT_COMPLETE123 + Transmit complete - set when a frame has been transmitted. Cleared by writing a one to this bit. + [5:5] + read-write + + + TRANSMIT_UNDER_RUN123 + Transmit under run - this bit is set if the transmitter was forced to terminate a frame that it had already began transmitting due to further data being unavailable. This bit is set if a transmitter status write back has not completed when another status write back is attempted. When using the DMA interface configured for packet buffer mode, this bit will never be set. Cleared by writing a 1. + [6:6] + read-write + + + LATE_COLLISION_OCCURRED + Late collision occurred - only set if the condition occurs in gigabit mode, as retry is not attempted. Cleared by writing a one to this bit. + [7:7] + read-write + + + RESP_NOT_OK123 + bresp/hresp not OK - set when the DMA block sees bresp/hresp not OK. Cleared by writing a one to this bit. + [8:8] + read-write + + + + + RECEIVE_Q_PTR + This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA (AXI) operation, the receive descriptors are read from memory using a single 32bit AXI access. When the datapath is configured at 64bit, the receive descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64bit AXI access. + 0x1018 + 32 + read-write + 0x0 + 0xFFFFFFFD + + + DMA_RX_DIS_Q + Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while receive is not enabled. + [0:0] + read-write + + + DMA_RX_Q_PTR + Receive buffer queue base address - written with the address of the start of the receive queue. + [31:2] + read-write + + + + + TRANSMIT_Q_PTR + This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit, the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access. + 0x101C + 32 + read-write + 0x0 + 0xFFFFFFFD + + + DMA_TX_DIS_Q + Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled. + [0:0] + read-write + + + DMA_TX_Q_PTR + Transmit buffer queue base address - written with the address of the start of the transmit queue. + [31:2] + read-write + + + + + RECEIVE_STATUS + This register, when read provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register. + 0x1020 + 32 + read-write + 0x0 + 0xF + + + BUFFER_NOT_AVAILABLE + Buffer not available - an attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA will reread the pointer each time an end of frame is received until a valid pointer is found. This bit is set following each descriptor read attempt that fails, even if consecutive pointers are unsuccessful and software has in the mean time cleared the status flag. Cleared by writing a one to this bit. + [0:0] + read-write + + + FRAME_RECEIVED + Frame received - one or more frames have been received and placed in memory. Cleared by writing a one to this bit. + [1:1] + read-write + + + RECEIVE_OVERRUN123 + Receive overrun - this bit is set if either the gem_dma RX FIFO or external RX FIFO were unable to store the receive frame due to a FIFO overflow, or if the receive status, reported by the gem_rx module to the gem_dma was not taken at end of frame. This bit is also set in DMA packet buffer mode if the packet buffer overflows. For DMA operation the buffer will be recovered if an overrun occurs. This bit is cleared by writing a one to it. + [2:2] + read-write + + + RESP_NOT_OK1234 + bresp not OK - set when the DMA block sees bresp/hresp not OK. Cleared by writing a one to this bit. + [3:3] + read-write + + + + + INT_STATUS + If not configured for priority queueing, the GEM generates a single interrupt. This register indicates the source of this interrupt. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the ethernet_int signal will be asserted. For test purposes each bit can be set or reset by writing to the interrupt mask register. The default configuration is shown below whereby all bits are reset to zero on read. Changing the validity of the `gem_irq_read_clear define will instead require a one to be written to the appropriate bit in order to clear it. In this mode reading has no affect on the status of the bit. + 0x1024 + 32 + read-write + 0x0 + 0x3FFFFEFF + + + MANAGEMENT_FRAME_SENT + Management frame sent - the PHY maintenance register has completed its operation. Cleared on read. + [0:0] + read-write + + + RECEIVE_COMPLETE + Receive complete - a frame has been stored in memory. Cleared on read. + [1:1] + read-write + + + RX_USED_BIT_READ + RX used bit read - set when a receive buffer descriptor is read with its used bit set. Cleared on read. + [2:2] + read-write + + + TX_USED_BIT_READ + TX used bit read - set when a transmit buffer descriptor is read with its used bit set. Cleared on read. + [3:3] + read-write + + + TRANSMIT_UNDER_RUN + Transmit under run - this interrupt is set if the transmitter was forced to terminate a frame that it has already began transmitting due to further data being unavailable. If an under run occurs, the transmitter will force bad crc and tx_er high. This interrupt is set if a transmitter status write back has not completed when another status write back is attempted. When using the DMA interface configured for internal FIFO mode, this interrupt is also set when the transmit DMA has written the SOP data into the FIFO and either the AHB bus was not granted in time for further data, or because an AHB/AXI error response was returned by the connected slave, or because a used bit was read. When using the DMA interface configured for packet buffer mode, this bit will never be set. When using the external FIFO interface, this interrupt is also set when the tx_r_underflow input was asserted during a frame transfer. Cleared on read. + [4:4] + read-write + + + RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION + Retry limit exceeded or late collision - transmit error. Late collision will only cause this status bit to be set in gigabit mode (as a retry is not attempted). Cleared on read. + [5:5] + read-write + + + AMBA_ERROR + Transmit frame corruption due to AMBA (AXI/AHB) error. Set if an error occurs whilst midway through reading transmit frame from external system memory, including HRESP (AHB), RRESP or BRESP(AXI) errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted). Also set in DMA packet buffer mode if single frame is too large for configured packet buffer memory size. Cleared on a read. + [6:6] + read-write + + + TRANSMIT_COMPLETE + Transmit complete - set when a frame has been transmitted. Cleared on read. + [7:7] + write-only + + + REMOVED_9 + Write ignore, read 0 + [9:9] + read-only + + + RECEIVE_OVERRUN + Receive overrun - set when the receive overrun status bit gets set. Cleared on read. + [10:10] + write-only + + + RESP_NOT_OK + bresp not OK - set when the DMA block sees bresp not OK. Cleared on read. + [11:11] + write-only + + + PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED + Pause frame with non-zero pause quantum received - indicates a valid pause has been received that has a non-zero pause quantum field. Cleared on read. + [12:12] + write-only + + + PAUSE_TIME_ELAPSED + Pause Time elapsed. set when either the pause time register at address 0x38 decrements to zero, or when a valid pause frame is received with a zero pause quantum field. Cleared on read. + [13:13] + write-only + + + PAUSE_FRAME_TRANSMITTED + Pause frame transmitted - indicates a pause frame has been successfully transmitted after being initiated from the network control register or from the tx_pause control pin. Cleared on read. + [14:14] + write-only + + + REMOVED_15 + Write ignore, read 0 + [15:15] + read-only + + + REMOVED_16 + Write ignore, read 0 + [16:16] + read-only + + + REMOVED_17 + Write ignore, read 0 + [17:17] + read-only + + + PTP_DELAY_REQ_FRAME_RECEIVED + PTP delay_req frame received indicates a PTP delay_req frame has been received. Cleared on read. + [18:18] + write-only + + + PTP_SYNC_FRAME_RECEIVED + PTP sync frame received indicates a PTP sync frame has been received. Cleared on read. + [19:19] + write-only + + + PTP_DELAY_REQ_FRAME_TRANSMITTED + PTP delay_req frame transmitted indicates a PTP delay_req frame has been transmitted. Cleared on read. + [20:20] + write-only + + + PTP_SYNC_FRAME_TRANSMITTED + PTP sync frame transmitted indicates a PTP sync frame has been transmitted. Cleared on read. + [21:21] + write-only + + + PTP_PDELAY_REQ_FRAME_RECEIVED + PTP pdelay_req frame received indicates a PTP pdelay_req frame has been received. Cleared on read. + [22:22] + write-only + + + PTP_PDELAY_RESP_FRAME_RECEIVED + PTP pdelay_resp frame received indicates a PTP pdelay_resp frame has been received. Cleared on read. + [23:23] + write-only + + + PTP_PDELAY_REQ_FRAME_TRANSMITTED + PTP pdelay_req frame transmitted indicates a PTP pdelay_req frame has been transmitted. Cleared on read. + [24:24] + write-only + + + PTP_PDELAY_RESP_FRAME_TRANSMITTED + PTP pdelay_resp frame transmitted indicates a PTP pdelay_resp frame has been transmitted. Cleared on read. + [25:25] + write-only + + + TSU_SECONDS_REGISTER_INCREMENT + TSU seconds register increment indicates the register has incremented. Cleared on read. + [26:26] + write-only + + + RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE + Receive LPI indication status bit change + [27:27] + write-only + + + REMOVED_28 + Write ignore, read 0 + [28:28] + read-only + + + TSU_TIMER_COMPARISON_INTERRUPT + TSU timer comparison interrupt. Indicates when TSU timer count value is equal to programmed value. + [29:29] + write-only + + + + + INT_ENABLE + At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero. + 0x1028 + 32 + write-only + 0x0 + 0x3FFFFFFF + + + ENABLE_MANAGEMENT_DONE_INTERRUPT + Enable management done interrupt + [0:0] + write-only + + + ENABLE_RECEIVE_COMPLETE_INTERRUPT + Enable receive complete interrupt + [1:1] + write-only + + + ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT + Enable receive used bit read interrupt + [2:2] + write-only + + + ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT + Enable transmit used bit read interrupt + [3:3] + write-only + + + ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT + Enable transmit buffer under run interrupt + [4:4] + write-only + + + ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT + Enable retry limit exceeded or late collision interrupt + [5:5] + write-only + + + ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT + Enable transmit frame corruption due to AMBA (AXI/AHB) error interrupt + [6:6] + write-only + + + ENABLE_TRANSMIT_COMPLETE_INTERRUPT + Enable transmit complete interrupt + [7:7] + write-only + + + UNUSED_8 + Not used + [8:8] + write-only + + + UNUSED_9 + Not used + [9:9] + write-only + + + ENABLE_RECEIVE_OVERRUN_INTERRUPT + Enable receive overrun interrupt + [10:10] + write-only + + + ENABLE_RESP_NOT_OK_INTERRUPT + Enable bresp not OK interrupt + [11:11] + write-only + + + ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT + Enable pause frame with non-zero pause quantum interrupt + [12:12] + write-only + + + ENABLE_PAUSE_TIME_ZERO_INTERRUPT + Enable pause time zero interrupt + [13:13] + write-only + + + ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT + Enable pause frame transmitted interrupt + [14:14] + write-only + + + UNUSED_15 + Not used + [15:15] + write-only + + + UNUSED_16 + Not used + [16:16] + write-only + + + UNUSED_17 + Not used + [17:17] + write-only + + + ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED + Enable PTP delay_req frame received + [18:18] + write-only + + + ENABLE_PTP_SYNC_FRAME_RECEIVED + Enable PTP sync frame received + [19:19] + write-only + + + ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED + Enable PTP delay_req frame transmitted + [20:20] + write-only + + + ENABLE_PTP_SYNC_FRAME_TRANSMITTED + Enable PTP sync frame transmitted + [21:21] + write-only + + + ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED + Enable PTP pdelay_req frame received + [22:22] + write-only + + + ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED + Enable PTP pdelay_resp frame received + [23:23] + write-only + + + ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED + Enable PTP pdelay_req frame transmitted + [24:24] + write-only + + + ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED + Enable PTP pdelay_resp frame transmitted + [25:25] + write-only + + + ENABLE_TSU_SECONDS_REGISTER_INCREMENT + Enable TSU seconds register increment + [26:26] + write-only + + + ENABLE_RX_LPI_INDICATION_INTERRUPT + Enable RX LPI indication interrupt + [27:27] + write-only + + + UNUSED_28 + Not used + [28:28] + write-only + + + ENABLE_TSU_TIMER_COMPARISON_INTERRUPT + Enable TSU timer comparison interrupt. + [29:29] + write-only + + + + + INT_DISABLE + Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero. + 0x102C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DISABLE_MANAGEMENT_DONE_INTERRUPT + 'Disable management done interrupt' + [0:0] + write-only + + + DISABLE_RECEIVE_COMPLETE_INTERRUPT + 'Disable receive complete interrupt' + [1:1] + write-only + + + DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT + 'Disable receive used bit read interrupt' + [2:2] + write-only + + + DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT + 'Disable transmit used bit read interrupt' + [3:3] + write-only + + + DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT + 'Disable transmit buffer under run interrupt' + [4:4] + write-only + + + DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT + 'Disable retry limit exceeded or late collision interrupt' + [5:5] + write-only + + + DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT + 'Disable transmit frame corruption due to AMBA (AHB/AXI) error interrupt' + [6:6] + write-only + + + DISABLE_TRANSMIT_COMPLETE_INTERRUPT + 'Disable transmit complete interrupt' + [7:7] + write-only + + + UNUSED_8 + Not used + [8:8] + write-only + + + UNUSED_9 + Not used + [9:9] + write-only + + + DISABLE_RECEIVE_OVERRUN_INTERRUPT + 'Disable receive overrun interrupt' + [10:10] + write-only + + + DISABLE_RESP_NOT_OK_INTERRUPT + 'Disable bresp/hresp not OK interrupt' + [11:11] + write-only + + + DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT + 'Disable pause frame with non-zero pause quantum interrupt' + [12:12] + write-only + + + DISABLE_PAUSE_TIME_ZERO_INTERRUPT + 'Disable pause time zero interrupt' + [13:13] + write-only + + + DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT + 'Disable pause frame transmitted interrupt' + [14:14] + write-only + + + UNUSED_15 + Not used + [15:15] + write-only + + + UNUSED_16 + Not used + [16:16] + write-only + + + UNUSED_17 + Not used + [17:17] + write-only + + + DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED + 'Disable PTP delay_req frame received' + [18:18] + write-only + + + DISABLE_PTP_SYNC_FRAME_RECEIVED + 'Disable PTP sync frame received' + [19:19] + write-only + + + DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED + 'Disable PTP delay_req frame transmitted ' + [20:20] + write-only + + + DISABLE_PTP_SYNC_FRAME_TRANSMITTED + 'Disable PTP sync frame transmitted ' + [21:21] + write-only + + + DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED + 'Disable PTP pdelay_req frame received' + [22:22] + write-only + + + DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED + 'Disable PTP pdelay_resp frame received' + [23:23] + write-only + + + DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED + 'Disable PTP pdelay_req frame transmitted' + [24:24] + write-only + + + DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED + 'Disable PTP pdelay_resp frame transmitted' + [25:25] + write-only + + + DISABLE_TSU_SECONDS_REGISTER_INCREMENT + 'Disable TSU seconds register increment' + [26:26] + write-only + + + DISABLE_RX_LPI_INDICATION_INTERRUPT + 'Disable RX LPI indication interrupt' + [27:27] + write-only + + + UNUSED_28 + Not used + [28:28] + write-only + + + DISABLE_TSU_TIMER_COMPARISON_INTERRUPT + 'Disable TSU timer comparison interrupt.' + [29:29] + write-only + + + RSVD_30_30 + N/A + [30:30] + read-only + + + RSVD_31_31 + N/A + [31:31] + read-only + + + + + INT_MASK + The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register. + 0x1030 + 32 + read-only + 0x3FFFFFFF + 0x3FFFFFFF + + + MANAGEMENT_DONE_INTERRUPT_MASK + management done interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [0:0] + read-only + + + RECEIVE_COMPLETE_INTERRUPT_MASK + receive complete interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [1:1] + read-only + + + RECEIVE_USED_BIT_READ_INTERRUPT_MASK + receive used bit read interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [2:2] + read-only + + + TRANSMIT_USED_BIT_READ_INTERRUPT_MASK + transmit used bit read interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [3:3] + read-only + + + TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK + transmit buffer under run interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [4:4] + read-only + + + RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK + A read of this register returns the value of the retry limit exceeded or late collision (gigabit mode only) interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [5:5] + read-only + + + AMBA_ERROR_INTERRUPT_MASK + transmit frame corruption due to AMBA (AXI) error interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [6:6] + read-only + + + TRANSMIT_COMPLETE_INTERRUPT_MASK + transmit complete interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [7:7] + read-only + + + UNUSED_8 + Not used + [8:8] + read-only + + + UNUSED_9 + Not used + [9:9] + read-only + + + RECEIVE_OVERRUN_INTERRUPT_MASK + receive overrun interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [10:10] + read-only + + + RESP_NOT_OK_INTERRUPT_MASK + bresp not OK interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [11:11] + read-only + + + PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK + pause frame with non-zero pause quantum interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [12:12] + read-only + + + PAUSE_TIME_ZERO_INTERRUPT_MASK + pause time zero interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [13:13] + read-only + + + PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK + pause frame transmitted interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [14:14] + read-only + + + UNUSED_15 + Not used + [15:15] + read-only + + + UNUSED_16 + Not used + [16:16] + read-only + + + UNUSED_17 + Not used + [17:17] + read-only + + + PTP_DELAY_REQ_FRAME_RECEIVED_MASK + A read of this register returns the value of the PTP delay_req frame received mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [18:18] + read-only + + + PTP_SYNC_FRAME_RECEIVED_MASK + A read of this register returns the value of the PTP sync frame received mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [19:19] + read-only + + + PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK + A read of this register returns the value of the PTP delay_req frame transmitted mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [20:20] + read-only + + + PTP_SYNC_FRAME_TRANSMITTED_MASK + A read of this register returns the value of the PTP sync frame transmitted mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [21:21] + read-only + + + PTP_PDELAY_REQ_FRAME_RECEIVED_MASK + A read of this register returns the value of the PTP pdelay_req frame received mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [22:22] + read-only + + + PTP_PDELAY_RESP_FRAME_RECEIVED_MASK + A read of this register returns the value of the PTP pdelay_resp frame received mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [23:23] + read-only + + + PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK + A read of this register returns the value of the PTP pdelay_req frame transmitted mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [24:24] + read-only + + + PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK + A read of this register returns the value of the PTP pdelay_resp frame transmitted mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [25:25] + read-only + + + TSU_SECONDS_REGISTER_INCREMENT_MASK + A read of this register returns the value of the TSU seconds register increment mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [26:26] + read-only + + + RX_LPI_INDICATION_MASK + A read of this register returns the value of the RX LPI indication mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written + [27:27] + read-only + + + UNUSED_28 + unused + [28:28] + read-only + + + TSU_TIMER_COMPARISON_MASK + Enable TSU timer comparison interrupt mask. + [29:29] + read-only + + + + + PHY_MANAGEMENT + The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit-2 is set in the network status register. It takes about 2000 pclk cycles to complete, when MDC is set for pclk divide by 32 in the network configuration register. An interrupt is generated upon completion. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO. See Section 22.2.4.5 of the IEEE 802.3 standard. Reading during the shift operation will return the current contents of the shift register. At the end of management operation, the bits will have shifted back to their original locations. For a read operation, the data bits will be updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced. The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bit 30 should be written with a 0 rather than a 1. For a description of MDC generation, see Network Configuration Register. + 0x1034 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + PHY_WRITE_READ_DATA + For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. + [15:0] + read-write + + + WRITE10 + Must be written with 10. + [17:16] + read-write + + + REGISTER_ADDRESS + Register address - specifies the register in the PHY to access. + [22:18] + read-write + + + PHY_ADDRESS + PHY address. + [27:23] + read-write + + + OPERATION + Operation. For a Clause 45 frame: 00 is an addr, 01 is a write, 10 is a post read increment, 11 is a read frame. For a Clause 22 frame: 10 is a read, 01 is a write. + [29:28] + read-write + + + WRITE1 + Must be written to 1 for a valid Clause 22 frame and to 0 for a valid Clause 45 frame. + [30:30] + read-write + + + WRITE0 + Must be written with 0. + [31:31] + read-write + + + + + PAUSE_TIME + Received Pause Quantum Register + 0x1038 + 32 + read-only + 0x0 + 0xFFFF + + + QUANTUM + Received pause quantum - stores the current value of the received pause quantum register which is decremented every 512 bit times. + [15:0] + read-only + + + + + TX_PAUSE_QUANTUM + Transmit Pause Quantum Register + 0x103C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + QUANTUM + Transmit pause quantum - written with the pause quantum value for pause frame transmission. + [15:0] + read-write + + + QUANTUM_P1 + Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 1. + [31:16] + read-write + + + + + PBUF_TXCUTTHRU + Partial store and forward is only applicable when using the DMA configured in SRAM based packet buffer mode. It is also not available when using multi buffer frames. TX Partial Store and Forward + 0x1040 + 32 + read-write + 0x1FF + 0x800001FF + + + DMA_TX_CUTTHRU_THRESHOLD + Watermark value. This value must be >= 0x9. The reset value depends on the value of the configuration option `gem_tx_pbuf_addr, which is defined in the verilog defs configuration file. The value chosen for the generation of the userguide was `gem_tx_pbuf_addr = 9 + [8:0] + read-write + + + DMA_TX_CUTTHRU + Enable TX partial store and forward operation + [31:31] + read-write + + + + + PBUF_RXCUTTHRU + RX Partial Store and Forward + 0x1044 + 32 + read-write + 0xFF + 0x800000FF + + + DMA_RX_CUTTHRU_THRESHOLD + Watermark value. The reset value depends on the value of the configuration option `gem_rx_pbuf_addr, which is defined in the verilog defs configuration file. The value chosen for the generation of the userguide was `gem_rx_pbuf_addr = 8. + [7:0] + read-write + + + DMA_RX_CUTTHRU + Enable RX partial store and forward operation + [31:31] + read-write + + + + + JUMBO_MAX_LENGTH + Maximum Jumbo Frame Size. + 0x1048 + 32 + read-write + 0x600 + 0x3FFF + + + JUMBO_MAX_LENGTH + Maximum Jumbo Frame Size - resets to the gem_jumbo_max_length define value. + [13:0] + read-write + + + + + EXTERNAL_FIFO_INTERFACE + Not presents. + 0x104C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + AXI_MAX_PIPELINE + Used to set the maximum amount of outstanding transactions on the AXI bus between AR / R channels and AW / W channels. Cannot be more than the depth of the configured AXI pipeline FIFO (defined in verilog defs.v) + 0x1054 + 32 + read-write + 0x101 + 0x1FFFF + + + AR2R_MAX_PIPELINE + Defines the maximum number of outstanding AXI read requests that can be issued by the DMA via the AR channel. + [7:0] + read-write + + + AW2W_MAX_PIPELINE + Defines the maximum number of outstanding AXI write requests that can be issued by the DMA via the AW channel. + [15:8] + read-write + + + USE_AW2B_FILL + For the write issuing capability as defined in bits 15:8 of this register, select whether the max number of transactions operates between the AW to W AXI channel or the AW to B channel. Set to 0 to operate between the AW and W channels. Set to 1 to operate between the AW and B channels. + [16:16] + read-write + + + + + RSC_CONTROL + Not presents. Access to the register will return AHB error. + 0x1058 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + INT_MODERATION + Used to moderate the number of transmit and receive complete interrupts issued. With interrupt moderation enabled receive and transmit interrupts are not generated immediately a frame is transmitted or received. Instead when a receive or transmit event occurs a timer is started and the interrupt is asserted after it times out. This limits the frequency with which the CPU receives interrupts. When interrupt moderation is enabled interrupt status bit one is always used for receive and bit 7 is always used for transmit even when priority queuing is enabled. With interrupt moderation 800ns periods are counted. GEM determines what constitutes an 800ns period by looking at the tbi (bit 11), gigabit bit (10) and speed (bit 0) bits in the network configuration register and counting tx_clk cycles. Bit 0 needs to be set to 1 for 100M operation. + 0x105C + 32 + read-write + 0x0 + 0xFF00FF + + + RX_INT_MODERATION + Count of 800ns periods before bit 1 is set in the interrupt status register after a frame is received. A non-zero value indicates receive interrupt moderation will be performed. + [7:0] + read-write + + + TX_INT_MODERATION + Count of 800ns periods before bit 7 is set in the interrupt status register after a frame is transmitted. A non-zero value indicates transmit interrupt moderation will be performed. + [23:16] + read-write + + + + + SYS_WAKE_TIME + Used to pause transmission after deassertion of tx_lpi_en. Each unit in this register corresponds to 64ns in gigabit mode, 320ns in 100M mode and 3200ns at 10M. After tx_lpi_en is deasserted transmission will pause for the set time. + 0x1060 + 32 + read-write + 0x0 + 0xFFFF + + + SYS_WAKE_TIME + Count of 64ns, 320ns or 3200ns intervals before transmission starts after deassertion of tx_lpi_en (each interval is equivalent to eight tx_clk periods and so varies with data rate). + [15:0] + read-write + + + + + HASH_BOTTOM + The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. Hash Register Bottom (31 to 0 bits) + 0x1080 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDRESS_HASH_B + The first 32 bits of the hash address register. + [31:0] + read-write + + + + + HASH_TOP + Hash Register Top (63 to 32 bits) + 0x1084 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDRESS_HASH_T + The remaining 32 bits of the hash address register. + [31:0] + read-write + + + + + SPEC_ADD1_BOTTOM + The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written. + 0x1088 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDRESS_ADD1_B + 'Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.' + [31:0] + read-write + + + + + SPEC_ADD1_TOP + Specific Address Top + 0x108C + 32 + read-write + 0x0 + 0x1FFFF + + + ADDRESS_TOP + Specific address 1. The most significant bits of the destination/source address that is to be compared, that is bits 47:32. + [15:0] + read-write + + + FILTER_TYPE + This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero, the filter is a destination address filter. When set to one, the filter is a source address filter. Specific address 1. The most significant bits of the destination address, that is bits 47:32. + [16:16] + read-write + + + + + SPEC_ADD2_BOTTOM + The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written. + 0x1090 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDRESS_BOTTOM + Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. + [31:0] + read-write + + + + + SPEC_ADD2_TOP + Specific Address Top + 0x1094 + 32 + read-write + 0x0 + 0x3F01FFFF + + + ADDRESS_TOP + Specific address 1. The most significant bits of the destination/source address that is to be compared, that is bits 47:32. + [15:0] + read-write + + + FILTER_TYPE + This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero, the filter is a destination address filter. When set to one, the filter is a source address filter. Specific address 1. The most significant bits of the destination address, that is bits 47:32. + [16:16] + read-write + + + FILTER_BYTE_MASK + When high, the associated byte of the specific address will not be compared. Bit 24 controls whether the first byte received should be compared. Bit 29 controls whether the last byte received should be compared. + [29:24] + read-write + + + + + SPEC_ADD3_BOTTOM + The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written. + 0x1098 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDRESS_BOTTOM + Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. + [31:0] + read-write + + + + + SPEC_ADD3_TOP + Specific Address Top + 0x109C + 32 + read-write + 0x0 + 0x3F01FFFF + + + ADDRESS_TOP + Specific address 1. The most significant bits of the destination/source address that is to be compared, that is bits 47:32. + [15:0] + read-write + + + FILTER_TYPE + This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero, the filter is a destination address filter. When set to one, the filter is a source address filter. Specific address 1. The most significant bits of the destination address, that is bits 47:32. + [16:16] + read-write + + + FILTER_BYTE_MASK + When high, the associated byte of the specific address will not be compared. Bit 24 controls whether the first byte received should be compared. Bit 29 controls whether the last byte received should be compared. + [29:24] + read-write + + + + + SPEC_ADD4_BOTTOM + The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written. + 0x10A0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDRESS_BOTTOM + Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. + [31:0] + read-write + + + + + SPEC_ADD4_TOP + Specific Address Top + 0x10A4 + 32 + read-write + 0x0 + 0x3F01FFFF + + + ADDRESS_TOP + Specific address 1. The most significant bits of the destination/source address that is to be compared, that is bits 47:32. + [15:0] + read-write + + + FILTER_TYPE + This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero, the filter is a destination address filter. When set to one, the filter is a source address filter. Specific address 1. The most significant bits of the destination address, that is bits 47:32. + [16:16] + read-write + + + FILTER_BYTE_MASK + When high, the associated byte of the specific address will not be compared. Bit 24 controls whether the first byte received should be compared. Bit 29 controls whether the last byte received should be compared. + [29:24] + read-write + + + + + SPEC_TYPE1 + Type ID Match 1 + 0x10A8 + 32 + read-write + 0x0 + 0x8000FFFF + + + MATCH + Type ID match 1. For use in comparisons with received frames type ID/length field. + [15:0] + read-write + + + ENABLE_COPY + Enable copying of type ID match 1 matched frames. + [31:31] + read-write + + + + + SPEC_TYPE2 + Type ID Match 2 + 0x10AC + 32 + read-write + 0x0 + 0x8000FFFF + + + MATCH + Type ID match 2. For use in comparisons with received frames type ID/length field. + [15:0] + read-write + + + ENABLE_COPY + Enable copying of type ID match 2 matched frames. + [31:31] + read-write + + + + + SPEC_TYPE3 + Type ID Match 3 + 0x10B0 + 32 + read-write + 0x0 + 0x8000FFFF + + + MATCH + Type ID match 3. For use in comparisons with received frames type ID/length field. + [15:0] + read-write + + + ENABLE_COPY + Enable copying of type ID match 3 matched frames. + [31:31] + read-write + + + + + SPEC_TYPE4 + Type ID Match 4 + 0x10B4 + 32 + read-write + 0x0 + 0x8000FFFF + + + MATCH + Type ID match 4. For use in comparisons with received frames type ID/length field. + [15:0] + read-write + + + ENABLE_COPY + Enable copying of type ID match 4 matched frames. + [31:31] + read-write + + + + + WOL_REGISTER + Wake on LAN Register. Presents in design, but feature is not supported. + 0x10B8 + 32 + read-write + 0x0 + 0xFFFFF + + + ADDR + Wake on LAN ARP request IP address. Written to define the least significant 16 bits of the target IP address that is matched to generate a Wake on LAN event. A value of zero will not generate an event, even if this is matched by the received frame. + [15:0] + read-write + + + WOL_MASK_0 + Wake on LAN magic packet event enable. When set magic packet events will cause the wol output to be asserted. + [16:16] + read-write + + + WOL_MASK_1 + Wake on LAN ARP request event enable. When set ARP request events will cause the wol output to be asserted. + [17:17] + read-write + + + WOL_MASK_2 + Wake on LAN specific address register 1 event enable. When set specific address 1 events will cause the wol output to be asserted. + [18:18] + read-write + + + WOL_MASK_3 + Wake on LAN multicast hash event enable. When set multicast hash events will cause the wol output to be asserted. + [19:19] + read-write + + + + + STRETCH_RATIO + IPG stretch register + 0x10BC + 32 + read-write + 0x0 + 0xFFFF + + + IPG_STRETCH + IPG Stretch. Bits 7:0 are multiplied with the previously transmitted frame length (including preamble) bits 15:8 +1 divide the frame length. If the resulting number is greater than 96 and bit 28 is set in the network configuration register then the resulting number is used for the transmit inter-packet-gap. 1 is added to bits 15:8 to prevent a divide by zero. + [15:0] + read-write + + + + + STACKED_VLAN + Stacked VLAN Register + 0x10C0 + 32 + read-write + 0x0 + 0x8000FFFF + + + MATCH + User defined VLAN_TYPE field. When Stacked VLAN is enabled, the first VLAN tag in a received frame will only be accepted if the VLAN type field is equal to this user defined VLAN_TYPE OR equal to the standard VLAN type (0x8100). Note that the second VLAN tag of a Stacked VLAN packet will only be matched correctly if its VLAN_TYPE field equals 0x8100. + [15:0] + read-write + + + ENABLE_PROCESSING + Enable stacked VLAN processing mode + [31:31] + read-write + + + + + TX_PFC_PAUSE + Transmit PFC Pause Register + 0x10C4 + 32 + read-write + 0x0 + 0xFFFF + + + VECTOR_ENABLE + Priority Vector Enable. If bit 17 of the network control register is written with a one then the priority enable vector of the PFC priority based pause frame will be set equal to the value stored in this register [7:0]. + [7:0] + read-write + + + VECTOR + Priority Vector Pause Size. If bit 17 of the network control register is written with a one then for each entry equal to zero in the Transmit PFC Pause Register[15:8], the PFC pause frame's pause quantum field associated with that entry will be taken from the transmit pause quantum register. For each entry equal to one in the Transmit PFC Pause Register [15:8], the pause quantum associated with that entry will be zero. + [15:8] + read-write + + + + + MASK_ADD1_BOTTOM + Specific Address Mask 1 Bottom (31 to 0 bits) + 0x10C8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDRESS_MASK_BOTTOM + Specific Address Mask. Setting a bit to one masks the corresponding bit in the specific address 1 register (31 to 0 bits) + [31:0] + read-write + + + + + MASK_ADD1_TOP + Specific Address Mask 1 Top (47 to 32 bits) + 0x10CC + 32 + read-write + 0x0 + 0xFFFF + + + ADDRESS_MASK_TOP + Specific Address Mask. Setting a bit to one masks the corresponding bit in the specific address 1 register (47 to 32 bits). + [15:0] + read-write + + + + + DMA_ADDR_OR_MASK + Receive DMA Data Buffer Address Mask + 0x10D0 + 32 + read-write + 0x0 + 0xF000000F + + + MASK_ENABLE + Data Buffer Address Mask Enable. These bits are associated directly with bits[31:28].When bit 0 is set, the AXI/AHB address bit 28 used for accessing the receive data buffers will be forced to the value stored in bit 28 of this register. When bit 1 is set, the AXI/AHB address bit 29 used for accessing the receive data buffers will be forced to the value stored in bit 29 of this register. When bit 2 is set, the AXI/AHB address bit 30 used for accessing the receive data buffers will be forced to the value stored in bit 30 of this register. When bit 3 is set, the AXI/AHB address bit 31 used for accessing the receive data buffers will be forced to the value stored in bit 31 of this register. When these bits are clear, the associated value stored in bits 31:28 have no effect on the AXI/AHB address used for receive data buffer accesses. Any changes to this register will be ignored while the DMA is currently processing a receive packet. It will only affect the next full packet to be written to external memory. + [3:0] + read-write + + + MASK_VALUE_DA + Data Buffer Address Mask Value. Values used to force bits 31:28 of the receive data buffer AHB address to a particular value when the associated enable bits stored in this register [3:0] are set. Any changes to this register will be ignored while the DMA is currently processing a receive packet. It will only affect the next full packet to be written to external system memory. + [31:28] + read-write + + + + + RX_PTP_UNICAST + PTP RX unicast IP destination address + 0x10D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDRESS_UNICAST + Unicast IP destination address. Used for detection of PTP frames on receive path. + [31:0] + read-write + + + + + TX_PTP_UNICAST + PTP TX unicast IP destination address + 0x10D8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADDRESS_UNICAST + Unicast IP destination address. Used for detection of PTP frames on transmit path. + [31:0] + read-write + + + + + TSU_NSEC_CMP + TSU timer comparison value nanoseconds + 0x10DC + 32 + read-write + 0x0 + 0x3FFFFF + + + COMPARISON_NSEC + TSU timer comparison value (ns). Value is compared to the bits[45:24] of the TSU timer count value (upper 22 bits of nanosecond value). + [21:0] + read-write + + + + + TSU_SEC_CMP + TSU timer comparison value seconds (31 to 0 bits) + 0x10E0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COMPARISON_SEC + TSU timer comparison value (s). Value is compared to seconds value bits [31:0] of the TSU timer count value. + [31:0] + read-write + + + + + TSU_MSB_SEC_CMP + TSU timer comparison value seconds (47 to 32 bits) + 0x10E4 + 32 + read-write + 0x0 + 0xFFFF + + + COMPARISON_MSB_SEC + TSU timer comparison value (s). Value is compared to the top 16 bits (most significant 16-bits {47:32] of seconds value) of the TSU timer count value. + [15:0] + read-write + + + + + TSU_PTP_TX_MSB_SEC + PTP Event Frame Transmitted Seconds Register (47 to 32 bits) + 0x10E8 + 32 + read-only + 0x0 + 0xFFFF + + + TIMER_SECONDS + PTP Event Frame TX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. + [15:0] + read-only + + + + + TSU_PTP_RX_MSB_SEC + PTP Event Frame Received Seconds Register (47 to 32 bits) + 0x10EC + 32 + read-only + 0x0 + 0xFFFF + + + TIMER_SECONDS + PTP Event Frame TX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. + [15:0] + read-only + + + + + TSU_PEER_TX_MSB_SEC + PTP Peer Event Frame Transmitted Seconds Register (47 to 32 bits) + 0x10F0 + 32 + read-only + 0x0 + 0xFFFF + + + TIMER_SECONDS + PTP Peer Event Frame TX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. + [15:0] + read-only + + + + + TSU_PEER_RX_MSB_SEC + PTP Peer Event Frame Received Seconds Register (47 to 32 bits) + 0x10F4 + 32 + read-only + 0x0 + 0xFFFF + + + TIMER_SECONDS + PTP Peer Event Frame RX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. + [15:0] + read-only + + + + + DPRAM_FILL_DBG + The fill levels for the TX & RX packet buffers can be read using this register, including the fill level for each queue in the TX direction. + 0x10F8 + 32 + read-write + 0x0 + 0xFFFF00F1 + + + DMA_TX_RX_FILL_LEVEL_SELECT + TX/RX Fill Level select - report the fill level for the TX or RX packet buffer. + [0:0] + read-write + + + DMA_TX_Q_FILL_LEVEL_SELECT + TX queue fill level select - select what TX queue to report fill levels for. + [7:4] + read-write + + + DMA_TX_RX_FILL_LEVEL + Fill Level - TX or RX packet buffer fill level, selected by the tx_q_fill_level_select and tx_rx_fill_level_select registers. Read this register to determine the fill level. + [31:16] + read-only + + + + + REVISION_REG + This register indicates a Cadence module identification number and module revision. The value of this register is read only as defined by `gem_revision_reg_value + 0x10FC + 32 + read-only + 0x70109 + 0xFFFFFFFF + + + MODULE_REVISION + Module revision - fixed value specific to the revision of the design which is incremented for each non-fix release of the IP. + [15:0] + read-only + + + MODULE_IDENTIFICATION_NUMBER + Module identification number - for the GEM, this value is fixed. + [27:16] + read-only + + + FIX_NUMBER + Fix number - incremented for fix releases. + [31:28] + read-only + + + + + OCTETS_TXED_BOTTOM + Octets Transmitted lower bits (31 to 0 bits) + 0x1100 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_BOTTOM + Transmitted octets in frame without errors [31:0]. The number of octets transmitted in valid frames of any type. This counter is 48-bits, and is read through two registers. This count does not include octets from automatically generated pause frames. + [31:0] + read-only + + + + + OCTETS_TXED_TOP + Octets Transmitted higher bits (47 to 32 bits) + 0x1104 + 32 + read-only + 0x0 + 0xFFFF + + + COUNT_TOP + Transmitted octets in frame without errors [47:32]. The number of octets transmitted in valid frames of any type. This counter is 48-bits, and is read through two registers. This count does not include octets from automatically generated pause frames. + [15:0] + read-only + + + + + FRAMES_TXED_OK + Frames Transmitted + 0x1108 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_OK + Frames transmitted without error. A 32 bit register counting the number of frames successfully transmitted, i.e. no under run and not too many retries. Excludes pause frames. + [31:0] + read-only + + + + + BROADCAST_TXED + Broadcast Frames Transmitted + 0x110C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_BROADCAST + Broadcast frames transmitted without error. A 32 bit register counting the number of broadcast frames successfully transmitted without error, i.e. no under run and not too many retries. Excludes pause frames. + [31:0] + read-only + + + + + MULTICAST_TXED + Multicast Frames Transmitted + 0x1110 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_MULTICAST + Multicast frames transmitted without error. A 32 bit register counting the number of multicast frames successfully transmitted without error, i.e. no under run and not too many retries. Excludes pause frames. + [31:0] + read-only + + + + + PAUSE_FRAMES_TXED + Pause Frames Transmitted + 0x1114 + 32 + read-only + 0x0 + 0xFFFF + + + COUNT_PAUSE + Transmitted pause frames - a 16 bit register counting the number of pause frames transmitted. Only pause frames triggered by the register interface or through the external pause pins are counted as pause frames. Pause frames received through the external FIFO interface are counted in the frames transmitted counter. + [15:0] + read-only + + + + + FRAMES_TXED_64 + 64 Byte Frames Transmitted + 0x1118 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_64 + 64 byte frames transmitted without error. A 32 bit register counting the number of 64 byte frames successfully transmitted without error, i.e. no under run and not too many retries. Excludes pause frames. + [31:0] + read-only + + + + + FRAMES_TXED_65 + 65 to 127 Byte Frames Transmitted + 0x111C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_65 + 65 to127 byte frames transmitted without error. A 32 bit register counting the number of 65 to127 byte frames successfully transmitted without error, i.e. no under run and not too many retries. + [31:0] + read-only + + + + + FRAMES_TXED_128 + 128 to 255 Byte Frames Transmitted + 0x1120 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_128 + 128 to 255 byte frames transmitted without error. A 32 bit register counting the number of 128 to 255 byte frames successfully transmitted without error, i.e. no under run and not too many retries. + [31:0] + read-only + + + + + FRAMES_TXED_256 + 256 to 511 Byte Frames Transmitted + 0x1124 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_256 + 256 to 511 byte frames transmitted without error. A 32 bit register counting the number of 256 to 511 byte frames successfully transmitted without error, i.e. no under run and not too many retries. + [31:0] + read-only + + + + + FRAMES_TXED_512 + 512 to 1023 Byte Frames Transmitted + 0x1128 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_512 + 512 to 1023 byte frames transmitted without error. A 32 bit register counting the number of 512 to 1023 byte frames successfully transmitted without error, i.e. no under run and not too many retries. + [31:0] + read-only + + + + + FRAMES_TXED_1024 + 1024 to 1518 Byte Frames Transmitted + 0x112C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_1024 + 1024 to 1518 byte frames transmitted without error. A 32 bit register counting the number of 1024 to 1518 byte frames successfully transmitted without error, i.e. no under run and not too many retries. + [31:0] + read-only + + + + + FRAMES_TXED_1519 + Greater Than 1518 Byte Frames Transmitted + 0x1130 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_1519 + Greater than 1518 byte frames transmitted without error. A 32 bit register counting the number of 1518 or above byte frames successfully transmitted without error, i.e. no under run and not too many retries. + [31:0] + read-only + + + + + TX_UNDERRUNS + Transmit Under Runs + 0x1134 + 32 + read-only + 0x0 + 0x3FF + + + COUNT_UN + Transmit under runs - a 10 bit register counting the number of frames not transmitted due to a transmit under run. If this register is incremented then no other statistics register is incremented. + [9:0] + read-only + + + + + SINGLE_COLLISIONS + Single Collision Frames. Presents in design but not support. + 0x1138 + 32 + read-only + 0x0 + 0x3FFFF + + + COUNT14 + Single collision frames - an 18 bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e. no under run. + [17:0] + read-only + + + + + MULTIPLE_COLLISIONS + Multiple Collision Frames. Presents in design but not support. + 0x113C + 32 + read-only + 0x0 + 0x3FFFF + + + COUNT15 + Multiple collision frames - an 18 bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e. no under run and not too many retries. + [17:0] + read-only + + + + + EXCESSIVE_COLLISIONS + Excessive Collisions. Presents in design but not support. + 0x1140 + 32 + read-only + 0x0 + 0x3FF + + + COUNT16 + Excessive collisions - a 10 bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions. + [9:0] + read-only + + + + + LATE_COLLISIONS + Late Collisions. Presents in design but not support. + 0x1144 + 32 + read-only + 0x0 + 0x3FF + + + COUNT17 + Late collisions - a 10 bit register counting the number of late collision occurring after the slot time (512 bits) has expired. In 10/100 mode, late collisions are counted twice i.e. both as a collision and a late collision. In gigabit mode, a late collision causes the transmission to be aborted, thus the single and multi collision registers are not updated. + [9:0] + read-only + + + + + DEFERRED_FRAMES + Deferred Transmission Frames. Presents in design but not support. + 0x1148 + 32 + read-only + 0x0 + 0x3FFFF + + + COUNT18 + Deferred transmission frames - an 18 bit register counting the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission. Frames involved in any collision are not counted nor are frames that experienced a transmit under run. + [17:0] + read-only + + + + + CRS_ERRORS + Carrier Sense Errors. Presents in design but not support. + 0x114C + 32 + read-only + 0x0 + 0x3FF + + + COUNT19 + Carrier sense errors - a 10 bit register counting the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit frame without collision (no under run). Only incremented in half duplex mode. The only effect of a carrier sense error is to increment this register. The behaviour of the other statistics registers is unaffected by the detection of a carrier sense error. + [9:0] + read-only + + + + + OCTETS_RXED_BOTTOM + Octets Received (31 to 0 bits) + 0x1150 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_BOTTOM + Received octets in frame without errors [31:0]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames, and is only incremented if the frame is successfully filtered. + [31:0] + read-only + + + + + OCTETS_RXED_TOP + Octets Received (47 to 32 bits) + 0x1154 + 32 + read-only + 0x0 + 0xFFFF + + + COUNT_TOP + Received octets in frame without errors [47:32]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames, and is only incremented if the frame is successfully filtered. + [15:0] + read-only + + + + + FRAMES_RXED_OK + Frames Received + 0x1158 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_OK + Frames received without error. A 32 bit register counting the number of frames successfully received. Excludes pause frames, and is only incremented if the frame is successfully filtered. + [31:0] + read-only + + + + + BROADCAST_RXED + Broadcast Frames Received + 0x115C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_BROADCAST + Broadcast frames received without error. A 32 bit register counting the number of broadcast frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. + [31:0] + read-only + + + + + MULTICAST_RXED + Multicast Frames Received + 0x1160 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_MULTICAST + Multicast frames received without error. A 32 bit register counting the number of multicast frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. + [31:0] + read-only + + + + + PAUSE_FRAMES_RXED + Pause Frames Received + 0x1164 + 32 + read-only + 0x0 + 0xFFFF + + + COUNT_PAUSE + Received pause frames - a 16 bit register counting the number of pause frames received without error. + [15:0] + read-only + + + + + FRAMES_RXED_64 + 64 Byte Frames Received + 0x1168 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_64 + 64 byte frames received without error. A 32 bit register counting the number of 64 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. + [31:0] + read-only + + + + + FRAMES_RXED_65 + 65 to 127 Byte Frames Received + 0x116C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_65 + 65 to 127 byte frames received without error. A 32 bit register counting the number of 65 to 127 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. + [31:0] + read-only + + + + + FRAMES_RXED_128 + 128 to 255 Byte Frames Received + 0x1170 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_128 + 128 to 255 byte frames received without error. A 32 bit register counting the number of 128 to 255 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. + [31:0] + read-only + + + + + FRAMES_RXED_256 + 256 to 511 Byte Frames Received + 0x1174 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_256 + 256 to 511 byte frames received without error. A 32 bit register counting the number of 256 to 511 byte frames successfully transmitted without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. + [31:0] + read-only + + + + + FRAMES_RXED_512 + 512 to 1023 Byte Frames Received + 0x1178 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_512 + 512 to 1023 byte frames received without error. A 32 bit register counting the number of 512 to 1023 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. + [31:0] + read-only + + + + + FRAMES_RXED_1024 + 1024 to 1518 Byte Frames Received + 0x117C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_1024 + 1024 to 1518 byte frames received without error. A 32 bit register counting the number of 1024 to 1518 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered. + [31:0] + read-only + + + + + FRAMES_RXED_1519 + 1519 to maximum Byte Frames Received + 0x1180 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + COUNT_1519 + 1519 to maximum byte frames received without error. A 32 bit register counting the number of 1519 byte or above frames successfully received without error. Maximum frame size is determined by the network configuration register bit 8 (1536 maximum frame size) or bit 3 (jumbo frame size). Excludes pause frames, and is only incremented if the frame is successfully filtered. + [31:0] + read-only + + + + + UNDERSIZE_FRAMES + Undersized Frames Received + 0x1184 + 32 + read-only + 0x0 + 0x3FF + + + COUNT_UNDERSIZE + Undersize frames received - a 10 bit register counting the number of frames received less than 64 bytes in length (10/100 mode or gigabit mode, full duplex) that do not have either a CRC error or an alignment error. In gigabit mode, half duplex, this register counts either frames not conforming to the minimum slot time of 512 bytes or frames not conforming to the minimum frame size once bursting is active. + [9:0] + read-only + + + + + EXCESSIVE_RX_LENGTH + Oversize Frames Received + 0x1188 + 32 + read-only + 0x0 + 0x3FF + + + COUNT_OVERSIZE + Oversize frames received - a 10 bit register counting the number of frames received exceeding 1518 bytes (1536 bytes if bit 8 is set in network configuration register, 10,240 bytes if bit 3 is set in the network configuration register) in length but do not have either a CRC error, an alignment error nor a receive symbol error. + [9:0] + read-only + + + + + RX_JABBERS + Jabbers Received + 0x118C + 32 + read-only + 0x0 + 0x3FF + + + COUNT_JABBERS + Jabbers received - a 10 bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register, 10,240 bytes if bit 3 is set in the network configuration register) in length and have either a CRC error, an alignment error or a receive symbol error. + [9:0] + read-only + + + + + FCS_ERRORS + Frame Check Sequence Errors + 0x1190 + 32 + read-only + 0x0 + 0x3FF + + + COUNT_FCS_ERR + Frame check sequence errors - a 10 bit register counting frames that are an integral number of bytes, have bad CRC and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register, 10,240 bytes if bit 3 is set in the network configuration register). This register is also incremented if a symbol error is detected and the frame is of valid length and has an integral number of bytes. This register is incremented for a frame with bad FCS, regardless of whether it is copied to memory due to ignore FCS mode being enabled in bit 26 of the network configuration register. + [9:0] + read-only + + + + + RX_LENGTH_ERRORS + Length Field Frame Errors + 0x1194 + 32 + read-only + 0x0 + 0x3FF + + + COUNT_LENGTH_ERR + Length field frame errors - this 10-bit register counts the number of frames received that have a measured length shorter than that extracted from the length field (bytes 13 and 14). This condition is only counted if the value of the length field is less than 0x0600, the frame is not of excessive length and checking is enabled through bit 16 of the network configuration register. + [9:0] + read-only + + + + + RX_SYMBOL_ERRORS + Receive Symbol Errors + 0x1198 + 32 + read-only + 0x0 + 0x3FF + + + COUNT_SYMBOL_ERR + Receive symbol errors - a 10-bit register counting the number of frames that had rx_er asserted during reception. For 10/100 mode symbol errors are counted regardless of frame length checks. For gigabit mode the frame must satisfy slot time requirements in order to count a symbol error. Additionally, in gigabit half duplex mode, carrier extension errors are also recorded. Receive symbol errors will also be counted as an FCS or alignment error if the frame is between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register, 10240 bytes if bit 3 is set in the network configuration register). If the frame is larger it will be recorded as a jabber error. + [9:0] + read-only + + + + + ALIGNMENT_ERRORS + Alignment Errors + 0x119C + 32 + read-only + 0x0 + 0x3FF + + + COUNT_ALIGNMENT_ERROR + Alignment errors - a 10 bit register counting frames that are not an integral number of bytes long and have bad CRC when their length is truncated to an integral number of bytes and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register, 10,240 bytes if bit 3 is set in the network configuration register). This register is also incremented if a symbol error is detected and the frame is of valid length and does not have an integral number of bytes. + [9:0] + read-only + + + + + RX_RESOURCE_ERRORS + Receive Resource Errors + 0x11A0 + 32 + read-only + 0x0 + 0x3FFFF + + + COUNT_RESOURCE_ERR + Receive resource errors - an 18 bit register counting the number of frames that were successfully received by the MAC (correct address matched frame and adequate slot time) but could not be copied to memory because no receive buffer was available. This occurs when the GEM reads a buffer descriptor with its ownership (or used) bit set. + [17:0] + read-only + + + + + RX_OVERRUNS + Receive Overruns + 0x11A4 + 32 + read-only + 0x0 + 0x3FF + + + COUNT_OVERRUN + Receive overruns - a 10 bit register counting the number of frames that are address recognized but were not copied to memory due to a receive overrun. + [9:0] + read-only + + + + + RX_IP_CK_ERRORS + IP Header Checksum Errors + 0x11A8 + 32 + read-only + 0x0 + 0xFF + + + COUNT_IPCK_ERR + IP header checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect IP header checksum, but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3 is in the network configuration register) and do not have a CRC error, an alignment error, nor a symbol error. + [7:0] + read-only + + + + + RX_TCP_CK_ERRORS + TCP Checksum Errors + 0x11AC + 32 + read-only + 0x0 + 0xFF + + + COUNT_TCPCK_ERR + TCP checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect TCP checksum, but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3 is in the network configuration register) and do not have a CRC error, an alignment error, nor a symbol error. + [7:0] + read-only + + + + + RX_UDP_CK_ERRORS + UDP Checksum Errors + 0x11B0 + 32 + read-only + 0x0 + 0xFF + + + COUNT_UDPCK_ERR + UDP checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect UDP checksum, but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3 is in the network configuration register) and do not have a CRC error, an alignment error, nor a symbol error. + [7:0] + read-only + + + + + AUTO_FLUSHED_PKTS + Receive DMA Flushed Packets + 0x11B4 + 32 + read-only + 0x0 + 0xFFFF + + + COUNT_FLUSHED + Flushed RX packets counter. A 16 bit register counting the number of frames that have been flushed from the receive SRAM based packet buffer due to one of the following reasons .1. When partial store and forward mode is enabled or bit 24 of the DMA configuration register is enabled, a packet is received while there is no AMBA (AXI/AHB) resource. 2. When partial store and forward mode is enabled and an AMBA (AXI/AHB) error is encountered while writing the packet data to external memory. When bit 18 of the network control register(software action to flush a packet from the head of the PBUF queue) is pulsed and the GEM DMA is not currently busy. + [15:0] + read-only + + + + + TSU_TIMER_INCR_SUB_NSEC + 1588 Timer Increment Register sub nsec + 0x11BC + 32 + read-write + 0x0 + 0xFF00FFFF + + + SUB_NS_INCR + These are the most significant bits [23:8] of the sub-ns value by which the 1588 timer will be incremented each clock cycle. 24 bits of sub nanosecond precision gives resolution of approximately 5.86E-17 seconds (16 bits gives 15.2 femtoseconds). + [15:0] + read-write + + + SUB_NS_INCR_LSB + These are the least significant bits [7:0] of the sub-ns value by which the 1588 timer will be incremented each clock cycle. + [31:24] + read-write + + + + + TSU_TIMER_MSB_SEC + 1588 Timer Seconds Register (47 to 32 bits) + 0x11C0 + 32 + read-write + 0x0 + 0xFFFF + + + TIMER_MSB_SEC + TSU timer value (s). Most significant 16 bits of seconds timer count. The register is writeable. The 48-bit counter increments by one when the 1588 nanoseconds counter counts to one second. It may also be incremented or decremented when the timer adjust register is written (if decremented from zero the 48-bit combined count would roll back to 0xFFFFFFFFFFFF). Note: The value of this register is used only when the lower 32 bit register is written to. This is to ensure a single update of the 48 bit seconds value + [15:0] + read-write + + + + + TSU_STROBE_MSB_SEC + 1588 Timer Sync Strobe Seconds Register (47 to 32 bits) + 0x11C4 + 32 + read-only + 0x0 + 0xFFFF + + + STROBE_MSB_SEC + 1588 Timer Sync Strobe Seconds. The most significant 16-bit value of the Timer Seconds register captured when gem_tsu_ms and gem_tsu_inc_ctrl are zero. + [15:0] + read-only + + + + + TSU_STROBE_SEC + 1588 Timer Sync Strobe Seconds Register (31 to 0 bits) + 0x11C8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + STROBE_SEC + 1588 Timer Sync Strobe Seconds. The lowest significant 32-bit value of the Timer Seconds register captured when gem_tsu_ms and gem_tsu_inc_ctrl are zero. + [31:0] + read-only + + + + + TSU_STROBE_NSEC + 1588 Timer Sync Strobe Nanoseconds Register + 0x11CC + 32 + read-only + 0x0 + 0x3FFFFFFF + + + STROBE_NSEC + 1588 Timer Sync Strobe Nanoseconds. The value of the Timer Nanoseconds register captured when gem_tsu_ms and gem_tsu_inc_ctrl are zero. + [29:0] + read-only + + + + + TSU_TIMER_SEC + 1588 Timer Seconds Register (31 to 0 bits) + 0x11D0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TIMER_SEC + 1588 Timer Seconds Register. TSU timer value (s). Least significant 32 bits of seconds timer count. This register is writeable. The 48-bit counter increments by one when the 1588 nanoseconds counter counts to one second. It may also be incremented or decremented when the timer adjust register is written (if decremented from zero the 48-bit combined count would roll back to 0xFFFFFFFFFFFF). + [31:0] + read-write + + + + + TSU_TIMER_NSEC + 1588 Timer Nanoseconds Register + 0x11D4 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + TIMER_NSEC + Timer count in nanoseconds. This register is writeable. It can also be adjusted by writes to the 1588 timer adjust register. It increments by the value of the 1588 timer increment register each clock cycle (if this register is close to zero and a write to the timer adjust register causes a decrement the seconds register will be decremented if necessary and the nanoseconds register will roll back to 9999999xx(decimal)). + [29:0] + read-write + + + + + TSU_TIMER_ADJUST + This register is used to adjust the value of the timer in the TSU. It allows an integral number of nanoseconds to be added or subtracted from the timer in a one-off operation. This register returns all zeroes when read. + 0x11D8 + 32 + write-only + 0x0 + 0xBFFFFFFF + + + INCREMENT_VALUE + Timer increment value. The number of nanoseconds to increment or decrement the 1588 timer nanoseconds register. If necessary the 1588 seconds register will be incremented or decremented. + [29:0] + write-only + + + ADD_SUBTRACT + Write as one to subtract from the 1588 timer. Write as zero to add to it. + [31:31] + write-only + + + + + TSU_TIMER_INCR + 1588 Timer Increment Register + 0x11DC + 32 + read-write + 0x0 + 0xFFFFFF + + + NS_INCREMENT + A count of nanoseconds by which the 1588 timer nanoseconds register will be incremented each clock cycle. These are the most significant 8 bits of the 32 bit timer_increment counter. The tsu_timer_incr_sub_nsec register holds the least significant 24 bits of the increment. + [7:0] + read-write + + + ALT_NS_INCR + Alternative nanoseconds count. Alternative count of nanoseconds by which the 1588 timer nanoseconds register will be incremented each clock cycle. + [15:8] + read-write + + + NUM_INCS + Number of incs before alt inc. The number of increments after which the alternative increment is used. + [23:16] + read-write + + + + + TSU_PTP_TX_SEC + PTP Event Frame Transmitted Seconds Register (31 to 0 bits) + 0x11E0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + TIMER_PTP_SEC + PTP Event Frame Transmitted Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. + [31:0] + read-only + + + + + TSU_PTP_TX_NSEC + PTP Event Frame Transmitted Nanoseconds Register + 0x11E4 + 32 + read-only + 0x0 + 0x3FFFFFFF + + + TIMER_PTP_NSEC + PTP Event Frame Transmitted Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. + [29:0] + read-only + + + + + TSU_PTP_RX_SEC + PTP Event Frame Received Seconds Register (31 to 0 bits) + 0x11E8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + TIMER_PTP_SEC + PTP Event Frame Received Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. + [31:0] + read-only + + + + + TSU_PTP_RX_NSEC + PTP Event Frame Received Nanoseconds Register + 0x11EC + 32 + read-only + 0x0 + 0x3FFFFFFF + + + TIMER_PTP_NSEC + PTP Event Frame Received Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP sync or delay_req frame. An interrupt is issued when the register is updated. + [29:0] + read-only + + + + + TSU_PEER_TX_SEC + PTP Peer Event Frame Transmitted Seconds Register (31 to 0 bits) + 0x11F0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + TIMER_PEER_SEC + PTP Peer Event Frame Received Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. + [31:0] + read-only + + + + + TSU_PEER_TX_NSEC + PTP Peer Event Frame Transmitted Nanoseconds Register + 0x11F4 + 32 + read-only + 0x0 + 0x3FFFFFFF + + + TIMER_PEER_NSEC + PTP Peer Event Frame Transmitted Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. + [29:0] + read-only + + + + + TSU_PEER_RX_SEC + PTP Peer Event Frame Received Seconds Register (31 to 0 bits) + 0x11F8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + TIMER_PEER_SEC + PTP Peer Event Frame Received Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. + [31:0] + read-only + + + + + TSU_PEER_RX_NSEC + PTP Peer Event Frame Received Nanoseconds Register + 0x11FC + 32 + read-only + 0x0 + 0x3FFFFFFF + + + TIMER_PEER_NSEC + PTP Peer Event Frame Received Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame as a PTP pdelay_req or pdelay_resp frame. An interrupt is issued when the register is updated. + [29:0] + read-only + + + + + PCS_CONTROL + Not presents. Access to the register returns AHB error. + 0x1200 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + PCS_STATUS + Not presents. Access to the register returns AHB error. + 0x1204 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + PCS_AN_ADV + Not presents. Access to the register returns AHB error. + 0x1210 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + PCS_AN_LP_BASE + Not presents. Access to the register returns AHB error. + 0x1214 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + PCS_AN_EXP + Not presents. Access to the register returns AHB error. + 0x1218 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + PCS_AN_NP_TX + Not presents. Access to the register returns AHB error. + 0x121C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + PCS_AN_LP_NP + Not presents. Access to the register returns AHB error. + 0x1220 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + PCS_AN_EXT_STATUS + Not presents. Access to the register returns AHB error. + 0x123C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + TX_PAUSE_QUANTUM1 + Transmit Pause Quantum Register 1 + 0x1260 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + QUANTUM_P2 + Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 2. + [15:0] + read-write + + + QUANTUM_P3 + Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 3. + [31:16] + read-write + + + + + TX_PAUSE_QUANTUM2 + Transmit Pause Quantum Register 2 + 0x1264 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + QUANTUM_P4 + Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 4. + [15:0] + read-write + + + QUANTUM_P5 + Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 5. + [31:16] + read-write + + + + + TX_PAUSE_QUANTUM3 + Transmit Pause Quantum Register 3 + 0x1268 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + QUANTUM_P6 + Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 6. + [15:0] + read-write + + + QUANTUM_P7 + Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 7. + [31:16] + read-write + + + + + RX_LPI + Received LPI transitions + 0x1270 + 32 + read-only + 0x0 + 0xFFFF + + + COUNT_LPI + Count of RX LPI transitions. A count of the number of times there is a transition from receiving normal idle to receiving low power idle. Cleared on read. + [15:0] + read-only + + + + + RX_LPI_TIME + Received LPI time + 0x1274 + 32 + read-only + 0x0 + 0xFFFFFF + + + LPI_TIME + Time in LPI. This register increments once every 16 pclk cycles when the LPI indication bit 20 is set in the receive configuration register. Cleared on read. + [23:0] + read-only + + + + + TX_LPI + Transmit LPI transitions + 0x1278 + 32 + read-only + 0x0 + 0xFFFF + + + COUNT_LPI + Count of LPI transmissions. A count of the number of times the enable LPI transmission bit 20 goes from low to high in the transmit control register. + [15:0] + read-only + + + + + TX_LPI_TIME + Transmit LPI time + 0x127C + 32 + read-only + 0x0 + 0xFFFFFF + + + LPI_TIME + Time in LPI. This register increments once every 16 pclk cycles when the enable LPI transmission bit 20 is set in the transmit control register. Cleared on read. + [23:0] + read-only + + + + + DESIGNCFG_DEBUG1 + The GEM_GXL(3PIP) has many parameterisation options to configure the IP during compilation stage. This is achieved using Verilog define compiler directives in an include file called mxeth_defs.v. + 0x1280 + 32 + read-only + 0x508503 + 0xFFFFFFFF + + + NO_PCS + Takes the value of the `gem_no_pcs DEFINE + [0:0] + read-only + + + EXCLUDE_QBV + Takes the value of the `gem_exclude_qbv DEFINE + [1:1] + read-only + + + RSVD_2 + N/A + [3:2] + read-only + + + INT_LOOPBACK + Takes the value of the `gem_int_loopback DEFINE + [4:4] + read-only + + + RSVD_5 + N/A + [5:5] + read-only + + + EXT_FIFO_INTERFACE + Takes the value of the `gem_ext_fifo_interface DEFINE + [6:6] + read-only + + + RSVD_7 + N/A + [7:7] + read-only + + + RSVD_8 + N/A + [8:8] + read-only + + + USER_IO + Takes the value of the `gem_user_io DEFINE + [9:9] + read-only + + + USER_OUT_WIDTH + Takes the value of the `gem_user_out_width DEFINE if `gem_user_io is set. +If 'gem_user_io is not set, the value is 0x01 + [14:10] + read-only + + + USER_IN_WIDTH + Takes the value of the `gem_user_in_width DEFINE `gem_user_io. +If 'gem_user_io is not set, the value is 0x01 + [19:15] + read-only + + + RSVD_20 + N/A + [20:20] + read-only + + + NO_STATS + Takes the value of the `gem_no_stats DEFINE + [21:21] + read-only + + + NO_SNAPSHOT + Takes the value of the `gem_no_snapshot DEFINE + [22:22] + read-only + + + IRQ_READ_CLEAR + Takes the value of the `gem_irq_read_clear DEFINE + [23:23] + read-only + + + EXCLUDE_CBS + Takes the value of the `gem_exclude_cbs DEFINE + [24:24] + read-only + + + DMA_BUS_WIDTH + Takes the value of bits 7:5 of the `gem_dma_bus_width DEFINE. So if the define is set to decimal 64 this will return binary 010. + [27:25] + read-only + + + AXI_CACHE_VALUE + Takes the value of the `gem_axi_cache_value DEFINE + [31:28] + read-only + + + + + DESIGNCFG_DEBUG2 + Design Configuration Register 2 + 0x1284 + 32 + read-only + 0xA6310600 + 0xFFFF3FFF + + + JUMBO_MAX_LENGTH + Takes the value of the `gem_jumbo_max_length DEFINE + [13:0] + read-only + + + HPROT_VALUE + Takes the value of the `gem_hprot_value DEFINE + [19:16] + read-only + + + RX_PKT_BUFFER + Takes the value of the `gem_rx_pkt_buffer DEFINE + [20:20] + read-only + + + TX_PKT_BUFFER + Takes the value of the `gem_tx_pkt_buffer DEFINE + [21:21] + read-only + + + RX_PBUF_ADDR + Takes the value of the `gem_rx_pbuf_addr DEFINE + [25:22] + read-only + + + TX_PBUF_ADDR + Takes the value of the `gem_tx_pbuf_addr DEFINE + [29:26] + read-only + + + AXI + Takes the value of the `gem_axi DEFINE + [30:30] + read-only + + + SPRAM + Takes the value of the `gem_spram DEFINE + [31:31] + read-only + + + + + DESIGNCFG_DEBUG3 + Design Configuration Register 3 + 0x1288 + 32 + read-only + 0x4000000 + 0x3F000000 + + + NUM_SPEC_ADD_FILTERS + Takes the value of the `num_spec_add_filters DEFINE + [29:24] + read-only + + + + + DESIGNCFG_DEBUG4 + Design Configuration Register 4 + 0x128C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RSVD_31_0 + N/A + [31:0] + read-only + + + + + DESIGNCFG_DEBUG5 + Design Configuration Register 5 + 0x1290 + 32 + read-only + 0x518E3744 + 0xFFFFFFFF + + + RX_FIFO_CNT_WIDTH + Takes the value of the `gem_rx_fifo_cnt_width DEFINE + [3:0] + read-only + + + TX_FIFO_CNT_WIDTH + Takes the value of the `gem_tx_fifo_cnt_width DEFINE + [7:4] + read-only + + + TSU + Takes the value of the `gem_tsu DEFINE + [8:8] + read-only + + + PHY_IDENT + Takes the value of the `gem_phy_ident DEFINE + [9:9] + read-only + + + DMA_BUS_WIDTH_DEF + Takes the value of the `gem_dma_bus_width_def DEFINE + [11:10] + read-only + + + MDC_CLOCK_DIV + Takes the value of the `gem_mdc_clock_div DEFINE + [14:12] + read-only + + + ENDIAN_SWAP_DEF + Takes the value of the `gem_endian_swap_def DEFINE + [16:15] + read-only + + + RX_PBUF_SIZE_DEF + Takes the value of the `gem_rx_pbuf_size_def DEFINE + [18:17] + read-only + + + TX_PBUF_SIZE_DEF + Takes the value of the `gem_tx_pbuf_size_def DEFINE + [19:19] + read-only + + + RX_BUFFER_LENGTH_DEF + Takes the value of the `gem_rx_buffer_length_def DEFINE + [27:20] + read-only + + + TSU_CLK + Takes the value of the `gem_tsu_clk DEFINE + [28:28] + read-only + + + AXI_PROT_VALUE + Takes the value of the `gem_axi_prot_value DEFINE + [31:29] + read-only + + + + + DESIGNCFG_DEBUG6 + Design Configuration Register 6 + 0x1294 + 32 + read-only + 0x3020006 + 0xFFFFFFE + + + DMA_PRIORITY_QUEUE1 + Takes the value of the `dma_priority_queue1 DEFINE + [1:1] + read-only + + + DMA_PRIORITY_QUEUE2 + Takes the value of the `dma_priority_queue2 DEFINE + [2:2] + read-only + + + DMA_PRIORITY_QUEUE3 + Takes the value of the `dma_priority_queue3 DEFINE + [3:3] + read-only + + + DMA_PRIORITY_QUEUE4 + Takes the value of the `dma_priority_queue4 DEFINE + [4:4] + read-only + + + DMA_PRIORITY_QUEUE5 + Takes the value of the `dma_priority_queue5 DEFINE + [5:5] + read-only + + + DMA_PRIORITY_QUEUE6 + Takes the value of the `dma_priority_queue6 DEFINE + [6:6] + read-only + + + DMA_PRIORITY_QUEUE7 + Takes the value of the `dma_priority_queue7 DEFINE + [7:7] + read-only + + + DMA_PRIORITY_QUEUE8 + Takes the value of the `dma_priority_queue8 DEFINE + [8:8] + read-only + + + DMA_PRIORITY_QUEUE9 + Takes the value of the `dma_priority_queue9 DEFINE + [9:9] + read-only + + + DMA_PRIORITY_QUEUE10 + Takes the value of the `dma_priority_queue10 DEFINE + [10:10] + read-only + + + DMA_PRIORITY_QUEUE11 + Takes the value of the `dma_priority_queue11 DEFINE + [11:11] + read-only + + + DMA_PRIORITY_QUEUE12 + Takes the value of the `dma_priority_queue12 DEFINE + [12:12] + read-only + + + DMA_PRIORITY_QUEUE13 + Takes the value of the `dma_priority_queue13 DEFINE + [13:13] + read-only + + + DMA_PRIORITY_QUEUE14 + Takes the value of the `dma_priority_queue14 DEFINE + [14:14] + read-only + + + DMA_PRIORITY_QUEUE15 + Takes the value of the `dma_priority_queue15 DEFINE + [15:15] + read-only + + + TX_PBUF_QUEUE_SEGMENT_SIZE + Takes the value of the `gem_tx_pbuf_queue_segment_size DEFINE + [19:16] + read-only + + + EXT_TSU_TIMER + Takes the value of the `gem_ext_tsu_timer DEFINE + [20:20] + read-only + + + TX_ADD_FIFO_IF + Takes the value of the `gem_tx_add_fifo_if DEFINE + [21:21] + read-only + + + HOST_IF_SOFT_SELECT + Takes the value of the `gem_host_if_soft_select DEFINE + [22:22] + read-only + + + DMA_ADDR_WIDTH_IS_64B + Takes the value of the `gem_dma_addr_width_is_64b DEFINE + [23:23] + read-only + + + PFC_MULTI_QUANTUM + Takes the value of the `gem_pfc_multi_quantum DEFINE + [24:24] + read-only + + + PBUF_CUTTHRU + Takes the value of the `gem_pbuf_cutthru DEFINE + [25:25] + read-only + + + PBUF_RSC + Takes the value of the `gem_pbuf_rsc DEFINE + [26:26] + read-only + + + PBUF_LSO + Takes the value of the `gem_pbuf_lso DEFINE + [27:27] + read-only + + + + + DESIGNCFG_DEBUG7 + Design Configuration Register 7 + 0x1298 + 32 + read-only + 0x1 + 0xFFFFFFFF + + + X_PBUF_NUM_SEGMENTS_Q0 + Takes the value of the `gem_tx_pbuf_num_segments_q0 DEFINE + [3:0] + read-only + + + X_PBUF_NUM_SEGMENTS_Q1 + Takes the value of the `gem_tx_pbuf_num_segments_q1 DEFINE + [7:4] + read-only + + + X_PBUF_NUM_SEGMENTS_Q2 + Takes the value of the `gem_tx_pbuf_num_segments_q2 DEFINE + [11:8] + read-only + + + X_PBUF_NUM_SEGMENTS_Q3 + Takes the value of the `gem_tx_pbuf_num_segments_q3 DEFINE + [15:12] + read-only + + + X_PBUF_NUM_SEGMENTS_Q4 + Takes the value of the `gem_tx_pbuf_num_segments_q4 DEFINE + [19:16] + read-only + + + X_PBUF_NUM_SEGMENTS_Q5 + Takes the value of the `gem_tx_pbuf_num_segments_q5 DEFINE + [23:20] + read-only + + + X_PBUF_NUM_SEGMENTS_Q6 + Takes the value of the `gem_tx_pbuf_num_segments_q6 DEFINE + [27:24] + read-only + + + X_PBUF_NUM_SEGMENTS_Q7 + Takes the value of the `gem_tx_pbuf_num_segments_q7 DEFINE + [31:28] + read-only + + + + + DESIGNCFG_DEBUG8 + Design Configuration Register 8 + 0x129C + 32 + read-only + 0x10100820 + 0xFFFFFFFF + + + NUM_SCR2_COMPARE_REGS + Takes the value of the `num_scr2_compare_regs DEFINE + [7:0] + read-only + + + NUM_SCR2_ETHTYPE_REGS + Takes the value of the `num_scr2_ethtype_regs DEFINE + [15:8] + read-only + + + NUM_TYPE2_SCREENERS + Takes the value of the `num_type2_screeners DEFINE + [23:16] + read-only + + + NUM_TYPE1_SCREENERS + Takes the value of the `num_type1_screeners DEFINE + [31:24] + read-only + + + + + DESIGNCFG_DEBUG9 + Design Configuration Register 9 + 0x12A0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + TX_PBUF_NUM_SEGMENTS_Q8 + Takes the value of the `gem_tx_pbuf_num_segments_q8 DEFINE + [3:0] + read-only + + + TX_PBUF_NUM_SEGMENTS_Q9 + Takes the value of the `gem_tx_pbuf_num_segments_q9 DEFINE + [7:4] + read-only + + + TX_PBUF_NUM_SEGMENTS_Q10 + Takes the value of the `gem_tx_pbuf_num_segments_q10 DEFINE + [11:8] + read-only + + + TX_PBUF_NUM_SEGMENTS_Q11 + Takes the value of the `gem_tx_pbuf_num_segments_q11 DEFINE + [15:12] + read-only + + + TX_PBUF_NUM_SEGMENTS_Q12 + Takes the value of the `gem_tx_pbuf_num_segments_q12 DEFINE + [19:16] + read-only + + + TX_PBUF_NUM_SEGMENTS_Q13 + Takes the value of the `gem_tx_pbuf_num_segments_q13 DEFINE + [23:20] + read-only + + + TX_PBUF_NUM_SEGMENTS_Q14 + Takes the value of the `gem_tx_pbuf_num_segments_q14 DEFINE + [27:24] + read-only + + + TX_PBUF_NUM_SEGMENTS_Q15 + Takes the value of the `gem_tx_pbuf_num_segments_q15 DEFINE + [31:28] + read-only + + + + + DESIGNCFG_DEBUG10 + Design Configuration Register 10 + 0x12A4 + 32 + read-only + 0x4411111 + 0xFFFFFFFF + + + AXI_RX_DESCR_WR_BUFF_BITS + Takes the value of the `gem_axi_rx_descr_wr_buff_bits DEFINE + [3:0] + read-only + + + AXI_TX_DESCR_WR_BUFF_BITS + Takes the value of the `gem_axi_tx_descr_wr_buff_bits DEFINE + [7:4] + read-only + + + AXI_RX_DESCR_RD_BUFF_BITS + Takes the value of the `gem_axi_rx_descr_rd_buff_bits DEFINE + [11:8] + read-only + + + AXI_TX_DESCR_RD_BUFF_BITS + Takes the value of the `gem_axi_tx_descr_rd_buff_bits DEFINE + [15:12] + read-only + + + AXI_ACCESS_PIPELINE_BITS + Takes the value of the `gem_axi_access_pipeline_bits DEFINE + [19:16] + read-only + + + RX_PBUF_DATA + Takes the value of the `gem_rx_pbuf_data DEFINE. 1 - The RX DPRAM has a datawidth of 32bits. 2 - The RX DPRAM has a datawidth of 64bits. 4 - RX The DPRAM has a datawidth of 128bits + [23:20] + read-only + + + TX_PBUF_DATA + Takes the value of the `gem_tx_pbuf_data DEFINE. 1 - The TX DPRAM has a datawidth of 32bits. 2 - The TX DPRAM has a datawidth of 64bits. 4 - The TX DPRAM has a datawidth of 128bits + [27:24] + read-only + + + EMAC_BUS_WIDTH + Takes the value of the `gem_emac_bus_width DEFINE. 1 - The MAC has a datawidth of 32bits. 2 - The MAC has a datawidth of 64bits. 4 - The MAC has a datawidth of 128bits + [31:28] + read-only + + + + + SPEC_ADD5_BOTTOM + Specific address registers 5 ~ 36 doesn't present. Access to the register returns AHB error. + 0x1300 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RSVD_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + SPEC_ADD5_TOP + Specific address registers 5 ~ 36 doesn't present. Access to the register returns AHB error. + 0x1304 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RSVD_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + SPEC_ADD36_BOTTOM + Not presents. + 0x13F8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RSVD_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + SPEC_ADD36_TOP + Not presents. + 0x13FC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RSVD_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + INT_Q1_STATUS + Priority queue Interrupt Status Register + 0x1400 + 32 + read-only + 0x0 + 0x8E6 + + + RECEIVE_COMPLETE + Receive complete + [1:1] + read-only + + + RX_USED_BIT_READ + RX used bit read + [2:2] + read-only + + + RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION + Retry limit exceeded or late collision + [5:5] + read-only + + + AMBA_ERROR + Transmit frame corruption due to AMBA (AXI/AHB) error set if an error occurs whilst midway through reading transmit frame from the external memory, including HRESP (AHB), RRESP and BRESP errors (AXI) and buffers exhausted mid frame + [6:6] + read-only + + + TRANSMIT_COMPLETE + Transmit complete + [7:7] + read-only + + + RESP_NOT_OK + bresp not OK + [11:11] + read-only + + + + + INT_Q2_STATUS + Priority queue Interrupt Status Register + 0x1404 + 32 + read-only + 0x0 + 0x8E6 + + + RECEIVE_COMPLETE + Receive complete + [1:1] + read-only + + + RX_USED_BIT_READ + RX used bit read + [2:2] + read-only + + + RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION + Retry limit exceeded or late collision + [5:5] + read-only + + + AMBA_ERROR + Transmit frame corruption due to AMBA (AXI/AHB) error set if an error occurs whilst midway through reading transmit frame from the external memory, including HRESP(AHB), RRESP and BRESP errors (AXI) and buffers exhausted mid frame + [6:6] + read-only + + + TRANSMIT_COMPLETE + Transmit complete + [7:7] + read-only + + + RESP_NOT_OK + bresp not OK + [11:11] + read-only + + + + + INT_Q3_STATUS + int_q3_status to int_q15_status doesn't present. Access to the register returns AHB error. + 0x1408 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + INT_Q15_STATUS + Not presents. + 0x1438 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + TRANSMIT_Q1_PTR + This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit , the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access. + 0x1440 + 32 + read-write + 0x0 + 0xFFFFFFFD + + + DMA_TX_DIS_Q + Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled. + [0:0] + read-write + + + DMA_TX_Q_PTR + This register holds the start address of the transmit buffer queue (transmit buffers +descriptor list). The transmit buffer queue base address register must be initialized before +transmit is started through bit 9 of the network control register. Once transmission has +started, any write to the transmit buffer queue base address register is illegal and +therefore ignored. Note that due to clock boundary synchronization, it takes a maximum +of four pclk cycles from the writing of the transmit start bit before the transmitter is active. +Writing to the transmit buffer queue base address register during this time may produce +unpredictable results. Reading this register returns the location of the descriptor currently +being accessed. Because the DMA can store data for multiple frames at once, this may +not necessarily be pointing to the current frame being transmitted. In terms of AMBA +AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit +AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors +should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from +memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be +aligned at 32-bit boundaries and the descriptors are read from memory using two +individual 32-bit non sequential accesses. + [31:2] + read-write + + + + + TRANSMIT_Q2_PTR + This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit , the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access. + 0x1444 + 32 + read-write + 0x0 + 0xFFFFFFFD + + + DMA_TX_DIS_Q + Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled. + [0:0] + read-write + + + DMA_TX_Q_PTR + This register holds the start address of the transmit buffer queue (transmit buffers +descriptor list). The transmit buffer queue base address register must be initialized before +transmit is started through bit 9 of the network control register. Once transmission has +started, any write to the transmit buffer queue base address register is illegal and +therefore ignored. Note that due to clock boundary synchronization, it takes a maximum +of four pclk cycles from the writing of the transmit start bit before the transmitter is active. +Writing to the transmit buffer queue base address register during this time may produce +unpredictable results. Reading this register returns the location of the descriptor currently +being accessed. Because the DMA can store data for multiple frames at once, this may +not necessarily be pointing to the current frame being transmitted. In terms of AMBA +AHB/AXI operation, the transmit descriptors are written to memory using a single 32bit +AHB access. When the datapath is configured as 64bit or 128bit, the transmit descriptors +should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from +memory using a single AHB/AXI access. For 32bit datapaths, the descriptors should be +aligned at 32-bit boundaries and the descriptors are read from memory using two +individual 32-bit non sequential accesses + [31:2] + read-write + + + + + TRANSMIT_Q3_PTR + transmit_q3_ptr to transmit_q15_ptr doesn't present. Access to the register returns AHB error. + 0x1448 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled. + [31:0] + read-only + + + + + TRANSMIT_Q15_PTR + Not presents. + 0x1478 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + RECEIVE_Q1_PTR + This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit , the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access. + 0x1480 + 32 + read-write + 0x0 + 0xFFFFFFFD + + + DMA_RX_DIS_Q + Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while receive is not enabled. + [0:0] + read-write + + + DMA_RX_Q_PTR + Receive buffer queue base address - written with the address of the start of the receive queue. + [31:2] + read-write + + + + + RECEIVE_Q2_PTR + This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four pclk cycles from the writing of the transmit start bit before the transmitter is active. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Because the DMA can store data for multiple frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a single 32bit AHB access. When the datapath is configured as 64bit , the transmit descriptors should be aligned at 64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single AXI access. + 0x1484 + 32 + read-write + 0x0 + 0xFFFFFFFD + + + DMA_RX_DIS_Q + Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while receive is not enabled. + [0:0] + read-write + + + DMA_RX_Q_PTR + Receive buffer queue base address - written with the address of the start of the receive queue. + [31:2] + read-write + + + + + RECEIVE_Q3_PTR + Not presents. Start address register doesn't present for queue3 ~ queue7. + 0x1488 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + RECEIVE_Q7_PTR + Not presents. + 0x1498 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + DMA_RXBUF_SIZE_Q1 + Receive Buffer queue 1 Size + 0x14A0 + 32 + read-write + 0x18 + 0xFF + + + DMA_RX_Q_BUF_SIZE + DMA receive buffer size in system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes. + 0x01 corresponds to buffers of 64 bytes. + 0x02 corresponds to 128 bytes etc. +For example: + 0x02: 128 byte + 0x18: 1536 byte (1*max length frame/buffer) + 0xA0: 10240 byte (1*10K jumbo frame/buffer) +Note that this value should never be written as zero. Note. The reset value of this field is equal to the gem_rx_buffer_length_def define, which is user configurable. + [7:0] + read-write + + + + + DMA_RXBUF_SIZE_Q2 + Receive Buffer queue 2 Size + 0x14A4 + 32 + read-write + 0x18 + 0xFF + + + DMA_RX_Q_BUF_SIZE + DMA receive buffer size in system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes. + 0x01 corresponds to buffers of 64 bytes. + 0x02 corresponds to 128 bytes etc. +For example: + 0x02: 128 byte + 0x18: 1536 byte (1*max length frame/buffer) + 0xA0: 10240 byte (1*10K jumbo frame/buffer) +Note that this value should never be written as zero. Note. The reset value of this field is equal to the gem_rx_buffer_length_def define, which is user configurable. + [7:0] + read-write + + + + + DMA_RXBUF_SIZE_Q3 + dma_rxbuf_size_q3 to dma_rxbuf_size_q7 doesn't present. + 0x14A8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + DMA receive buffer size in system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes. + 0x01 corresponds to buffers of 64 bytes. + 0x02 corresponds to 128 bytes etc. +For example: + 0x02: 128 byte + 0x18: 1536 byte (1*max length frame/buffer) + 0xA0: 10240 byte (1*10K jumbo frame/buffer) +Note that this value should never be written as zero. Note. The reset value of this field is equal to the gem_rx_buffer_length_def define, which is user configurable. + [31:0] + read-only + + + + + DMA_RXBUF_SIZE_Q7 + Not presents. + 0x14B8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + CBS_CONTROL + The IdleSlope value is defined as the rate of change of credit when a packet is waiting to be sent. This must not exceed the portTransmitRate which is dependent on the speed of operation, eg, portTranmsitRate. 1Gb/s = 32'h07735940 (125 Mbytes/s), 100Mb/sec = 32'h017D7840 (25 Mnibbles/s), 10Mb/sec = 32'h002625A0 (2.5 Mnibbles/s). If 50 percent of bandwidth was to be allocated to a particular queue in 1Gb/sec mode then the IdleSlope value for that queue would be calculated as 32'h07735940/2. Note that Credit-Based Shaping should be disabled prior to updating the IdleSlope values. As another example, for a 1722 audio packet with a payload of 6 samples per channel, the packet size would be 7 (preamble) + 1 (SFD) + 50 (packet header) + 6x4x2(payload) + 4 (CRC) = 110 bytes. For a rate of 8000 packets per second, the desired rate would 110 x 8000 bytes per second, so the programmed idleSlope value would be 880000 for a 1Gb/s connection, or 1760000 for a 100Mb/s or 10Mbs connection. See Figure 6.3 in the IEEE 1722 standard. In practice, the actual transmission rate will be vary slightly from that calculated. In this case, the idleSlope value should be recalibrated based on the variance between the measured and expected rate, and in this case very accurate transmission rates can be achieved. + 0x14BC + 32 + read-write + 0x0 + 0x3 + + + CBS_ENABLE_QUEUE_A + Enable Credit-Based Shaping on the highest priority queue (queue A). Write 1 to enable + [0:0] + read-write + + + CBS_ENABLE_QUEUE_B + Enable Credit-Based shaping on the 2nd highest priority queue (queue B). Write 1 to enable + [1:1] + read-write + + + + + CBS_IDLESLOPE_Q_A + queue A is the highest priority queue. This would be queue 8 in an 8 queue configuration. + 0x14C0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + IDLESLOPE_A + IdleSlope value for queue A in bytes/sec for gigabit operation and nibbles/sec for 10/100 operation + [31:0] + read-write + + + + + CBS_IDLESLOPE_Q_B + queue B is the 2nd highest priority queue. This would be queue 7 in an 8 queue configuration. + 0x14C4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + IDLESLOPE_B + IdleSlope value for queue B in bytes/sec for gigabit operation and nibbles/sec for 10/100 operation + [31:0] + read-write + + + + + UPPER_TX_Q_BASE_ADDR + Upper 32 bits of transmit buffer descriptor queue base address. + 0x14C8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + UPPER_TX_Q_BASE_ADDR + Upper 32 bits of transmit buffer descriptor queue base address. Used when 64 bit addressing is enabled. (In releases earlier to 1p06f2 this register also affected the receive descriptor queue.) + [31:0] + read-write + + + + + TX_BD_CONTROL + TX BD control register + 0x14CC + 32 + read-write + 0x0 + 0x30 + + + TX_BD_TS_MODE + TX Descriptor Timestamp Insertion mode, 00: TS insertion disable, 01: TS inserted for PTP Event Frames only, 10: TS inserted for All PTP Frames only, 11: TS insertion for All Frames + [5:4] + read-write + + + + + RX_BD_CONTROL + RX BD control register + 0x14D0 + 32 + read-write + 0x0 + 0x30 + + + RX_BD_TS_MODE + RX Descriptor Timestamp Insertion mode, 00: TS insertion disable, 01: TS inserted for PTP Event Frames only, 10: TS inserted for All PTP Frames only, 11: TS insertion for All Frames + [5:4] + read-write + + + + + UPPER_RX_Q_BASE_ADDR + Upper 32 bits of receive buffer descriptor queue base address. + 0x14D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + UPPER_RX_Q_BASE_ADDR + Upper 32 bits of receive buffer descriptor queue base address. Used when 64 bit addressing is enabled. + [31:0] + read-write + + + + + HIDDEN_REG0 + Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_10m 12'h4e0 // 10M Port TX Rate *** HIDDEN Register ***'. Default value of cbs related hidden registers (0x14E0~0x14E8) are depicted in cbs_control register. + 0x14E0 + 32 + read-write + 0x2625A0 + 0xFFFFFFFF + + + HIDDEN0_FIELD + default value is defined per description of register cbs_control. + [31:0] + read-write + + + + + HIDDEN_REG1 + Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_100m 12'h4e4 // 100M Port TX Rate *** HIDDEN Register ***' + 0x14E4 + 32 + read-write + 0x17D7840 + 0xFFFFFFFF + + + HIDDEN1_FIELD + default value is defined per description of register cbs_control. + [31:0] + read-write + + + + + HIDDEN_REG2 + Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_1g 12'h4e8 // 1G Port TX Rate *** HIDDEN Register ***' + 0x14E8 + 32 + read-write + 0x7735940 + 0xFFFFFFFF + + + HIDDEN2_FIELD + default value is defined per description of register cbs_control. + [31:0] + read-write + + + + + HIDDEN_REG3 + Hidden registers defined in edma_defs.v '`define gem_wd_counter 12'h4ec // *** HIDDEN Register ***'. + 0x14EC + 32 + read-write + 0x7 + 0xF + + + HIDDEN3_FIELD + default value is defined per description of register cbs_control. + [3:0] + read-write + + + + + HIDDEN_REG4 + Hidden registers defined in edma_defs.v '`define gem_axi_tx_full_threshold0 12'h4f8 // AXI full threshold setting *** HIDDEN Register ***'. Note. When using AXI mode with a single port ram ( gem_spram == 1) mode and a 32b dma bus width ( gem_dma_bus_width == 32 or bits 22 to 21 of the network_config register are set to 0) the AXI hidden registers (0x14F8 and 0x14FC) need to be updated (these registers are used for fine tuning AXI dma bursts and normally should not be touched). + 0x14F8 + 32 + read-write + 0x60008 + 0x1FF01FF + + + HIDDEN4_FIELD_L + The valid bits is defined by `gem_tx_pbuf_addr. + [8:0] + read-write + + + HIDDEN4_FIELD_H + The valid bits is defined by `gem_tx_pbuf_addr. + [24:16] + read-write + + + + + HIDDEN_REG5 + Hidden registers defined in edma_defs.v '`define gem_axi_tx_full_threshold1 12'h4fc // AXI full threshold setting *** HIDDEN Register ***'. + 0x14FC + 32 + read-write + 0x0 + 0x1FF01FF + + + HIDDEN5_FIELD_L + The valid bits is defined by `gem_tx_pbuf_addr. + [8:0] + read-write + + + HIDDEN5_FIELD_H + The valid bits is defined by `gem_tx_pbuf_addr. + [24:16] + read-write + + + + + SCREENING_TYPE_1_REGISTER_0 + Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TCfield (traffic class) of IPv6 headers are matched against bits 11 to 4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27 to 12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 2 to 0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C. + 0x1500 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + QUEUE_NUMBER + Queue Number (0 to 15) + [3:0] + read-write + + + DSTC_MATCH + DS/TC Match + [11:4] + read-write + + + UDP_PORT_MATCH + UDP Port Match + [27:12] + read-write + + + DSTC_ENABLE + DS/TC Enable + [28:28] + read-write + + + UDP_PORT_MATCH_ENABLE + UDP port match enable + [29:29] + read-write + + + + + SCREENING_TYPE_1_REGISTER_1 + screening type 1 register 1, same as screening_type_1_register_0 + 0x1504 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + QUEUE_NUMBER + Queue Number (0 to 15) + [3:0] + read-write + + + DSTC_MATCH + DS/TC Match + [11:4] + read-write + + + UDP_PORT_MATCH + UDP Port Match + [27:12] + read-write + + + DSTC_ENABLE + DS/TC Enable + [28:28] + read-write + + + UDP_PORT_MATCH_ENABLE + UDP port match enable + [29:29] + read-write + + + + + SCREENING_TYPE_1_REGISTER_2 + screening type 1 register 2, same as screening_type_1_register_0 + 0x1508 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + QUEUE_NUMBER + Queue Number (0 to 15) + [3:0] + read-write + + + DSTC_MATCH + DS/TC Match + [11:4] + read-write + + + UDP_PORT_MATCH + UDP Port Match + [27:12] + read-write + + + DSTC_ENABLE + DS/TC Enable + [28:28] + read-write + + + UDP_PORT_MATCH_ENABLE + UDP port match enable + [29:29] + read-write + + + + + SCREENING_TYPE_1_REGISTER_3 + screening type 1 register 3, same as screening_type_1_register_0 + 0x150C + 32 + read-write + 0x0 + 0x3FFFFFFF + + + QUEUE_NUMBER + Queue Number (0 to 15) + [3:0] + read-write + + + DSTC_MATCH + DS/TC Match + [11:4] + read-write + + + UDP_PORT_MATCH + UDP Port Match + [27:12] + read-write + + + DSTC_ENABLE + DS/TC Enable + [28:28] + read-write + + + UDP_PORT_MATCH_ENABLE + UDP port match enable + [29:29] + read-write + + + + + SCREENING_TYPE_1_REGISTER_4 + screening type 1 register 4, same as screening_type_1_register_0 + 0x1510 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + QUEUE_NUMBER + Queue Number (0 to 15) + [3:0] + read-write + + + DSTC_MATCH + DS/TC Match + [11:4] + read-write + + + UDP_PORT_MATCH + UDP Port Match + [27:12] + read-write + + + DSTC_ENABLE + DS/TC Enable + [28:28] + read-write + + + UDP_PORT_MATCH_ENABLE + UDP port match enable + [29:29] + read-write + + + + + SCREENING_TYPE_1_REGISTER_5 + screening type 1 register 5, same as screening_type_1_register_0 + 0x1514 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + QUEUE_NUMBER + Queue Number (0 to 15) + [3:0] + read-write + + + DSTC_MATCH + DS/TC Match + [11:4] + read-write + + + UDP_PORT_MATCH + UDP Port Match + [27:12] + read-write + + + DSTC_ENABLE + DS/TC Enable + [28:28] + read-write + + + UDP_PORT_MATCH_ENABLE + UDP port match enable + [29:29] + read-write + + + + + SCREENING_TYPE_1_REGISTER_6 + screening type 1 register 6, same as screening_type_1_register_0 + 0x1518 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + QUEUE_NUMBER + Queue Number (0 to 15) + [3:0] + read-write + + + DSTC_MATCH + DS/TC Match + [11:4] + read-write + + + UDP_PORT_MATCH + UDP Port Match + [27:12] + read-write + + + DSTC_ENABLE + DS/TC Enable + [28:28] + read-write + + + UDP_PORT_MATCH_ENABLE + UDP port match enable + [29:29] + read-write + + + + + SCREENING_TYPE_1_REGISTER_7 + screening type 1 register 7, same as screening_type_1_register_0 + 0x151C + 32 + read-write + 0x0 + 0x3FFFFFFF + + + QUEUE_NUMBER + Queue Number (0 to 15) + [3:0] + read-write + + + DSTC_MATCH + DS/TC Match + [11:4] + read-write + + + UDP_PORT_MATCH + UDP Port Match + [27:12] + read-write + + + DSTC_ENABLE + DS/TC Enable + [28:28] + read-write + + + UDP_PORT_MATCH_ENABLE + UDP port match enable + [29:29] + read-write + + + + + SCREENING_TYPE_1_REGISTER_8 + screening type 1 register 8, same as screening_type_1_register_0 + 0x1520 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + QUEUE_NUMBER + Queue Number (0 to 15) + [3:0] + read-write + + + DSTC_MATCH + DS/TC Match + [11:4] + read-write + + + UDP_PORT_MATCH + UDP Port Match + [27:12] + read-write + + + DSTC_ENABLE + DS/TC Enable + [28:28] + read-write + + + UDP_PORT_MATCH_ENABLE + UDP port match enable + [29:29] + read-write + + + + + SCREENING_TYPE_1_REGISTER_9 + screening type 1 register 9, same as screening_type_1_register_0 + 0x1524 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + QUEUE_NUMBER + Queue Number (0 to 15) + [3:0] + read-write + + + DSTC_MATCH + DS/TC Match + [11:4] + read-write + + + UDP_PORT_MATCH + UDP Port Match + [27:12] + read-write + + + DSTC_ENABLE + DS/TC Enable + [28:28] + read-write + + + UDP_PORT_MATCH_ENABLE + UDP port match enable + [29:29] + read-write + + + + + SCREENING_TYPE_1_REGISTER_10 + screening type 1 register 10, same as screening_type_1_register_0 + 0x1528 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + QUEUE_NUMBER + Queue Number (0 to 15) + [3:0] + read-write + + + DSTC_MATCH + DS/TC Match + [11:4] + read-write + + + UDP_PORT_MATCH + UDP Port Match + [27:12] + read-write + + + DSTC_ENABLE + DS/TC Enable + [28:28] + read-write + + + UDP_PORT_MATCH_ENABLE + UDP port match enable + [29:29] + read-write + + + + + SCREENING_TYPE_1_REGISTER_11 + screening type 1 register 11, same as screening_type_1_register_0 + 0x152C + 32 + read-write + 0x0 + 0x3FFFFFFF + + + QUEUE_NUMBER + Queue Number (0 to 15) + [3:0] + read-write + + + DSTC_MATCH + DS/TC Match + [11:4] + read-write + + + UDP_PORT_MATCH + UDP Port Match + [27:12] + read-write + + + DSTC_ENABLE + DS/TC Enable + [28:28] + read-write + + + UDP_PORT_MATCH_ENABLE + UDP port match enable + [29:29] + read-write + + + + + SCREENING_TYPE_1_REGISTER_12 + screening type 1 register 12, same as screening_type_1_register_0 + 0x1530 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + QUEUE_NUMBER + Queue Number (0 to 15) + [3:0] + read-write + + + DSTC_MATCH + DS/TC Match + [11:4] + read-write + + + UDP_PORT_MATCH + UDP Port Match + [27:12] + read-write + + + DSTC_ENABLE + DS/TC Enable + [28:28] + read-write + + + UDP_PORT_MATCH_ENABLE + UDP port match enable + [29:29] + read-write + + + + + SCREENING_TYPE_1_REGISTER_13 + screening type 1 register 13, same as screening_type_1_register_0 + 0x1534 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + QUEUE_NUMBER + Queue Number (0 to 15) + [3:0] + read-write + + + DSTC_MATCH + DS/TC Match + [11:4] + read-write + + + UDP_PORT_MATCH + UDP Port Match + [27:12] + read-write + + + DSTC_ENABLE + DS/TC Enable + [28:28] + read-write + + + UDP_PORT_MATCH_ENABLE + UDP port match enable + [29:29] + read-write + + + + + SCREENING_TYPE_1_REGISTER_14 + screening type 1 register 14, same as screening_type_1_register_0 + 0x1538 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + QUEUE_NUMBER + Queue Number (0 to 15) + [3:0] + read-write + + + DSTC_MATCH + DS/TC Match + [11:4] + read-write + + + UDP_PORT_MATCH + UDP Port Match + [27:12] + read-write + + + DSTC_ENABLE + DS/TC Enable + [28:28] + read-write + + + UDP_PORT_MATCH_ENABLE + UDP port match enable + [29:29] + read-write + + + + + SCREENING_TYPE_1_REGISTER_15 + screening type 1 register 15, same as screening_type_1_register_0 + 0x153C + 32 + read-write + 0x0 + 0x3FFFFFFF + + + QUEUE_NUMBER + Queue Number (0 to 15) + [3:0] + read-write + + + DSTC_MATCH + DS/TC Match + [11:4] + read-write + + + UDP_PORT_MATCH + UDP Port Match + [27:12] + read-write + + + DSTC_ENABLE + DS/TC Enable + [28:28] + read-write + + + UDP_PORT_MATCH_ENABLE + UDP port match enable + [29:29] + read-write + + + + + SCREENING_TYPE_2_REGISTER_0 + Screener Type 2 match registers operate independently of screener type 1 registers and offer additional match capabilities, extending the capabilities into vendor specific protocols. + 0x1540 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + QUEUE_NUMBER + 'Queue Number (0 to 15)' + [3:0] + read-write + + + VLAN_PRIORITY + 'VLAN Priority' + [6:4] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + VLAN_ENABLE + 'VLAN Enable' + [8:8] + read-write + + + INDEX + 'Index to screener type 2 EtherType register' + [11:9] + read-write + + + ETHERTYPE_ENABLE + 'EtherType Enable' + [12:12] + read-write + + + COMPARE_A + 'Compare A - Index to screener type 2 Compare register ' + [17:13] + read-write + + + COMPARE_A_ENABLE + 'Compare A Enable' + [18:18] + read-write + + + COMPARE_B + 'Compare B - Index to screener type 2 Compare register' + [23:19] + read-write + + + COMPARE_B_ENABLE + 'Compare B Enable' + [24:24] + read-write + + + COMPARE_C + 'Compare C - Index to screener type 2 Compare register' + [29:25] + read-write + + + COMPARE_C_ENABLE + 'Compare C Enable' + [30:30] + read-write + + + RSVD_31 + N/A + [31:31] + read-only + + + + + SCREENING_TYPE_2_REGISTER_1 + screening type 2 register 1, same as screening_type_2_register_0 + 0x1544 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + QUEUE_NUMBER + 'Queue Number (0 to 15)' + [3:0] + read-write + + + VLAN_PRIORITY + 'VLAN Priority' + [6:4] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + VLAN_ENABLE + 'VLAN Enable' + [8:8] + read-write + + + INDEX + 'Index to screener type 2 EtherType register' + [11:9] + read-write + + + ETHERTYPE_ENABLE + 'EtherType Enable' + [12:12] + read-write + + + COMPARE_A + 'Compare A - Index to screener type 2 Compare register ' + [17:13] + read-write + + + COMPARE_A_ENABLE + 'Compare A Enable' + [18:18] + read-write + + + COMPARE_B + 'Compare B - Index to screener type 2 Compare register' + [23:19] + read-write + + + COMPARE_B_ENABLE + 'Compare B Enable' + [24:24] + read-write + + + COMPARE_C + 'Compare C - Index to screener type 2 Compare register' + [29:25] + read-write + + + COMPARE_C_ENABLE + 'Compare C Enable' + [30:30] + read-write + + + RSVD_31 + N/A + [31:31] + read-only + + + + + SCREENING_TYPE_2_REGISTER_2 + screening type 2 register 2, same as screening_type_2_register_0 + 0x1548 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + QUEUE_NUMBER + 'Queue Number (0 to 15)' + [3:0] + read-write + + + VLAN_PRIORITY + 'VLAN Priority' + [6:4] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + VLAN_ENABLE + 'VLAN Enable' + [8:8] + read-write + + + INDEX + 'Index to screener type 2 EtherType register' + [11:9] + read-write + + + ETHERTYPE_ENABLE + 'EtherType Enable' + [12:12] + read-write + + + COMPARE_A + 'Compare A - Index to screener type 2 Compare register ' + [17:13] + read-write + + + COMPARE_A_ENABLE + 'Compare A Enable' + [18:18] + read-write + + + COMPARE_B + 'Compare B - Index to screener type 2 Compare register' + [23:19] + read-write + + + COMPARE_B_ENABLE + 'Compare B Enable' + [24:24] + read-write + + + COMPARE_C + 'Compare C - Index to screener type 2 Compare register' + [29:25] + read-write + + + COMPARE_C_ENABLE + 'Compare C Enable' + [30:30] + read-write + + + RSVD_31 + N/A + [31:31] + read-only + + + + + SCREENING_TYPE_2_REGISTER_3 + screening type 2 register 3, same as screening_type_2_register_0 + 0x154C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + QUEUE_NUMBER + 'Queue Number (0 to 15)' + [3:0] + read-write + + + VLAN_PRIORITY + 'VLAN Priority' + [6:4] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + VLAN_ENABLE + 'VLAN Enable' + [8:8] + read-write + + + INDEX + 'Index to screener type 2 EtherType register' + [11:9] + read-write + + + ETHERTYPE_ENABLE + 'EtherType Enable' + [12:12] + read-write + + + COMPARE_A + 'Compare A - Index to screener type 2 Compare register ' + [17:13] + read-write + + + COMPARE_A_ENABLE + 'Compare A Enable' + [18:18] + read-write + + + COMPARE_B + 'Compare B - Index to screener type 2 Compare register' + [23:19] + read-write + + + COMPARE_B_ENABLE + 'Compare B Enable' + [24:24] + read-write + + + COMPARE_C + 'Compare C - Index to screener type 2 Compare register' + [29:25] + read-write + + + COMPARE_C_ENABLE + 'Compare C Enable' + [30:30] + read-write + + + RSVD_31 + N/A + [31:31] + read-only + + + + + SCREENING_TYPE_2_REGISTER_4 + screening type 2 register 4, same as screening_type_2_register_0 + 0x1550 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + QUEUE_NUMBER + 'Queue Number (0 to 15)' + [3:0] + read-write + + + VLAN_PRIORITY + 'VLAN Priority' + [6:4] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + VLAN_ENABLE + 'VLAN Enable' + [8:8] + read-write + + + INDEX + 'Index to screener type 2 EtherType register' + [11:9] + read-write + + + ETHERTYPE_ENABLE + 'EtherType Enable' + [12:12] + read-write + + + COMPARE_A + 'Compare A - Index to screener type 2 Compare register ' + [17:13] + read-write + + + COMPARE_A_ENABLE + 'Compare A Enable' + [18:18] + read-write + + + COMPARE_B + 'Compare B - Index to screener type 2 Compare register' + [23:19] + read-write + + + COMPARE_B_ENABLE + 'Compare B Enable' + [24:24] + read-write + + + COMPARE_C + 'Compare C - Index to screener type 2 Compare register' + [29:25] + read-write + + + COMPARE_C_ENABLE + 'Compare C Enable' + [30:30] + read-write + + + RSVD_31 + N/A + [31:31] + read-only + + + + + SCREENING_TYPE_2_REGISTER_5 + screening type 2 register 5, same as screening_type_2_register_0 + 0x1554 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + QUEUE_NUMBER + 'Queue Number (0 to 15)' + [3:0] + read-write + + + VLAN_PRIORITY + 'VLAN Priority' + [6:4] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + VLAN_ENABLE + 'VLAN Enable' + [8:8] + read-write + + + INDEX + 'Index to screener type 2 EtherType register' + [11:9] + read-write + + + ETHERTYPE_ENABLE + 'EtherType Enable' + [12:12] + read-write + + + COMPARE_A + 'Compare A - Index to screener type 2 Compare register ' + [17:13] + read-write + + + COMPARE_A_ENABLE + 'Compare A Enable' + [18:18] + read-write + + + COMPARE_B + 'Compare B - Index to screener type 2 Compare register' + [23:19] + read-write + + + COMPARE_B_ENABLE + 'Compare B Enable' + [24:24] + read-write + + + COMPARE_C + 'Compare C - Index to screener type 2 Compare register' + [29:25] + read-write + + + COMPARE_C_ENABLE + 'Compare C Enable' + [30:30] + read-write + + + RSVD_31 + N/A + [31:31] + read-only + + + + + SCREENING_TYPE_2_REGISTER_6 + screening type 2 register 6, same as screening_type_2_register_0 + 0x1558 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + QUEUE_NUMBER + 'Queue Number (0 to 15)' + [3:0] + read-write + + + VLAN_PRIORITY + 'VLAN Priority' + [6:4] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + VLAN_ENABLE + 'VLAN Enable' + [8:8] + read-write + + + INDEX + 'Index to screener type 2 EtherType register' + [11:9] + read-write + + + ETHERTYPE_ENABLE + 'EtherType Enable' + [12:12] + read-write + + + COMPARE_A + 'Compare A - Index to screener type 2 Compare register ' + [17:13] + read-write + + + COMPARE_A_ENABLE + 'Compare A Enable' + [18:18] + read-write + + + COMPARE_B + 'Compare B - Index to screener type 2 Compare register' + [23:19] + read-write + + + COMPARE_B_ENABLE + 'Compare B Enable' + [24:24] + read-write + + + COMPARE_C + 'Compare C - Index to screener type 2 Compare register' + [29:25] + read-write + + + COMPARE_C_ENABLE + 'Compare C Enable' + [30:30] + read-write + + + RSVD_31 + N/A + [31:31] + read-only + + + + + SCREENING_TYPE_2_REGISTER_7 + screening type 2 register 7, same as screening_type_2_register_0 + 0x155C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + QUEUE_NUMBER + 'Queue Number (0 to 15)' + [3:0] + read-write + + + VLAN_PRIORITY + 'VLAN Priority' + [6:4] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + VLAN_ENABLE + 'VLAN Enable' + [8:8] + read-write + + + INDEX + 'Index to screener type 2 EtherType register' + [11:9] + read-write + + + ETHERTYPE_ENABLE + 'EtherType Enable' + [12:12] + read-write + + + COMPARE_A + 'Compare A - Index to screener type 2 Compare register ' + [17:13] + read-write + + + COMPARE_A_ENABLE + 'Compare A Enable' + [18:18] + read-write + + + COMPARE_B + 'Compare B - Index to screener type 2 Compare register' + [23:19] + read-write + + + COMPARE_B_ENABLE + 'Compare B Enable' + [24:24] + read-write + + + COMPARE_C + 'Compare C - Index to screener type 2 Compare register' + [29:25] + read-write + + + COMPARE_C_ENABLE + 'Compare C Enable' + [30:30] + read-write + + + RSVD_31 + N/A + [31:31] + read-only + + + + + SCREENING_TYPE_2_REGISTER_8 + screening type 2 register 8, same as screening_type_2_register_0 + 0x1560 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + QUEUE_NUMBER + 'Queue Number (0 to 15)' + [3:0] + read-write + + + VLAN_PRIORITY + 'VLAN Priority' + [6:4] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + VLAN_ENABLE + 'VLAN Enable' + [8:8] + read-write + + + INDEX + 'Index to screener type 2 EtherType register' + [11:9] + read-write + + + ETHERTYPE_ENABLE + 'EtherType Enable' + [12:12] + read-write + + + COMPARE_A + 'Compare A - Index to screener type 2 Compare register ' + [17:13] + read-write + + + COMPARE_A_ENABLE + 'Compare A Enable' + [18:18] + read-write + + + COMPARE_B + 'Compare B - Index to screener type 2 Compare register' + [23:19] + read-write + + + COMPARE_B_ENABLE + 'Compare B Enable' + [24:24] + read-write + + + COMPARE_C + 'Compare C - Index to screener type 2 Compare register' + [29:25] + read-write + + + COMPARE_C_ENABLE + 'Compare C Enable' + [30:30] + read-write + + + RSVD_31 + N/A + [31:31] + read-only + + + + + SCREENING_TYPE_2_REGISTER_9 + screening type 2 register 9, same as screening_type_2_register_0 + 0x1564 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + QUEUE_NUMBER + 'Queue Number (0 to 15)' + [3:0] + read-write + + + VLAN_PRIORITY + 'VLAN Priority' + [6:4] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + VLAN_ENABLE + 'VLAN Enable' + [8:8] + read-write + + + INDEX + 'Index to screener type 2 EtherType register' + [11:9] + read-write + + + ETHERTYPE_ENABLE + 'EtherType Enable' + [12:12] + read-write + + + COMPARE_A + 'Compare A - Index to screener type 2 Compare register ' + [17:13] + read-write + + + COMPARE_A_ENABLE + 'Compare A Enable' + [18:18] + read-write + + + COMPARE_B + 'Compare B - Index to screener type 2 Compare register' + [23:19] + read-write + + + COMPARE_B_ENABLE + 'Compare B Enable' + [24:24] + read-write + + + COMPARE_C + 'Compare C - Index to screener type 2 Compare register' + [29:25] + read-write + + + COMPARE_C_ENABLE + 'Compare C Enable' + [30:30] + read-write + + + RSVD_31 + N/A + [31:31] + read-only + + + + + SCREENING_TYPE_2_REGISTER_10 + screening type 2 register 10, same as screening_type_2_register_0 + 0x1568 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + QUEUE_NUMBER + 'Queue Number (0 to 15)' + [3:0] + read-write + + + VLAN_PRIORITY + 'VLAN Priority' + [6:4] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + VLAN_ENABLE + 'VLAN Enable' + [8:8] + read-write + + + INDEX + 'Index to screener type 2 EtherType register' + [11:9] + read-write + + + ETHERTYPE_ENABLE + 'EtherType Enable' + [12:12] + read-write + + + COMPARE_A + 'Compare A - Index to screener type 2 Compare register ' + [17:13] + read-write + + + COMPARE_A_ENABLE + 'Compare A Enable' + [18:18] + read-write + + + COMPARE_B + 'Compare B - Index to screener type 2 Compare register' + [23:19] + read-write + + + COMPARE_B_ENABLE + 'Compare B Enable' + [24:24] + read-write + + + COMPARE_C + 'Compare C - Index to screener type 2 Compare register' + [29:25] + read-write + + + COMPARE_C_ENABLE + 'Compare C Enable' + [30:30] + read-write + + + RSVD_31 + N/A + [31:31] + read-only + + + + + SCREENING_TYPE_2_REGISTER_11 + screening type 2 register 11, same as screening_type_2_register_0 + 0x156C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + QUEUE_NUMBER + 'Queue Number (0 to 15)' + [3:0] + read-write + + + VLAN_PRIORITY + 'VLAN Priority' + [6:4] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + VLAN_ENABLE + 'VLAN Enable' + [8:8] + read-write + + + INDEX + 'Index to screener type 2 EtherType register' + [11:9] + read-write + + + ETHERTYPE_ENABLE + 'EtherType Enable' + [12:12] + read-write + + + COMPARE_A + 'Compare A - Index to screener type 2 Compare register ' + [17:13] + read-write + + + COMPARE_A_ENABLE + 'Compare A Enable' + [18:18] + read-write + + + COMPARE_B + 'Compare B - Index to screener type 2 Compare register' + [23:19] + read-write + + + COMPARE_B_ENABLE + 'Compare B Enable' + [24:24] + read-write + + + COMPARE_C + 'Compare C - Index to screener type 2 Compare register' + [29:25] + read-write + + + COMPARE_C_ENABLE + 'Compare C Enable' + [30:30] + read-write + + + RSVD_31 + N/A + [31:31] + read-only + + + + + SCREENING_TYPE_2_REGISTER_12 + screening type 2 register 12, same as screening_type_2_register_0 + 0x1570 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + QUEUE_NUMBER + 'Queue Number (0 to 15)' + [3:0] + read-write + + + VLAN_PRIORITY + 'VLAN Priority' + [6:4] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + VLAN_ENABLE + 'VLAN Enable' + [8:8] + read-write + + + INDEX + 'Index to screener type 2 EtherType register' + [11:9] + read-write + + + ETHERTYPE_ENABLE + 'EtherType Enable' + [12:12] + read-write + + + COMPARE_A + 'Compare A - Index to screener type 2 Compare register ' + [17:13] + read-write + + + COMPARE_A_ENABLE + 'Compare A Enable' + [18:18] + read-write + + + COMPARE_B + 'Compare B - Index to screener type 2 Compare register' + [23:19] + read-write + + + COMPARE_B_ENABLE + 'Compare B Enable' + [24:24] + read-write + + + COMPARE_C + 'Compare C - Index to screener type 2 Compare register' + [29:25] + read-write + + + COMPARE_C_ENABLE + 'Compare C Enable' + [30:30] + read-write + + + RSVD_31 + N/A + [31:31] + read-only + + + + + SCREENING_TYPE_2_REGISTER_13 + screening type 2 register 13, same as screening_type_2_register_0 + 0x1574 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + QUEUE_NUMBER + 'Queue Number (0 to 15)' + [3:0] + read-write + + + VLAN_PRIORITY + 'VLAN Priority' + [6:4] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + VLAN_ENABLE + 'VLAN Enable' + [8:8] + read-write + + + INDEX + 'Index to screener type 2 EtherType register' + [11:9] + read-write + + + ETHERTYPE_ENABLE + 'EtherType Enable' + [12:12] + read-write + + + COMPARE_A + 'Compare A - Index to screener type 2 Compare register ' + [17:13] + read-write + + + COMPARE_A_ENABLE + 'Compare A Enable' + [18:18] + read-write + + + COMPARE_B + 'Compare B - Index to screener type 2 Compare register' + [23:19] + read-write + + + COMPARE_B_ENABLE + 'Compare B Enable' + [24:24] + read-write + + + COMPARE_C + 'Compare C - Index to screener type 2 Compare register' + [29:25] + read-write + + + COMPARE_C_ENABLE + 'Compare C Enable' + [30:30] + read-write + + + RSVD_31 + N/A + [31:31] + read-only + + + + + SCREENING_TYPE_2_REGISTER_14 + screening type 2 register 14, same as screening_type_2_register_0 + 0x1578 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + QUEUE_NUMBER + 'Queue Number (0 to 15)' + [3:0] + read-write + + + VLAN_PRIORITY + 'VLAN Priority' + [6:4] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + VLAN_ENABLE + 'VLAN Enable' + [8:8] + read-write + + + INDEX + 'Index to screener type 2 EtherType register' + [11:9] + read-write + + + ETHERTYPE_ENABLE + 'EtherType Enable' + [12:12] + read-write + + + COMPARE_A + 'Compare A - Index to screener type 2 Compare register ' + [17:13] + read-write + + + COMPARE_A_ENABLE + 'Compare A Enable' + [18:18] + read-write + + + COMPARE_B + 'Compare B - Index to screener type 2 Compare register' + [23:19] + read-write + + + COMPARE_B_ENABLE + 'Compare B Enable' + [24:24] + read-write + + + COMPARE_C + 'Compare C - Index to screener type 2 Compare register' + [29:25] + read-write + + + COMPARE_C_ENABLE + 'Compare C Enable' + [30:30] + read-write + + + RSVD_31 + N/A + [31:31] + read-only + + + + + SCREENING_TYPE_2_REGISTER_15 + screening type 2 register 15, same as screening_type_2_register_0 + 0x157C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + QUEUE_NUMBER + 'Queue Number (0 to 15)' + [3:0] + read-write + + + VLAN_PRIORITY + 'VLAN Priority' + [6:4] + read-write + + + RSVD_7 + N/A + [7:7] + read-write + + + VLAN_ENABLE + 'VLAN Enable' + [8:8] + read-write + + + INDEX + 'Index to screener type 2 EtherType register' + [11:9] + read-write + + + ETHERTYPE_ENABLE + 'EtherType Enable' + [12:12] + read-write + + + COMPARE_A + 'Compare A - Index to screener type 2 Compare register ' + [17:13] + read-write + + + COMPARE_A_ENABLE + 'Compare A Enable' + [18:18] + read-write + + + COMPARE_B + 'Compare B - Index to screener type 2 Compare register' + [23:19] + read-write + + + COMPARE_B_ENABLE + 'Compare B Enable' + [24:24] + read-write + + + COMPARE_C + 'Compare C - Index to screener type 2 Compare register' + [29:25] + read-write + + + COMPARE_C_ENABLE + 'Compare C Enable' + [30:30] + read-write + + + RSVD_31 + N/A + [31:31] + read-only + + + + + TX_SCHED_CTRL + This register controls the transmit scheduling algorithm the user can select for each active transmit queue. By default all queues are initialized to fixed priority, with the top indexed queue having overall priority + 0x1580 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TX_SCHED_Q0 + 'Queue 0 selection. + 00 : Fixed Priority + 01 : CBS Enabled only valid for top two enabled queues and if CBS capability selected. + 10 : DWRR Enabled + 11 : ETS Enabled' + [1:0] + read-write + + + TX_SCHED_Q1 + 'Queue 1 selection. + 00 : Fixed Priority + 01 : CBS Enabled only valid for top two enabled queues and if CBS capability selected. + 10 : DWRR Enabled + 11 : ETS Enabled' + [3:2] + read-write + + + TX_SCHED_Q2 + 'Queue 2 selection. + 00 : Fixed Priority + 01 : CBS Enabled only valid for top two enabled queues and if CBS capability selected. + 10 : DWRR Enabled + 11 : ETS Enabled + [5:4] + read-write + + + TX_SCHED_Q3 + Write ignore, read 0 + [7:6] + read-only + + + REMOVED_31_8 + Write ignore, read 0 + [31:8] + read-only + + + + + BW_RATE_LIMIT_Q0TO3 + This register holds the DWRR weighting value or the ETS bandwidth percentage value used by the transmit scheduler for queues 0 to 3. + 0x1590 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DWRR_ETS_WEIGHT_Q0 + 'DWRR Weighting / ETS Bandwidth Allocation for queue 0' + [7:0] + read-write + + + DWRR_ETS_WEIGHT_Q1 + 'DWRR Weighting / ETS Bandwidth Allocation for queue 1' + [15:8] + read-write + + + DWRR_ETS_WEIGHT_Q2 + 'DWRR Weighting / ETS Bandwidth Allocation for queue 2' + [23:16] + read-write + + + DWRR_ETS_WEIGHT_Q3 + Write ignore, read 0 + [31:24] + read-only + + + + + BW_RATE_LIMIT_Q4TO7 + Not presents. MXETH has only 3 queues. Access to the register returns AHB error. + 0x1594 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + 'DWRR Weighting / ETS Bandwidth Allocation for queue 0' + [31:0] + read-write + + + + + BW_RATE_LIMIT_Q8TO11 + Not presents. MXETH has only 3 queues. Access to the register returns AHB error. + 0x1598 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + BW_RATE_LIMIT_Q12TO15 + Not presents. MXETH has only 3 queues. Access to the register returns AHB error. + 0x159C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + TX_Q_SEG_ALLOC_Q0TO7 + This register allows the user to distribute the Transmit SRAM used by the DMA across the priority queues, for queues 0 to 7. The SRAM itself is split into a number of evenly sized segments (this is defined in the verilog configuration defs file - for the configuration used to generate this register description, the total number of segments was set to '16'). Those segments can then be freely distributed across the active queues, in powers of 2. I.e. a value of 0 would mean 1 segment has been allocated to the queue. A value of 1 would mean 2 segments, a value of 2 means 4 segments and so on. The reset values of these registers are defined in the configuration defs file. + 0x15A0 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + SEGMENT_ALLOC_Q0 + Number of segments allocated to q0. This should be entered as a log 2, for example entering a value of 2 would grant 4 segments. A maximum of 32 segments can be granted. The default value is determined by `gem_tx_pbuf_num_segments_q0 + [2:0] + read-write + + + RSVD_3_3 + N/A + [3:3] + read-only + + + SEGMENT_ALLOC_Q1 + Number of segments allocated to q1. This should be entered as a log 2, for example entering a value of 2 would grant 4 segments. A maximum of 32 segments can be granted + [6:4] + read-write + + + RSVD_7_7 + N/A + [7:7] + read-only + + + SEGMENT_ALLOC_Q2 + Number of segments allocated to q2. This should be entered as a log 2, for example entering a value of 2 would grant 4 segments. A maximum of 32 segments can be granted + [10:8] + read-write + + + RSVD_11_11 + Write ignore, read 0 + [11:11] + read-only + + + REMOVED_14_12 + Write ignore, read 0 + [14:12] + read-only + + + RSVD_15_15 + Write ignore, read 0 + [15:15] + read-only + + + REMOVED_18_16 + Write ignore, read 0 + [18:16] + read-only + + + RSVD_19_19 + Write ignore, read 0 + [19:19] + read-only + + + REMOVED_22_20 + Write ignore, read 0 + [22:20] + read-only + + + RSVD_23 + Write ignore, read 0 + [23:23] + read-only + + + REMOVED_26_24 + Write ignore, read 0 + [26:24] + read-only + + + RSVD_27_27 + Write ignore, read 0 + [27:27] + read-only + + + REMOVED_30_28 + Write ignore, read 0 + [30:28] + read-only + + + RSVD_31_31 + Write ignore, read 0 + [31:31] + read-only + + + + + TX_Q_SEG_ALLOC_Q8TO15 + Not presents. Access to the register returns AHB error. + 0x15A4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + RECEIVE_Q8_PTR + receive_q8_ptr to receive_q15_ptr doesn't present. Access to the register returns AHB error. + 0x15C0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + RECEIVE_Q15_PTR + Not presents. + 0x15DC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + DMA_RXBUF_SIZE_Q8 + dma_rxbuf_size_q8 to dma_rxbuf_size_q15 doesn't present. Access to the register returns AHB error. + 0x15E0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + DMA_RXBUF_SIZE_Q15 + Not presents. + 0x15FC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + INT_Q1_ENABLE + At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero. + 0x1600 + 32 + write-only + 0x0 + 0x8E6 + + + ENABLE_RECEIVE_COMPLETE_INTERRUPT + Enable Receive complete interrupt + [1:1] + write-only + + + ENABLE_RX_USED_BIT_READ_INTERRUPT + Enable RX used bit read interrupt + [2:2] + write-only + + + ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT + Enable Retry limit exceeded or late collision interrupt + [5:5] + write-only + + + ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT + Enable Transmit frame corruption due to AMBA (AXI/AHB) error interrupt + [6:6] + write-only + + + ENABLE_TRANSMIT_COMPLETE_INTERRUPT + Enable Transmit complete interrupt + [7:7] + write-only + + + ENABLE_RESP_NOT_OK_INTERRUPT + Enable bresp not OK interrupt + [11:11] + write-only + + + + + INT_Q2_ENABLE + At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero. + 0x1604 + 32 + write-only + 0x0 + 0x8E6 + + + ENABLE_RECEIVE_COMPLETE_INTERRUPT + Enable Receive complete interrupt + [1:1] + write-only + + + ENABLE_RX_USED_BIT_READ_INTERRUPT + Enable RX used bit read interrupt + [2:2] + write-only + + + ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT + Enable Retry limit exceeded or late collision interrupt + [5:5] + write-only + + + ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT + Enable Transmit frame corruption due to AMBA (AXI/AHB) error interrupt + [6:6] + write-only + + + ENABLE_TRANSMIT_COMPLETE_INTERRUPT + Enable Transmit complete interrupt + [7:7] + write-only + + + ENABLE_RESP_NOT_OK_INTERRUPT + Enable bresp not OK interrupt + [11:11] + write-only + + + + + INT_Q3_ENABLE + int_q3_enable to int_q7_enable doesn't present. Access to the register returns AHB error. + 0x1608 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + INT_Q7_ENABLE + Not presents. + 0x1618 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + INT_Q1_DISABLE + Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero. + 0x1620 + 32 + write-only + 0x0 + 0x8E6 + + + DISABLE_RECEIVE_COMPLETE_INTERRUPT + Disable Receive complete interrupt + [1:1] + write-only + + + DISABLE_RX_USED_BIT_READ_INTERRUPT + Disable RX used bit read interrupt + [2:2] + write-only + + + DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT + Disable Retry limit exceeded or late collision interrupt + [5:5] + write-only + + + DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT + Disable Transmit frame corruption due to AMBA (AXI/AHB) error interrupt + [6:6] + write-only + + + DISABLE_TRANSMIT_COMPLETE_INTERRUPT + Disable Transmit complete interrupt + [7:7] + write-only + + + DISABLE_RESP_NOT_OK_INTERRUPT + Disable bresp not OK interrupt + [11:11] + write-only + + + + + INT_Q2_DISABLE + Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero. + 0x1624 + 32 + write-only + 0x0 + 0x8E6 + + + DISABLE_RECEIVE_COMPLETE_INTERRUPT + Disable Receive complete interrupt + [1:1] + write-only + + + DISABLE_RX_USED_BIT_READ_INTERRUPT + Disable RX used bit read interrupt + [2:2] + write-only + + + DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT + Disable Retry limit exceeded or late collision interrupt + [5:5] + write-only + + + DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT + Disable Transmit frame corruption due to AMBA (AXI/AHB) error interrupt + [6:6] + write-only + + + DISABLE_TRANSMIT_COMPLETE_INTERRUPT + Disable Transmit complete interrupt + [7:7] + write-only + + + DISABLE_RESP_NOT_OK_INTERRUPT + Disable bresp not OK interrupt + [11:11] + write-only + + + + + INT_Q3_DISABLE + int_q3_disable to int_q7_disable doesn't present. Access to the register returns AHB error. + 0x1628 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + INT_Q7_DISABLE + Not presents. + 0x1638 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + INT_Q1_MASK + The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register. + 0x1640 + 32 + read-only + 0x8E6 + 0x8E6 + + + RECEIVE_COMPLETE_INTERRUPT_MASK + receive complete interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [1:1] + read-only + + + RX_USED_INTERRUPT_MASK + A read of this register returns the value of the RX Used interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [2:2] + read-only + + + RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK + retry limit exceeded or late collision interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [5:5] + read-only + + + AMBA_ERROR_INTERRUPT_MASK + A read of this register returns the value of the AMBA (AXI/AHB) error interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [6:6] + read-only + + + TRANSMIT_COMPLETE_INTERRUPT_MASK + transmit complete interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [7:7] + read-only + + + RESP_NOT_OK_INTERRUPT_MASK + bresp not OK interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [11:11] + read-only + + + + + INT_Q2_MASK + The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register. + 0x1644 + 32 + read-only + 0x8E6 + 0x8E6 + + + RECEIVE_COMPLETE_INTERRUPT_MASK + receive complete interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [1:1] + read-only + + + RX_USED_INTERRUPT_MASK + A read of this register returns the value of the RX Used interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [2:2] + read-only + + + RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK + retry limit exceeded or late collision interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [5:5] + read-only + + + AMBA_ERROR_INTERRUPT_MASK + A read of this register returns the value of the AMBA (AXI/AHB) error interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [6:6] + read-only + + + TRANSMIT_COMPLETE_INTERRUPT_MASK + transmit complete interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [7:7] + read-only + + + RESP_NOT_OK_INTERRUPT_MASK + bresp not OK interrupt mask. + 0: Interrupt is enabled. + 1: Interrupt is disabled. +A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. + [11:11] + read-only + + + + + INT_Q3_MASK + int_q3_mask to int_q7_mask doesn't present. Access to the register returns AHB error. + 0x1648 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + INT_Q7_MASK + Not presents. + 0x1658 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + INT_Q8_ENABLE + int_q8_enable to int_q15_enable doesn't present. Access to the register returns AHB error. + 0x1660 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + INT_Q15_ENABLE + Not presents. + 0x167C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + INT_Q8_DISABLE + int_q8_disable to int_q15_disable doesn't present. Access to the register returns AHB error. + 0x1680 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + INT_Q15_DISABLE + Not presents. + 0x169C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + INT_Q8_MASK + int_q8_mask to int_q15_mask doesn't present. Access to the register returns AHB error. + 0x16A0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + INT_Q15_MASK + Not presents. + 0x16BC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REMOVED_31_0 + Write ignore, read 0 + [31:0] + read-only + + + + + SCREENING_TYPE_2_ETHERTYPE_REG_0 + Ethertype Register + 0x16E0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COMPARE_VALUE + 'EtherType compare value' + [15:0] + read-write + + + RSVD_31_16 + N/A + [31:16] + read-only + + + + + SCREENING_TYPE_2_ETHERTYPE_REG_1 + Ethertype Register + 0x16E4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COMPARE_VALUE + 'EtherType compare value' + [15:0] + read-write + + + RSVD_31_16 + N/A + [31:16] + read-only + + + + + SCREENING_TYPE_2_ETHERTYPE_REG_2 + Ethertype Register + 0x16E8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COMPARE_VALUE + 'EtherType compare value' + [15:0] + read-write + + + RSVD_31_16 + N/A + [31:16] + read-only + + + + + SCREENING_TYPE_2_ETHERTYPE_REG_3 + Ethertype Register + 0x16EC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COMPARE_VALUE + 'EtherType compare value' + [15:0] + read-write + + + RSVD_31_16 + N/A + [31:16] + read-only + + + + + SCREENING_TYPE_2_ETHERTYPE_REG_4 + Ethertype Register + 0x16F0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COMPARE_VALUE + 'EtherType compare value' + [15:0] + read-write + + + RSVD_31_16 + N/A + [31:16] + read-only + + + + + SCREENING_TYPE_2_ETHERTYPE_REG_5 + Ethertype Register + 0x16F4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COMPARE_VALUE + 'EtherType compare value' + [15:0] + read-write + + + RSVD_31_16 + N/A + [31:16] + read-only + + + + + SCREENING_TYPE_2_ETHERTYPE_REG_6 + Ethertype Register + 0x16F8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COMPARE_VALUE + 'EtherType compare value' + [15:0] + read-write + + + RSVD_31_16 + N/A + [31:16] + read-only + + + + + SCREENING_TYPE_2_ETHERTYPE_REG_7 + Ethertype Register + 0x16FC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COMPARE_VALUE + 'EtherType compare value' + [15:0] + read-write + + + RSVD_31_16 + N/A + [31:16] + read-only + + + + + TYPE2_COMPARE_0_WORD_0 + 'Compare A, B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value if the mask is enabled, is equal to the COMPARE Value. Either a 16 bit comparison or a 32 bit comparison is done. This selection is made via the associated compare word1 register bit 9. If a 16 bit comparison is selected, then a 16 bit mask is also available to the user to select which bits should be compared. If the 32 bit compare option is selected, then no mask is available. The byte at the OFFSET number of bytes from the index start is compared thru bits 7 to 0 of the configured VALUE. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15 to 8 of the configured VALUE and so on. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the therType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value it's not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used. ' + 0x1700 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_0_WORD_1 + 'Type2 Compare Word 1' + 0x1704 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_1_WORD_0 + same as type2_compare_0_word_0 + 0x1708 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_1_WORD_1 + same as type2_compare_0_word_1 + 0x170C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_2_WORD_0 + same as type2_compare_0_word_0 + 0x1710 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_2_WORD_1 + same as type2_compare_0_word_1 + 0x1714 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_3_WORD_0 + same as type2_compare_0_word_0 + 0x1718 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_3_WORD_1 + same as type2_compare_0_word_1 + 0x171C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_4_WORD_0 + same as type2_compare_0_word_0 + 0x1720 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_4_WORD_1 + same as type2_compare_0_word_1 + 0x1724 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_5_WORD_0 + same as type2_compare_0_word_0 + 0x1728 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_5_WORD_1 + same as type2_compare_0_word_1 + 0x172C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_6_WORD_0 + same as type2_compare_0_word_0 + 0x1730 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_6_WORD_1 + same as type2_compare_0_word_1 + 0x1734 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_7_WORD_0 + same as type2_compare_0_word_0 + 0x1738 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_7_WORD_1 + same as type2_compare_0_word_1 + 0x173C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_8_WORD_0 + same as type2_compare_0_word_0 + 0x1740 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_8_WORD_1 + same as type2_compare_0_word_1 + 0x1744 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_9_WORD_0 + same as type2_compare_0_word_0 + 0x1748 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_9_WORD_1 + same as type2_compare_0_word_1 + 0x174C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_10_WORD_0 + same as type2_compare_0_word_0 + 0x1750 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_10_WORD_1 + same as type2_compare_0_word_1 + 0x1754 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_11_WORD_0 + same as type2_compare_0_word_0 + 0x1758 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_11_WORD_1 + same as type2_compare_0_word_1 + 0x175C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_12_WORD_0 + same as type2_compare_0_word_0 + 0x1760 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_12_WORD_1 + same as type2_compare_0_word_1 + 0x1764 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_13_WORD_0 + same as type2_compare_0_word_0 + 0x1768 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_13_WORD_1 + same as type2_compare_0_word_1 + 0x176C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_14_WORD_0 + same as type2_compare_0_word_0 + 0x1770 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_14_WORD_1 + same as type2_compare_0_word_1 + 0x1774 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_15_WORD_0 + same as type2_compare_0_word_0 + 0x1778 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_15_WORD_1 + same as type2_compare_0_word_1 + 0x177C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_16_WORD_0 + same as type2_compare_0_word_0 + 0x1780 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_16_WORD_1 + same as type2_compare_0_word_1 + 0x1784 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_17_WORD_0 + same as type2_compare_0_word_0 + 0x1788 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_17_WORD_1 + same as type2_compare_0_word_1 + 0x178C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_18_WORD_0 + same as type2_compare_0_word_0 + 0x1790 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_18_WORD_1 + same as type2_compare_0_word_1 + 0x1794 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_19_WORD_0 + same as type2_compare_0_word_0 + 0x1798 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_19_WORD_1 + same as type2_compare_0_word_1 + 0x179C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_20_WORD_0 + same as type2_compare_0_word_0 + 0x17A0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_20_WORD_1 + same as type2_compare_0_word_1 + 0x17A4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_21_WORD_0 + same as type2_compare_0_word_0 + 0x17A8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_21_WORD_1 + same as type2_compare_0_word_1 + 0x17AC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_22_WORD_0 + same as type2_compare_0_word_0 + 0x17B0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_22_WORD_1 + same as type2_compare_0_word_1 + 0x17B4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_23_WORD_0 + same as type2_compare_0_word_0 + 0x17B8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_23_WORD_1 + same as type2_compare_0_word_1 + 0x17BC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_24_WORD_0 + same as type2_compare_0_word_0 + 0x17C0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_24_WORD_1 + same as type2_compare_0_word_1 + 0x17C4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_25_WORD_0 + same as type2_compare_0_word_0 + 0x17C8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_25_WORD_1 + same as type2_compare_0_word_1 + 0x17CC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_26_WORD_0 + same as type2_compare_0_word_0 + 0x17D0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_26_WORD_1 + same as type2_compare_0_word_1 + 0x17D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_27_WORD_0 + same as type2_compare_0_word_0 + 0x17D8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_27_WORD_1 + same as type2_compare_0_word_1 + 0x17DC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_28_WORD_0 + same as type2_compare_0_word_0 + 0x17E0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_28_WORD_1 + same as type2_compare_0_word_1 + 0x17E4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_29_WORD_0 + same as type2_compare_0_word_0 + 0x17E8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_29_WORD_1 + same as type2_compare_0_word_1 + 0x17EC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_30_WORD_0 + same as type2_compare_0_word_0 + 0x17F0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_30_WORD_1 + same as type2_compare_0_word_1 + 0x17F4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + TYPE2_COMPARE_31_WORD_0 + same as type2_compare_0_word_0 + 0x17F8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MASK_VALUE + These bits can be either a 2 byte mask field or an additional 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [7:0] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [15:8] is compared against the byte in the received frame from the selected offset+1. +If bit 9 of the associated compare_word1 register is clear, these bits become a direct 2-byte mask for the 2-byte compare register in bits [31:16]. + [15:0] + read-write + + + COMPARE_VALUE_TYPE2 + 2 byte Compare Value. +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [31:16] + read-write + + + + + TYPE2_COMPARE_31_WORD_1 + same as type2_compare_0_word_1 + 0x17FC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OFFSET_VALUE + 'Offset value in bytes' + [6:0] + read-write + + + COMPARE_OFFSET + 'Compare byte offset. +00 : Offset from beginning of the frame. +01 : Offset from byte after Ether Type. +10 : Offset from byte following end of IP header. +11 : Offset from byte following end of TCP/UDP header' + +If bit 9 of the associated compare_word1 register is set, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+2 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+3. +If bit 9 of the associated compare_word1 register is clear, then the byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0 and the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+1. + [8:7] + read-write + + + DISABLE_MASK + 'This bit is used to control whether the compare register word_0 contains a 4-byte compare value, or a 2-byte compare value with a 2-byte mask value. +1 - 4-byte compare value +0 - 2-byte compare, 2-byte mask ' + [9:9] + read-write + + + RSVD_31_10 + N/A + [31:10] + read-only + + + + + + + LIN0 + LIN + LIN + 0x40500000 + + 0 + 65536 + registers + + + + ERROR_CTL + Error control + 0x0 + 32 + read-write + 0x0 + 0x80EF001F + + + CH_IDX + Specifies the channel index of the channel to which HW injected channel transmitter errors applies. + [4:0] + read-write + + + TX_SYNC_ERROR + The synchronization field is changed from 0x55 to 0x00. + +At the receiver, this should result in INTR.RX_HEADER_SYNC_ERROR activation. + [16:16] + read-write + + + TX_SYNC_STOP_ERROR + The synchronization field STOP bits are inverted to '0'. + +At the receiver, this should result in INTR.RX_HEADER_SYNC_ERROR or INTR.RX_HEADER_FRAME_ERROR activation. + [17:17] + read-write + + + TX_PARITY_ERROR + In LIN mode, the PID parity bit P[1] is inverted from !(ID[5] ^ ID[4] ^ ID[3] ^ ID[1]) to (ID[5] ^ ID[4] ^ ID[3] ^ ID[1]). + +At the receiver, this should result in INTR.RX_HEADER_PARITY_ERROR activation. + +In UART mode, a data field's parity bit is inverted. + [18:18] + read-write + + + TX_PID_STOP_ERROR + The PID field STOP bits are inverted to '0'. + +At the receiver, this should result in INTR.RX_HEADER_FRAME_ERROR activation. + [19:19] + read-write + + + TX_DATA_STOP_ERROR + The data field STOP bits are inverted to '0'. + +At the receiver, this should result in INTR.RX_RESPONSE_FRAME_ERROR activation. + +Note: Used in UART mode. + [21:21] + read-write + + + TX_CHECKSUM_ERROR + The checksum field is inverted. + +At the receiver, this should result in INTR.RX_RESPONSE_CHECKSUM_ERROR activation. + [22:22] + read-write + + + TX_CHECKSUM_STOP_ERROR + The checksum field STOP bits are inverted to '0'. + +At the receiver, this should result in INTR.RX_RESPONSE_FRAME_ERROR activation. + [23:23] + read-write + + + ENABLED + Error injection enable: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + TEST_CTL + Test control + 0x4 + 32 + read-write + 0x0 + 0x8001001F + + + CH_IDX + Specifies the channel index of the channel to which test applies. The channel IO signals of channel indices CH_IDX and CH_NR-1 are connected as specified by MODE. CH_IDX should be in the range [0, CH_NR-2], as channel index CH_NR-1 is always involved in test and cannot be connected to itself. The test mode allows BOTH of the two connected channels to be tested. + +Note: this testing functionality simplifies SW development, but may also be used in the field to verify correct channel functionality. + [4:0] + read-write + + + MODE + Test mode: +'0': Partial disconnect from IOSS. This mode's isolation allows for device test without relying on an external LIN transceiver. The IOSS 'tx' IO cell can be used to observe messages outside of the device. +- tx_in[CH_IDX] = IOSS lin_tx_in[CH_IDX]. +- tx_in[CH_NR-1] = IOSS lin_tx_in[CH_IDX]. +- rx_in[CH_IDX] = IOSS lin_tx_in[CH_IDX]. +- rx_in[CH_NR-1] = IOSS lin_tx_in[CH_IDX]. +- lin_tx_out[CH_IDX] = tx_out[CH_IDX] & tx_out[CH_NR-1]. +- lin_tx_out[CH_NR-1] = tx_out[CH_IDX] & tx_out[CH_NR-1]. + +'1': Full disconnect from IOSS (the IOSS/HSIOM should disconnect 'tx_out' from the 'tx' IO cell). This mode's isolation allows for device test without effecting an operational LIN cluster. +- tx_in[CH_IDX] = lin_tx_out[CH_IDX]. +- tx_in[CH_NR-1] = lin_tx_out[CH_IDX]. +- rx_in[CH_IDX] = lin_tx_out[CH_IDX]. +- rx_in[CH_NR-1] = lin_tx_out[CH_IDX]. +- lin_tx_out[CH_IDX] = tx_out[CH_IDX] & tx_out[CH_NR-1]. +- lin_tx_out[CH_NR-1] = tx_out[CH_IDX] & tx_out[CH_NR-1]. + [16:16] + read-write + + + ENABLED + Test enable: +'0': Disabled. Functional mode. +- tx_in[CH_IDX] = IOSS lin_tx_in[CH_IDX]. +- tx_in[CH_NR-1] = IOSS lin_tx_in[CH_NR-1]. +- rx_in[CH_IDX] = IOSS lin_rx_in[CH_IDX]. +- rx_in[CH_NR-1] = IOSS lin_rx_in[CH_NR-1]. +- lin_tx_out[CH_IDX] = tx_out[CH_IDX]. +- lin_tx_out[CH_NR-1] = tx_out[CH_NR-1]. +'1': Enabled. Test mode, specific test mode is specified by MODE. + [31:31] + read-write + + + + + 16 + 256 + CH[%s] + LIN channel structure + 0x00008000 + + CTL0 + Control 0 + 0x0 + 32 + read-write + 0x400C0101 + 0xF91F0313 + + + STOP_BITS + STOP bit periods: +'0': 1/2 bit period. +'1': 1 bit period. +'2': 1 1/2 bit period. +'3': 2 bit periods. + + +In LIN mode, this field should be set to '1' (the default value) . + +In UART mode, this field can be programmed as desired. + +Note: receiver STOP bit frame errors can only be detected if the number of STOP bit periods is 1 or more bit period. + [1:0] + read-write + + + AUTO_EN + LIN transceiver auto enable: +'0': Disabled. +'1': Enabled. The TX_RX_STATUS.EN_OUT field is controlled by HW. + [4:4] + read-write + + + BREAK_DELIMITER_LENGTH + In LIN mode, this field specifies the break delimiter length: +(used in header transmission, not used in header reception). +'0': 1 bit period. +'1': 2 bit periods (default value). +'2': 3 bit periods. +'3': 4 bit periods. + +In UART mode, this field specifies the data field size: +'0': 5 bit data field. +'1': 6 bit data field. +'2': 7 bit data field. +'3': 8 bit data field. +When the data field size is less than 8 bits, the most significant (unused) bits of the DATAx.DATAy[7:0] fields should be set to '0' for the transmitter. + [9:8] + read-write + + + BREAK_WAKEUP_LENGTH + Break/wakeup length (minus 1) in bit periods: +'0': 1 bit period. +... +'10': 11 bit periods (break length for slave nodes) +... +'12': 13 bit periods (break length for master nodes) +... +'30': 31 bit periods. +'31': Illegal (should NOT be used!!!) + +This field is used for transmission/reception of BOTH break and wakeup signals. Note that these functions are mutually exclusive: +- When CMD.TX_HEADER is '1', the field specifies the transmitted break field. +- When CMD.TX_WAKEUP is '1', the field specifies the transmitted wakeup field. +- When CMD.RX_HEADER is '1', the field specifies the to be received break field. +- Otherwise, the field specifies the to be received wakeup field. + +Per the standard, the master wakeup duration is between 250 us and 5 ms. To support uncalibrated slaves, a slave has a detection threshold of 150 us (3 bit periods at 20 kbps). After transmission of a break or wakeup signal, the INTR.TX_BREAK_WAKEUP_DONE interrupt cause is activated. After reception of a wakeup signal, the INTR.RX_BREAK_WAKEUP_DONE interrupt cause is activated. + +To specify longer wakeup signals in terms of absolute time (us/ms rather than bit periods), the associated PERI clock divider value can be (temporarily) increased to make the LIN bit period longer. + +Note: entering bus sleep mode is achieved with the 'go-to-sleep' command. + [20:16] + read-write + + + MODE + Mode of operation: +'0': LIN mode. +'1': UART mode. + [24:24] + read-write + + + LIN + LIN mode. + 0 + + + UART + UART mode. + 1 + + + + + BIT_ERROR_IGNORE + Specifies behavior on a detected bit error during header or response transmission: +'0': Message transfer is aborted. +'1': Message transfer is NOT aborted. + +Note: this field does NOT effect the reporting of the bit error through INTR/STATUS.TX_HEADER/RESPONSE_BIT_ERROR; i.e. bit errors are always reported. + [27:27] + read-write + + + PARITY + Parity mode: +'0': Even parity: even number of '1' bits (including parity). +'1': Odd parity. + +Note: Used in UART mode only. + [28:28] + read-write + + + PARITY_EN + Parity generation enable: +'0': Disabled. No parity bit is transferred. +'1': Enabled. The parity bit is transferred after the last (most significant) data field bit. + +Note: Used in UART mode only. + [29:29] + read-write + + + FILTER_EN + RX filter (for 'lin_rx_in'): +'0': No filter. +'1': Median 3 (default value) operates on the last three 'lin_rx_in' values. The sequences '000', '001', '010' and '100' result in a filtered value '0'. The sequences '111', '110', '101' and '011' result in a filtered value '1'. + [30:30] + read-write + + + ENABLED + Channel enable: +'0': Disabled. If a channel is disabled, all non-retained MMIO registers (e.g. the TX_RX_STATUS, and INTR registers) have their fields reset to their default value. +'1': Enabled. + [31:31] + read-write + + + + + CTL1 + Control 1 + 0x4 + 32 + read-write + 0x0 + 0x3000000 + + + DATA_NR + Number of data fields (minus 1) in the response (not including the checksum): +'0': 1 data field. +'1': 2 data fields. +... +'7': 8 data fields. + +Note: master and slave nodes need to agree upon the number of data fields before message transfer. +In RX_RESPONSE case, When PID (header) is received, firmware has the time of one response data byte, to modify CTL1.DATA_NR. + [2:0] + read-write + + + CHECKSUM_ENHANCED + Checksum mode: +'0': Classic mode. PID field is NOT included in the checksum calculation. +'1': Enhanced mode. PID field is included in the checksum calculation. This mode requires special attention when the master node transmits the header and a (different) slave node transmits the response: the slave node will use the calculated partial checksum over the received PID field as a starting point for the calculation over the to be transmitted data fields. + +Note: If the frame identifier ID[5:0] is 0x3c or 0x3d, the classic mode will ALWAYS be used for transmission and assumed for reception, independent of the CHECKSUM_ENHANCED value. + [8:8] + read-write + + + FRAME_TIMEOUT + Specifies the maximum allowed length (timeout value) for a frame, frame header or frame response in bit periods. The LIN specification prescribes to set the maximum length to 1.4x the nominal length (Theader_max = 1.4 x Theader_nom and Tresponse_max = 1.4 x Tresponse_nom). The nominal header length Theader_nom is 34 bit periods and the nominal response length Tresponse_nom is 10 * (data_nr + 1) bit periods (data_nr is the number of data fields) + +Note: the LIN specification specifies the following: 'Tools and tests shall check the Tframe_max (= Theader_max + Tresponse_max). Nodes shall not check this time. The receiving node of the frame shall accept the frame up to the next frame slot (i.e. next break field), even if it is longer then Tframe_max).' + [23:16] + read-write + + + FRAME_TIMEOUT_SEL + Specifies the frame timeout mode: +'0': No timeout functionality (default value). +'1': Frame mode: detects timeout from the start of break field to checksum field STOP bits (inclusive). The minimum FRAME_TIMEOUT value is 34+20 bit periods (header and a response with 1 data field). +'2': Frame header mode: detects timeout from the start of break field to PID field STOP bits (inclusive). The minimum FRAME_TIMEOUT value is 34 bit periods (header). +'3': Frame response mode: detects timeout from the PID field STOP bits (exclusive) to checksum field STOP bits (the response space is included in the frame response). The minimum FRAME_TIMEOUT value is 20 bit periods (response with 1 data field). + [25:24] + read-write + + + + + STATUS + Status + 0x8 + 32 + read-only + 0x0 + 0x1F03333F + + + DATA_IDX + Number of transferred data and checksum fields in the response (also acts as an index/address into response data field and checksum field registers (DATA0, DATA1, PID_CHECKSUM)) : +'0': No data fields transferred. +'1': Data field 1 transferred. +... +'7': Data fields 1, 2, 3, ... and 7 transferred. +'8': Data fields 1, 2, 3, ... and 8 transferred. +'9': Data fields 1, 2, 3, ..., 8 and checksum field transferred. +'10'-'15': Unused. + +Set to '0' on the start of a TX_HEADER or RX_HEADER command. + [3:0] + read-only + + + HEADER_RESPONSE + Frame header / response identifier (only valid when TX_BUSY or RX_BUSY is '1'): +'0': Frame header being transferred. +'1': Frame response being transferred. + [4:4] + read-only + + + RX_DATA0_FRAME_ERROR + Frame response, first data field frame error. HW sets this field to '1' when the received STOP bits of the first response data field have an unexpected value (only after a RX_HEADER command), and this data byte is 0x00. HW clears this field to '0' at the falling edge of SYNC start bit (after INTR.RX_HEADER_BREAK_WAKEUP_DONE). This field is used together with INTR.RX_RESPONSE_FRAME_ERROR to distinguish 'no response', 'error response' and 'correct response' scenarios. + +Note: The ongoing message transfer is NOT aborted. + [5:5] + read-only + + + TX_BUSY + Transmitter busy. +- Set to '1' on the start of the following commands: TX_HEADER, TX_RESPONSE, TX_WAKEUP. +- Set to '0' on successful completion of previous commands or when an error is detected. + In 'TX_HEADER, RX_RESPONSE' case, set to '0' at the start bit falling edge in the first response data byte, after header transmission + [8:8] + read-only + + + RX_BUSY + Receiver busy. +- Set to '1' on the start of the following commands: RX_HEADER, RX_RESPONSE. + in RX_HEADER case, set at Break filed rising edge. + in RX_RESPONSE case, set at the start bit falling edge in the first response data byte. + +- Set to '0' on successful completion of previous commands or when an error is detected. + [9:9] + read-only + + + TX_DONE + Transmitter done: +- Set to '0' on the start of a new command. +- Set to '1' on successful completion of the following command sequences (if CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble): +- TX_HEADER. +- TX_HEADER, TX_RESPONSE. +- RX_HEADER, TX_RESPONSE. +- TX_WAKEUP. + [12:12] + read-only + + + RX_DONE + Receiver done: +- Set to '0' on the start of a new command. +- Set to '1' on successful completion of the following command sequences (if CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble): +- RX_HEADER, RX_RESPONSE. +- TX_HEADER, RX_RESPONSE. + [13:13] + read-only + + + TX_HEADER_BIT_ERROR + Copy of INTR.TX_HEADER_BIT_ERROR. + [16:16] + read-only + + + TX_RESPONSE_BIT_ERROR + Copy of INTR.TX_RESPONSE_BIT_ERROR. + [17:17] + read-only + + + RX_HEADER_FRAME_ERROR + Copy of INTR.RX_HEADER_FRAME_ERROR. + [24:24] + read-only + + + RX_HEADER_SYNC_ERROR + Copy of INTR.RX_HEADER_SYNC_ERROR. + [25:25] + read-only + + + RX_HEADER_PARITY_ERROR + Copy of INTR.RX_HEADER_PARITY_ERROR. + [26:26] + read-only + + + RX_RESPONSE_FRAME_ERROR + Copy of INTR.RX_RESPONSE_FRAME_ERROR. + [27:27] + read-only + + + RX_RESPONSE_CHECKSUM_ERROR + Copy of INTR.RX_RESPONSE_CHECKSUM_ERROR. + [28:28] + read-only + + + + + CMD + Command + 0x10 + 32 + read-write + 0x0 + 0x307 + + + TX_HEADER + SW sets this field to '1' to transmit a header. HW sets this field to '0' on successful completion of ANY of the following legal command sequences (also set to '0' when an error is detected): +- TX_HEADER +- TX_HEADER, TX_RESPONSE. +- TX_HEADER, RX_RESPONSE. +- RX_HEADER, TX_RESPONSE. +- RX_HEADER, RX_RESPONSE. +- TX_WAKEUP. + +The header is transmitted when the PID field STOP bits are transmitted (INTR.TX_HEADER_DONE). + +HW sets this field to '1', when the 'tr_cmd_tx_header' input trigger is activated. This allows for time triggered LIN message transfer. HW driven time triggered transfer eliminates the jitter that is typically associated with SW driven transfer. + +In UART mode, a single data field (DATA0.DATA1) is transmitted. + [0:0] + read-write + + + TX_RESPONSE + SW sets this field to '1' to transmit a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected). + +The response is transmitted when the checksum field STOP bits are transmitted (INTR.TX_RESPONSE_DONE). + [1:1] + read-write + + + TX_WAKEUP + SW sets this field to '1' to transmit a wakeup signal. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected). + +The command generates CTL.BREAK_WAKEUP_LENGTH bit periods in the dominant state (low/'0') and transitions to the recessive state (high/'1') (INTR.TX_WAKEUP_DONE). + [2:2] + read-write + + + RX_HEADER + SW sets this field to '1' to receive a header. HW sets this field to '0' on successful completion of the ANY of the legal command sequences (NOT set to '0' when an error is detected in LIN mode). + +The header is received when the PID field STOP bits are received (INTR.RX_HEADER_DONE). + +Typically, a slave node SW sets both RX_HEADER and RX_RESPONSE to '1', anticipating a transfer of a response from the master node to this slave node. After receipt of the header PID field (INTR.RX_HEADER_PID_DONE is activated), the slave node may decide to set TX_RESPONSE to '1' (which has a higher priority than RX_RESPONSE) to transmit a response. + +the Break detection is performed regardless of CMD.RX_HEADER. +INTR.RX_BREAK_WAKEUP_DONE will trigger at LIN_RX rising edge, when the low pulse meet CTL0.BREAK_WAKEUP_LENGTH. when Break is detected, HW check CMD.RX_HEADER before entering SYNC byte processing state. when RX_HEADER is cleared, SW has at least 11 bit times to set RX_HEADER again, before next Break is detected (RX_BREAK_WAKEUP_DONE). in this case, there is no gap, Break will never be missed. + + +In UART mode, a single data field in received (in DATA0.DATA1). HW set this field to '0' when the data field is received, or when an error is detected. + [8:8] + read-write + + + RX_RESPONSE + SW sets this field to '1' to receive a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (NOT set to '0' when an error is detected). + +The response is received when the checksum field STOP bits are received (INTR.RX_RESPONSE_DONE). + [9:9] + read-write + + + + + TX_RX_STATUS + TX/RX status + 0x60 + 32 + read-write + 0x5000000 + 0x5000000 + + + SYNC_COUNTER + Synchronization counter in LIN channel clock periods. After the receipt of a synchronization field, this fields reflects the duration of the synchronization field. Ideally, SYNC_COUNTER = 8*16 = 128 (the synchronization fields consists of eight bit period of 16 LIN channel clock periods each). +- If SYNC_COUNTER is less than 128, the LIN channel clock is too slow and the PERI/PCLK divider value should be decreased. +- If SYNC_COUNTER is greater than 128, the LIN channel clock is too fast and the PERI/PCLK divider value should be increased. + +The biggest master-slave clock discrepancy occurs when the master is slow and the slave is fast or vice versa. At a 0.5 percent master inaccuracy and a 14 percent slave inaccuracy, this results in the extreme synchronization values of (.86 * 128) / 1.005 = 109.5 and (1.14 *128) / 0.995 = 146.6. We add a little margin for a valid range of [106, 152]. + +Note: Only slave nodes with imprecise clocks require clock resynchronization. Master and slave nodes with precise clocks do NOT require clock resynchronization. + [7:0] + read-only + + + TX_IN + LIN transmitter input ('tx_in', 'lin_tx_in' in functional mode). TX_IN and RX_IN can be used to determine a wakeup source. Note that wakeup source detection relies on the external transceiver functionality. + [16:16] + read-only + + + RX_IN + LIN receiver input ('rx_in', 'lin_rx_in' in functional mode). + [17:17] + read-only + + + TX_OUT + LIN transmitter output ('tx_out', 'lin_tx_out'). + [24:24] + read-only + + + EN_OUT + LIN transceiver enable ('en_out', 'lin_en_out'). This field controls the enable (or low active sleep enable) of the external transceiver: +'0': Disabled. +'1': Enabled. + +If CTL.AUTO_EN is '0', SW controls this field to enable the external transceiver. If CTL.AUTO_EN is '1', HW controls this field to enable the external transceiver: +- Before a legal command sequence, HW sets this field to '1', if it is '0'. The start of the command sequence is effectively postponed by a 4-bit period preamble. +- After a legal command sequence, HW clears this field to '0'. The end of the command sequence is effectively postponed by a 4-bit period postamble. + +Note: external transceivers require a 'power up' or 'power down' period of 1 or 2 bit periods, so a 4-bit period suffices for all known transceivers. + [26:26] + read-write + + + + + PID_CHECKSUM + PID and checksum + 0x80 + 32 + read-write + 0x0 + 0x0 + + + PID + Header protected identifier (PID). +- Bits 5 down to 0: frame identifier ID[5:0]. +Frame identifier 0x3c is for a 'master request' frame, 0x3d is for a 'slave response' frame, 0x3e and 0x3f are for future LIN enhancements. Frame identifier ID[5:4] is optionally used for length control; i.e. specifies the number of response data fields. +- Bits 1 down to 0: parity bits P[1] and P[0]. + - P[1] = ! (ID[5] ^ ID[4] ^ ID[3] ^ ID[1]) + - P[0] = (ID[4] ^ ID[2] ^ ID[1] ^ ID[0]) + +Transmission: To be transmitted PID field. SW needs to calculate the PID field parity bits P[1] and P[0]. + +Reception: Received PID field. Slave node SW uses the PID field to determine how to handle the response for a received frame header: TX_RESPONSE or RX_RESPONSE. + [7:0] + read-write + + + CHECKSUM + Checksum. + +Transmission: HW calculated checksum (SW does not need to calculate the checksum) over the transmitted PID field (optional per CTL.CHECKSUM_ENHANCED) and data fields. + +Reception: Received checksum. Note that in case of a RX_CHECKSUM_ERROR, SW can use the received PID field and the received data fields to calculate the correct checksum value. + [15:8] + read-only + + + + + DATA0 + Response data 0 + 0x84 + 32 + read-write + 0x0 + 0x0 + + + DATA1 + Data field 1. + +Transmission: To be transmitted data field. SW provides data field. + +Reception: Received data field. SW uses the data field. + [7:0] + read-write + + + DATA2 + Data field 2. + [15:8] + read-write + + + DATA3 + Data field 3. + [23:16] + read-write + + + DATA4 + Data field 4. + [31:24] + read-write + + + + + DATA1 + Response data 1 + 0x88 + 32 + read-write + 0x0 + 0x0 + + + DATA5 + Data field 5. + [7:0] + read-write + + + DATA6 + Data field 6. + [15:8] + read-write + + + DATA7 + Data field 7. + [23:16] + read-write + + + DATA8 + Data field 8. + [31:24] + read-write + + + + + INTR + Interrupt + 0xC0 + 32 + read-write + 0x0 + 0x1F036F07 + + + TX_HEADER_DONE + HW sets this field to '1', when a frame header (break field, synchronization field and PID field) is transmitted (the CMD.TX_HEADER is completed). Specifically: +- When followed by CMD.TX_RESPONSE or CMD.RX_RESPONSE, this field is set to '1' after completion of the frame header transfer. +- When not followed by a response command, this field is set to '1' after completion of the frame header transfer. If CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble. + +Note: used in UART mode. + [0:0] + read-write + + + TX_RESPONSE_DONE + HW sets this field to '1', when a frame response (data fields and checksum field) is transmitted (the CMD.TX_RESPONSE is completed). If CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble. + [1:1] + read-write + + + TX_WAKEUP_DONE + HW sets this field to '1', when a wakeup signal is transmitted (per CTL.BREAK_WAKEUP_LENGTH). This cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal. + [2:2] + read-write + + + RX_HEADER_DONE + HW sets this field to '1', when a frame header (break field, synchronization field and PID field) is received (the CMD.RX_HEADER is completed). Specifically: +- When followed by CMD.TX_RESPONSE or CMD.RX_RESPONSE, this field is set to '1' after completion of the frame header transfer. +- When not followed by a response command, this field is set to '1' after completion of the frame header transfer. If CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble. + +Note: used in UART mode. + [8:8] + read-write + + + RX_RESPONSE_DONE + HW sets this field to '1', when a frame response (data fields and checksum field) is received (the CMD.RX_RESPONSE is completed). If CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble. + +Note: activation implies that RX_RESPONSE_FRAME_ERROR and RX_RESPONSE_CHECKSUM_ERROR are not activated during response reception + [9:9] + read-write + + + RX_BREAK_WAKEUP_DONE + HW sets this field to '1', when a break or wakeup signal is received (per CTL.BREAK_WAKEUP_LENGTH). This cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal. + +The break or wakeup detection is always enabled, regardless of CMD register setting. + [10:10] + read-write + + + RX_HEADER_SYNC_DONE + HW sets this field to '1', when a synchronization field is received (including trailing STOP bits). + [11:11] + read-write + + + RX_NOISE_DETECT + HW sets this field to '1', when isolated '0' or '1' 'in_rx_in' values are observed or when during sampling the last three 'lin_rx_in' values do NOT all have the same value. This mismatch is an indication of noise on the LIN line. + +Note: The ongoing frame transfer is NOT aborted. + +Note: Used in UART mode. + [13:13] + read-write + + + TIMEOUT + HW sets this field to '1', when a frame, frame header or frame response timeout is detected (per CTL.FRAME_TIMEOUT_SEL). + +Note: The ongoing frame transfer is NOT aborted. + [14:14] + read-write + + + TX_HEADER_BIT_ERROR + HW sets this field to '1', when a transmitted 'lin_tx_out' value does NOT match a received 'lin_rx_in' value (during header transmission). This specific test allows for delay through the external transceiver. This mismatch is an indication of bus collisions on the LIN line. + +The match is performed for the Wakeup, Break, SYNC and the PID fields (for the START bit, data Byte and STOP bit). + +Note: When CTL.BIT_ERROR_IGNORE is '0', the ongoing message transfer is aborted (INTR.TX_HEADER_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. + +Note: Used in UART mode. + [16:16] + read-write + + + TX_RESPONSE_BIT_ERROR + HW sets this field to '1', when a transmitted 'lin_tx_out' value does NOT match a received 'lin_rx_in' value (during response transmission). + +The match is performed for the data fields and the checksum field (for the START bit, data Byte and STOP bit). + +Note: When CTL.BIT_ERROR_IGNORE is '0', the ongoing message transfer is aborted (INTR.TX_RESPONSE_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. + [17:17] + read-write + + + RX_HEADER_FRAME_ERROR + HW sets this field to '1', when the received START or STOP bits have an unexpected value (during header reception). + +Note: The ongoing message transfer is aborted (INTR.RX_HEADER_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. + +Note: Used in UART mode. + [24:24] + read-write + + + RX_HEADER_SYNC_ERROR + HW sets this field to '1', when the received synchronization field is not received within the synchronization counter range [106, 152] (see TX_RX_STATUS.SYNC_COUNTER). + +Note: The ongoing message transfer is aborted (INTR.RX_HEADER_SYNC_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. + [25:25] + read-write + + + RX_HEADER_PARITY_ERROR + HW sets this field to '1', when the received PID field has a parity error. + +Note: The ongoing message transfer is aborted (INTR.RX_PID_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. + ++G119 HW sets this field to '1', when the received data field has a parity error (when CTL0.PARITY_EN is '1'). + [26:26] + read-write + + + RX_RESPONSE_FRAME_ERROR + HW sets this field to '1', when the received START or STOP bits have an unexpected value (during response reception). HW does NOT use this field for the STOP bits of the first data field after a RX_HEADER command, if the received data byte is 0x00. (STATUS.RX_DATA0_FRAME_ERROR is used instead). + +Note: The ongoing message transfer is aborted (INTR.RX_RESPONSE_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. + [27:27] + read-write + + + RX_RESPONSE_CHECKSUM_ERROR + HW sets this field to '1', when the calculated checksum over the received PID and data fields is not the same as the received checksum. + +Note: The ongoing message transfer is aborted (INTR.RX_RESPONSE_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'. + [28:28] + read-write + + + + + INTR_SET + Interrupt set + 0xC4 + 32 + read-write + 0x0 + 0x1F036F07 + + + TX_HEADER_DONE + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [0:0] + read-write + + + TX_RESPONSE_DONE + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [1:1] + read-write + + + TX_WAKEUP_DONE + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [2:2] + read-write + + + RX_HEADER_DONE + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [8:8] + read-write + + + RX_RESPONSE_DONE + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [9:9] + read-write + + + RX_BREAK_WAKEUP_DONE + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [10:10] + read-write + + + RX_HEADER_SYNC_DONE + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [11:11] + read-write + + + RX_NOISE_DETECT + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [13:13] + read-write + + + TIMEOUT + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [14:14] + read-write + + + TX_HEADER_BIT_ERROR + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [16:16] + read-write + + + TX_RESPONSE_BIT_ERROR + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [17:17] + read-write + + + RX_HEADER_FRAME_ERROR + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [24:24] + read-write + + + RX_HEADER_SYNC_ERROR + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [25:25] + read-write + + + RX_HEADER_PARITY_ERROR + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [26:26] + read-write + + + RX_RESPONSE_FRAME_ERROR + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [27:27] + read-write + + + RX_RESPONSE_CHECKSUM_ERROR + Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). + [28:28] + read-write + + + + + INTR_MASK + Interrupt mask + 0xC8 + 32 + read-write + 0x0 + 0x1F036F07 + + + TX_HEADER_DONE + Mask for corresponding field in INTR register. + [0:0] + read-write + + + TX_RESPONSE_DONE + Mask for corresponding field in INTR register. + [1:1] + read-write + + + TX_WAKEUP_DONE + Mask for corresponding field in INTR register. + [2:2] + read-write + + + RX_HEADER_DONE + Mask for corresponding field in INTR register. + [8:8] + read-write + + + RX_RESPONSE_DONE + Mask for corresponding field in INTR register. + [9:9] + read-write + + + RX_BREAK_WAKEUP_DONE + Mask for corresponding field in INTR register. + [10:10] + read-write + + + RX_HEADER_SYNC_DONE + Mask for corresponding field in INTR register. + [11:11] + read-write + + + RX_NOISE_DETECT + Mask for corresponding field in INTR register. + [13:13] + read-write + + + TIMEOUT + Mask for corresponding field in INTR register. + [14:14] + read-write + + + TX_HEADER_BIT_ERROR + Mask for corresponding field in INTR register. + [16:16] + read-write + + + TX_RESPONSE_BIT_ERROR + Mask for corresponding field in INTR register. + [17:17] + read-write + + + RX_HEADER_FRAME_ERROR + Mask for corresponding field in INTR register. + [24:24] + read-write + + + RX_HEADER_SYNC_ERROR + Mask for corresponding field in INTR register. + [25:25] + read-write + + + RX_HEADER_PARITY_ERROR + Mask for corresponding field in INTR register. + [26:26] + read-write + + + RX_RESPONSE_FRAME_ERROR + Mask for corresponding field in INTR register. + [27:27] + read-write + + + RX_RESPONSE_CHECKSUM_ERROR + Mask for corresponding field in INTR register. + [28:28] + read-write + + + + + INTR_MASKED + Interrupt masked + 0xCC + 32 + read-only + 0x0 + 0x1F036F07 + + + TX_HEADER_DONE + Logical AND of corresponding INTR and INTR_MASK fields. + [0:0] + read-only + + + TX_RESPONSE_DONE + Logical AND of corresponding INTR and INTR_MASK fields. + [1:1] + read-only + + + TX_WAKEUP_DONE + Logical AND of corresponding INTR and INTR_MASK fields. + [2:2] + read-only + + + RX_HEADER_DONE + Logical AND of corresponding INTR and INTR_MASK fields. + [8:8] + read-only + + + RX_RESPONSE_DONE + Logical AND of corresponding INTR and INTR_MASK fields. + [9:9] + read-only + + + RX_BREAK_WAKEUP_DONE + Logical AND of corresponding INTR and INTR_MASK fields. + [10:10] + read-only + + + RX_HEADER_SYNC_DONE + Logical AND of corresponding INTR and INTR_MASK fields. + [11:11] + read-only + + + RX_NOISE_DETECT + Logical AND of corresponding INTR and INTR_MASK fields. + [13:13] + read-only + + + TIMEOUT + Logical AND of corresponding INTR and INTR_MASK fields. + [14:14] + read-only + + + TX_HEADER_BIT_ERROR + Logical AND of corresponding INTR and INTR_MASK fields. + [16:16] + read-only + + + TX_RESPONSE_BIT_ERROR + Logical AND of corresponding INTR and INTR_MASK fields. + [17:17] + read-only + + + RX_HEADER_FRAME_ERROR + Logical AND of corresponding INTR and INTR_MASK fields. + [24:24] + read-only + + + RX_HEADER_SYNC_ERROR + Logical AND of corresponding INTR and INTR_MASK fields. + [25:25] + read-only + + + RX_HEADER_PARITY_ERROR + Logical AND of corresponding INTR and INTR_MASK fields. + [26:26] + read-only + + + RX_RESPONSE_FRAME_ERROR + Logical AND of corresponding INTR and INTR_MASK fields. + [27:27] + read-only + + + RX_RESPONSE_CHECKSUM_ERROR + Logical AND of corresponding INTR and INTR_MASK fields. + [28:28] + read-only + + + + + + + + CANFD0 + CAN Controller + CANFD + 0x40520000 + + 0 + 131072 + registers + + + + 4 + 512 + CH[%s] + FIFO wrapper around M_TTCAN 3PIP, to enable DMA + 0x00000000 + + M_TTCAN + TTCAN 3PIP, includes FD + 0x00000000 + + CREL + Core Release Register + 0x0 + 32 + read-only + 0x32380609 + 0xFFFFFFFF + + + DAY + Time Stamp Day +Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. + [7:0] + read-only + + + MON + Time Stamp Month +Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. + [15:8] + read-only + + + YEAR + Time Stamp Year +One digit, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis. + [19:16] + read-only + + + SUBSTEP + Sub-step of Core Release +One digit, BCD-coded. + [23:20] + read-only + + + STEP + Step of Core Release +One digit, BCD-coded. + [27:24] + read-only + + + REL + Core Release +One digit, BCD-coded. + [31:28] + read-only + + + + + ENDN + Endian Register + 0x4 + 32 + read-only + 0x87654321 + 0xFFFFFFFF + + + ETV + Endianness Test Value +The endianness test value is 0x87654321. + [31:0] + read-only + + + + + DBTP + Data Bit Timing & Prescaler Register + 0xC + 32 + read-write + 0xA33 + 0x9F1FFF + + + DSJW + Data (Re)Synchronization Jump Width +0x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + [3:0] + read-write + + + DTSEG2 + Data time segment after sample point +0x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is +such that one more than the programmed value is used. + [7:4] + read-write + + + DTSEG1 + Data time segment before sample point +0x00-0x1F Valid values are 0 to 31. The actual interpretation by the hardware of this value is +such that one more than the programmed value is used. + [12:8] + read-write + + + DBRP + Data Bit Rate Prescaler +0x00-0x1F The value by which the oscillator frequency is divided for generating the bit time +quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit +Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + [20:16] + read-write + + + TDC + Transmitter Delay Compensation +0= Transmitter Delay Compensation disabled +1= Transmitter Delay Compensation enabled + [23:23] + read-write + + + + + TEST + Test Register + 0x10 + 32 + read-write + 0x0 + 0x7F + + + TAM + ASC is not supported by M_TTCAN +Test ASC Multiplexer Control +Controls output pin m_ttcan_ascm in test mode, ORed with the signal from the FSE +0= Level at pin m_ttcan_ascm controlled by FSE +1= Level at pin m_ttcan_ascm = '1' + [0:0] + read-write + + + TAT + ASC is not supported by M_TTCAN +Test ASC Transmit Control +Controls output pin m_ttcan_asct in test mode, ORed with the signal from the FSE +0= Level at pin m_ttcan_asct controlled by FSE +1= Level at pin m_ttcan_asct = '1' + [1:1] + read-write + + + CAM + ASC is not supported by M_TTCAN +Check ASC Multiplexer Control +Monitors level at output pin m_ttcan_ascm. +0= Output pin m_ttcan_ascm = '0' +1= Output pin m_ttcan_ascm = '1' + [2:2] + read-write + + + CAT + ASC is not supported by M_TTCAN +Check ASC Transmit Control +Monitors level at output pin m_ttcan_asct. +0= Output pin m_ttcan_asct = '0' + [3:3] + read-write + + + LBCK + Loop Back Mode +0= Reset value, Loop Back Mode is disabled +1= Loop Back Mode is enabled (see Section 3.1.9, Test Modes) + [4:4] + read-write + + + TX + Control of Transmit Pin +00 Reset value, m_ttcan_tx controlled by the CAN Core, updated at the end of the CAN bit time +01 Sample Point can be monitored at pin m_ttcan_tx +10 Dominant ('0') level at pin m_ttcan_tx +11 Recessive ('1') at pin m_ttcan_tx + [6:5] + read-write + + + RX + Receive Pin +Monitors the actual value of pin m_ttcan_rx +0= The CAN bus is dominant (m_ttcan_rx = '0') +1= The CAN bus is recessive (m_ttcan_rx = '1') + [7:7] + read-only + + + + + RWD + RAM Watchdog + 0x14 + 32 + read-write + 0x0 + 0xFFFF + + + WDC + Watchdog Configuration +Start value of the Message RAM Watchdog Counter. With the reset value of '00' the counter is +disabled. + [7:0] + read-write + + + WDV + Watchdog Value +Actual Message RAM Watchdog Counter Value. + [15:8] + read-only + + + + + CCCR + CC Control Register + 0x18 + 32 + read-write + 0x1 + 0xF3FF + + + INIT + Initialization +0= Normal Operation +1= Initialization is started + [0:0] + read-write + + + CCE + Configuration Change Enable +0= The CPU has no write access to the protected configuration registers +1= The CPU has write access to the protected configuration registers (while CCCR.INIT = '1') + [1:1] + read-write + + + ASM + Restricted Operation Mode +Bit ASM can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by +the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. +0= Normal CAN operation +1= Restricted Operation Mode active + [2:2] + read-write + + + CSA + Clock Stop Acknowledge +0= No clock stop acknowledged +1= M_TTCAN may be set in power down by stopping m_ttcan_hclk and m_ttcan_cclk + [3:3] + read-write + + + CSR + Clock Stop Request, not supported by M_TTCAN use CTL.STOP_REQ at the group level instead. +0= No clock stop is requested +1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after +all pending transfer requests have been completed and the CAN bus reached idle. + [4:4] + read-write + + + MON_ + Bus Monitoring Mode +Bit MON can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by +the Host at any time. +0= Bus Monitoring Mode is disabled +1= Bus Monitoring Mode is enabled + [5:5] + read-write + + + DAR + Disable Automatic Retransmission +0= Automatic retransmission of messages not transmitted successfully enabled +1= Automatic retransmission disabled + [6:6] + read-write + + + TEST + Test Mode Enable +0= Normal operation, register TEST holds reset values +1= Test Mode, write access to register TEST enabled + [7:7] + read-write + + + FDOE + FD Operation Enable +0= FD operation disabled +1= FD operation enabled + [8:8] + read-write + + + BRSE + Bit Rate Switch Enable +0= Bit rate switching for transmissions disabled +1= Bit rate switching for transmissions enabled + [9:9] + read-write + + + PXHD + Protocol Exception Handling Disable +0= Protocol exception handling enabled +1= Protocol exception handling disabled + [12:12] + read-write + + + EFBI + Edge Filtering during Bus Integration +0= Edge filtering disabled +1= Two consecutive dominant tq required to detect an edge for hard synchronization + [13:13] + read-write + + + TXP + Transmit Pause +If this bit is set, the M_TTCAN pauses for two CAN bit times before starting the next transmission +after itself has successfully transmitted a frame (see Section 3.5). +0= Transmit pause disabled +1= Transmit pause enabled + [14:14] + read-write + + + NISO + Non ISO Operation +If this bit is set, the M_TTCAN uses the CAN FD frame format as specified by the Bosch CAN FD +Specification V1.0. +0= CAN FD frame format according to ISO 11898-1:2015 +1= CAN FD frame format according to Bosch CAN FD Specification V1.0 addressing the non-ISO CAN FD + [15:15] + read-write + + + + + NBTP + Nominal Bit Timing & Prescaler Register + 0x1C + 32 + read-write + 0x6000A03 + 0xFFFFFF7F + + + NTSEG2 + Nominal Time segment after sample point +0x01-0x7F Valid values are 1 to 127. The actual interpretation by the hardware of this value is +such that one more than the programmed value is used. + [6:0] + read-write + + + NTSEG1 + Nominal Time segment before sample point +0x01-0xFF Valid values are 1 to 255. The actual interpretation by the hardware of this value is +such that one more than the programmed value is used. + [15:8] + read-write + + + NBRP + Nominal Bit Rate Prescaler +0x000-0x1FFThe value by which the oscillator frequency is divided for generating the bit time +quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit +Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + [24:16] + read-write + + + NSJW + Nominal (Re)Synchronization Jump Width +0x00-0x7F Valid values are 0 to 127. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + [31:25] + read-write + + + + + TSCC + Timestamp Counter Configuration + 0x20 + 32 + read-write + 0x0 + 0xF0003 + + + TSS + Timestamp Select, should always be set to external timestamp counter +00= Timestamp counter value always 0x0000 +01= Timestamp counter value incremented according to TCP +10= External timestamp counter value used +11= Same as '00' + [1:0] + read-write + + + TCP + Timestamp Counter Prescaler (still used for TOCC) +0x0-0xF Configures the timestamp and timeout counters time unit in multiples of CAN bit times +[1...16]. The actual interpretation by the hardware of this value is such that one more +than the value programmed here is used. + [19:16] + read-write + + + + + TSCV + Timestamp Counter Value + 0x24 + 32 + read-write + 0x0 + 0xFFFF + + + TSC + Timestamp Counter, not used for M_TTCAN +The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). +When TSCC.TSS = '01', the Timestamp Counter is incremented in multiples of CAN bit times +[1...16] depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. +Write access resets the counter to zero. When TSCC.TSS = '10', TSC reflects the external +Timestamp Counter value. A write access has no impact. + [15:0] + read-write + + + + + TOCC + Timeout Counter Configuration + 0x28 + 32 + read-write + 0xFFFF0000 + 0xFFFF0007 + + + ETOC + Enable Timeout Counter +0= Timeout Counter disabled +1= Timeout Counter enabled + [0:0] + read-write + + + TOS + Timeout Select +When operating in Continuous mode, a write to TOCV presets the counter to the value configured +by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the +FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting +is started when the first FIFO element is stored. +00= Continuous operation +01= Timeout controlled by Tx Event FIFO +10= Timeout controlled by Rx FIFO 0 +11= Timeout controlled by Rx FIFO 1 + [2:1] + read-write + + + TOP + Timeout Period +Start value of the Timeout Counter (down-counter). Configures the Timeout Period. + [31:16] + read-write + + + + + TOCV + Timeout Counter Value + 0x2C + 32 + read-write + 0xFFFF + 0xFFFF + + + TOC + Timeout Counter +The Timeout Counter is decremented in multiples of CAN bit times [1...16] depending on the +configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the +Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. + [15:0] + read-write + + + + + ECR + Error Counter Register + 0x40 + 32 + read-only + 0x0 + 0xFFFFFF + + + TEC + Transmit Error Counter +Actual state of the Transmit Error Counter, values between 0 and 255 + [7:0] + read-only + + + REC + Receive Error Counter +Actual state of the Receive Error Counter, values between 0 and 127 + [14:8] + read-only + + + RP + Receive Error Passive +0= The Receive Error Counter is below the error passive level of 128 +1= The Receive Error Counter has reached the error passive level of 128 + [15:15] + read-only + + + CEL + CAN Error Logging +The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter +or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops +at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. + [23:16] + read-only + + + + + PSR + Protocol Status Register + 0x44 + 32 + read-only + 0x707 + 0x7F7FFF + + + LEC + Last Error Code, +Set on Read0 +The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' +when a message has been transferred (reception or transmission) without error. + +0= No Error: No error occurred since LEC has been reset by successful reception or transmission. +1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. +2= Form Error: A fixed format part of a received frame has the wrong format. +3= AckError: The message transmitted by the M_TTCAN was not acknowledged by another node. +4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), +the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus + value was dominant. +5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or +overload flag), the device wanted to send a dominant level (data or identifier bit logical value +0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set +each time a sequence of 11 recessive bits has been monitored. This enables the CPU to +monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at +dominant or continuously disturbed). +6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming +message does not match with the CRC calculated from the received data. +7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to '7'. +When the LEC shows the value '7', no CAN bus event was detected since the last CPU read +access to the Protocol Status Register. + [2:0] + read-only + + + ACT + Activity +Monitors the module's CAN communication state. +00= Synchronizing - node is synchronizing on CAN communication +01= Idle - node is neither receiver nor transmitter +10= Receiver - node is operating as receiver +11= Transmitter - node is operating as transmitter + [4:3] + read-only + + + EP + Error Passive +0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected +1= The M_CAN is in the Error_Passive state + [5:5] + read-only + + + EW + Warning Status +0= Both error counters are below the Error_Warning limit of 96 +1= At least one of error counter has reached the Error_Warning limit of 96 + [6:6] + read-only + + + BO + Bus_Off Status +0= The M_CAN is not Bus_Off +1= The M_CAN is in Bus_Off state + [7:7] + read-only + + + DLEC + Data Phase Last Error Code +, Set on Read +Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error. + [10:8] + read-only + + + RESI + ESI flag of last received CAN FD Message +, Reset on Read +This bit is set together with RFDF, independent of acceptance filtering. +0= Last received CAN FD message did not have its ESI flag set +1= Last received CAN FD message had its ESI flag set + [11:11] + read-only + + + RBRS + BRS flag of last received CAN FD Message +, Reset on Read +This bit is set together with RFDF, independent of acceptance filtering. +0= Last received CAN FD message did not have its BRS flag set +1= Last received CAN FD message had its BRS flag set + [12:12] + read-only + + + RFDF + Received a CAN FD Message +, Reset on Read +This bit is set independent of acceptance filtering. +0= Since this bit was reset by the CPU, no CAN FD message has been received +1= Message in CAN FD format with FDF flag set has been received + [13:13] + read-only + + + PXE + Protocol Exception Event +, Reset on Read +0= No protocol exception event occurred since last read access +1= Protocol exception event occurred + [14:14] + read-only + + + TDCV + Transmitter Delay Compensation Value +0x00-0x7F Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. + [22:16] + read-only + + + + + TDCR + Transmitter Delay Compensation Register + 0x48 + 32 + read-write + 0x0 + 0x7F7F + + + TDCF + Transmitter Delay Compensation Filter Window Length +0x00-0x7F Defines the minimum value for the SSP position, dominant edges on m_ttcan_rx +that would result in an earlier SSP position are ignored for transmitter delay measurement. +The feature is enabled when TDCF is configured to a value greater than +TDCO. Valid values are 0 to 127 mtq + [6:0] + read-write + + + TDCO + Transmitter Delay Compensation Offset +0x00-0x7F Offset value defining the distance between the measured delay from m_ttcan_tx to +m_ttcan_rx and the secondary sample point. Valid values are 0 to 127 mtq. + [14:8] + read-write + + + + + IR + Interrupt Register + 0x50 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + RF0N + N/A + [0:0] + read-write + + + RF0W + N/A + [1:1] + read-write + + + RF0F + N/A + [2:2] + read-write + + + RF0L_ + N/A + [3:3] + read-write + + + RF1N + N/A + [4:4] + read-write + + + RF1W + N/A + [5:5] + read-write + + + RF1F + N/A + [6:6] + read-write + + + RF1L_ + N/A + [7:7] + read-write + + + HPM + N/A + [8:8] + read-write + + + TC + N/A + [9:9] + read-write + + + TCF + N/A + [10:10] + read-write + + + TFE + N/A + [11:11] + read-write + + + TEFN + N/A + [12:12] + read-write + + + TEFW + N/A + [13:13] + read-write + + + TEFF + N/A + [14:14] + read-write + + + TEFL_ + N/A + [15:15] + read-write + + + TSW + N/A + [16:16] + read-write + + + MRAF + N/A + [17:17] + read-write + + + TOO + N/A + [18:18] + read-write + + + DRX + N/A + [19:19] + read-write + + + BEC + Bit Error Corrected +This bit always reads as 0. + [20:20] + read-write + + + BEU + Bit Error Uncorrected +Message RAM bit error detected, uncorrected. The flag is set in the folloiwng cases. +- M_TTCAN detects uncorrectable ECC error from Message RAM when ECC is enabled and ECC error injection is disabled. +- M_TTCAN reads from an out of range Message RAM address. +Message RAM bit error sets CCCR.INIT to '1'. This is done to avoid transmission of corrupted data. +0= No bit error detected when reading from Message RAM +1= Bit error detected, uncorrected + [21:21] + read-write + + + ELO + N/A + [22:22] + read-write + + + EP_ + N/A + [23:23] + read-write + + + EW_ + N/A + [24:24] + read-write + + + BO_ + N/A + [25:25] + read-write + + + WDI + N/A + [26:26] + read-write + + + PEA + N/A + [27:27] + read-write + + + PED + N/A + [28:28] + read-write + + + ARA + N/A + [29:29] + read-write + + + + + IE + Interrupt Enable + 0x54 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + RF0NE + Rx FIFO 0 New Message Interrupt Enable + +0= Interrupt Disabled +1= Interrupt Enabled + [0:0] + read-write + + + RF0WE + Rx FIFO 0 Watermark Reached Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [1:1] + read-write + + + RF0FE + Rx FIFO 0 Full Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [2:2] + read-write + + + RF0LE + Rx FIFO 0 Message Lost Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [3:3] + read-write + + + RF1NE + Rx FIFO 1 New Message Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [4:4] + read-write + + + RF1WE + Rx FIFO 1 Watermark Reached Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [5:5] + read-write + + + RF1FE + Rx FIFO 1 Full Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [6:6] + read-write + + + RF1LE + Rx FIFO 1 Message Lost Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [7:7] + read-write + + + HPME + High Priority Message Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [8:8] + read-write + + + TCE + Transmission Completed Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [9:9] + read-write + + + TCFE + Transmission Cancellation Finished Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [10:10] + read-write + + + TFEE + Tx FIFO Empty Interrupt Enable +0= Interrupt Disabled +1= Interrupt EnabledTx FIFO Empty Interrupt Enable + [11:11] + read-write + + + TEFNE + Tx Event FIDO New Entry Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [12:12] + read-write + + + TEFWE + Tx Event FIFO Watermark Reached Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [13:13] + read-write + + + TEFFE + Tx Event FIFO Full Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [14:14] + read-write + + + TEFLE + Tx Event FIFO Event Lost Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [15:15] + read-write + + + TSWE + Timestamp Wraparound Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [16:16] + read-write + + + MRAFE + Message RAM Access Failure Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [17:17] + read-write + + + TOOE + Timeout Occurred Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [18:18] + read-write + + + DRXE + Message stored to Dedicated Rx Buffer Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [19:19] + read-write + + + BECE + Bit Error Corrected Interrupt Enable (not used in M_TTCAN) +0= Interrupt Disabled +1= Interrupt Enabled + [20:20] + read-write + + + BEUE + Bit Error Uncorrected Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [21:21] + read-write + + + ELOE + Error Logging Overflow Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [22:22] + read-write + + + EPE + Error Passive Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [23:23] + read-write + + + EWE + Warning Status Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [24:24] + read-write + + + BOE + Bus_Off Status Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [25:25] + read-write + + + WDIE + Watchdog Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [26:26] + read-write + + + PEAE + Protocol Error in Arbitration Phase Enable +0= Interrupt Disabled +1= Interrupt Enabled + [27:27] + read-write + + + PEDE + Protocol Error in Data Phase Enable +0= Interrupt Disabled +1= Interrupt Enabled + [28:28] + read-write + + + ARAE + N/A + [29:29] + read-write + + + + + ILS + Interrupt Line Select + 0x58 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + RF0NL + Rx FIFO 0 New Message Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [0:0] + read-write + + + RF0WL + Rx FIFO 0 Watermark Reached Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [1:1] + read-write + + + RF0FL + Rx FIFO 0 Full Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [2:2] + read-write + + + RF0LL + Rx FIFO 0 Message Lost Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [3:3] + read-write + + + RF1NL + Rx FIFO 1 New Message Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [4:4] + read-write + + + RF1WL + Rx FIFO 1 Watermark Reached Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [5:5] + read-write + + + RF1FL + Rx FIFO 1 Full Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [6:6] + read-write + + + RF1LL + Rx FIFO 1 Message Lost Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [7:7] + read-write + + + HPML + High Priority Message Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [8:8] + read-write + + + TCL + Transmission Completed Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [9:9] + read-write + + + TCFL + Transmission Cancellation Finished Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [10:10] + read-write + + + TFEL + Tx FIFO Empty Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [11:11] + read-write + + + TEFNL + Tx Event FIFO New Entry Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [12:12] + read-write + + + TEFWL + Tx Event FIFO Watermark Reached Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [13:13] + read-write + + + TEFFL + Tx Event FIFO Full Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [14:14] + read-write + + + TEFLL + Tx Event FIFO Event Lost Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [15:15] + read-write + + + TSWL + Timestamp Wraparound Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [16:16] + read-write + + + MRAFL + Message RAM Access Failure Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [17:17] + read-write + + + TOOL + Timeout Occurred Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [18:18] + read-write + + + DRXL + Message stored to Dedicated Rx Buffer Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [19:19] + read-write + + + BECL + Bit Error Corrected Interrupt Select (not used in M_TTCAN) +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [20:20] + read-write + + + BEUL + Bit Error Uncorrected Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [21:21] + read-write + + + ELOL + Error Logging Overflow Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [22:22] + read-write + + + EPL + Error Passive Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [23:23] + read-write + + + EWL + Warning Status Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [24:24] + read-write + + + BOL + Bus_Off Status Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [25:25] + read-write + + + WDIL + Watchdog Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [26:26] + read-write + + + PEAL + Protocol Error in Arbitration Phase Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [27:27] + read-write + + + PEDL + Protocol Error in Data Phase Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [28:28] + read-write + + + ARAL + N/A + [29:29] + read-write + + + + + ILE + Interrupt Line Enable + 0x5C + 32 + read-write + 0x0 + 0x3 + + + EINT0 + Enable Interrupt Line 0 +0= Interrupt line m_ttcan_int0 disabled +1= Interrupt line m_ttcan_int0 enabled + [0:0] + read-write + + + EINT1 + Enable Interrupt Line 1 +0= Interrupt line m_ttcan_int1 disabled +1= Interrupt line m_ttcan_int1 enabled + [1:1] + read-write + + + + + GFC + Global Filter Configuration + 0x80 + 32 + read-write + 0x0 + 0x3F + + + RRFE + Reject Remote Frames Extended +0= Filter remote frames with 29-bit extended IDs +1= Reject all remote frames with 29-bit extended IDs + [0:0] + read-write + + + RRFS + Reject Remote Frames Standard +0= Filter remote frames with 11-bit standard IDs +1= Reject all remote frames with 11-bit standard IDs + [1:1] + read-write + + + ANFE + Accept Non-matching Frames Extended +Defines how received messages with 29-bit IDs that do not match any element of the filter list are +treated. +00= Accept in Rx FIFO 0 +01= Accept in Rx FIFO 1 +10= Reject +11= Reject + [3:2] + read-write + + + ANFS + Accept Non-matching Frames Standard +Defines how received messages with 11-bit IDs that do not match any element of the filter list are +treated. +00= Accept in Rx FIFO 0 +01= Accept in Rx FIFO 1 +10= Reject +11= Reject + [5:4] + read-write + + + + + SIDFC + Standard ID Filter Configuration + 0x84 + 32 + read-write + 0x0 + 0xFFFFFC + + + FLSSA + Filter List Standard Start Address +Start address of standard Message ID filter list (32-bit word address, see Figure 2). + [15:2] + read-write + + + LSS + List Size Standard +0= No standard Message ID filter +1-128= Number of standard Message ID filter elements +128= Values greater than 128 are interpreted as 128 + [23:16] + read-write + + + + + XIDFC + Extended ID Filter Configuration + 0x88 + 32 + read-write + 0x0 + 0x7FFFFC + + + FLESA + Filter List Extended Start Address +Start address of extended Message ID filter list (32-bit word address, see Figure 2). + [15:2] + read-write + + + LSE + List Size Extended +0= No extended Message ID filter +1-64= Number of extended Message ID filter elements +64= Values greater than 64 are interpreted as 64 + [22:16] + read-write + + + + + XIDAM + Extended ID AND Mask + 0x90 + 32 + read-write + 0x1FFFFFFF + 0x1FFFFFFF + + + EIDM + Extended ID Mask +For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message +ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all +bits set to one the mask is not active. + [28:0] + read-write + + + + + HPMS + High Priority Message Status + 0x94 + 32 + read-only + 0x0 + 0xFFFF + + + BIDX + Buffer Index +Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = '1'. + [5:0] + read-only + + + MSI + Message Storage Indicator +00= No FIFO selected +01= FIFO message lost +10= Message stored in FIFO 0 +11= Message stored in FIFO 1 + [7:6] + read-only + + + FIDX + Filter Index +Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. + [14:8] + read-only + + + FLST + Filter List +Indicates the filter list of the matching filter element. +0= Standard Filter List +1= Extended Filter List + [15:15] + read-only + + + + + NDAT1 + New Data 1 + 0x98 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ND + New Data +The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective +Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. +A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard +reset will clear the register. +0= Rx Buffer not updated +1= Rx Buffer updated from new message + [31:0] + read-write + + + + + NDAT2 + New Data 2 + 0x9C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ND + New Data +The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective +Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. +A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard +reset will clear the register. +0= Rx Buffer not updated +1= Rx Buffer updated from new message + [31:0] + read-write + + + + + RXF0C + Rx FIFO 0 Configuration + 0xA0 + 32 + read-write + 0x0 + 0xFF7FFFFC + + + F0SA + Rx FIFO 0 Start Address +Start address of Rx FIFO 0 in Message RAM (32-bit word address, see Figure 2). + [15:2] + read-write + + + F0S + Rx FIFO 0 Size +0= No Rx FIFO 0 +1-64= Number of Rx FIFO 0 elements +64= Values greater than 64 are interpreted as 64 +The Rx FIFO 0 elements are indexed from 0 to F0S-1 + [22:16] + read-write + + + F0WM + Rx FIFO 0 Watermark +0= Watermark interrupt disabled +1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) +64= Watermark interrupt disabled + [30:24] + read-write + + + F0OM + FIFO 0 Operation Mode +FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). +0= FIFO 0 blocking mode +1= FIFO 0 overwrite mode + [31:31] + read-write + + + + + RXF0S + Rx FIFO 0 Status + 0xA4 + 32 + read-only + 0x0 + 0x33F3F7F + + + F0FL + Rx FIFO 0 Fill Level +Number of elements stored in Rx FIFO 0, range 0 to 64. +When the software reading the value immediately after writing to RXF0A.F0AI, this value should be read twice to ensure that the update is reflected. + [6:0] + read-only + + + F0GI + Rx FIFO 0 Get Index +Rx FIFO 0 read index pointer, range 0 to 63. +This field is updated by the software writing to RXF0A.F0AI. +When the software reading the value immediately after writing to RXF0A.F0AI, this value should be read twice to ensure that the update is reflected. + [13:8] + read-only + + + F0PI + Rx FIFO 0 Put Index +Rx FIFO 0 write index pointer, range 0 to 63. + [21:16] + read-only + + + F0F + Rx FIFO 0 Full +0= Rx FIFO 0 not full +1= Rx FIFO 0 full + [24:24] + read-only + + + RF0L + Rx FIFO 0 Message Lost +This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. +0= No Rx FIFO 0 message lost +1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero + [25:25] + read-only + + + + + RXF0A + Rx FIFO 0 Acknowledge + 0xA8 + 32 + read-write + 0x0 + 0x3F + + + F0AI + Rx FIFO 0 Acknowledge Index +After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the + buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index + RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. + [5:0] + read-write + + + + + RXBC + Rx Buffer Configuration + 0xAC + 32 + read-write + 0x0 + 0xFFFC + + + RBSA + Rx Buffer Start Address +Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address). +Also used to reference debug messages A,B,C. + [15:2] + read-write + + + + + RXF1C + Rx FIFO 1 Configuration + 0xB0 + 32 + read-write + 0x0 + 0xFF7FFFFC + + + F1SA + Rx FIFO 1 Start Address +Start address of Rx FIFO 1 in Message RAM (32-bit word address, see Figure 2). + [15:2] + read-write + + + F1S + Rx FIFO 1 Size +0= No Rx FIFO 1 +1-64= Number of Rx FIFO 1 elements +64= Values greater than 64 are interpreted as 64 +The Rx FIFO 1 elements are indexed from 0 to F1S - 1 + [22:16] + read-write + + + F1WM + Rx FIFO 1 Watermark +0= Watermark interrupt disabled +1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) +64= Watermark interrupt disabled + [30:24] + read-write + + + F1OM + FIFO 1 Operation Mode +FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). +0= FIFO 1 blocking mode +1= FIFO 1 overwrite mode + [31:31] + read-write + + + + + RXF1S + Rx FIFO 1 Status + 0xB4 + 32 + read-only + 0x0 + 0xC33F3F7F + + + F1FL + Rx FIFO 1 Fill Level +Number of elements stored in Rx FIFO 1, range 0 to 64. +When the software reading the value immediately after writing to RXF1A.F1AI, this value should be read twice to ensure that the update is reflected. + [6:0] + read-only + + + F1GI + Rx FIFO 1 Get Index +Rx FIFO 1 read index pointer, range 0 to 63. +This field is updated by the software writing to RXF1A.F1AI. +When the software reading the value immediately after writing to RXF1A.F1AI, this value should be read twice to ensure that the update is reflected. + [13:8] + read-only + + + F1PI + Rx FIFO 1 Put Index +Rx FIFO 1 write index pointer, range 0 to 63. + [21:16] + read-only + + + F1F + Rx FIFO 1 Full +0= Rx FIFO 1 not full +1= Rx FIFO 1 full + [24:24] + read-only + + + RF1L + Rx FIFO 1 Message Lost +This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. +0= No Rx FIFO 1 message lost +1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + [25:25] + read-only + + + DMS + Debug Message Status +00= Idle state, wait for reception of debug messages, DMA request is cleared +01= Debug message A received +10= Debug messages A, B received +11= Debug messages A, B, C received, DMA request is set + [31:30] + read-only + + + + + RXF1A + Rx FIFO 1 Acknowledge + 0xB8 + 32 + read-write + 0x0 + 0x3F + + + F1AI + Rx FIFO 1 Acknowledge Index +After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the + buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index + RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. + [5:0] + read-write + + + + + RXESC + Rx Buffer / FIFO Element Size Configuration + 0xBC + 32 + read-write + 0x0 + 0x777 + + + F0DS + Rx FIFO 0 Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + [2:0] + read-write + + + F1DS + Rx FIFO 1 Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + [6:4] + read-write + + + RBDS + Rx Buffer Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + [10:8] + read-write + + + + + TXBC + Tx Buffer Configuration + 0xC0 + 32 + read-write + 0x0 + 0x7F3FFFFC + + + TBSA + Tx Buffers Start Address +Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). + [15:2] + read-write + + + NDTB + Number of Dedicated Transmit Buffers +0= No Dedicated Tx Buffers +1-32= Number of Dedicated Tx Buffers +32= Values greater than 32 are interpreted as 32 + [21:16] + read-write + + + TFQS + Transmit FIFO/Queue Size +0= No Tx FIFO/Queue +1-32= Number of Tx Buffers used for Tx FIFO/Queue +32= Values greater than 32 are interpreted as 32 + [29:24] + read-write + + + TFQM + Tx FIFO/Queue Mode +0= Tx FIFO operation +1= Tx Queue operation + [30:30] + read-write + + + + + TXFQS + Tx FIFO/Queue Status + 0xC4 + 32 + read-only + 0x0 + 0x3F1F3F + + + TFFL + Tx FIFO Free Level +Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when +Tx Queue operation is configured (TXBC.TFQM = '1') + [5:0] + read-only + + + TFGI + Tx FIFO Get Index +Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured +TXBC.TFQM = '1'). + [12:8] + read-only + + + TFQPI + Tx FIFO/Queue Put Index +Tx FIFO/Queue write index pointer, range 0 to 31. + [20:16] + read-only + + + TFQF + Tx FIFO/Queue Full +0= Tx FIFO/Queue not full +1= Tx FIFO/Queue full + [21:21] + read-only + + + + + TXESC + Tx Buffer Element Size Configuration + 0xC8 + 32 + read-write + 0x0 + 0x7 + + + TBDS + Tx Buffer Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + [2:0] + read-write + + + + + TXBRP + Tx Buffer Request Pending + 0xCC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + TRP + Transmission Request Pending +Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR. +The bits are reset after a requested transmission has completed or has been cancelled via register +TXBCR. +TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, +a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the +highest priority (Tx Buffer with lowest Message ID). +A cancellation request resets the corresponding transmission request pending bit of register +TXBRP. In case a transmission has already been started when a cancellation is requested, this is +done at the end of the transmission, regardless whether the transmission was successful or not. The +cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. +After a cancellation has been requested, a finished cancellation is signaled via TXBCF +after successful transmission together with the corresponding TXBTO bit +when the transmission has not yet been started at the point of cancellation +when the transmission has been aborted due to lost arbitration +when an error occurred during frame transmission +In DAR mode all transmissions are automatically cancelled if they are not successful. The +corresponding TXBCF bit is set for all unsuccessful transmissions. +0= No transmission request pending +1= Transmission request pending + [31:0] + read-only + + + + + TXBAR + Tx Buffer Add Request + 0xD0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + AR + Add Request +Each Tx Buffer has its own Add Request bit. Writing a '1' will set the corresponding Add Request +bit; writing a '0' has no impact. This enables the Host to set transmission requests for multiple Tx +Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. +When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan +process has completed. +0= No transmission request added +1= Transmission requested added + [31:0] + read-write + + + + + TXBCR + Tx Buffer Cancellation Request + 0xD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CR + Cancellation Request +Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding +Cancellation Request bit; writing a '0' has no impact. This enables the Host to set cancellation +requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx +Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. +0= No cancellation pending +1= Cancellation pending + [31:0] + read-write + + + + + TXBTO + Tx Buffer Transmission Occurred + 0xD8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + TO + Transmission Occurred +Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding +TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission +is requested by writing a '1' to the corresponding bit of register TXBAR. +0= No transmission occurred +1= Transmission occurred + [31:0] + read-only + + + + + TXBCF + Tx Buffer Cancellation Finished + 0xDC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CF + Cancellation Finished +Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding +TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding +TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a +new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. +0= No transmit buffer cancellation +1= Transmit buffer cancellation finished + [31:0] + read-only + + + + + TXBTIE + Tx Buffer Transmission Interrupt Enable + 0xE0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TIE + Transmission Interrupt Enable +Each Tx Buffer has its own Transmission Interrupt Enable bit. +0= Transmission interrupt disabled +1= Transmission interrupt enable + [31:0] + read-write + + + + + TXBCIE + Tx Buffer Cancellation Finished Interrupt Enable + 0xE4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CFIE + Cancellation Finished Interrupt Enable +Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. +0= Cancellation finished interrupt disabled +1= Cancellation finished interrupt enabled + [31:0] + read-write + + + + + TXEFC + Tx Event FIFO Configuration + 0xF0 + 32 + read-write + 0x0 + 0x3F3FFFFC + + + EFSA + Event FIFO Start Address +Start address of Tx Event FIFO in Message RAM (32-bit word address, see Figure 2). + [15:2] + read-write + + + EFS + Event FIFO Size +0= Tx Event FIFO disabled +1-32= Number of Tx Event FIFO elements +32= Values greater than 32 are interpreted as 32 +The Tx Event FIFO elements are indexed from 0 to EFS-1 + [21:16] + read-write + + + EFWM + Event FIFO Watermark +0= Watermark interrupt disabled +1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) +32= Watermark interrupt disabled + [29:24] + read-write + + + + + TXEFS + Tx Event FIFO Status + 0xF4 + 32 + read-only + 0x0 + 0x31F1F3F + + + EFFL + Event FIFO Fill Level +Number of elements stored in Tx Event FIFO, range 0 to 32. +When the software reading the value immediately after writing to TXEFA.EFAI, this value should be read twice to ensure that the update is reflected. + [5:0] + read-only + + + EFGI + Event FIFO Get Index +Tx Event FIFO read index pointer, range 0 to 31. +This field is updated by the software writing to TXEFA.EFAI. +When the software reading the value immediately after writing to TXEFA.EFAI, this value should be read twice to ensure that the update is reflected. + [12:8] + read-only + + + EFPI + Event FIFO Put Index +Tx Event FIFO write index pointer, range 0 to 31. + [20:16] + read-only + + + EFF + Event FIFO Full +0= Tx Event FIFO not full +1= Tx Event FIFO full + [24:24] + read-only + + + TEFL + Tx Event FIFO Element Lost +This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. +0= No Tx Event FIFO element lost +1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. + [25:25] + read-only + + + + + TXEFA + Tx Event FIFO Acknowledge + 0xF8 + 32 + read-write + 0x0 + 0x1F + + + EFAI + Event FIFO Acknowledge Index +After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write +the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get +Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. + [4:0] + read-write + + + + + TTTMC + TT Trigger Memory Configuration + 0x100 + 32 + read-write + 0x0 + 0x7FFFFC + + + TMSA + Trigger Memory Start Address +Start address of Trigger Memory in Message RAM (32-bit word address, see Figure 2). + [15:2] + read-write + + + TME + Trigger Memory Elements +0= No Trigger Memory +1-64= Number of Trigger Memory elements +64= Values greater than 64 are interpreted as 64 + [22:16] + read-write + + + + + TTRMC + TT Reference Message Configuration + 0x104 + 32 + read-write + 0x0 + 0xDFFFFFFF + + + RID + Reference Identifier +Identifier transmitted with reference message and used for reference message filtering. Standard or +extended reference identifier depending on bit XTD. A standard identifier has to be written to +ID[28:18]. + [28:0] + read-write + + + XTD + Extended Identifier +0= 11-bit standard identifier +1= 29-bit extended identifier + [30:30] + read-write + + + RMPS + Reference Message Payload Select +Ignored in case of time slaves. +0= Reference message has no additional payload +1= The following elements are taken from Tx Buffer 0: +Message Marker MM, Event FIFO Control EFC, Data Length Code DLC, Data Bytes DB +Level 1: bytes 2-8, Level 0,2: bytes 5-8) + [31:31] + read-write + + + + + TTOCF + TT Operation Configuration + 0x108 + 32 + read-write + 0x10000 + 0x7FFFFFB + + + OM + Operation Mode +00= Event-driven CAN communication, default +01= TTCAN level 1 +10= TTCAN level 2 +11= TTCAN level 0 + [1:0] + read-write + + + GEN + Gap Enable +0= Strictly time-triggered operation +1= External event-synchronized time-triggered operation + [3:3] + read-write + + + TM + Time Master +0= Time Master function disabled +1= Potential Time Master + [4:4] + read-write + + + LDSDL + LD of Synchronization Deviation Limit +The Synchronization Deviation Limit SDL is configured by its dual logarithm LDSDL with SDL = +2(LDSDL + 5). It should not exceed the clock tolerance given by the CAN bit timing configuration. +0x0-7 LD of Synchronization Deviation Limit (SDL <= 32...4096) + [7:5] + read-write + + + IRTO + Initial Reference Trigger Offset +0x00-7F Positive offset, range from 0 to 127 + [14:8] + read-write + + + EECS + Enable External Clock Synchronization +If enabled, TUR configuration (TURCF.NCL only) may be updated during TTCAN operation. +0= External clock synchronization in TTCAN Level 0,2 disabled +1= External clock synchronization in TTCAN Level 0,2 enabled + [15:15] + read-write + + + AWL + Application Watchdog Limit +The application watchdog can be disabled by programming AWL to 0x00. +0x00-FF Maximum time after which the application has to serve the application watchdog. +The application watchdog is incremented once each 256 NTUs. + [23:16] + read-write + + + EGTF + Enable Global Time Filtering +0= Global time filtering in TTCAN Level 0,2 is disabled +1= Global time filtering in TTCAN Level 0,2 is enabled + [24:24] + read-write + + + ECC + Enable Clock Calibration +0= Automatic clock calibration in TTCAN Level 0,2 is disabled +1= Automatic clock calibration in TTCAN Level 0,2 is enabled + [25:25] + read-write + + + EVTP + Event Trigger Polarity +0= Rising edge trigger +1= Falling edge trigger + [26:26] + read-write + + + + + TTMLM + TT Matrix Limits + 0x10C + 32 + read-write + 0x0 + 0xFFF0FFF + + + CCM + N/A + [5:0] + read-write + + + CSS + N/A + [7:6] + read-write + + + TXEW + Tx Enable Window +0x0-F Length of Tx enable window, 1-16 NTU cycles + [11:8] + read-write + + + ENTT + Expected Number of Tx Triggers +0x000-FFF Expected number of Tx Triggers in one Matrix Cycle + [27:16] + read-write + + + + + TURCF + TUR Configuration + 0x110 + 32 + read-write + 0x10000000 + 0xBFFFFFFF + + + NCL + Numerator Configuration Low +Write access to the TUR Numerator Configuration Low is only possible during configuration with +TURCF.ELT = '0' or if TTOCF.EECS (external clock synchronization enabled) is set. When a new +value for NCL is written outside TT Configuration Mode, the new value takes effect when +TTOST.WECS is cleared to '0'. NCL is locked TTOST.WECS is '1'. +0x0000-FFFF Numerator Configuration Low + [15:0] + read-write + + + DC + Denominator Configuration +0x0000 Illegal value +0x0001-3FFF Denominator Configuration + [29:16] + read-write + + + ELT + Enable Local Time +0= Local time is stopped, default +1= Local time is enabled + [31:31] + read-write + + + + + TTOCN + TT Operation Control + 0x114 + 32 + read-write + 0x0 + 0xBFFF + + + SGT + Set Global time +Writing a '1' to SGT sets TTOST.WGDT if the node is the actual Time Master. SGT is reset after one +Host clock period. The global time preset takes effect when the node transmits the next reference +message with the Master_Ref_Mark modified by the preset value written to TTGTP. + [0:0] + read-write + + + ECS + External Clock Synchronization +Writing a '1' to ECS sets TTOST.WECS if the node is the actual Time Master. ECS is reset after one +Host clock period. The external clock synchronization takes effect at the start of the next basic cycle. + [1:1] + read-write + + + SWP + Stop Watch Polarity +0= Rising edge trigger +1= Falling edge trigger + [2:2] + read-write + + + SWS + Stop Watch Source +00= Stop Watch disabled +01= Actual value of cycle time is copied to TTCPT.SWV +10= Actual value of local time is copied to TTCPT.SWV +11= Actual value of global time is copied to TTCPT.SWV + [4:3] + read-write + + + RTIE + Register Time Mark Interrupt Pulse Enable +Register time mark interrupts are configured by register TTTMK. A register time mark interrupt pulse +with the length of one NTU is generated when the time referenced by TTOCN.TMC (cycle, local, or +global) equals TTTMK.TM, independent of the synchronization state. +0= Register Time Mark Interrupt output m_ttcan_rtp disabled +1= Register Time Mark Interrupt output m_ttcan_rtp enabled + [5:5] + read-write + + + TMC + Register Time Mark Compare +00= No Register Time Mark Interrupt generated +01= Register Time Mark Interrupt if Time Mark = cycle time +10= Register Time Mark Interrupt if Time Mark = local time +11= Register Time Mark Interrupt if Time Mark = global time + [7:6] + read-write + + + TTIE + Trigger Time Mark Interrupt Pulse Enable +External time mark events are configured by trigger memory element TMEX (see Section 2.4.7). A +trigger time mark interrupt pulse is generated when the trigger memory element becomes active, +and the M_TTCAN is in synchronization state In_Schedule or In_Gap. +0= Trigger Time Mark Interrupt output m_ttcan_tmp disabled +1= Trigger Time Mark Interrupt output m_ttcan_tmp enabled + [8:8] + read-write + + + GCS + Gap Control Select +0= Gap control independent from m_ttcan_evt +1= Gap control by input pin m_ttcan_evt + [9:9] + read-write + + + FGP + Finish Gap +Set by the CPU, reset by each reference message +0= No reference message requested +1= Application requested start of reference message + [10:10] + read-write + + + TMG + Time Mark Gap +0= Reset by each reference message +1= Next reference message started when Register Time Mark interrupt TTIR.RTMI is activated + [11:11] + read-write + + + NIG + Next is Gap +This bit can only be set when the M_TTCAN is the actual Time Master and when it is configured for +external event-synchronized time-triggered operation (TTOCF.GEN = '1') +0= No action, reset by reception of any reference message +1= Transmit next reference message with Next_is_Gap = '1' + [12:12] + read-write + + + ESCN + External Synchronization Control +If enabled the M_TTCAN synchronizes its cycle time phase to an external event signaled by a rising +edge at pin m_ttcan_evt (see Section 4.11). +0= External synchronization disabled +1= External synchronization enabled + [13:13] + read-write + + + LCKC + TT Operation Control Register Locked +Set by a write access to register TTOCN. Reset when the updated configuration has been +synchronized into the CAN clock domain. +0= Write access to TTOCN enabled +1= Write access to TTOCN locked + [15:15] + read-only + + + + + TTGTP + TT Global Time Preset + 0x118 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + TP + N/A + [15:0] + read-write + + + CTP + Cycle Time Target Phase +CTP is write-protected while TTOCN.ESCN or TTOST.SPL are set (see Section 4.11). +0x0000-FFFF Defines target value of cycle time when a rising edge of m_ttcan_evt is expected + [31:16] + read-write + + + + + TTTMK + TT Time Mark + 0x11C + 32 + read-write + 0x0 + 0x807FFFFF + + + TM_ + Time Mark +0x0000-FFFF Time Mark + [15:0] + read-write + + + TICC + Time Mark Cycle Code +Cycle count for which the time mark is valid. +0b000000x valid for all cycles +0b000001c valid every second cycle at cycle count mod2 = c +0b00001cc valid every fourth cycle at cycle count mod4 = cc +0b0001ccc valid every eighth cycle at cycle count mod8 = ccc +0b001cccc valid every sixteenth cycle at cycle count mod16 = cccc +0b01ccccc valid every thirty-second cycle at cycle count mod32 = ccccc +0b1cccccc valid every sixty-fourth cycle at cycle count mod64 = cccccc + [22:16] + read-write + + + LCKM + TT Time Mark Register Locked +Always set by a write access to registers TTOCN. Set by write access to register TTTMK when +TTOCN.TMC != '00'. Reset when the registers have been synchronized into the CAN clock domain. +0= Write access to TTTMK enabled +1= Write access to TTTMK locked + [31:31] + read-only + + + + + TTIR + TT Interrupt Register + 0x120 + 32 + read-write + 0x0 + 0x7FFFF + + + SBC + Start of Basic Cycle +0= No Basic Cycle started since bit has been reset +1= Basic Cycle started + [0:0] + read-write + + + SMC + Start of Matrix Cycle +0= No Matrix Cycle started since bit has been reset +1= Matrix Cycle started + [1:1] + read-write + + + CSM_ + Change of Synchronization Mode +0= No change in master to slave relation or schedule synchronization +1= Master to slave relation or schedule synchronization changed, +also set when TTOST.SPL is reset + [2:2] + read-write + + + SOG + Start of Gap +0= No reference message seen with Next_is_Gap bit set +1= Reference message with Next_is_Gap bit set becomes valid + [3:3] + read-write + + + RTMI + Register Time Mark Interrupt +Set when time referenced by TTOCN.TMC (cycle, local, or global) equals TTTMK.TM, independent +of the synchronization state. +0= Time mark not reached +1= Time mark reached + [4:4] + read-write + + + TTMI + Trigger Time Mark Event Internal +Internal time mark events are configured by trigger memory element TMIN (see Section 2.4.7). Set +when the trigger memory element becomes active, and the M_TTCAN is in synchronization state +In_Gap or In_Schedule. +0= Time mark not reached +1= Time mark reached (Level 0: cycle time TTOCF.IRTO * 0x200) + [5:5] + read-write + + + SWE + Stop Watch Event +0= No rising/falling edge at stop watch trigger pin m_ttcan_swt detected +1= Rising/falling edge at stop watch trigger pin m_ttcan_swt detected + [6:6] + read-write + + + GTW + Global Time Wrap +0= No global time wrap occurred +1= Global time wrap from 0xFFFF to 0x0000 occurred + [7:7] + read-write + + + GTD + Global Time Discontinuity +0= No discontinuity of global time +1= Discontinuity of global time + [8:8] + read-write + + + GTE + Global Time Error +Synchronization deviation SD exceeds limit specified by TTOCF.LDSDL, TTCAN Level 0,2 only. +0= Synchronization deviation within limit +1= Synchronization deviation exceeded limit + [9:9] + read-write + + + TXU + Tx Count Underflow +0= Number of Tx Trigger as expected +1= Less Tx trigger than expected in one matrix cycle + [10:10] + read-write + + + TXO + Tx Count Overflow +0= Number of Tx Trigger as expected +1= More Tx trigger than expected in one matrix cycle + [11:11] + read-write + + + SE1 + Scheduling Error 1 +0= No scheduling error 1 +1= Scheduling error 1 occurred + [12:12] + read-write + + + SE2 + Scheduling Error 2 +0= No scheduling error 2 +1= Scheduling error 2 occurred + [13:13] + read-write + + + ELC + Error Level Changed +Not set when error level changed during initialization. +0= No change in error level +1= Error level changed + [14:14] + read-write + + + IWT + Initialization Watch Trigger +The initialization is restarted by resetting IWT. +0= No missing reference message during system startup +1= No system startup due to missing reference message + [15:15] + read-write + + + WT + Watch Trigger +0= No missing reference message +1= Missing reference message (Level 0: cycle time 0xFF00) + [16:16] + read-write + + + AW + Application Watchdog +0= Application watchdog served in time +1= Application watchdog not served in time + [17:17] + read-write + + + CER + Configuration Error +Trigger out of order. +0= No error found in trigger list +1= Error found in trigger list + [18:18] + read-write + + + + + TTIE + TT Interrupt Enable + 0x124 + 32 + read-write + 0x0 + 0x7FFFF + + + SBCE + Start of Basic Cycle Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [0:0] + read-write + + + SMCE + Start of Matrix Cycle Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [1:1] + read-write + + + CSME + Change of Synchronization Mode Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [2:2] + read-write + + + SOGE + Start of Gap Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [3:3] + read-write + + + RTMIE + Register Time Mark Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [4:4] + read-write + + + TTMIE + Trigger Time Mark Event Internal Enable +0= Interrupt Disabled +1= Interrupt Enabled + [5:5] + read-write + + + SWEE + Stop Watch Event Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [6:6] + read-write + + + GTWE + Global Time Wrap Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [7:7] + read-write + + + GTDE + Global Time Discontinuity Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [8:8] + read-write + + + GTEE + Global Time Error Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [9:9] + read-write + + + TXUE + Tx Count Underflow Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [10:10] + read-write + + + TXOE + Tx Count Overflow Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [11:11] + read-write + + + SE1E + Scheduling Error 1 Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [12:12] + read-write + + + SE2E + Scheduling Error 2 Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [13:13] + read-write + + + ELCE + Change Error Level Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [14:14] + read-write + + + IWTE + Initialization Watch Trigger Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [15:15] + read-write + + + WTE + Watch Trigger Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [16:16] + read-write + + + AWE_ + Application Watchdog Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [17:17] + read-write + + + CERE + Configuration Error Interrupt Enable +0= Interrupt Disabled +1= Interrupt Enabled + [18:18] + read-write + + + + + TTILS + TT Interrupt Line Select + 0x128 + 32 + read-write + 0x0 + 0x7FFFF + + + SBCL + Start of Basic Cycle Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [0:0] + read-write + + + SMCL + Start of Matrix Cycle Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [1:1] + read-write + + + CSML + Change of Synchronization Mode Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [2:2] + read-write + + + SOGL + Start of Gap Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [3:3] + read-write + + + RTMIL + Register Time Mark Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [4:4] + read-write + + + TTMIL + Trigger Time Mark Event Internal Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [5:5] + read-write + + + SWEL + Stop Watch Event Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [6:6] + read-write + + + GTWL + Global Time Wrap Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [7:7] + read-write + + + GTDL + Global Time Discontinuity Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [8:8] + read-write + + + GTEL + Global Time Error Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [9:9] + read-write + + + TXUL + Tx Count Underflow Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [10:10] + read-write + + + TXOL + Tx Count Overflow Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [11:11] + read-write + + + SE1L + Scheduling Error 1 Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [12:12] + read-write + + + SE2L + Scheduling Error 2 Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [13:13] + read-write + + + ELCL + Change Error Level Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [14:14] + read-write + + + IWTL + Initialization Watch Trigger Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [15:15] + read-write + + + WTL + Watch Trigger Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [16:16] + read-write + + + AWL_ + Application Watchdog Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [17:17] + read-write + + + CERL + Configuration Error Interrupt Select +0= Assign to interrupt enabled by ILE.EINT0 +1= Assign to interrupt enabled by ILE.EINT1 + [18:18] + read-write + + + + + TTOST + TT Operation Status + 0x12C + 32 + read-only + 0x80 + 0xFFC0FFFF + + + EL + Error Level +00= Severity 0 - No Error +01= Severity 1 - Warning +10= Severity 2 - Error +11= Severity 3 - Severe Error + [1:0] + read-only + + + MS + Master State +00= Master_Off, no master properties relevant +01= Operating as Time Slave +10= Operating as Backup Time Master +11= Operating as current Time Master + [3:2] + read-only + + + SYS + Synchronization State +00= Out of Synchronization +01= Synchronizing to TTCAN communication +10= Schedule suspended by Gap (In_Gap) +11= Synchronized to schedule (In_Schedule) + [5:4] + read-only + + + QGTP + Quality of Global Time Phase +Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '0'. +0= Global time not valid +1= Global time in phase with Time Master + [6:6] + read-only + + + QCS + Quality of Clock Speed +Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '1'. +0= Local clock speed not synchronized to Time Master clock speed +1= Synchronization Deviation <= SDL + [7:7] + read-only + + + RTO + Reference Trigger Offset +The Reference Trigger Offset value is a signed integer with a range from -127 (0x81) to 127 (0x7F). +There is no notification when the lower limit of -127 is reached. In case the M_TTCAN becomes +Time Master (MS[1:0] = '11'), the reset of RTO is delayed due to synchronization between Host and +CAN clock domain. For time slaves the value configured by TTOCF.IRTO is read. +0x00-FF Actual Reference Trigger offset value + [15:8] + read-only + + + WGTD + Wait for Global Time Discontinuity +0= No global time preset pending +1= Node waits for the global time preset to take effect. The bit is reset when the node has transmitted +a reference message with Disc_Bit = '1' or after it received a reference message. + [22:22] + read-only + + + GFI + Gap Finished Indicator +Set when the CPU writes TTOCN.FGP, or by a time mark interrupt if TMG = '1', or via input pin +m_ttcan_evt if TTOCN.GCS = '1'. Not set by Ref_Trigger_Gap or when Gap is finished by another +node sending a reference message. +0= Reset at the end of each reference message +1= Gap finished by M_TTCAN + [23:23] + read-only + + + TMP + Time Master Priority +0x0-7 Priority of actual Time Master + [26:24] + read-only + + + GSI + Gap Started Indicator +0= No Gap in schedule, reset by each reference message and for all time slaves +1= Gap time after Basic Cycle has started + [27:27] + read-only + + + WFE + Wait for Event +0= No Gap announced, reset by a reference message with Next_is_Gap = '0' +1= Reference message with Next_is_Gap = '1' received + [28:28] + read-only + + + AWE + Application Watchdog Event +The application watchdog is served by reading TTOST. When the watchdog is not served in time, +bit AWE is set, all TTCAN communication is stopped, and the M_TTCAN is set into Bus Monitoring +Mode. +0= Application Watchdog served in time +1= Failed to serve Application Watchdog in time + [29:29] + read-only + + + WECS + Wait for External Clock Synchronization +0= No external clock synchronization pending +1= Node waits for external clock synchronization to take effect. The bit is reset at the start of the +next basic cycle. + [30:30] + read-only + + + SPL + Schedule Phase Lock +The bit is valid only when external synchronization is enabled (TTOCN.ESCN = '1'). In this case it +signals that the difference between cycle time configured by TTGTP.CTP and the cycle time at the +rising edge at pin m_ttcan_evt is less or equal 9 NTU (see Section 4.11). +0= Phase outside range +1= Phase inside range + [31:31] + read-only + + + + + TURNA + TUR Numerator Actual + 0x130 + 32 + read-only + 0x10000 + 0x3FFFF + + + NAV + N/A + [17:0] + read-only + + + + + TTLGT + TT Local & Global Time + 0x134 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + LT + Local Time +Non-fractional part of local time, incremented once each local NTU (see Section 4.5). +0x0000-FFFF Local time value of TTCAN node + [15:0] + read-only + + + GT + Global Time +Non-fractional part of the sum of the node's local time and its local offset (see Section 4.5). +0x0000-FFFF Global time value of TTCAN network + [31:16] + read-only + + + + + TTCTC + TT Cycle Time & Count + 0x138 + 32 + read-only + 0x3F0000 + 0x3FFFFF + + + CT + Cycle Time +Non-fractional part of the difference of the node's local time and Ref_Mark (see Section 4.5). +0x0000-FFFF Cycle time value of TTCAN Basic Cycle + [15:0] + read-only + + + CC + Cycle Count +0x00-3F Number of actual Basic Cycle in the System Matrix + [21:16] + read-only + + + + + TTCPT + TT Capture Time + 0x13C + 32 + read-only + 0x0 + 0xFFFF003F + + + CCV + Cycle Count Value +Cycle count value captured together with SWV. +0x00-3F Captured cycle count value + [5:0] + read-only + + + SWV + Stop Watch Value +On a rising/falling edge (as configured via TTOCN.SWP) at the Stop Watch Trigger pin m_ttcan_swt, when TTOCN.SWS is != '00' and TTIR.SWE is '0', the actual time value as selected +by TTOCN.SWS (cycle, local, global) is copied to SWV and TTIR.SWE will be set to '1'. Capturing of the next stop watch value is enabled by resetting TTIR.SWE. +0x0000-FFFF Captured Stop Watch value + [31:16] + read-only + + + + + TTCSM + TT Cycle Sync Mark + 0x140 + 32 + read-only + 0x0 + 0xFFFF + + + CSM + Cycle Sync Mark +The Cycle Sync Mark is measured + [15:0] + read-only + + + + + + RXFTOP_CTL + Receive FIFO Top control + 0x180 + 32 + read-write + 0x0 + 0x3 + + + F0TPE + FIFO 0 Top Pointer Enable. +This enables the FIFO top pointer logic to set the FIFO Top Address (FnTA) and message word counter. +This logic is also disabled when the IP is being reconfigured (CCCR.CCE=1). +When this logic is disabled a Read from RXFTOP0_DATA is undefined. + [0:0] + read-write + + + F1TPE + FIFO 1 Top Pointer Enable. + [1:1] + read-write + + + + + RXFTOP0_STAT + Receive FIFO 0 Top Status + 0x1A0 + 32 + read-only + 0x0 + 0xFFFF + + + F0TA + Current FIFO 0 Top Address. +This is a pointer to the next word in the message buffer defined by the FIFO Start Address (FnSA), Get Index (FnGI), the FIFO message size (FnDS) and the message word counter (FnMWC) +FnTA = FnSA + FnGI * msg_size[FnDS] + FnMWC + [15:0] + read-only + + + + + RXFTOP0_DATA + Receive FIFO 0 Top Data + 0x1A8 + 32 + read-only + 0x0 + 0x0 + + + F0TD + When enabled (F0TPE=1) read data from MRAM at location FnTA. This register can have a read side effect if the following conditions are met: +- M_TTCAN not being reconfigured (CCCR.CCE=0) +- FIFO Top Pointer logic is enabled (FnTPE=1) +- FIFO is not empty (FnFL!=0) +The read side effect is as follows: +- if FnMWC pointed to the last word of the message (as indicated by FnDS) then the corresponding message index (FnGI) is automatically acknowledge by a write to FnAI +- FnMWC is incremented (or restarted if FnMWC pointed to the last word of the message) +- the FIFO top address FnTA is incremented (with FIFO wrap around) +When this logic is disabled (F0TPE=0) a Read from this register returns undefined data. + [31:0] + read-only + + + + + RXFTOP1_STAT + Receive FIFO 1 Top Status + 0x1B0 + 32 + read-only + 0x0 + 0xFFFF + + + F1TA + See F0TA description + [15:0] + read-only + + + + + RXFTOP1_DATA + Receive FIFO 1 Top Data + 0x1B8 + 32 + read-only + 0x0 + 0x0 + + + F1TD + See F0TD description + [31:0] + read-only + + + + + + CTL + Global CAN control register + 0x1000 + 32 + read-write + 0x0 + 0x800000FF + + + STOP_REQ + N/A + [7:0] + read-write + + + MRAM_OFF + MRAM off +0= Default MRAM on (with MRAM retained in DeepSleep). +1= Switch MRAM off (not retained) to save power. Before setting this bit all the CAN channels have to be powered down using the STOP_REQ/ACK bits. +When the MRAM is off any access attempt to it is considered an address error (as if MRAM_SIZE=0). +After switching the MRAM on again software needs to allow for a certain power up time before MRAM can be used, i.e. before STOP_REQ can be de-asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register. + +MRAM_OFF should be set to 0 prior to transitioning to Hibernate mode. + [31:31] + read-write + + + + + STATUS + Global CAN status register + 0x1004 + 32 + read-only + 0x0 + 0xFF + + + STOP_ACK + Clock Stop Acknowledge for each TTCAN IP. +These bits are directly driven by m_ttcan_clkstop_ack of each TTCAN IP. +When this bit is set the corresponding TTCAN IP clocks will be gated off, except HCLK will enabled for each AHB write + [7:0] + read-only + + + + + INTR0_CAUSE + Consolidated interrupt0 cause register + 0x1010 + 32 + read-only + 0x0 + 0xFF + + + INT0 + Show pending m_ttcan_int0 of each channel + [7:0] + read-only + + + + + INTR1_CAUSE + Consolidated interrupt1 cause register + 0x1014 + 32 + read-only + 0x0 + 0xFF + + + INT1 + Show pending m_ttcan_int1 of each channel + [7:0] + read-only + + + + + TS_CTL + Time Stamp control register + 0x1020 + 32 + read-write + 0x0 + 0x8000FFFF + + + PRESCALE + Time Stamp counter prescale value. +When enabled divide the Host clock (HCLK) by PRESCALE+1 to create Time Stamp clock ticks. + [15:0] + read-write + + + ENABLED + Counter enable bit +0 = Count disabled. Stop counting up and keep the counter value +1 = Count enabled. Start counting up from the current value + [31:31] + read-write + + + + + TS_CNT + Time Stamp counter value + 0x1024 + 32 + read-write + 0x0 + 0xFFFF + + + VALUE + The counter value of the Time Stamp Counter. +When enabled this counter will count Time Stamp clock ticks from the pre-scaler. +When written this counter and the pre-scaler will reset to 0 (write data is ignored). + [15:0] + read-write + + + + + ECC_CTL + ECC control + 0x1080 + 32 + read-write + 0x0 + 0x10000 + + + ECC_EN + Enable ECC for CANFD SRAM +When disabled also all error injection functionality is disabled. + [16:16] + read-write + + + + + ECC_ERR_INJ + ECC error injection + 0x1084 + 32 + read-write + 0xFFFC + 0x7F10FFFC + + + ERR_ADDR + Specifies the address of the word where an error will be injected on write or an non-correctable error will be suppressed. +When the ERR_EN bit is set an error parity (ERR_PAR) is injected when any write, from bus or a CAN channel, is done to this address. +When the ERR_EN bit is set and the access address matches ERR_ADDR then a non-correctable ECC error or an Address error will NOT result in a bus error or CAN channel shutdown. +Note that error reporting to the fault structure cannot be suppressed. + [15:2] + read-write + + + ERR_EN + Enable error injection (ECC_EN must be 1). +When this bit is set the error parity (ERR_PAR) will be used when an AHB write is done to the ERR_ADDR address. +When the error word is read a single or double error will be reported to the fault structure just like for a real ECC error (even if this bit is no longer set). +When this bit is set (and ECC_EN=1) a non-correctable error (ECC or address error) for the ERR_ADDR will not be reported back to the CAN channel or AHB bus. + [20:20] + read-write + + + ERR_PAR + ECC Parity bits to use for ECC error injection at address ERR_ADDR. + [30:24] + read-write + + + + + + + CANFD1 + 0x40540000 + + + TCPWM0 + Timer/Counter/PWM + TCPWM + 0x40580000 + + 0 + 131072 + registers + + + + 3 + 32768 + GRP[%s] + Group of counters + 0x00000000 + + 63 + 128 + CNT[%s] + Timer/Counter/PWM Counter Module + 0x00000000 + + CTRL + Counter control register + 0x0 + 32 + read-write + 0xF0 + 0xC73737FF + + + AUTO_RELOAD_CC0 + Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER, QUAD (QUAD_RANGE0_CMP, QUAD_RANGE1_CMP range modes), SR, PWM, PWM_DT and PWM_PR modes. +Timer, QUAD, SR modes: +'0': never switch. +'1': switch on a compare match 0 event. +PWM, PWM_DT, PWM_PR modes: +'0: never switch. +'1': switch on a terminal count event with an actively pending switch event. + [0:0] + read-write + + + AUTO_RELOAD_CC1 + Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER, QUAD (QUAD_RANGE0_CMP, QUAD_RANGE1_CMP range modes), SR, PWM, PWM_DT and PWM_PR modes. +Timer, QUAD, SR modes: +'0': never switch. +'1': switch on a compare match 1 event. +PWM, PWM_DT, PWM_PR modes: +'0: never switch. +'1': switch on a terminal count event with an actively pending switch event. + [1:1] + read-write + + + AUTO_RELOAD_PERIOD + Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes. +'0': never switch. +'1': switch on a terminal count event with and actively pending switch event. + +In QUAD mode, QUAD_RANGE0_CMP range mode this field is used to select the index / wrap-around capture function. +'0': Captures on index (reload) event. The counter value is copied to the PERIOD register on an index (reload) event. +'1': Captures when COUNTER equals 0 or 0xffff. The counter value is copied to the PERIOD register when COUNTER equals 0 or 0xffff. + [2:2] + read-write + + + AUTO_RELOAD_LINE_SEL + Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes. +'0': never switch. +'1': switch on a terminal count event with and actively pending switch event. + [3:3] + read-write + + + CC0_MATCH_UP_EN + Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode. +'0': compare match 0 event generation disabled when counting up +'1': compare match 0 event generation enabled when counting up + +This field has a function in PWM and PWM_DT modes only. + [4:4] + read-write + + + CC0_MATCH_DOWN_EN + Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode. +'0': compare match 0 event generation disabled when counting down +'1': compare match 0 event generation enabled when counting down + +This field has a function in PWM and PWM_DT modes only. + [5:5] + read-write + + + CC1_MATCH_UP_EN + Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode. +'0': compare match 1 event generation disabled when counting up +'1': compare match 1 event generation enabled when counting up + +This field has a function in PWM and PWM_DT modes only. + [6:6] + read-write + + + CC1_MATCH_DOWN_EN + Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode. +'0': compare match 1 event generation disabled when counting down +'1': compare match 1 event generation enabled when counting down + +This field has a function in PWM and PWM_DT modes only. + [7:7] + read-write + + + PWM_IMM_KILL + Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter'). +'0': synchronous kill activation. Deactivates the 'dt_line_out' and 'dt_line_compl_out' signals with the next module clock ('active count' pre-scaled 'clk_counter'). +'1': immediate kill activation. Immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals. + +This field has a function in PWM, PWM_DT and PWM_PR modes only. + [8:8] + read-write + + + PWM_STOP_ON_KILL + Specifies whether the counter stops on a kill events: +'0': kill event does NOT stop counter. +'1': kill event stops counter. + +This field has a function in PWM, PWM_DT and PWM_PR modes only. + [9:9] + read-write + + + PWM_SYNC_KILL + Specifies asynchronous/synchronous kill behavior: +'1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. +'0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. + +This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'. + [10:10] + read-write + + + PWM_DISABLE_MODE + Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped. + +Note: The output signal of this selection can be further modified by the immediate kill logic and line_out polarity settings (CTRL.QUAD_ENCODING_MODE). + [13:12] + read-write + + + Z + The behavior is the same is in previous mxtcpwm (version 1). + 0 + + + RETAIN + When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM. +When the counter is disabled or stopped upon a stop event the PWM outputs are retained (keep their previous levels). +While the counter is disabled or stopped the PWM outputs can be changed via LINE_SEL (when parameter GRP_SMC_PRESENT = 1). + 1 + + + L + When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM. +When the counter is disabled or stopped upon a stop event the PWM output 'line_out' is driven as a fixed '0' and the PWM output 'line_compl_out' is driven as a fixed '1'. + 2 + + + H + When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM. +When the counter is disabled or stopped upon a stop event the PWM output 'line_out' is driven as a fixed '1' and the PWM output 'line_compl_out' is driven as a fixed '0'. + 3 + + + + + UP_DOWN_MODE + Determines counter direction. + +In QUAD mode this field acts as QUAD_RANGE_MODE field selecting between different counter range, reload value and compare / capture behavior. + [17:16] + read-write + + + COUNT_UP + Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD. + 0 + + + COUNT_DOWN + Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. + 1 + + + COUNT_UPDN1 + Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'. + 2 + + + COUNT_UPDN2 + Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates). + 3 + + + + + ONE_SHOT + When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated. + [18:18] + read-write + + + QUAD_ENCODING_MODE + In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode. +In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUAD_ENCODING_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUAD_ENCODING_MODE[1]. + [21:20] + read-write + + + X1 + X1 encoding (QUAD mode) +This encoding is identical with an up / down counting functionality of the following way: Rising edges of input phiA increment or decrement the counter depending on the state of input phiB (direction input). + 0 + + + X2 + X2 encoding (QUAD mode) + 1 + + + X4 + X4 encoding (QUAD mode) + 2 + + + UP_DOWN + Up / Down rotary counting mode. Input phiA increments the counter, input phiB decrements the counter. The trigger edge detection settings apply. + 3 + + + + + MODE + Counter mode. + [26:24] + read-write + + + TIMER + Timer mode + 0 + + + RSVD1 + N/A + 1 + + + CAPTURE + Capture mode + 2 + + + QUAD + Quadrature mode + 3 + + + PWM + Pulse width modulation (PWM) mode + 4 + + + PWM_DT + PWM with deadtime insertion mode + 5 + + + PWM_PR + Pseudo random pulse width modulation + 6 + + + SR + Shift register mode. + 7 + + + + + DBG_FREEZE_EN + Specifies the counter behavior in debug mode. +'0': The counter operation continues in debug mode. +'1': The counter operation freezes in debug mode. + [30:30] + read-write + + + ENABLED + Counter enable. +'0': counter disabled. +'1': counter enabled. +Counter static configuration information (e.g. CTRL.MODE, all TR_IN_SEL, TR_IN_EDGE_SEL, TR_PWM_CTRL and TR_OUT_SEL register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes: +- the associated counter triggers in the CMD register are set to '0'. +- the counter's interrupt cause fields in counter's INTR register. +- the counter's status fields in counter's STATUS register.. +- the counter's trigger outputs ('tr_out0' and tr_out1'). +- the counter's line outputs ('line_out' and 'line_compl_out'). + [31:31] + read-write + + + + + STATUS + Counter status register + 0x4 + 32 + read-only + 0x20 + 0xFFFF8FF1 + + + DOWN + When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented. + [0:0] + read-only + + + TR_CAPTURE0 + Indicates the actual level of the selected capture 0 trigger. + [4:4] + read-only + + + TR_COUNT + Indicates the actual level of the selected count trigger. + [5:5] + read-only + + + TR_RELOAD + Indicates the actual level of the selected reload trigger. + [6:6] + read-only + + + TR_STOP + Indicates the actual level of the selected stop trigger. + [7:7] + read-only + + + TR_START + Indicates the actual level of the selected start trigger. + [8:8] + read-only + + + TR_CAPTURE1 + Indicates the actual level of the selected capture 1 trigger. + [9:9] + read-only + + + LINE_OUT + Indicates the actual level of the PWM line output signal. + [10:10] + read-only + + + LINE_COMPL_OUT + Indicates the actual level of the complementary PWM line output signal. + [11:11] + read-only + + + RUNNING + When '0', the counter is NOT running. When '1', the counter is running. + +This field is used to indicate that the counter is running after a start/reload event and that the counter is stopped after a stop event. +When a running counter operation is paused in debug state (see CTRL.DBG_PAUSE) then the RUNNING bit is still '1'. + [15:15] + read-only + + + DT_CNT_L + Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter). +In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality. + [23:16] + read-only + + + DT_CNT_H + High byte of 16-bit dead time counter. In PWM_DT mode, this counter is used for dead time insertion. +In all other modes, this field has no effect. + +Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8bit wide and the only the field DT_CNT_L is used as dead time counter. + [31:24] + read-only + + + + + COUNTER + Counter count register + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + COUNTER + 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running. + [31:0] + read-write + + + + + CC0 + Counter compare/capture 0 register + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CC + In CAPTURE mode, captures the counter value. In other modes, compared to counter value. + [31:0] + read-write + + + + + CC0_BUFF + Counter buffered compare/capture 0 register + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CC + Additional buffer for counter CC register. + [31:0] + read-write + + + + + CC1 + Counter compare/capture 1 register + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CC + In CAPTURE mode, captures the counter value. In other modes, compared to counter value. + [31:0] + read-write + + + + + CC1_BUFF + Counter buffered compare/capture 1 register + 0x1C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CC + Additional buffer for counter CC1 register. + [31:0] + read-write + + + + + PERIOD + Counter period register + 0x20 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PERIOD + Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1. + [31:0] + read-write + + + + + PERIOD_BUFF + Counter buffered period register + 0x24 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + PERIOD + Additional buffer for counter PERIOD register. + +In PWM_PR mode PEROD_BUFF defines the LFSR polynomial. Each bit represents a tap of the shift register which can be feed back to the MSB via an XOR tree. +Examples for GRP_CNT_WIDTH = 16: +- Maximum length 16bit LFSR + - polynomial x^16 + x^14 + x^13 + x^11 + 1 + - taps 0,2,3,5 -> PERIOD = 0x002d + - period is 2^16-1 = 65535 cycles +- Maximum length 8bit LFSR: + - polynomial x^8 + x^6 + x^5 + x^4 + 1 + - taps 8,10,11,12 (realized in 8 MSBs of 16bit LFSR) + - period is 2^8-1 = 255 cycles + +In SR mode PERIOD_BUFF defines which tap of the shift register generates the PWM output signals. For a delay of n cycles (from capture event to PWM output) the bit CNT_WIDTH-n should be set to '1'. For a shift register function only one tap should be use, i.e. a one-hot value must be written to PERIOD_BUFF. If multiple bits in PERIOD_BUFF are set then the taps are XOR combined. + [31:0] + read-write + + + + + LINE_SEL + Counter line selection register + 0x28 + 32 + read-write + 0x32 + 0x77 + + + OUT_SEL + Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control. +This field has a function in PWM and PWM_PR modes only. + +Note: The output signal of this selection can be further modified by the stop / kill logic and line_out polarity setting (CTRL.QUAD_ENCODING_MODE[0]). + [2:0] + read-write + + + L + fixed '0' + 0 + + + H + fixed '1' + 1 + + + PWM + PWM signal 'line' + 2 + + + PWM_INV + inverted PWM signal 'line' + 3 + + + Z + The output 'line_out' is not driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance). + +Note: This is realized by driving the output 'line_out_en' to 0. + 4 + + + RSVD5 + N/A + 5 + + + RSVD6 + N/A + 6 + + + RSVD7 + N/A + 7 + + + + + COMPL_OUT_SEL + Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control. +This field has a function in PWM and PWM_PR modes only. + +Note: The output signal of this selection can be further modified by the stop / kill logic and line_compl_out polarity setting (CTRL.QUAD_ENCODING_MODE[1]). + [6:4] + read-write + + + L + fixed '0' + 0 + + + H + fixed '1' + 1 + + + PWM + PWM signal 'line' + 2 + + + PWM_INV + inverted PWM signal 'line' + 3 + + + Z + The output 'line_compl_out' is not driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance). + +Note: This is realized by driving the output 'line_compl_out_en' to 0. + 4 + + + RSVD5 + N/A + 5 + + + RSVD6 + N/A + 6 + + + RSVD7 + N/A + 7 + + + + + + + LINE_SEL_BUFF + Counter buffered line selection register + 0x2C + 32 + read-write + 0x32 + 0x77 + + + OUT_SEL + Buffer for LINE_SEL.OUT_SEL. +Can be exchanged with LINE_SEL.LINE_OUT_SEL on a terminal count event with an actively pending switch event. + +This field has a function in PWM and PWM_PR modes only. + [2:0] + read-write + + + COMPL_OUT_SEL + Buffer for LINE_SEL.COMPL.OUT_SEL. +Can be exchanged with LINE_SEL.LINE_COMPL_OUT_SEL on a terminal count event with an actively pending switch event. + +This field has a function in PWM and PWM_PR modes only. + [6:4] + read-write + + + + + DT + Counter PWM dead time register + 0x30 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DT_LINE_OUT_L + In PWM_DT mode, this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain. +In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock. + +Note: This field determines the low byte of the 16-bit dead time before activating 'line_out' when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by this DT_LINE_OUT_L field is used before activating 'line_out' and 'line_compl_out'. + [7:0] + read-write + + + DT_LINE_OUT_H + In PWM_DT mode, this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain. +In all other modes, this field has no effect. + +Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by field DT_LINE_OUT_L is used before activating 'line_out' and 'line_compl_out'. + [15:8] + read-write + + + DT_LINE_COMPL_OUT + In PWM_DT mode, this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain. +In all other modes, this field has no effect. + +Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by field DT_LINE_OUT_L is used before activating 'line_out' and 'line_compl_out'. + [31:16] + read-write + + + + + TR_CMD + Counter trigger command register + 0x40 + 32 + read-write + 0x0 + 0x3D + + + CAPTURE0 + SW capture 0 trigger. When written with '1', a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.ENABLED, the field is immediately set to '0'. + [0:0] + read-write + + + RELOAD + SW reload trigger. For HW behavior, see COUNTER_CAPTURE0 field. + [2:2] + read-write + + + STOP + SW stop trigger. For HW behavior, see COUNTER_CAPTURE0 field. + [3:3] + read-write + + + START + SW start trigger. For HW behavior, see COUNTER_CAPTURE0 field. + [4:4] + read-write + + + CAPTURE1 + SW capture 1 trigger. For HW behavior, see COUNTER_CAPTURE0 field. + [5:5] + read-write + + + + + TR_IN_SEL0 + Counter input trigger selection register 0 + 0x44 + 32 + read-write + 0x100 + 0xFFFFFFFF + + + CAPTURE0_SEL + Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing, the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by setting 2 and above. The settings above are used for the general purpose trigger inputs 'tr_all_cnt_in' connected to all counters selected. +In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts. + [7:0] + read-write + + + COUNT_SEL + Selects one of the 256 input triggers as a count trigger. +In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'. + +Note: In the modes: TIMER, CAPTURE, PWM, PWM_DT, and SR, If the counter is externally triggered ( COUNT_SEL > 1), an external trigger will be required for each TR_CMD to execute. For example, a write to TR_CMD.START will not start the counter until the trigger selected by COUNT_SEL asserts. The next trigger will increment the counter since the counter is now running. This goes for all TR_CMD fields. + [15:8] + read-write + + + RELOAD_SEL + Selects one of the 256 input triggers as a reload trigger. +In QUAD mode, this is the index or revolution pulse. In these modes, it will update the counter with 0x8000 (counter midpoint) or 0x0000 depending on the QUAD_RANGE_MODE. + [23:16] + read-write + + + STOP_SEL + Selects one of the 256 input triggers as a stop trigger. +In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event. + [31:24] + read-write + + + + + TR_IN_SEL1 + Counter input trigger selection register 1 + 0x48 + 32 + read-write + 0x0 + 0xFFFF + + + START_SEL + Selects one of the 256 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B). + [7:0] + read-write + + + CAPTURE1_SEL + Selects one of the 256 input triggers as a capture 1 trigger. + [15:8] + read-write + + + + + TR_IN_EDGE_SEL + Counter input trigger edge selection register + 0x4C + 32 + read-write + 0xFFF + 0xFFF + + + CAPTURE0_EDGE + A capture 0 event will copy the counter value into the CC0 register. + [1:0] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + ANY_EDGE + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + COUNT_EDGE + A counter event will increase or decrease the counter by '1'. + [3:2] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + ANY_EDGE + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + RELOAD_EDGE + A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD. + [5:4] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + ANY_EDGE + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + STOP_EDGE + A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter. + [7:6] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + ANY_EDGE + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + START_EDGE + A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does. + [9:8] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + ANY_EDGE + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + CAPTURE1_EDGE + A capture 1 event will copy the counter value into the CC1 register. + [11:10] + read-write + + + RISING_EDGE + Rising edge. Any rising edge generates an event. + 0 + + + FALLING_EDGE + Falling edge. Any falling edge generates an event. + 1 + + + ANY_EDGE + Rising AND falling edge. Any odd amount of edges generates an event. + 2 + + + NO_EDGE_DET + No edge detection, use trigger as is. + 3 + + + + + + + TR_PWM_CTRL + Counter trigger PWM control register + 0x50 + 32 + read-write + 0xFF + 0xFF + + + CC0_MATCH_MODE + Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. +To generate a duty cycle of 0 percent, the counter CC0 register should be set to '0'. For a 100 percent duty cycle, the counter CC0 register should be set to larger than the counter PERIOD register. + [1:0] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + OVERFLOW_MODE + Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals. + [3:2] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + UNDERFLOW_MODE + Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals. + [5:4] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + CC1_MATCH_MODE + Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals. + [7:6] + read-write + + + SET + Set to '1' + 0 + + + CLEAR + Set to '0' + 1 + + + INVERT + Invert + 2 + + + NO_CHANGE + No Change + 3 + + + + + + + TR_OUT_SEL + Counter output trigger selection register + 0x54 + 32 + read-write + 0x32 + 0x77 + + + OUT0 + Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event. + [2:0] + read-write + + + OVERFLOW + Overflow event + 0 + + + UNDERFLOW + Underflow event + 1 + + + TC + Terminal count event (default selection) + 2 + + + CC0_MATCH + Compare match 0 event + 3 + + + CC1_MATCH + Compare match 1 event + 4 + + + LINE_OUT + PWM output signal 'line_out' + 5 + + + RSVD6 + N/A + 6 + + + Disabled + Output trigger disabled. + 7 + + + + + OUT1 + Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event. + [6:4] + read-write + + + OVERFLOW + Overflow event + 0 + + + UNDERFLOW + Underflow event + 1 + + + TC + Terminal count event + 2 + + + CC0_MATCH + Compare match 0 event (default selection) + 3 + + + CC1_MATCH + Compare match 1 event + 4 + + + LINE_OUT + PWM output signal 'line_out' + 5 + + + RSVD6 + N/A + 6 + + + Disabled + Output trigger disabled. + 7 + + + + + + + INTR + Interrupt request register + 0x70 + 32 + read-write + 0x0 + 0x7 + + + TC + Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit. + [0:0] + read-write + + + CC0_MATCH + Counter matches CC0 register event. Set to '1', when event is detected. Write with '1' to clear bit. + [1:1] + read-write + + + CC1_MATCH + Counter matches CC1 register event. Set to '1', when event is detected. Write with '1' to clear bit. + [2:2] + read-write + + + + + INTR_SET + Interrupt set request register + 0x74 + 32 + read-write + 0x0 + 0x7 + + + TC + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + CC0_MATCH + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + CC1_MATCH + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + + + INTR_MASK + Interrupt mask register + 0x78 + 32 + read-write + 0x0 + 0x7 + + + TC + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + CC0_MATCH + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + CC1_MATCH + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + + + INTR_MASKED + Interrupt masked request register + 0x7C + 32 + read-only + 0x0 + 0x7 + + + TC + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + CC0_MATCH + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + CC1_MATCH + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + + + + + + + SCB0 + Serial Communications Block (SPI/UART/I2C) + SCB + 0x40600000 + + 0 + 65536 + registers + + + + CTRL + Generic control + 0x0 + 32 + read-write + 0x300400F + 0x9303D70F + + + OVS + N/A + [3:0] + read-write + + + EC_AM_MODE + This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI) +'0': Internally clocked mode +'1': Externally clocked mode + +In internally clocked mode, the serial interface protocols run off the SCB clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. + +The clocking for the rest of the logic is determined by CTRL.EC_OP_MODE. + +Externally clocked mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. + +In UART mode this field should be '0'. + [8:8] + read-write + + + EC_OP_MODE + This field specifies the clocking for the SCB block +'0': Internally clocked mode +'1': externally clocked mode + In internally clocked mode, the serial interface protocols run off the SCB clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. + +Externally clocked operation mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode AND EZ mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The maximum SPI slave, EZ mode bitrate is 48 Mbps (transmission and IO delays outside the IP will degrade the effective bitrate). + +In UART mode this field should be '0'. + [9:9] + read-write + + + EZ_MODE + Non EZ mode ('0') or EZ mode ('1'). +In EZ mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory address, a write memory data element or a read memory data element. EZ mode is only used for synchronous serial interface protocols: SPI and I2C. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported and the transmitter should use continuous data frames; i.e. data frames not separated by slave deselection. This mode is only applicable to slave functionality. In EZ mode, the slave can read from and write to an addressable memory structure of 32 bytes. In EZ mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first. + +In UART mode this field should be '0'. + [10:10] + read-write + + + CMD_RESP_MODE + N/A + [12:12] + read-write + + + MEM_WIDTH + N/A + [15:14] + read-write + + + BYTE + 8-bit FIFO data elements. +This mode provides the biggest amount of FIFO entries, but TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 7]. + 0 + + + HALFWORD + 16-bit FIFO data elements. +TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 15]. + 1 + + + WORD + 32-bit FIFO data elements. +This mode provides the smallest amount of FIFO entries, but TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH can be in a range of [0, 31]. + 2 + + + RSVD + N/A + 3 + + + + + ADDR_ACCEPT + Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0'). + +In I2C mode, this field is used to allow the slave to put the received slave address or general call address in the RX FIFO. Note that a received matching address is put in the RX FIFO when this bit is '1' for both I2C read and write transfers. + +In multi-processor UART receiver mode, this field is used to allow the receiver to put the received address in the RX FIFO. Note: non-matching addresses are never put in the RX FIFO. + [16:16] + read-write + + + BLOCK + Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide, this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0'). IF BLOCK is '0' and the accesses collide, CPU read operations return 0xffff:ffff and CPU write operations are ignored. Colliding accesses are registered as interrupt causes: INTR_TX.BLOCKED and INTR_RX.BLOCKED. + [17:17] + read-write + + + MODE + N/A + [25:24] + read-write + + + I2C + Inter-Integrated Circuits (I2C) mode. + 0 + + + SPI + Serial Peripheral Interface (SPI) mode. + 1 + + + UART + Universal Asynchronous Receiver/Transmitter (UART) mode. + 2 + + + + + EC_ACCESS + EC_ACCESS is used to enable I2CS_EC or SPIS_EC access to internal EZ memory. +1: enable clk_scb +0: disable clk_scb + +Before going to deepsleep this field should be set to 1. +when waking up from DeepSleep power mode, and PLL is locked (clk_scb is at expected frequency), this filed should be set to 0. + [28:28] + read-write + + + ENABLED + SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows: +- Program protocol specific information using SPI_CTRL, UART_CTRL (and UART_TX_CTRL and UART_RX_CTRL) or I2C_CTRL registers. This includes selection of a submode, master/slave functionality and transmitter/receiver functionality when applicable. +- Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality. +- Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information. +- Program CTRL register to enable SCB, select the specific operation mode and oversampling factor. +Generally when this block is enabled, no control information should be changed. Changes should be made AFTER disabling this block, e.g. to modify the operation mode (from I2C to SPI) or to go from externally to internally clocked. The change takes effect after the block is re-enabled. Note that disabling the block will cause re-initialization of the design and associated state is lost (e.g. FIFO content). + +Specific to SPI master case, when SCB is idle, below registers can be changed without disabling SCB block, + TX_CTRL + TX_FIFO_CTRL + RX_CTRL + RX_FIFO_CTRL + SPI_CTRL.SSEL, + [31:31] + read-write + + + + + STATUS + Generic status + 0x4 + 32 + read-only + 0x0 + 0x0 + + + EC_BUSY + Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a blocked SW access) or bus errors being generated). Note that the INTR_TX.BLOCKED and INTR_RX.BLOCKED interrupt causes are used to indicate whether a SW access was actually blocked by externally clocked logic. + [0:0] + read-only + + + + + CMD_RESP_CTRL + Command/response control + 0x8 + 32 + read-write + 0x0 + 0x1FF01FF + + + BASE_RD_ADDR + I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers. + [8:0] + read-write + + + BASE_WR_ADDR + I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers. + [24:16] + read-write + + + + + CMD_RESP_STATUS + Command/response status + 0xC + 32 + read-only + 0x0 + 0x0 + + + CURR_RD_ADDR + I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address). + +The field is used to determine how many bytes have been read (# bytes = CURR_RD_ADDR - CMD_RESP_CTRL.BASE_RD_ADDR). + +This field is reliable when there is no bus transfer. This field is potentially unreliable when there is a ongoing bus transfer, i.e. when CMD_RESP_EC_BUSY is '0', the field is reliable. + [8:0] + read-only + + + CURR_WR_ADDR + I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address). + +The field is used to determine how many bytes have been written (# bytes = CURR_WR_ADDR - CMD_RESP_CTRL.BASE_WR_ADDR). + +This field is reliable when there is no bus transfer. This field is potentially unreliable when there is a ongoing bus transfer, i.e. when CMD_RESP_EC_BUSY is '0', the field is reliable. + [24:16] + read-only + + + CMD_RESP_EC_BUS_BUSY + Indicates whether there is an ongoing bus transfer to the IP. +'0': no ongoing bus transfer. +'1': ongoing bus transfer. + +For SPI, the field is '1' when slave mode is selected. + +For I2C, the field is set to '1' at a I2C START/RESTART. In case of an address match, the field is set to '0' on a I2C STOP. In case of NO address match, the field is set to '0' after the failing address match. + [30:30] + read-only + + + CMD_RESP_EC_BUSY + N/A + [31:31] + read-only + + + + + SPI_CTRL + SPI control + 0x20 + 32 + read-write + 0x3000010 + 0x8F017F3F + + + SSEL_CONTINUOUS + Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode, both continuous and non-continuous SPI data transfers are supported independent of this field. + +When continuous transfers are enabled individual data frame transfers are not necessarily separated by slave deselection (as indicated by the level or pulse on the SELECT line): if the TX FIFO has multiple data frames, data frames are send out without slave deselection. + +When continuous transfers are not enabled individual data frame transfers are always separated by slave deselection: independent of the availability of TX FIFO data frames, data frames are sent out with slave deselection. + [0:0] + read-write + + + SELECT_PRECEDE + Only used in SPI Texas Instruments' submode. + +When '1', the data frame start indication is a pulse on the Slave SELECT line that precedes the transfer of the first data frame bit. + +When '0', the data frame start indication is a pulse on the Slave SELECT line that coincides with the transfer of the first data frame bit. + [1:1] + read-write + + + CPHA + N/A + [2:2] + read-write + + + CPOL + N/A + [3:3] + read-write + + + LATE_MISO_SAMPLE + Changes the SCLK edge on which MISO is captured. Only used in master mode. + +When '0', the default applies ( +for Motorola as determined by CPOL and CPHA, +for Texas Instruments on the falling edge of SCLK and +for National Semiconductors on the rising edge of SCLK). + +When '1', the alternate clock edge is used (which comes half a SPI SCLK period later). Late sampling addresses the round trip delay associated with transmitting SCLK from the master to the slave and transmitting MISO from the slave to the master. + [4:4] + read-write + + + SCLK_CONTINUOUS + N/A + [5:5] + read-write + + + SSEL_POLARITY0 + N/A + [8:8] + read-write + + + SSEL_POLARITY1 + N/A + [9:9] + read-write + + + SSEL_POLARITY2 + N/A + [10:10] + read-write + + + SSEL_POLARITY3 + N/A + [11:11] + read-write + + + SSEL_SETUP_DEL + N/A + [12:12] + read-write + + + SSEL_HOLD_DEL + N/A + [13:13] + read-write + + + SSEL_INTER_FRAME_DEL + N/A + [14:14] + read-write + + + LOOPBACK + Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode. +'0': No local loopback +'1': the SPI master MISO line is connected to the SPI master MOSI line. In other words, in loopback mode the SPI master receives on MISO what it transmits on MOSI. + [16:16] + read-write + + + MODE + N/A + [25:24] + read-write + + + SPI_MOTOROLA + SPI Motorola submode. In master mode, when not transmitting data (SELECT is inactive), SCLK is stable at CPOL. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive. + 0 + + + SPI_TI + SPI Texas Instruments submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive; i.e. no pulse is generated. + 1 + + + SPI_NS + SPI National Semiconductors submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive. + 2 + + + + + SSEL + Selects one of the four incoming/outgoing SPI slave select signals: +- 0: Slave 0, SSEL[0]. +- 1: Slave 1, SSEL[1]. +- 2: Slave 2, SSEL[2]. +- 3: Slave 3, SSEL[3]. +SCB block should be disabled when changes are made to this field. + [27:26] + read-write + + + MASTER_MODE + N/A + [31:31] + read-write + + + + + SPI_STATUS + SPI status + 0x24 + 32 + read-only + 0x0 + 0x0 + + + BUS_BUSY + SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes, the busy bit is '1', when the slave selection is activated. For TI submode, the busy bit is '1' from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted. + [0:0] + read-only + + + SPI_EC_BUSY + Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are reliable. + [1:1] + read-only + + + CURR_EZ_ADDR + SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1'), as clock domain synchronization is not performed in the design. + [15:8] + read-only + + + BASE_EZ_ADDR + SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design. + [23:16] + read-only + + + + + SPI_TX_CTRL + SPI transmitter control + 0x28 + 32 + read-write + 0x0 + 0x30 + + + PARITY + Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity. + [4:4] + read-write + + + PARITY_ENABLED + Parity generation enabled ('1') or not ('0'). + [5:5] + read-write + + + + + SPI_RX_CTRL + SPI receiver control + 0x2C + 32 + read-write + 0x0 + 0x130 + + + PARITY + Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. + [4:4] + read-write + + + PARITY_ENABLED + Parity checking enabled ('1') or not ('0'). + [5:5] + read-write + + + DROP_ON_PARITY_ERROR + Behavior when a parity check fails. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. + [8:8] + read-write + + + + + UART_CTRL + UART control + 0x40 + 32 + read-write + 0x3000000 + 0x3010000 + + + LOOPBACK + Local loopback control (does NOT affect the information on the pins). +0: Loopback is not enabled +1: UART_TX is connected to UART_RX. UART_RTS is connected to UART_CTS. +This allows a SCB UART transmitter to communicate with its receiver counterpart. + [16:16] + read-write + + + MODE + N/A + [25:24] + read-write + + + UART_STD + Standard UART submode. + 0 + + + UART_SMARTCARD + SmartCard (ISO7816) submode. Support for negative acknowledgement (NACK) on the receiver side and retransmission on the transmitter side. + 1 + + + UART_IRDA + Infrared Data Association (IrDA) submode. Return to Zero modulation scheme. + 2 + + + + + + + UART_TX_CTRL + UART transmitter control + 0x44 + 32 + read-write + 0x2 + 0x137 + + + STOP_BITS + Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. + [2:0] + read-write + + + PARITY + Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes. + [4:4] + read-write + + + PARITY_ENABLED + Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode, parity generation is always enabled through hardware. In IrDA submode, parity generation is always disabled through hardware + [5:5] + read-write + + + RETRY_ON_NACK + When '1', a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode. + [8:8] + read-write + + + + + UART_RX_CTRL + UART receiver control + 0x48 + 32 + read-write + 0xA0002 + 0x10F3777 + + + STOP_BITS + Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. + +Note that in case of a stop bits error, the successive data frames may get lost as the receiver needs to resynchronize its start bit detection. The amount of lost data frames depends on both the amount of stop bits, the idle time between data frames and the data frame value. + [2:0] + read-write + + + PARITY + N/A + [4:4] + read-write + + + PARITY_ENABLED + N/A + [5:5] + read-write + + + POLARITY + Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality. + [6:6] + read-write + + + DROP_ON_PARITY_ERROR + Behavior when a parity check fails. +When '0', received data is sent to the RX FIFO. +When '1', received data is dropped and lost. +Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field). + [8:8] + read-write + + + DROP_ON_FRAME_ERROR + Behavior when an error is detected in a start or stop period. +When '0', received data is sent to the RX FIFO. + When '1', received data is dropped and lost. + [9:9] + read-write + + + MP_MODE + N/A + [10:10] + read-write + + + LIN_MODE + Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minimum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. + [12:12] + read-write + + + SKIP_START + N/A + [13:13] + read-write + + + BREAK_WIDTH + N/A + [19:16] + read-write + + + BREAK_LEVEL + N/A + [24:24] + read-write + + + + + UART_RX_STATUS + UART receiver status + 0x4C + 32 + read-only + 0x0 + 0x0 + + + BR_COUNTER + Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has valid data when INTR_RX.BAUD_DETECT is set to '1'. + [11:0] + read-only + + + + + UART_FLOW_CTRL + UART flow control + 0x50 + 32 + read-write + 0x0 + 0x30100FF + + + TRIGGER_LEVEL + Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal is activated. By setting this field to '0', flow control is effectively disabled (may be useful for debug purposes). + [7:0] + read-write + + + RTS_POLARITY + Polarity of the RTS output signal: +'0': RTS is active low; +'1': RTS is active high; + +During SCB reset (Hibernate system power mode), RTS output signal is '1'. This represents an inactive state assuming an active low polarity. + [16:16] + read-write + + + CTS_POLARITY + Polarity of the CTS input signal +'0': CTS is active low ; +'1': CTS is active high; + [24:24] + read-write + + + CTS_ENABLED + Enable use of CTS input signal by the UART transmitter: +'0': Disabled. The UART transmitter ignores the CTS input signal and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register. +'1': Enabled. The UART transmitter uses CTS input signal to qualify the transmission of data. It transmits when CTS input signal is active and a data frame is available for transmission in the TX FIFO or the TX shift register. + +If UART_CTRL.LOOPBACK is '1', the CTS input signal is driven by the RTS output signal locally in SCB (both signals are subjected to signal polarity changes are indicated by RTS_POLARITY and CTS_POLARITY). + [25:25] + read-write + + + + + I2C_CTRL + I2C control + 0x60 + 32 + read-write + 0xFB88 + 0xC001FBFF + + + HIGH_PHASE_OVS + Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5, 15] with input signal median filtering and [4, 15] without input signal median filtering. + +The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the SCB clock wrt. the regular interface (IF) high time to guarantee functional correct behavior. With input signal median filtering, the IF high time should be >= 6 SCB clock cycles and <= 16 SCB clock cycles. Without input signal median filtering, the IF high time should be >= 5 SCB clock cycles and <= 16 SCB clock cycles. + [3:0] + read-write + + + LOW_PHASE_OVS + Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7, 15] with input signal median filtering and [6, 15] without input signal median filtering. + +The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the SCB clock wrt. the regular (no stretching) interface (IF) low time to guarantee functionally correct behavior. With input signal median filtering, the IF low time should be >= 8 SCB clock cycles and <= 16 IP clock cycles. Without input signal median filtering, the IF low time should be >= 7 SCB clock cycles and <= 16 SCB clock cycles. + +in slave mode, this field is used to define number of clk_scb cycles for tSU-DAT timing (from ACK/NACK/data ready, to SCL rising edge (released from I2C slave clock stretching)) + [7:4] + read-write + + + M_READY_DATA_ACK + N/A + [8:8] + read-write + + + M_NOT_READY_DATA_NACK + N/A + [9:9] + read-write + + + S_GENERAL_IGNORE + N/A + [11:11] + read-write + + + S_READY_ADDR_ACK + N/A + [12:12] + read-write + + + S_READY_DATA_ACK + N/A + [13:13] + read-write + + + S_NOT_READY_ADDR_NACK + This field is used during an address match or general call address in internally clocked mode +Only used when: + - EC_AM_MODE is '0', EC_OP_MODE is '0', S_GENERAL_IGNORE is '0] and non EZ mode. +Functionality is as follows: +- 1: a received (matching) slave address is immediately NACK'd when the receiver FIFO is full. +- 0: clock stretching is performed (till the receiver FIFO is no longer full). + +For externally clocked logic (EC_AM is '1') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when (NOT used when EC_AM is '1' and EC_OP is '1' and address match and EZ mode): +- EC_AM is '1' and EC_OP is '0'. +- EC_AM is '1' and general call address match. +- EC_AM is '1' and non EZ mode. +Functionality is as follows: +- 1: a received (matching or general) slave address is always immediately NACK'd. There are two possibilities: + 1). the SCB clock is available (in Active system power mode) and it handles the rest of the current transfer. In this case the I2C master will not observe the NACK. + 2).SCB clock is not present (in DeepSleep system power mode). In this case the I2C master will observe the NACK and may retry the transfer in the future (which gives the internally clocked logic the time to wake up from DeepSleep system power mode). +- 0: clock stretching is performed (till the SCB clock is available). The logic will handle the ongoing transfer as soon as the clock is enabled. + [14:14] + read-write + + + S_NOT_READY_DATA_NACK + Only used when: +- non EZ mode +Functionality is as follows: +- 1: a received data element byte the slave is immediately NACK'd when the receiver FIFO is full. +- 0: clock stretching is performed (till the receiver FIFO is no longer full). + [15:15] + read-write + + + LOOPBACK + Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. +When '0', no loopback +When '1', loopback is enabled internally in the peripheral, and as a result unaffected by other I2C devices. This allows a SCB I2C peripheral to address itself. + [16:16] + read-write + + + SLAVE_MODE + N/A + [30:30] + read-write + + + MASTER_MODE + N/A + [31:31] + read-write + + + + + I2C_STATUS + I2C status + 0x64 + 32 + read-only + 0x0 + 0x35 + + + BUS_BUSY + I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If SCB block is disabled, BUS_BUSY is '0'. After enabling the block, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period). + +For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions). + +For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions). + [0:0] + read-only + + + I2C_EC_BUSY + N/A + [1:1] + read-only + + + I2CS_IC_BUSY + N/A + [2:2] + read-only + + + S_READ + N/A + [4:4] + read-only + + + M_READ + N/A + [5:5] + read-only + + + CURR_EZ_ADDR + N/A + [15:8] + read-only + + + BASE_EZ_ADDR + N/A + [23:16] + read-only + + + + + I2C_M_CMD + I2C master command + 0x68 + 32 + read-write + 0x0 + 0x1F + + + M_START + When '1', transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START is transmitted when the master state machine is not in the default state, but is working on an ongoing transaction. The REPEATED START can only be transmitted after a NACK or ACK has been received for a transmitted data element or after a NACK has been transmitted for a received data element. When this action is performed, the hardware sets this field to '0'. + [0:0] + read-write + + + M_START_ON_IDLE + When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result, bus idle detection is only functional after at least one I2C bus transfer has been detected on the bus (default/reset value of BUSY is '0') . A START is only transmitted when the master state machine is in the default state. When this action is performed, the hardware sets this field to '0'. + [1:1] + read-write + + + M_ACK + When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. + [2:2] + read-write + + + M_NACK + When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. + [3:3] + read-write + + + M_STOP + When '1', attempt to transmit a STOP. When this action is performed, the hardware sets this field to '0'. + I2C_M_CMD.M_START has a higher priority than this command: in situations where both a STOP and a REPEATED START could be transmitted, M_START takes precedence over M_STOP. + [4:4] + read-write + + + + + I2C_S_CMD + I2C slave command + 0x6C + 32 + read-write + 0x0 + 0x3 + + + S_ACK + When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). + [0:0] + read-write + + + S_NACK + When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher priority than I2C_S_CMD.S_ACK, I2C_CTRL.S_READY_ADDR_ACK or I2C_CTRL.S_READY_DATA_ACK. + [1:1] + read-write + + + + + I2C_CFG + I2C configuration + 0x70 + 32 + read-write + 0x2A1013 + 0x303F1313 + + + SDA_IN_FILT_TRIM + Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required + [1:0] + read-write + + + SDA_IN_FILT_SEL + Enable for 50ns glitch filter on SDA input +'0': 0 ns. +'1: 50 ns (filter enabled). + [4:4] + read-write + + + SCL_IN_FILT_TRIM + Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required + [9:8] + read-write + + + SCL_IN_FILT_SEL + Enable for 50ns glitch filter on SCL input +'0': 0 ns. +'1: 50 ns (filter enabled). + [12:12] + read-write + + + SDA_OUT_FILT0_TRIM + Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required + [17:16] + read-write + + + SDA_OUT_FILT1_TRIM + Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required + [19:18] + read-write + + + SDA_OUT_FILT2_TRIM + Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required + [21:20] + read-write + + + SDA_OUT_FILT_SEL + Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter +'0': 0 ns. +'1': 50 ns (filter 0 enabled). +'2': 100 ns (filters 0 and 1 enabled). +'3': 150 ns (filters 0, 1 and 2 enabled). + [29:28] + read-write + + + + + TX_CTRL + Transmitter control + 0x200 + 32 + read-write + 0x107 + 0x1011F + + + DATA_WIDTH + Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 31]. For I2C the only valid value is 7. + [4:0] + read-write + + + MSB_FIRST + Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. + [8:8] + read-write + + + OPEN_DRAIN + Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'. +'0': Normal operation mode. Typically, this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by a single IO cell. In this operation mode, for an IO cell 'xxx' that is used as an output, the 'xxx_out_en' output enable signal is typically constant '1' the 'xxx_out' output is the outputted value. In other words, in normal operation mode, the 'xxx_out' output is used to control the IO cell output value: 'xxx_out' is '0' to drive an IO cell output value of '0' and 'xxx_out' is '1' to drive an IO cell output value of '1'. +'1': Open drain operation mode. Typically this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by multiple IO cells (possibly on multiple chips). In this operation mode, for and IO cell 'xxx' that is used as an output, the 'xxx_out_en' output controls the outputted value. Typically, open drain operation mode drives low/'0' and the 'xxx_out' output is constant '1'. In other words, in open drain operation mode, the 'xxx_out_en' output is used to control the IO cell output value: in drive low/'0' mode: 'xxx_out_en' is '1' (drive enabled) to drive an IO cell output value of '0' and 'xxx_out_en' is '1' (drive disabled) to not drive an IO cell output value (another IO cell can drive the wire/line or a pull up results in a wire/line value '1'). + +The open drain mode is supported for: +- UART mode, 'uart_tx' IO cell. +- SPI mode, 'spi_miso' IO cell. + +not applicable to I2C mode, 'i2c_scl' and 'i2c_sda' IO cells. (I2C SCL/SDA always work in open-drain mode) + [16:16] + read-write + + + + + TX_FIFO_CTRL + Transmitter FIFO control + 0x204 + 32 + read-write + 0x0 + 0x300FF + + + TRIGGER_LEVEL + Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event INTR_TX.TRIGGER is generated. + [7:0] + read-write + + + CLEAR + When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + [16:16] + read-write + + + FREEZE + When '1', hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. + [17:17] + read-write + + + + + TX_FIFO_STATUS + Transmitter FIFO status + 0x208 + 32 + read-only + 0x0 + 0xFFFF81FF + + + USED + Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2). + [8:0] + read-only + + + SR_VALID + Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is transmitted next (when the protocol state machine is not transmitting a data frame). + [15:15] + read-only + + + RD_PTR + FIFO read pointer: FIFO location from which a data frame is read by the hardware. + [23:16] + read-only + + + WR_PTR + FIFO write pointer: FIFO location at which a new data frame is written. + [31:24] + read-only + + + + + TX_FIFO_WR + Transmitter FIFO write + 0x240 + 32 + write-only + 0x0 + 0xFFFFFFFF + + + DATA + Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0', only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1', only DATA[15:0] are used. + +A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'. + [31:0] + write-only + + + + + RX_CTRL + Receiver control + 0x300 + 32 + read-write + 0x107 + 0x31F + + + DATA_WIDTH + Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 31]. For I2C the only valid value is 7. In EZ mode (for both SPI and I2C), the only valid value is 7. + [4:0] + read-write + + + MSB_FIRST + Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. + [8:8] + read-write + + + MEDIAN + Median filter. When '1', a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However, its requires higher oversampling values. For UART IrDA submode, this field should always be '1'. + [9:9] + read-write + + + + + RX_FIFO_CTRL + Receiver FIFO control + 0x304 + 32 + read-write + 0x0 + 0x300FF + + + TRIGGER_LEVEL + Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event INTR_RX.TRIGGER is generated. + [7:0] + read-write + + + CLEAR + When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + [16:16] + read-write + + + FREEZE + When '1', hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer. + [17:17] + read-write + + + + + RX_FIFO_STATUS + Receiver FIFO status + 0x308 + 32 + read-only + 0x0 + 0xFFFF81FF + + + USED + Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2). + [8:0] + read-only + + + SR_VALID + Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame). + [15:15] + read-only + + + RD_PTR + FIFO read pointer: FIFO location from which a data frame is read. + [23:16] + read-only + + + WR_PTR + FIFO write pointer: FIFO location at which a new data frame is written by the hardware. + [31:24] + read-only + + + + + RX_MATCH + Slave address and mask + 0x310 + 32 + read-write + 0x0 + 0xFF00FF + + + ADDR + N/A + [7:0] + read-write + + + MASK + Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR & MASK) == ('slave address' & MASK)). + [23:16] + read-write + + + + + RX_FIFO_RD + Receiver FIFO read + 0x340 + 32 + read-only + 0x0 + 0x0 + + + DATA + Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0', only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1', only DATA[15:0] are used + +A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. + +When this register is read through the debugger, the data frame will not be removed from the FIFO. Similar in operation to RX_FIFO_RD_SILENT + [31:0] + read-only + + + + + RX_FIFO_RD_SILENT + Receiver FIFO read silent + 0x344 + 32 + read-only + 0x0 + 0x0 + + + DATA + Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0', only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1', only DATA[15:0] are used + +A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. + [31:0] + read-only + + + + + INTR_CAUSE + Active clocked interrupt signal + 0xE00 + 32 + read-only + 0x0 + 0x3F + + + M + Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0. + [0:0] + read-only + + + S + Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0. + [1:1] + read-only + + + TX + Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0. + [2:2] + read-only + + + RX + Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0. + [3:3] + read-only + + + I2C_EC + Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0. + [4:4] + read-only + + + SPI_EC + Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0. + [5:5] + read-only + + + + + INTR_I2C_EC + Externally clocked I2C interrupt request + 0xE80 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Wake up request. Active on incoming slave request (with address match). + +Only used when CTRL.EC_AM_MODE is '1'. + [0:0] + read-write + + + EZ_STOP + STOP detection. Activated on the end of a every transfer (I2C STOP). + +Only available for a slave request with an address match, in EZ and CMD_RESP modes, when CTRL.EC_OP_MODE is '1'. + [1:1] + read-write + + + EZ_WRITE_STOP + STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. + +Only available for a slave request with an address match, in EZ and CMD_RESP modes, when CTRL.EC_OP_MODE is '1'. + [2:2] + read-write + + + EZ_READ_STOP + STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from. + +Only available for a slave request with an address match, in EZ and CMD_RESP modes, when CTRL.EC_OP_MODE is '1'. + [3:3] + read-write + + + + + INTR_I2C_EC_MASK + Externally clocked I2C interrupt mask + 0xE88 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + EZ_STOP + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + EZ_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + EZ_READ_STOP + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + + + INTR_I2C_EC_MASKED + Externally clocked I2C interrupt masked + 0xE8C + 32 + read-only + 0x0 + 0xF + + + WAKE_UP + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + EZ_STOP + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EZ_WRITE_STOP + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + EZ_READ_STOP + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + + + INTR_SPI_EC + Externally clocked SPI interrupt request + 0xEC0 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Wake up request. Active on incoming slave request when externally clocked selection is '1'. + +Only used when CTRL.EC_AM_MODE is '1'. + [0:0] + read-write + + + EZ_STOP + STOP detection. Activated on the end of a every transfer (SPI deselection). + +Only available in EZ and CMD_RESP mode and when CTRL.EC_OP_MODE is '1'. + [1:1] + read-write + + + EZ_WRITE_STOP + STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. + +Only used in EZ and CMD_RESP modes and when CTRL.EC_OP_MODE is '1'. + [2:2] + read-write + + + EZ_READ_STOP + STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from. + +Only used in EZ and CMD_RESP modes and when CTRL.EC_OP_MODE is '1'. + [3:3] + read-write + + + + + INTR_SPI_EC_MASK + Externally clocked SPI interrupt mask + 0xEC8 + 32 + read-write + 0x0 + 0xF + + + WAKE_UP + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + EZ_STOP + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + EZ_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + EZ_READ_STOP + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + + + INTR_SPI_EC_MASKED + Externally clocked SPI interrupt masked + 0xECC + 32 + read-only + 0x0 + 0xF + + + WAKE_UP + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + EZ_STOP + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EZ_WRITE_STOP + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + EZ_READ_STOP + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + + + INTR_M + Master interrupt request + 0xF00 + 32 + read-write + 0x0 + 0x317 + + + I2C_ARB_LOST + I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line. + [0:0] + read-write + + + I2C_NACK + I2C master negative acknowledgement. Set to '1', when the master receives a NACK (typically after the master transmitted the slave address or TX data). + [1:1] + read-write + + + I2C_ACK + I2C master acknowledgement. Set to '1', when the master receives a ACK (typically after the master transmitted the slave address or TX data). + [2:2] + read-write + + + I2C_STOP + I2C master STOP. Set to '1', when the master has transmitted a STOP. + [4:4] + read-write + + + I2C_BUS_ERROR + I2C master bus error (unexpected detection of START or STOP condition). + [8:8] + read-write + + + SPI_DONE + SPI master transfer done event: all data frames in the transmit FIFO are sent, the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty), and SPI select output pin is deselected. + [9:9] + read-write + + + + + INTR_M_SET + Master interrupt set request + 0xF04 + 32 + read-write + 0x0 + 0x317 + + + I2C_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_STOP + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_BUS_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_DONE + Write with '1' to set corresponding bit in interrupt request register. + [9:9] + read-write + + + + + INTR_M_MASK + Master interrupt mask + 0xF08 + 32 + read-write + 0x0 + 0x317 + + + I2C_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_STOP + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_BUS_ERROR + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_DONE + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + + + INTR_M_MASKED + Master interrupt masked request + 0xF0C + 32 + read-only + 0x0 + 0x317 + + + I2C_ARB_LOST + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + I2C_NACK + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + I2C_ACK + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + I2C_STOP + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + I2C_BUS_ERROR + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + SPI_DONE + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + + + INTR_S + Slave interrupt request + 0xF40 + 32 + read-write + 0x0 + 0xFFF + + + I2C_ARB_LOST + I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine aborts the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error. + [0:0] + read-write + + + I2C_NACK + N/A + [1:1] + read-write + + + I2C_ACK + N/A + [2:2] + read-write + + + I2C_WRITE_STOP + N/A + [3:3] + read-write + + + I2C_STOP + N/A + [4:4] + read-write + + + I2C_START + I2C slave START received. Set to '1', when START or REPEATED START event is detected. + +In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. The Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL. + [5:5] + read-write + + + I2C_ADDR_MATCH + N/A + [6:6] + read-write + + + I2C_GENERAL + N/A + [7:7] + read-write + + + I2C_BUS_ERROR + N/A + [8:8] + read-write + + + SPI_EZ_WRITE_STOP + N/A + [9:9] + read-write + + + SPI_EZ_STOP + N/A + [10:10] + read-write + + + SPI_BUS_ERROR + N/A + [11:11] + read-write + + + + + INTR_S_SET + Slave interrupt set request + 0xF44 + 32 + read-write + 0x0 + 0xFFF + + + I2C_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_WRITE_STOP + Write with '1' to set corresponding bit in interrupt request register. + [3:3] + read-write + + + I2C_STOP + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_START + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + I2C_ADDR_MATCH + Write with '1' to set corresponding bit in interrupt request register. + [6:6] + read-write + + + I2C_GENERAL + Write with '1' to set corresponding bit in interrupt request register. + [7:7] + read-write + + + I2C_BUS_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_EZ_WRITE_STOP + Write with '1' to set corresponding bit in interrupt request register. + [9:9] + read-write + + + SPI_EZ_STOP + Write with '1' to set corresponding bit in interrupt request register. + [10:10] + read-write + + + SPI_BUS_ERROR + Write with '1' to set corresponding bit in interrupt request register. + [11:11] + read-write + + + + + INTR_S_MASK + Slave interrupt mask + 0xF48 + 32 + read-write + 0x0 + 0xFFF + + + I2C_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + I2C_NACK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + I2C_ACK + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + I2C_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + I2C_STOP + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + I2C_START + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + I2C_ADDR_MATCH + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + I2C_GENERAL + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + I2C_BUS_ERROR + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + SPI_EZ_WRITE_STOP + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + SPI_EZ_STOP + Mask bit for corresponding bit in interrupt request register. + [10:10] + read-write + + + SPI_BUS_ERROR + Mask bit for corresponding bit in interrupt request register. + [11:11] + read-write + + + + + INTR_S_MASKED + Slave interrupt masked request + 0xF4C + 32 + read-only + 0x0 + 0xFFF + + + I2C_ARB_LOST + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + I2C_NACK + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + I2C_ACK + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + I2C_WRITE_STOP + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + I2C_STOP + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + I2C_START + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + I2C_ADDR_MATCH + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + I2C_GENERAL + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + I2C_BUS_ERROR + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + SPI_EZ_WRITE_STOP + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + SPI_EZ_STOP + Logical and of corresponding request and mask bits. + [10:10] + read-only + + + SPI_BUS_ERROR + Logical and of corresponding request and mask bits. + [11:11] + read-only + + + + + INTR_TX + Transmitter interrupt request + 0xF80 + 32 + read-write + 0x0 + 0x7F3 + + + TRIGGER + N/A + [0:0] + read-write + + + NOT_FULL + N/A + [1:1] + read-write + + + EMPTY + N/A + [4:4] + read-write + + + OVERFLOW + N/A + [5:5] + read-write + + + UNDERFLOW + Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'. + +Only used in FIFO mode. +(Note: This bit may be set unintentionally, even if the FIFO is not empty. +Workaround: Ignore the bit when the clock frequency of the AHB bus is greater than 3x the internal frequency of SCB and the FIFO is not empty) + [6:6] + read-write + + + BLOCKED + SW cannot get access to the EZ memory (EZ data access), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'. + [7:7] + read-write + + + UART_NACK + N/A + [8:8] + read-write + + + UART_DONE + N/A + [9:9] + read-write + + + UART_ARB_LOST + N/A + [10:10] + read-write + + + + + INTR_TX_SET + Transmitter interrupt set request + 0xF84 + 32 + read-write + 0x0 + 0x7F3 + + + TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_FULL + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + EMPTY + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [6:6] + read-write + + + BLOCKED + Write with '1' to set corresponding bit in interrupt request register. + [7:7] + read-write + + + UART_NACK + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + UART_DONE + Write with '1' to set corresponding bit in interrupt request register. + [9:9] + read-write + + + UART_ARB_LOST + Write with '1' to set corresponding bit in interrupt request register. + [10:10] + read-write + + + + + INTR_TX_MASK + Transmitter interrupt mask + 0xF88 + 32 + read-write + 0x0 + 0x7F3 + + + TRIGGER + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_FULL + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + EMPTY + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + BLOCKED + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + UART_NACK + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + UART_DONE + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + UART_ARB_LOST + Mask bit for corresponding bit in interrupt request register. + [10:10] + read-write + + + + + INTR_TX_MASKED + Transmitter interrupt masked request + 0xF8C + 32 + read-only + 0x0 + 0x7F3 + + + TRIGGER + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + NOT_FULL + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + EMPTY + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + OVERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + UNDERFLOW + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + BLOCKED + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + UART_NACK + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + UART_DONE + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + UART_ARB_LOST + Logical and of corresponding request and mask bits. + [10:10] + read-only + + + + + INTR_RX + Receiver interrupt request + 0xFC0 + 32 + read-write + 0x0 + 0xFED + + + TRIGGER + N/A + [0:0] + read-write + + + NOT_EMPTY + N/A + [2:2] + read-write + + + FULL + N/A + [3:3] + read-write + + + OVERFLOW + N/A + [5:5] + read-write + + + UNDERFLOW + N/A + [6:6] + read-write + + + BLOCKED + SW cannot get access to the EZ memory (EZ_DATA accesses), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'. + [7:7] + read-write + + + FRAME_ERROR + N/A + [8:8] + read-write + + + PARITY_ERROR + N/A + [9:9] + read-write + + + BAUD_DETECT + N/A + [10:10] + read-write + + + BREAK_DETECT + N/A + [11:11] + read-write + + + + + INTR_RX_SET + Receiver interrupt set request + 0xFC4 + 32 + read-write + 0x0 + 0xFED + + + TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_EMPTY + Write with '1' to set corresponding bit in interrupt status register. + [2:2] + read-write + + + FULL + Write with '1' to set corresponding bit in interrupt status register. + [3:3] + read-write + + + OVERFLOW + Write with '1' to set corresponding bit in interrupt status register. + [5:5] + read-write + + + UNDERFLOW + Write with '1' to set corresponding bit in interrupt status register. + [6:6] + read-write + + + BLOCKED + Write with '1' to set corresponding bit in interrupt status register. + [7:7] + read-write + + + FRAME_ERROR + Write with '1' to set corresponding bit in interrupt status register. + [8:8] + read-write + + + PARITY_ERROR + Write with '1' to set corresponding bit in interrupt status register. + [9:9] + read-write + + + BAUD_DETECT + Write with '1' to set corresponding bit in interrupt status register. + [10:10] + read-write + + + BREAK_DETECT + Write with '1' to set corresponding bit in interrupt status register. + [11:11] + read-write + + + + + INTR_RX_MASK + Receiver interrupt mask + 0xFC8 + 32 + read-write + 0x0 + 0xFED + + + TRIGGER + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + NOT_EMPTY + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + FULL + Mask bit for corresponding bit in interrupt request register. + [3:3] + read-write + + + OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + BLOCKED + Mask bit for corresponding bit in interrupt request register. + [7:7] + read-write + + + FRAME_ERROR + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + PARITY_ERROR + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + BAUD_DETECT + Mask bit for corresponding bit in interrupt request register. + [10:10] + read-write + + + BREAK_DETECT + Mask bit for corresponding bit in interrupt request register. + [11:11] + read-write + + + + + INTR_RX_MASKED + Receiver interrupt masked request + 0xFCC + 32 + read-only + 0x0 + 0xFED + + + TRIGGER + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + NOT_EMPTY + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + FULL + Logical and of corresponding request and mask bits. + [3:3] + read-only + + + OVERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + UNDERFLOW + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + BLOCKED + Logical and of corresponding request and mask bits. + [7:7] + read-only + + + FRAME_ERROR + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + PARITY_ERROR + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + BAUD_DETECT + Logical and of corresponding request and mask bits. + [10:10] + read-only + + + BREAK_DETECT + Logical and of corresponding request and mask bits. + [11:11] + read-only + + + + + + + SCB1 + 0x40610000 + + + SCB2 + 0x40620000 + + + SCB3 + 0x40630000 + + + SCB4 + 0x40640000 + + + SCB5 + 0x40650000 + + + SCB6 + 0x40660000 + + + SCB7 + 0x40670000 + + + SCB8 + 0x40680000 + + + SCB9 + 0x40690000 + + + SCB10 + 0x406A0000 + + + I2S0 + I2S registers + I2S + 0x40800000 + + 0 + 4096 + registers + + + + CTL + Control + 0x0 + 32 + read-write + 0x0 + 0xC0000000 + + + TX_ENABLED + Enables the I2S TX component: +'0': Disabled. +'1': Enabled. + [30:30] + read-write + + + RX_ENABLED + Enables the I2S RX component: +'0': Disabled. +'1': Enabled. + [31:31] + read-write + + + + + CLOCK_CTL + Clock control + 0x10 + 32 + read-write + 0x3000 + 0x1313F + + + CLOCK_DIV + Frequency divisor for generating I2S clock frequency. +The selected clock with CLOCK_SEL is divided by this. +'0': Bypass +'1': 2 x +'2': 3 x +'3': 4 x +... +'62': 63 x +'63': 64 x + [5:0] + read-write + + + CLOCK_SEL + Selects clock to be used by I2S: +'0': Internal clock ('clk_audio_i2s') +'1': External clock ('clk_i2s_if') + [8:8] + read-write + + + MCLK_DIV + Selects clock divider for MCLK_OUT. +CTL.TX_ENABLED=1 or CTL.RX_ENABLED=1 and and CLOCK_CTL.CLOCK_SEL=0 to enable the clock. + [13:12] + read-write + + + DIV1 + Divide clk_audio_i2s by 1 (Bypass) + 0 + + + DIV2 + Divide clk_audio_i2s by 2 + 1 + + + DIV4 + Divide clk_audio_i2s by 4 + 2 + + + DIV8 + Divide clk-audio_i2s by 8 + 3 + + + + + MCLK_EN + Enable MCLK - enables MCLK divider operation +Upon assertion allows MCLK Divider to begin operation. +Upon de-assertion, i.e. 1-0 transition, allows MCLK divider to reach the all 0s state (reset state) then freezes the divider. This permits a controlled power-on/power-off sequence that may be used prior to going to DeepSleep/IP Disable and avoids glitching the MCLK. + [16:16] + read-write + + + + + CLOCK_STAT + Clock Status + 0x14 + 32 + read-only + 0x0 + 0x1 + + + MCLK_DIV_OFF + MCLK Divider OFF +0: Indicates MCLK Divider not a reset state +1: Indicates MCLK Divider at reset state. This is ONLY set when IP is enabled (CTL.RX_ENABLED=1 or CTL.TX_ENABLED=1), CLOCK_CTL.MCLK_EN=0, and MCLK_DIV reaches it's reset state. + +The intent is that this bit indicates successful shutdown of the MCLK_DIVIDER after CLOCK_CTL.MCLK_EN transitions from 1 to 0. + [0:0] + read-only + + + + + CMD + Command + 0x20 + 32 + read-write + 0x0 + 0x10101 + + + TX_START + Transmitter enable: +'0': Disabled. +'1': Enabled. + [0:0] + read-write + + + TX_PAUSE + Pause enable: +'0': Disabled (TX FIFO data is sent over I2S). +'1': Enabled ('0' data is sent over I2S, instead of TX FIFO data). + [8:8] + read-write + + + RX_START + Receiver enable: +'0': Disabled. +'1': Enabled. + [16:16] + read-write + + + + + TR_CTL + Trigger control + 0x40 + 32 + read-write + 0x0 + 0x10001 + + + TX_REQ_EN + Trigger output ('tr_i2s_tx_req') enable for requests of DMA transfer in transmission +'0': Disabled. +'1': Enabled. + [0:0] + read-write + + + RX_REQ_EN + Trigger output ('tr_i2s_rx_req') enable for requests of DMA transfer in reception +'0': Disabled. +'1': Enabled. + [16:16] + read-write + + + + + TX_CTL + Transmitter control + 0x80 + 32 + read-write + 0x440510 + 0x37737F8 + + + B_CLOCK_INV + Serial data transmission is advanced by 0.5 SCK cycles. This bit is valid only in TX slave mode. +When set to '1', the serial data will be transmitted 0.5 SCK cycles earlier than when set to '0'. + +1) TX_CTL.SCKI_POL=0 and TX_CTL.B_CLOCK_INV=0: Serial data will be transmitted off the SCK falling edge +2) TX_CTL.SCKI_POL=0 and TX_CTL.B_CLOCK_INV=1: Serial data will be transmitted off the SCK rising edge that is 0.5 SCK cycles before the SCK falling edge in 1) +3) TX_CTL.SCKI_POL=1 and TX_CTL.B_CLOCK_INV=0: Serial data will be transmitted off the SCK rising edge +4) TX_CTL.SCKI_POL=1 and TX_CTL.B_CLOCK_INV=1: Serial data will be transmitted off the SCK falling edge that is 0.5 SCK cycles before the SCK rising edge in 3) + +(Note that this is only the appearance w.r.t. SCK edge, the actual timing is generated by an internal clock that runs 8x the SCK frequency). The word sync (TX_WS) signal is not affected by this bit setting. +Note: When Master mode, must be '0'. + [3:3] + read-write + + + FALLING_EDGE_TX + SDO transmitted at SCK falling edge when TX_CTL.SCKI_POL=0 + 0 + + + RISING_EDGE_TX + SDO transmitted at SCK rising edge when TX_CTL.SCKI_POL=0 + 1 + + + + + CH_NR + Specifies number of channels per frame: + +Note: only '2channels' is supported during Left Justfied or I2S mode. Hence software must set '1' to this field in the modes. + [6:4] + read-write + + + CH_NUM1 + 1 channel + 0 + + + CH_NUM2 + 2 channels + 1 + + + CH_NUM3 + 3 channels + 2 + + + CH_NUM4 + 4 channels + 3 + + + CH_NUM5 + 5 channels + 4 + + + CH_NUM6 + 6 channels + 5 + + + CH_NUM7 + 7 channels + 6 + + + CH_NUM8 + 8 channels + 7 + + + + + MS + Set interface in master or slave mode: + [7:7] + read-write + + + SLAVE + Slave + 0 + + + MASTER + Master + 1 + + + + + I2S_MODE + Select I2S, left-justified or TDM: + [9:8] + read-write + + + LEFT_JUSTIFIED + Left Justified + 0 + + + I2S + I2S mode + 1 + + + TDM_A + TDM mode A, the 1st Channel align to WSO +Rising Edge + 2 + + + TDM_B + TDM mode B, the 1st Channel align to WSO +Rising edge with1 SCK Delay + 3 + + + + + WS_PULSE + Set WS pulse width in TDM mode: + +Note: When not TDM mode, must be '1'. + [10:10] + read-write + + + SCK_PERIOD + Pulse width is 1 SCK period + 0 + + + CH_LENGTH + Pulse width is 1 channel length + 1 + + + + + OVHDATA + Set overhead value: +'0': Set to '0' +'1': Set to '1' + [12:12] + read-write + + + WD_EN + N/A + [13:13] + read-write + + + CH_LEN + Channel length in number of bits: + +Note: +- When this field is configured to '6' or '7', the length is set to 32-bit (same as '5'). +- When TDM mode, must be 32-bit length to this field. + [18:16] + read-write + + + BIT_LEN8 + 8-bit + 0 + + + BIT_LEN16 + 16-bit + 1 + + + BIT_LEN18 + 18-bit + 2 + + + BIT_LEN20 + 20-bit + 3 + + + BIT_LEN24 + 24-bit + 4 + + + BIT_LEN32 + 32-bit + 5 + + + + + WORD_LEN + Word length in number of bits: + +Note: +- When this field is configured to '6' or '7', the length is set to 32-bit (same as '5'). +- Don't configure this field as beyond Channel length. + [22:20] + read-write + + + BIT_LEN8 + 8-bit + 0 + + + BIT_LEN16 + 16-bit + 1 + + + BIT_LEN18 + 18-bit + 2 + + + BIT_LEN20 + 20-bit + 3 + + + BIT_LEN24 + 24-bit + 4 + + + BIT_LEN32 + 32-bit + 5 + + + + + SCKO_POL + N/A + [24:24] + read-write + + + SCKI_POL + N/A + [25:25] + read-write + + + + + TX_WATCHDOG + Transmitter watchdog + 0x84 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WD_COUNTER + Start value of the TX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'. + [31:0] + read-write + + + + + RX_CTL + Receiver control + 0xA0 + 32 + read-write + 0x440510 + 0x3F727F8 + + + B_CLOCK_INV + Serial data capture is delayed by 0.5 SCK cycles. This bit is valid only in RX master mode. +When set to '1', the serial data will be captured 0.5 SCK cycles later than when set to '0'. + +1) RX_CTL.SCKO_POL=0 and RX_CTL.B_CLOCK_INV=0: Serial data will be captured by the SCK rising edge +2) RX_CTL.SCKO_POL=0 and RX_CTL.B_CLOCK_INV=1: Serial data will be captured by the SCK falling edge that is 0.5 SCK cycles after the SCK rising edge in 1) +3) RX_CTL.SCKO_POL=1 and RX_CTL.B_CLOCK_INV=0: Serial data will be captured by the SCK falling edge +4) RX_CTL.SCKO_POL=1 and RX_CTL.B_CLOCK_INV=1: Serial data will be captured by the SCK rising edge that is 0.5 SCK cycles after the SCK falling edge in 3) + +(Note that this is only the appearance w.r.t. SCK edge, the actual capture timing is derived from an internal clock that runs 8x the SCK frequency). The word sync (RX_WS) signal is not affected by this bit setting. +Note: When Slave mode, must be '0'. + [3:3] + read-write + + + RISING_EDGE_RX + SDI received at SCK rising edge when RX_CTL.SCKO_POL=0 + 0 + + + FALLING_EDGE_RX + SDI received at SCK falling edge when RX_CTL.SCKO_POL=0 + 1 + + + + + CH_NR + Specifies number of channels per frame: + +Note: only '2channels' is supported during Left Justfied or I2S mode. Hence software must set '1' to this field in the modes. + [6:4] + read-write + + + CH_NUM1 + 1 channel + 0 + + + CH_NUM2 + 2 channels + 1 + + + CH_NUM3 + 3 channels + 2 + + + CH_NUM4 + 4 channels + 3 + + + CH_NUM5 + 5 channels + 4 + + + CH_NUM6 + 6 channels + 5 + + + CH_NUM7 + 7 channels + 6 + + + CH_NUM8 + 8 channels + 7 + + + + + MS + Set interface in master or slave mode: + [7:7] + read-write + + + SLAVE + Slave + 0 + + + MASTER + Master + 1 + + + + + I2S_MODE + Select I2S, left-justified or TDM: + [9:8] + read-write + + + LEFT_JUSTIFIED + Left Justified + 0 + + + I2S + I2S mode + 1 + + + TDM_A + TDM mode A, the 1st Channel align to WSO +Rising Edge + 2 + + + TDM_B + TDM mode B, the 1st Channel align to WSO +Rising edge with1 SCK Delay + 3 + + + + + WS_PULSE + Set WS pulse width in TDM mode: +Note: When not TDM mode, must be '1'. + [10:10] + read-write + + + SCK_PERIOD + Pulse width is 1 SCK period + 0 + + + CH_LENGTH + Pulse width is 1 channel length + 1 + + + + + WD_EN + N/A + [13:13] + read-write + + + CH_LEN + Channel length in number of bits: + +Note: +- When this field is configured to '6' or '7', the length is set to 32-bit (same as '5'). +- When TDM mode, must be 32-bit length to this field. + [18:16] + read-write + + + BIT_LEN8 + 8-bit + 0 + + + BIT_LEN16 + 16-bit + 1 + + + BIT_LEN18 + 18-bit + 2 + + + BIT_LEN20 + 20-bit + 3 + + + BIT_LEN24 + 24-bit + 4 + + + BIT_LEN32 + 32-bit + 5 + + + + + WORD_LEN + Word length in number of bits: + +Note: +- When this field is configured to '6' or '7', the length is set to 32-bit (same as '5'). +- Don't configure this field as beyond Channel length. + [22:20] + read-write + + + BIT_LEN8 + 8-bit + 0 + + + BIT_LEN16 + 16-bit + 1 + + + BIT_LEN18 + 18-bit + 2 + + + BIT_LEN20 + 20-bit + 3 + + + BIT_LEN24 + 24-bit + 4 + + + BIT_LEN32 + 32-bit + 5 + + + + + BIT_EXTENSION + N/A + [23:23] + read-write + + + SCKO_POL + N/A + [24:24] + read-write + + + SCKI_POL + N/A + [25:25] + read-write + + + + + RX_WATCHDOG + Receiver watchdog + 0xA4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + WD_COUNTER + Start value of the RX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'. + [31:0] + read-write + + + + + TX_FIFO_CTL + TX FIFO control + 0x200 + 32 + read-write + 0x0 + 0x300FF + + + TRIGGER_LEVEL + Trigger level. When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated. + [7:0] + read-write + + + CLEAR + When '1', the TX FIFO and TX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + [16:16] + read-write + + + FREEZE + When '1', hardware reads from the TX FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. This field is used only for debugging purposes. + [17:17] + read-write + + + + + TX_FIFO_STATUS + TX FIFO status + 0x204 + 32 + read-only + 0x0 + 0xFFFF01FF + + + USED + Number of entries in the TX FIFO. The field value is in the range [0, 256]. + [8:0] + read-only + + + RD_PTR + TX FIFO read pointer: FIFO location from which a data frame is read by the hardware.This field is used only for debugging purposes. + [23:16] + read-only + + + WR_PTR + TX FIFO write pointer: FIFO location at which a new data frame is written by the host. This field is used only for debugging purposes. + [31:24] + read-only + + + + + TX_FIFO_WR + TX FIFO write + 0x208 + 32 + write-only + 0x0 + 0xFFFFFFFF + + + DATA + Data written into the TX FIFO. Behavior is similar to that of a PUSH operation. +Note: Don't access to this register while TX_FIFO_CTL.CLEAR is '1'. + [31:0] + write-only + + + + + RX_FIFO_CTL + RX FIFO control + 0x300 + 32 + read-write + 0x0 + 0x300FF + + + TRIGGER_LEVEL + Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated. +Note: software can configure up to 253 in I2S mode or Left Justified (RX_CTL.I2S_MODE = '0' or '1'). In TDM mode (RX_CTL.I2S_MODE = '2' or '3'), it can configure up to [256 - (RX_CTL.CH_NR+2)]. + [7:0] + read-write + + + CLEAR + When '1', the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. + [16:16] + read-write + + + FREEZE + When '1', hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer. This field is used only for debugging purposee. + [17:17] + read-write + + + + + RX_FIFO_STATUS + RX FIFO status + 0x304 + 32 + read-only + 0x0 + 0xFFFF01FF + + + USED + Number of entries in the RX FIFO. The field value is in the range [0, 256]. + [8:0] + read-only + + + RD_PTR + RX FIFO read pointer: FIFO location from which a data frame is read by the host. This field is used only for debugging purposes. + [23:16] + read-only + + + WR_PTR + RX FIFO write pointer: FIFO location at which a new data frame is written by the hardware. This field is used only for debugging purposes. + [31:24] + read-only + + + + + RX_FIFO_RD + RX FIFO read + 0x308 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA + Data read from the RX FIFO. Reading a data frame will remove the data frame from the RX FIFO; i.e. behavior is similar to that of a POP operation. +Notes: + - Don't access to this register while RX_FIFO_CTL.CLEAR is '1'. + - Two stored data may be not valid after CMD.RX_START is set '1'. Therefore we recommend software discard those data. + [31:0] + read-only + + + + + RX_FIFO_RD_SILENT + RX FIFO silent read + 0x30C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DATA + Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes. +Notes: + - Don't access to this register while RX_FIFO_CTL.CLEAR is '1'. + - Two stored data may be not valid after CMD.RX_START is set '1'. Therefore we recommend software discard those data. + [31:0] + read-only + + + + + INTR + Interrupt register + 0xF00 + 32 + read-write + 0x0 + 0x16D0173 + + + TX_TRIGGER + Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in TX_FIFO_CTRL. + [0:0] + read-write + + + TX_NOT_FULL + TX FIFO is not full. + [1:1] + read-write + + + TX_EMPTY + TX FIFO is empty; i.e. it has 0 entries. + [4:4] + read-write + + + TX_OVERFLOW + Attempt to write to a full TX FIFO. + [5:5] + read-write + + + TX_UNDERFLOW + Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and TX_EMPTY is '1'. + [6:6] + read-write + + + TX_WD + Triggers (sets to '1') when the Tx watchdog event occurs. + [8:8] + read-write + + + RX_TRIGGER + More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTRL. + [16:16] + read-write + + + RX_NOT_EMPTY + RX FIFO is not empty. + [18:18] + read-write + + + RX_FULL + RX FIFO is full. + [19:19] + read-write + + + RX_OVERFLOW + Attempt to write to a full RX FIFO. + [21:21] + read-write + + + RX_UNDERFLOW + Attempt to read from an empty RX FIFO. + [22:22] + read-write + + + RX_WD + Triggers (sets to '1') when the Rx watchdog event occurs. + [24:24] + read-write + + + + + INTR_SET + Interrupt set register + 0xF04 + 32 + read-write + 0x0 + 0x16D0173 + + + TX_TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + TX_NOT_FULL + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + TX_EMPTY + Write with '1' to set corresponding bit in interrupt request register. + [4:4] + read-write + + + TX_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [5:5] + read-write + + + TX_UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [6:6] + read-write + + + TX_WD + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + RX_TRIGGER + Write with '1' to set corresponding bit in interrupt request register. + [16:16] + read-write + + + RX_NOT_EMPTY + Write with '1' to set corresponding bit in interrupt request register. + [18:18] + read-write + + + RX_FULL + Write with '1' to set corresponding bit in interrupt request register. + [19:19] + read-write + + + RX_OVERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [21:21] + read-write + + + RX_UNDERFLOW + Write with '1' to set corresponding bit in interrupt request register. + [22:22] + read-write + + + RX_WD + Write with '1' to set corresponding bit in interrupt request register. + [24:24] + read-write + + + + + INTR_MASK + Interrupt mask register + 0xF08 + 32 + read-write + 0x0 + 0x16D0173 + + + TX_TRIGGER + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + TX_NOT_FULL + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + TX_EMPTY + Mask bit for corresponding bit in interrupt request register. + [4:4] + read-write + + + TX_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [5:5] + read-write + + + TX_UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [6:6] + read-write + + + TX_WD + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + RX_TRIGGER + Mask bit for corresponding bit in interrupt request register. + [16:16] + read-write + + + RX_NOT_EMPTY + Mask bit for corresponding bit in interrupt request register. + [18:18] + read-write + + + RX_FULL + Mask bit for corresponding bit in interrupt request register. + [19:19] + read-write + + + RX_OVERFLOW + Mask bit for corresponding bit in interrupt request register. + [21:21] + read-write + + + RX_UNDERFLOW + Mask bit for corresponding bit in interrupt request register. + [22:22] + read-write + + + RX_WD + Mask bit for corresponding bit in interrupt request register. + [24:24] + read-write + + + + + INTR_MASKED + Interrupt masked register + 0xF0C + 32 + read-only + 0x0 + 0x16D0173 + + + TX_TRIGGER + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + TX_NOT_FULL + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + TX_EMPTY + Logical and of corresponding request and mask bits. + [4:4] + read-only + + + TX_OVERFLOW + Logical and of corresponding request and mask bits. + [5:5] + read-only + + + TX_UNDERFLOW + Logical and of corresponding request and mask bits. + [6:6] + read-only + + + TX_WD + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + RX_TRIGGER + Logical and of corresponding request and mask bits. + [16:16] + read-only + + + RX_NOT_EMPTY + Logical and of corresponding request and mask bits. + [18:18] + read-only + + + RX_FULL + Logical and of corresponding request and mask bits. + [19:19] + read-only + + + RX_OVERFLOW + Logical and of corresponding request and mask bits. + [21:21] + read-only + + + RX_UNDERFLOW + Logical and of corresponding request and mask bits. + [22:22] + read-only + + + RX_WD + Logical and of corresponding request and mask bits. + [24:24] + read-only + + + + + + + I2S1 + 0x40801000 + + + I2S2 + 0x40802000 + + + PASS0 + Programmable Analog Subsystem for S40E + PASS + 0x40900000 + + 0 + 1048576 + registers + + + + 3 + 4096 + SAR[%s] + SAR ADC with Sequencer for S40E + 0x00000000 + + CTL + Analog control register. + 0x0 + 32 + read-write + 0x0 + 0xE00007FF + + + PWRUP_TIME + Number cycles to wait to power up after IDLE_PWRDWN. +Check the STATUS.PWRUP_BUSY flag to see if the delay is still in progress. +The power up delay is 1 us. + [7:0] + read-write + + + IDLE_PWRDWN + When idle automatically power down the analog. +After an automatic power down a new trigger will power up the analog, however it will take PWRUP_TIME cycles before the first acquisition can be started. Note that re-arbitration happens at that time, i.e. the trigger that caused the power up may not get handled first. + [8:8] + read-write + + + MSB_STRETCH + When set use 2 cycles for the Most Significant Bit (MSB) +- 0: Use 1 clock cycle for MSB +- 1: Use 2 clock cycles for MSB + [9:9] + read-write + + + HALF_LSB + When set take an extra cycle to convert the half LSB and add it to 12-bit result for Missing Code Recovery +This bit should always be set to '1' +- 0: disable half LSB conversion (not recommended) +- 1: enable half LSB conversion + [10:10] + read-write + + + SARMUX_EN + Enable the SARMUX (only valid if ENABLED=1) +- 0: SARMUX disabled (put analog in power down) +- 1: SARMUX enabled. + [29:29] + read-write + + + ADC_EN + Enable the SAR ADC and SAR sequencer (only valid if ENABLED=1) +- 0: SARADC and SARSEQ are disabled (put SARADC analog in power down and stop clocks), also clears all pending triggers. +- 1: SAR ADC and SARSEQ are enabled. +To enable ADC0 to borrow SARMUX1-3 the corresponding ADC_EN must be set to 0. + [30:30] + read-write + + + ENABLED + - 0: SAR IP disabled (put analog in power down and stop clocks), also clears all pending triggers. +- 1: SAR IP enabled. + [31:31] + read-write + + + + + DIAG_CTL + Diagnostic Reference control register. + 0x4 + 32 + read-write + 0x0 + 0x8000000F + + + DIAG_SEL + Select Diagnostic Reference function + [3:0] + read-write + + + VREFL + DiagOut = VrefL + 0 + + + VREFH_1DIV8 + DiagOut = VrefH * 1/8 + 1 + + + VREFH_2DIV8 + DiagOut = VrefH * 2/8 + 2 + + + VREFH_3DIV8 + DiagOut = VrefH * 3/8 + 3 + + + VREFH_4DIV8 + DiagOut = VrefH * 4/8 + 4 + + + VREFH_5DIV8 + DiagOut = VrefH * 5/8 + 5 + + + VREFH_6DIV8 + DiagOut = VrefH * 6/8 + 6 + + + VREFH_7DIV8 + DiagOut = VrefH * 7/8 + 7 + + + VREFH + DiagOut = VrefH + 8 + + + VREFX + DiagOut = VrefX = VrefH * 199/200 + 9 + + + VBG + DiagOut = Vbg from SRSS + 10 + + + VIN1 + DiagOut = Vin1 + 11 + + + VIN2 + DiagOut = Vin2 + 12 + + + VIN3 + DiagOut = Vin3 + 13 + + + I_SOURCE + DiagOut = Isource (10uA) + 14 + + + I_SINK + DiagOut = Isink (10uA) + 15 + + + + + DIAG_EN + Diagnostic Reference enable (only valid if ENABLED=1) +- 0: Diagnostic Reference disabled (powered down resistor ladder and current mirrors, DiagOut = Vssa). +- 1: Diagnostic Reference enabled, output signal select according to DIAG_SEL (note also EPASS_MMIO.PASS_CTL.REFBUF_EN must be set). + [31:31] + read-write + + + + + PRECOND_CTL + Preconditioning control register. + 0x10 + 32 + read-write + 0x0 + 0xF + + + PRECOND_TIME + Number ADC clock cycles that Preconditioning is done before the sample window starts. If OVERLAP_EN=0 there will be 1 additional break before make cycle between preconditioning and sampling. +Note that the minimum value is 1 (0 gives the same result as 1). + [3:0] + read-write + + + + + ANA_CAL + Current analog calibration values + 0x80 + 32 + read-write + 0x0 + 0x1F00FF + + + AOFFSET + Analog offset correction + [7:0] + read-write + + + AGAIN + Analog gain correction + [20:16] + read-write + + + + + DIG_CAL + Current digital calibration values + 0x84 + 32 + read-write + 0x0 + 0x3F0FFF + + + DOFFSET + Digital offset correction +Subtract DOFFSET from ADC output. + [11:0] + read-write + + + DGAIN + Digital gain correction. +Signed value to correct +/- 30 codes for the maximum input voltage. +Corrected = (D - DOFFSET) + ( (D - DOFFSET) * DGAIN + 0x800) / 0x1000 + [21:16] + read-write + + + + + ANA_CAL_ALT + Alternate analog calibration values + 0x90 + 32 + read-write + 0x0 + 0x1F00FF + + + AOFFSET + See corresponding ANA_CAL field + [7:0] + read-write + + + AGAIN + See corresponding ANA_CAL field + [20:16] + read-write + + + + + DIG_CAL_ALT + Alternate digital calibration values + 0x94 + 32 + read-write + 0x0 + 0x3F0FFF + + + DOFFSET + See corresponding DIG_CAL field + [11:0] + read-write + + + DGAIN + See corresponding DIG_CAL field + [21:16] + read-write + + + + + CAL_UPD_CMD + Calibration update command + 0x98 + 32 + read-write + 0x0 + 0x1 + + + UPDATE + Calibration update command: coherently copy values from alternate calibration regs to current calibration regs. +Software sets this bit when the alternate calibration values have been set with the new values. Hardware will do the calibration update as soon as the ADC is idle or a 'continuous' triggered group completes. This ensures that all acquisitions within a group scan (even if preempted) are done with the same calibration values. +This bit is cleared at the same time the calibration update is done. By clearing this bit software can cancel a requested update. +Note: if the ADC is always busy with acquisitions for non continuously triggered groups/channels then the calibration update will remain pending forever. In such a case the software can either do a non coherent update by writing directly to the current calibration registers, or software can force the ADC to idle by disabling some or all channels. +Software can check/poll this bit to see if the calibration update has taken effect. + [0:0] + read-write + + + + + TR_PEND + Trigger pending status + 0x100 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + TR_PEND + Trigger Pending. +Hardware will set this bit if a hardware trigger is received. + [31:0] + read-only + + + + + WORK_VALID + Channel working data register 'valid' bits + 0x180 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + WORK_VALID + If set the corresponding WORK register is valid, i.e. was already acquired during the current group scan. If this bit is low then either the channel is not enabled, not yet acquired or it is used as a pulse detect channel. + [31:0] + read-only + + + + + WORK_RANGE + Range detected + 0x184 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RANGE + N/A + [31:0] + read-only + + + + + WORK_RANGE_HI + Range detect above Hi flag + 0x188 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + ABOVE_HI + Out of range was detected and the value was above the Hi threshold + [31:0] + read-only + + + + + WORK_PULSE + Pulse detected + 0x18C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PULSE + N/A + [31:0] + read-only + + + + + RESULT_VALID + Channel result data register 'valid' bits + 0x1A0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + RESULT_VALID + If set the corresponding RESULT register is valid, i.e. was acquired during the preceding group scan. If this bit is low, after a group scan completed, then either the channel is not enabled or is used as a pulse detect channel. + [31:0] + read-only + + + + + RESULT_RANGE_HI + Channel Range above Hi flags + 0x1A4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + ABOVE_HI + Out of range was detected and the value was above the Hi threshold + [31:0] + read-only + + + + + STATUS + Current status of internal SAR registers (mostly for debug) + 0x200 + 32 + read-only + 0x0 + 0xE000371F + + + CUR_CHAN + current channel being acquired, only valid if BUSY. + [4:0] + read-only + + + CUR_PRIO + priority of current group/channel, only valid if BUSY. + [10:8] + read-only + + + CUR_PREEMPT_TYPE + Preempting type of current group/channel, only valid if BUSY. + [13:12] + read-only + + + DBG_FREEZE + If high then the SAR is prevented from starting a new acquisition, see DBG_FREEZE_EN. + [29:29] + read-only + + + PWRUP_BUSY + If high then the SAR is waiting for PWRUP_TIME due to IDLE_PWRDWN + [30:30] + read-only + + + BUSY + If high then the SAR is busy with a conversion. + [31:31] + read-only + + + + + AVG_STAT + Current averaging status (for debug) + 0x204 + 32 + read-only + 0x0 + 0xFF0FFFFF + + + CUR_AVG_ACCU + the current value of the averaging accumulator + [19:0] + read-only + + + CUR_AVG_CNT + the current value of the averaging counter. Note that the value shown is updated after the sample window and therefore runs ahead of the accumulator update. + [31:24] + read-only + + + + + 32 + 64 + CH[%s] + Channel structure + 0x00000800 + + TR_CTL + Trigger control. + 0x0 + 32 + read-write + 0x800 + 0x80000B77 + + + SEL + Trigger select + [2:0] + read-write + + + OFF + Use for channels in group, except the first channel + 0 + + + TCPWM + Trigger from corresponding TCPWM channel + 1 + + + GENERIC0 + Generic trigger input 0 + 2 + + + GENERIC1 + N/A + 3 + + + GENERIC2 + N/A + 4 + + + GENERIC3 + N/A + 5 + + + GENERIC4 + N/A + 6 + + + CONTINUOUS + Always triggered (also called idle), can only be used for at most 1 channel + 7 + + + + + PRIO + Channel priority: +'0': highest priority. +'1' +... +'6' +'7': lowest priority. + +Channels with the same priority constitute a priority level. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority level with pending channels is identified. Second, within this priority level, round robin arbitration is applied. Round robin arbitration (within a priority level) gives the highest priority to the lower channel indices (within the priority level). + [6:4] + read-write + + + PREEMPT_TYPE + Preemption type allow for this group + [9:8] + read-write + + + ABORT_CANCEL + Abort ongoing acquisition, do not return +Clear pending trigger for aborted group and set Cancelled interrupt. +Also 'Abort' whenever this group (do not pend the trigger) is not immediately scheduled for acquisition after a new trigger arrives. ... + 0 + + + ABORT_RESTART + Abort ongoing acquisition, up on return Restart group from first channel. + 1 + + + ABORT_RESUME + Abort ongoing acquisition, up on return Resume group from aborted channel +If averaging, discard averaging results so far and restart averaging. + 2 + + + FINISH_RESUME + Complete ongoing acquisition (including averaging), up on return Resume group from next channel + 3 + + + + + GROUP_END + 0: continue group with next channel +1: last channel of a group. + +Note that for the channel with the highest index (SAR_CH_NR) this always needs to be set + [11:11] + read-write + + + DONE_LEVEL + select level or pulse for 'tr_ch_done' trigger output +Also see POST_CTL.TR_DONE_GRP_VIO + [31:31] + read-write + + + PULSE + tr_ch_done generates a 2 cycle pulse (clk_sys), no need to read the result to clear (also no ch_overflow detection) + 0 + + + LEVEL + tr_ch_done is a level output until the result register is read (typical for DW usage, this also enables ch_overflow detection when DW is too slow) + 1 + + + + + + + SAMPLE_CTL + Sample control. + 0x4 + 32 + read-write + 0x0 + 0x0 + + + PIN_ADDR + N/A + [5:0] + read-write + + + PORT_ADDR + Select the physical port. This field is only valid for ADC0. +ADC0 can control and connect to the SARMUX of the neighboring ADC1-3. This requires the corresponding ADC to be off while the SARMUX is left on. +When ADC0 controls another SARMUX it uses the PIN_ADDR, EXT_MUX_EN/SEL of this channel to control the other SARMUX. + [7:6] + read-write + + + SARMUX0 + ADC uses it's own SARMUX + 0 + + + SARMUX1 + ADC0 uses SARMUX1 (only valid for ADC0, undefined result if used for ADC1-3) + 1 + + + SARMUX2 + ADC0 uses SARMUX2 (only valid for ADC0, undefined result if used for ADC1-3) + 2 + + + SARMUX3 + ADC0 uses SARMUX3 (only valid for ADC0, undefined result if used for ADC1-3) + 3 + + + + + EXT_MUX_SEL + External analog mux select. +This bit setting is related to EXT_MUX[x]_y on pin assignment. + 0x0: Select EXT_MUX[x]_0 pin + 0x1: Select EXT_MUX[x]_1 pin + [10:8] + read-write + + + EXT_MUX_EN + External analog mux enable. +This enable can be used as enable (chip select) for the external analog mux (this enable is not used as enable for the GPIO output driver). +This enable also prevents unnecessary toggle activity on the select signals of the external analog mux. When this enable is low EXT_MUX_SEL value will be ignored and the previous value will be maintained. +Note that an external analog mux can only be used in combination with a pin input, i.e. PIN_ADDR<32 or Vmotor. If an internal signal is selected this enable should be 0. + [11:11] + read-write + + + PRECOND_MODE + Select preconditioning mode. +Preconditioning (dis)charges the SAR sample capacitor to the selected reference voltage for PRECOND_TIME (global) cycles, a break before make cycle will be inserted before sampling starts (SAMPLE_TIME). + [13:12] + read-write + + + OFF + No preconditioning + 0 + + + VREFL + Discharge to VREFL + 1 + + + VREFH + Charge to VREFH + 2 + + + DIAG + Connect the Diagnostic reference output during preconditioning. The Diagnostic reference should be configured to output a reference voltage. +Note: this selection is mutual exclusive with using the Diagnostic reference to supply an ibias current for OVERLAP. + 3 + + + + + OVERLAP_DIAG + Select Overlap mode or SARMUX Diagnostics, in both cases the Diagnostic reference is used. +With Overlap the Diagnostic reference typically sources or sinks a small current which is connected at the same time as the analog signal being sampled. +For SARMUX Diagnostics the Diagnostic reference should provide a reference voltage which is selected at the SARMUX input instead of the normal analog signal being sampled. + [15:14] + read-write + + + OFF + No overlap or SARMUX Diagnostics + 0 + + + HALF + Sample the selected analog input for 2 SAMPLE_TIME periods. During the first period use overlap sampling, i.e. connect both the analog input and Diagnostic reference. During second period only connect the analog input. + 1 + + + FULL + Like normal sample the selected analog input for a single SAMPLE_TIME period but use overlap sampling, i.e. connect both the analog input and Diagnostic reference. + 2 + + + MUX_DIAG + Select Diagnostic reference instead of analog signal at the input of the SARMUX. This enables a functional safety check of the SARMUX analog connections. + 3 + + + + + SAMPLE_TIME + Sample time (aperture) in ADC clock cycles. Minimum is 1 (0 gives the same result as 1), minimum time needed for proper settling is at least 412ns, i.e.11 clock cycles at the max frequency of 26.7MHz. + [27:16] + read-write + + + ALT_CAL + Use alternate calibration values instead of the current calibration values. +This allows the firmware to allocate one or more channels to quietly re-calibrate the ADC in the background of regular processing. +0 = use regular calibration values (ANA/DIG_CAL) +1 = use alternate calibration values (ANA/DIG_CAL_ALT) +Note: typically calibration measurements select VrefL (PIN_ADDR=62) or VrefH (PIN_ADDR=63) + [31:31] + read-write + + + + + POST_CTL + Post processing control + 0x8 + 32 + read-write + 0x0 + 0x0 + + + POST_PROC + Post processing + [2:0] + read-write + + + NONE + No postprocessing + 0 + + + AVG + Averaging + 1 + + + AVG_RANGE + Averaging followed by Range detect + 2 + + + RANGE + Range detect + 3 + + + RANGE_PULSE + Range detect followed by pulse detect + 4 + + + RSVD0 + N/A + 5 + + + RSVD1 + N/A + 6 + + + RSVD2 + N/A + 7 + + + + + LEFT_ALIGN + Left or right align data in result[15:0]. +0: the data is right aligned in result[11:0], with sign extension to 16 bits if enabled +1: the data is left aligned in result[15:4] with the lower nibble 0. Caveat if the result was more than 12 bits (e.g. after averaging) then the bits above 12 will be discarded. + [6:6] + read-write + + + SIGN_EXT + Output data is sign extended + [7:7] + read-write + + + UNSIGNED + Default: result data is unsigned (zero extended if needed) + 0 + + + SIGNED + Result data is signed (sign extended if needed) + 1 + + + + + AVG_CNT + Either averaging count (minus 1) or Pulse positive reload value + +Averaging Count for channels that have averaging enabled. A channel will be sampled (AVG_CNT+1) = [1..256] times. +The signal will be acquired back to back (1st order accumulate and dump filter), the average result is calculated and stored and then the next enabled channel is sampled. +If more than 16 sample are taken (AVG_CNT>=16) then AVG_SHIFT must be set so that the result after shifting fits in 16 bits + +Pulse detect positive reload value PULSE_POS_RL[7:0] + [15:8] + read-write + + + SHIFT_R + Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled) + +Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here. Software has to make sure that the result fits in less than 16 bits. +Any value >12 will be treated as 12, bit [4] is always ignored. This can also be used to fit the 12-bit result in 8 bits. + +Pulse detect negative reload value PULSE_NEG_RL[4:0] + [20:16] + read-write + + + RANGE_MODE + Range detect mode + [23:22] + read-write + + + BELOW_LO + Below Low threshold (result < Lo) + 0 + + + INSIDE_RANGE + Inside range (Lo <= result < Hi) + 1 + + + ABOVE_HI + Above high threshold (Hi <= result) + 2 + + + OUTSIDE_RANGE + Outside range (result < Lo || Hi <= result) + 3 + + + + + TR_DONE_GRP_VIO + Select tr_sar_ch_done mode for last channel of a group, ignored for all other channels +Also see TR_CTL.DONE_LEVEL + [25:25] + read-write + + + DONE + Default: tr_sar_ch_done is set when the group is done + 0 + + + GRP_RANGE_VIO + tr_sar_ch_done is only set if any of the channels in the group has a Range Violation. This mode is ignored if this is not the last channel in the group. +Note that if none of the channels in the group have Range detection enabled then the trigger will never get set. + 1 + + + + + + + RANGE_CTL + Range thresholds + 0xC + 32 + read-write + 0x0 + 0x0 + + + RANGE_LO + Range detect low threshold (Lo) + [15:0] + read-write + + + RANGE_HI + Range detect high threshold (Hi) + [31:16] + read-write + + + + + INTR + Interrupt request register. + 0x10 + 32 + read-write + 0x0 + 0x707 + + + GRP_DONE + Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done. Write with '1' to clear bit. + [0:0] + read-write + + + GRP_CANCELLED + Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED. Note that it is possible that also the GRP_DONE interrupt is set. If that is the case one or more new triggers were detected while the group was already busy, i.e. triggers are too fast. Write with '1' to clear bit. + [1:1] + read-write + + + GRP_OVERFLOW + Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending. Write with '1' to clear bit. + [2:2] + read-write + + + CH_RANGE + Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. This interrupt is mutual exclusive with Pulse detect interrupt. Write with '1' to clear bit. + [8:8] + read-write + + + CH_PULSE + Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero. This interrupt is mutual exclusive with Range detect interrupt. Write with '1' to clear bit. + [9:9] + read-write + + + CH_OVERFLOW + Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup. Write with '1' to clear bit. + [10:10] + read-write + + + + + INTR_SET + Interrupt set request register + 0x14 + 32 + read-write + 0x0 + 0x707 + + + GRP_DONE_SET + Write with '1' to set corresponding bit in interrupt request register. + [0:0] + read-write + + + GRP_CANCELLED_SET + Write with '1' to set corresponding bit in interrupt request register. + [1:1] + read-write + + + GRP_OVERFLOW_SET + Write with '1' to set corresponding bit in interrupt request register. + [2:2] + read-write + + + CH_RANGE_SET + Write with '1' to set corresponding bit in interrupt request register. + [8:8] + read-write + + + CH_PULSE_SET + Write with '1' to set corresponding bit in interrupt request register. + [9:9] + read-write + + + CH_OVERFLOW_SET + Write with '1' to set corresponding bit in interrupt request register. + [10:10] + read-write + + + + + INTR_MASK + Interrupt mask register. + 0x18 + 32 + read-write + 0x0 + 0x707 + + + GRP_DONE_MASK + Mask bit for corresponding bit in interrupt request register. + [0:0] + read-write + + + GRP_CANCELLED_MASK + Mask bit for corresponding bit in interrupt request register. + [1:1] + read-write + + + GRP_OVERFLOW_MASK + Mask bit for corresponding bit in interrupt request register. + [2:2] + read-write + + + CH_RANGE_MASK + Mask bit for corresponding bit in interrupt request register. + [8:8] + read-write + + + CH_PULSE_MASK + Mask bit for corresponding bit in interrupt request register. + [9:9] + read-write + + + CH_OVERFLOW_MASK + Mask bit for corresponding bit in interrupt request register. + [10:10] + read-write + + + + + INTR_MASKED + Interrupt masked request register + 0x1C + 32 + read-only + 0x0 + 0x707 + + + GRP_DONE_MASKED + Logical and of corresponding request and mask bits. + [0:0] + read-only + + + GRP_CANCELLED_MASKED + Logical and of corresponding request and mask bits. + [1:1] + read-only + + + GRP_OVERFLOW_MASKED + Logical and of corresponding request and mask bits. + [2:2] + read-only + + + CH_RANGE_MASKED + Logical and of corresponding request and mask bits. + [8:8] + read-only + + + CH_PULSE_MASKED + Logical and of corresponding request and mask bits. + [9:9] + read-only + + + CH_OVERFLOW_MASKED + Logical and of corresponding request and mask bits. + [10:10] + read-only + + + + + WORK + Working data register + 0x20 + 32 + read-only + 0x0 + 0xF0000000 + + + WORK + SAR conversion working data of the channel. The data is written here right after sampling this channel. + [15:0] + read-only + + + ABOVE_HI_MIR + mirror bit of the corresponding ABOVE_HI bit + [28:28] + read-only + + + RANGE_MIR + mirror bit of corresponding bit in WORK_RANGE register + [29:29] + read-only + + + PULSE_MIR + mirror bit of corresponding bit in WORK_PULSE register + [30:30] + read-only + + + VALID_MIR + mirror bit of corresponding bit in WORK_VALID register + [31:31] + read-only + + + + + RESULT + Result data register + 0x24 + 32 + read-only + 0x0 + 0xF0000000 + + + RESULT + SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. + [15:0] + read-only + + + ABOVE_HI_MIR + mirror bit of the corresponding ABOVE_HI bit + [28:28] + read-only + + + RANGE_INTR_MIR + mirror bit of INTR.CH_RANGE bit + [29:29] + read-only + + + PULSE_INTR_MIR + mirror bit of INTR.CH_PULSE bit + [30:30] + read-only + + + VALID_MIR + mirror bit of the corresponding bit in RESULT_VALID register + [31:31] + read-only + + + + + GRP_STAT + Group status register + 0x28 + 32 + read-only + 0x0 + 0x10707 + + + GRP_COMPLETE + Group acquisition complete. +This is a copy of the INTR.GRP_DONE bit. + [0:0] + read-only + + + GRP_CANCELLED + Group Cancelled. +This is a copy of the INTR.GRP_CANCELLED bit. + [1:1] + read-only + + + GRP_OVERFLOW + Group Overflow. +This is a copy of the INTR.GRP_OVERFLOW bit. + [2:2] + read-only + + + CH_RANGE_COMPLETE + Channel Range complete. +This is a copy of the INTR.CH_RANGE bit. + [8:8] + read-only + + + CH_PULSE_COMPLETE + Channel Pulse complete. +This is a copy of the INTR.CH_PULSE bit. + [9:9] + read-only + + + CH_OVERFLOW + Channel Overflow. +This is a copy of the INTR.CH_OVERFLOW bit. + [10:10] + read-only + + + GRP_BUSY + Group acquisition busy. +This is a copy of the TR_PENDING bit of the first channel of the group. + [16:16] + read-only + + + + + ENABLE + Enable register + 0x38 + 32 + read-write + 0x0 + 0x1 + + + CHAN_EN + Channel enable. +- 0: the corresponding channel is disabled. Corresponding trigger will be reset immediately. +- 1: the corresponding channel is enabled. + +Note: To disable a group either stop the trigger first or begin with disabling the lowest channel first. To enable a group either start with enabling the last channel first and the first channel last, or start the trigger after all channels are enabled. If these rules are not followed the result is undefined. + [0:0] + read-write + + + + + TR_CMD + Software triggers + 0x3C + 32 + read-write + 0x0 + 0x1 + + + START + Software start trigger. When written with '1', a start trigger is generated which sets the corresponding TR_PEND bit (only if the channel is enabled). A read always returns a 0. + [0:0] + read-write + + + + + + + EPASS_MMIO + PASS top-level MMIO (Generic Triggers) + 0x000F0000 + + PASS_CTL + PASS control register + 0x0 + 32 + read-write + 0x0 + 0xF0600033 + + + SUPPLY_MON_EN_A + Supply monitor enable for AMUXBUS_A (amuxbus_a_mon) + [0:0] + read-write + + + SUPPLY_MON_LVL_A + Supply monitor level select for AMUXBUS_A + [1:1] + read-write + + + VRL + amuxbus_a_mon = VRL + 0 + + + VRH + amuxbus_a_mon = VRH + 1 + + + + + SUPPLY_MON_EN_B + Supply monitor enable for AMUXBUS_B (amuxbus_b_mon) + [4:4] + read-write + + + SUPPLY_MON_LVL_B + Supply monitor level select for AMUXBUS_B + [5:5] + read-write + + + VRL + amuxbus_b_mon = VRL + 0 + + + VRH + amuxbus_b_mon = VRH + 1 + + + + + REFBUF_MODE + Reference mode. +The reference needs to be present when using TEMP sensor or diagnostic reference (in addition to SAR.DIAG_CTL.DIAG_EN). +Note that setting this mode is not required for the ADC operation itself. + [22:21] + read-write + + + OFF + No reference + 0 + + + ON + Reference = buffered Vbg from SRSS + 1 + + + RSVD + undefined + 2 + + + BYPASS + Reference = unbuffered Vbg from SRSS + 3 + + + + + DBG_FREEZE_EN + Debug pause enable, 1 per ADC. +When set a high tr_debug_freeze trigger will prevent the scheduler from starting acquisitions on a new channel. Note that averaging for an already started channel will be completed. + [31:28] + read-write + + + + + 4 + 4 + SAR_TR_IN_SEL[%s] + per SAR generic input trigger select + 0x20 + 32 + read-write + 0x43210 + 0xFFFFF + + + IN0_SEL + Select generic trigger for SAR generic trigger input 0 + [3:0] + read-write + + + IN1_SEL + Select generic trigger for SAR generic trigger input 1 + [7:4] + read-write + + + IN2_SEL + Select generic trigger for SAR generic trigger input 2 + [11:8] + read-write + + + IN3_SEL + Select generic trigger for SAR generic trigger input 3 + [15:12] + read-write + + + IN4_SEL + Select generic trigger for SAR generic trigger input 4 + [19:16] + read-write + + + + + 4 + 4 + SAR_TR_OUT_SEL[%s] + per SAR generic output trigger select + 0x40 + 32 + read-write + 0x100 + 0x3F3F + + + OUT0_SEL + Select SAR output trigger for generic trigger output 0 +0-31: selects a tr_sar_ch_done trigger +32-63: selects a tr_sar_ch_rangvio trigger + [5:0] + read-write + + + OUT1_SEL + Select SAR output trigger for generic trigger output 1 + [13:8] + read-write + + + + + TEST_CTL + Test control bits + 0x80 + 32 + read-write + 0x0 + 0x137D + + + TS_CAL_CUR_IN + External current input switch control, for Temperature Sensor Calibration + [0:0] + read-write + + + TS_CAL_VB_OUT + Voltage Base switch control, for Temperature Sensor Calibration + [2:2] + read-write + + + TS_CAL_VE_OUT + Voltage Emitter switch control, for Temperature Sensor Calibration + [3:3] + read-write + + + TS_CAL_DIODE_EN + Diode Enable, disconnect or connect the base and collector terminal of the BJT + [4:4] + read-write + + + TS_CAL_DIODE_PNP_EN + Enable signal for PNP transistor. This transistor will be used only during calibration for accurate estimation of chip temp. +0 = Turn PNP off +1 = Configure PNP as a diode (short base and collector) + [5:5] + read-write + + + TS_CAL_VI_SEL + Select current or voltage output on 'v_temp' pin, for Temperature Sensor Calibration + [6:6] + read-write + + + CURRENT + Current is selected + 0 + + + VOLTAGE + Voltage is selected + 1 + + + + + TS_CAL_CUR_SEL + Select the current going into the BJT, for Temperature Sensor Calibration + [9:8] + read-write + + + I_1U + Select 1 uA + 0 + + + I_2U + Select 2 uA + 1 + + + I_5U + Select 5 uA + 2 + + + I_10U + Select 10 uA + 3 + + + + + TS_CAL_SPARE + Spare + [12:12] + read-write + + + + + + + + \ No newline at end of file diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/project.uvoptx b/bsp/Infineon/xmc7100d-f144k4160aa/project.uvoptx new file mode 100644 index 00000000000..0e5b71fe6d1 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/project.uvoptx @@ -0,0 +1,1524 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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+ -std=gnu99 + __RT_KERNEL_SOURCE__ + + + + + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + -std=gnu99 + __RT_KERNEL_SOURCE__ + + + + + + + + + + + klibc + + + kstdio.c + 1 + ..\..\..\src\klibc\kstdio.c + + + rt_vsscanf.c + 1 + ..\..\..\src\klibc\rt_vsscanf.c + + + kstring.c + 1 + ..\..\..\src\klibc\kstring.c + + + rt_vsnprintf_tiny.c + 1 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + kerrno.c + 1 + ..\..\..\src\klibc\kerrno.c + + + + + libcpu + + + atomic_arm.c + 1 + ..\..\..\libcpu\arm\common\atomic_arm.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m7\context_rvds.S + + + cpu_cache.c + 1 + ..\..\..\libcpu\arm\cortex-m7\cpu_cache.c + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m7\cpuport.c + + + + + Libraries + + + xmc7100_cm0p_sleep.c + 1 + packages\Infineon_cat1cm0p-latest\COMPONENT_CAT1C\COMPONENT_XMC7x_CM0P_SLEEP\xmc7100_cm0p_sleep.c + + + xmc7200_cm0p_sleep.c + 1 + packages\Infineon_cat1cm0p-latest\COMPONENT_CAT1C\COMPONENT_XMC7x_CM0P_SLEEP\xmc7200_cm0p_sleep.c + + + cyhal_xmc7100_144_teqfp.c + 1 + packages\Infineon_mtb-hal-cat1-latest\COMPONENT_CAT1C\source\pin_packages\cyhal_xmc7100_144_teqfp.c + + + cyhal_triggers_xmc7100.c + 1 + packages\Infineon_mtb-hal-cat1-latest\COMPONENT_CAT1C\source\triggers\cyhal_triggers_xmc7100.c + + + cyhal_clock.c + 1 + packages\Infineon_mtb-hal-cat1-latest\source\cyhal_clock.c + + + cyhal_dma.c + 1 + packages\Infineon_mtb-hal-cat1-latest\source\cyhal_dma.c + + + cyhal_dma_dmac.c + 1 + packages\Infineon_mtb-hal-cat1-latest\source\cyhal_dma_dmac.c + + + cyhal_dma_dw.c + 1 + packages\Infineon_mtb-hal-cat1-latest\source\cyhal_dma_dw.c + + + cyhal_gpio.c + 1 + packages\Infineon_mtb-hal-cat1-latest\source\cyhal_gpio.c + + + cyhal_hwmgr.c + 1 + packages\Infineon_mtb-hal-cat1-latest\source\cyhal_hwmgr.c + + + cyhal_interconnect.c + 1 + packages\Infineon_mtb-hal-cat1-latest\source\cyhal_interconnect.c + + + cyhal_irq_impl.c + 1 + packages\Infineon_mtb-hal-cat1-latest\source\cyhal_irq_impl.c + + + cyhal_lptimer.c + 1 + packages\Infineon_mtb-hal-cat1-latest\source\cyhal_lptimer.c + + + cyhal_scb_common.c + 1 + packages\Infineon_mtb-hal-cat1-latest\source\cyhal_scb_common.c + + + cyhal_syspm.c + 1 + packages\Infineon_mtb-hal-cat1-latest\source\cyhal_syspm.c + + + cyhal_system.c + 1 + packages\Infineon_mtb-hal-cat1-latest\source\cyhal_system.c + + + cyhal_uart.c + 1 + packages\Infineon_mtb-hal-cat1-latest\source\cyhal_uart.c + + + cyhal_utils.c + 1 + packages\Infineon_mtb-hal-cat1-latest\source\cyhal_utils.c + + + cyhal_utils_impl.c + 1 + packages\Infineon_mtb-hal-cat1-latest\source\cyhal_utils_impl.c + + + cy_device.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\devices\COMPONENT_CAT1C\source\cy_device.c + + + cy_dma.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_dma.c + + + cy_dmac.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_dmac.c + + + cy_gpio.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_gpio.c + + + cy_ipc_drv.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_ipc_drv.c + + + cy_ipc_pipe.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_ipc_pipe.c + + + cy_ipc_sema.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_ipc_sema.c + + + cy_mcwdt.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_mcwdt.c + + + cy_mcwdt_b.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_mcwdt_b.c + + + cy_prot.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_prot.c + + + cy_scb_common.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_scb_common.c + + + cy_scb_i2c.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_scb_i2c.c + + + cy_scb_uart.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_scb_uart.c + + + cy_sysclk.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_sysclk.c + + + cy_sysclk_v2.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_sysclk_v2.c + + + cy_sysint.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_sysint.c + + + cy_syslib.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_syslib.c + + + cy_syspm.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_syspm.c + + + cy_syspm_v3.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_syspm_v3.c + + + cy_systick.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_systick.c + + + cy_trigmux.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_trigmux.c + + + cy_wdt_b.c + 1 + packages\Infineon_mtb-pdl-cat1-latest\drivers\source\cy_wdt_b.c + + + cy_retarget_io.c + 1 + packages\Infineon_retarget-io-latest\cy_retarget_io.c + + + + + libs + + + cycfg_clocks.c + 1 + libs\TARGET_APP_KIT_XMC71_EVK_LITE_V2\config\GeneratedSource\cycfg_clocks.c + + + cycfg_qspi_memslot.c + 1 + libs\TARGET_APP_KIT_XMC71_EVK_LITE_V2\config\GeneratedSource\cycfg_qspi_memslot.c + + + startup_cm7.c + 1 + libs\TARGET_APP_KIT_XMC71_EVK_LITE_V2\COMPONENT_CM7\startup_cm7.c + + + system_cm7.c + 1 + libs\TARGET_APP_KIT_XMC71_EVK_LITE_V2\COMPONENT_CM7\system_cm7.c + + + cycfg_system.c + 1 + libs\TARGET_APP_KIT_XMC71_EVK_LITE_V2\config\GeneratedSource\cycfg_system.c + + + cybsp.c + 1 + libs\TARGET_APP_KIT_XMC71_EVK_LITE_V2\cybsp.c + + + cycfg_pins.c + 1 + libs\TARGET_APP_KIT_XMC71_EVK_LITE_V2\config\GeneratedSource\cycfg_pins.c + + + cycfg.c + 1 + libs\TARGET_APP_KIT_XMC71_EVK_LITE_V2\config\GeneratedSource\cycfg.c + + + + + + + + + + + + + + diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/rtconfig.h b/bsp/Infineon/xmc7100d-f144k4160aa/rtconfig.h new file mode 100644 index 00000000000..6d238ddf27d --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/rtconfig.h @@ -0,0 +1,418 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_HOOKLIST +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart4" +#define RT_VER_NUM 0x50201 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_CACHE +#define RT_USING_HW_ATOMIC +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M7 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +#define PKG_USING_INFINEON_CAT1CM0P +#define PKG_USING_INFINEON_CAT1CM0P_LATEST_VERSION +#define PKG_USING_INFINEON_CMSIS +#define PKG_USING_INFINEON_CMSIS_LATEST_VERSION +#define PKG_USING_INFINEON_CORE_LIB +#define PKG_USING_INFINEON_CORE_LIB_LATEST_VERSION +#define PKG_USING_INFINEON_MTB_HAL_CAT1 +#define PKG_USING_INFINEON_MTB_HAL_CAT1_LATEST_VERSION +#define PKG_USING_INFINEON_MTB_PDL_CAT1 +#define PKG_USING_INFINEON_MTB_PDL_CAT1_LATEST_VERSION +#define PKG_USING_INFINEON_RETARGET_IO +#define PKG_USING_INFINEON_RETARGET_IO_LATEST_VERSION +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_FAMILY_IFX +#define SOC_SERIES_IFX_XMC + +/* Hardware Drivers Config */ + +#define SOC_XMC7100D_F144K4160AA + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_USB_TO_USART +/* end of Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART2 +#define BSP_USING_UART4 +#define UART_CPU_IRQ_Number 3 +/* end of On-chip Peripheral Drivers */ +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/rtconfig.py b/bsp/Infineon/xmc7100d-f144k4160aa/rtconfig.py new file mode 100644 index 00000000000..b7c20229f53 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/rtconfig.py @@ -0,0 +1,136 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m7' +CROSS_TOOL='armclang' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armclang' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv5-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections -nostdlib -ffunction-sections -fno-strict-aliasing' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb --specs=nano.specs -ffat-lto-objects' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -Og -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n '+OBJCPY+' -O ihex rt-thread.elf rt-thread.hex\n' + + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M7.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M7.fp ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m7 ' + CFLAGS += ' -mcpu=cortex-m7 -mfpu=fpv4-d16 ' + CFLAGS += ' -mfloat-abi=softfp -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -nostdlib' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/template.uvoptx b/bsp/Infineon/xmc7100d-f144k4160aa/template.uvoptx new file mode 100644 index 00000000000..5c07bc087a2 --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/template.uvoptx @@ -0,0 +1,180 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 6 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN5 -FCFFF0 -FD28001000 -FF0CAT1C_SFLASH_TOC2 -FF1CAT1C_SFLASH_PKEY -FF2CAT1C_SFLASH_USER -FF3CAT1C_WFLASH_256 -FF4CAT1C_4160 -FL0200 -FL1C00 -FL2800 -FL340000 -FL4410000 -FS017007C00 -FS117006400 -FS217000800 -FS314000000 -FS410000000 -FP0($$Device:XMC7100D-F144K4160$Flash\CAT1C_SFLASH_TOC2.FLM) -FP1($$Device:XMC7100D-F144K4160$Flash\CAT1C_SFLASH_PKEY.FLM) -FP2($$Device:XMC7100D-F144K4160$Flash\CAT1C_SFLASH_USER.FLM) -FP3($$Device:XMC7100D-F144K4160$Flash\CAT1C_WFLASH_256.FLM) -FP4($$Device:XMC7100D-F144K4160$Flash\CAT1C_4160.FLM) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/template.uvprojx b/bsp/Infineon/xmc7100d-f144k4160aa/template.uvprojx new file mode 100644 index 00000000000..9d184e8bccc --- /dev/null +++ b/bsp/Infineon/xmc7100d-f144k4160aa/template.uvprojx @@ -0,0 +1,394 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 6090000::V6.9::.\ARMCLANG + 1 + + + XMC7100D-F144K4160:Cortex-M7-0 + Infineon + Infineon.CAT1C_DFP.1.0.0 + https://github.com/Infineon/cmsis-packs/raw/master/CAT1C_DFP/ + IRAM(0x28000000,0xC0000) IROM(0x10000000,0x410000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD28001000 -FCFFF0 -FN5 -FF0CAT1C_SFLASH_TOC2 -FS017007C00 -FL0200 -FF1CAT1C_SFLASH_PKEY -FS117006400 -FL1C00 -FF2CAT1C_SFLASH_USER -FS217000800 -FL2800 -FF3CAT1C_WFLASH_256 -FS314000000 -FL340000 -FF4CAT1C_4160 -FS410000000 -FL4410000 -FP0($$Device:XMC7100D-F144K4160$Flash\CAT1C_SFLASH_TOC2.FLM) -FP1($$Device:XMC7100D-F144K4160$Flash\CAT1C_SFLASH_PKEY.FLM) -FP2($$Device:XMC7100D-F144K4160$Flash\CAT1C_SFLASH_USER.FLM) -FP3($$Device:XMC7100D-F144K4160$Flash\CAT1C_WFLASH_256.FLM) -FP4($$Device:XMC7100D-F144K4160$Flash\CAT1C_4160.FLM)) + 0 + + + + + + + + + + + $$Device:XMC7100D-F144K4160$SVD\cat1c4m.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + rtthread + 1 + 0 + 1 + 1 + 0 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x28000000 + 0xc0000 + + + 1 + 0x10000000 + 0x410000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10000000 + 0x410000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x28000000 + 0xc0000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 1 + 0 + 3 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x10000000 + 0x08000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + +