From 9db8a00a26bcb7dc2466ac122b58c3baf6a0a5d2 Mon Sep 17 00:00:00 2001 From: koudai <786410175@qq.com> Date: Wed, 23 Apr 2025 17:23:21 +0800 Subject: [PATCH 1/6] =?UTF-8?q?=E6=B7=BB=E5=8A=A0=E4=B8=B2=E5=8F=A3v2?= =?UTF-8?q?=E9=A9=B1=E5=8A=A8=E9=80=82=E9=85=8D?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/n32/libraries/n32_drivers/drv_usart_v2.c | 1607 +++++++++++++++++ bsp/n32/libraries/n32_drivers/drv_usart_v2.h | 27 + .../.ci/attachconfig/ci.attachconfig.yml | 42 + bsp/n32/n32g45xvl-stb/board/Kconfig | 314 +++- 4 files changed, 1977 insertions(+), 13 deletions(-) create mode 100644 bsp/n32/libraries/n32_drivers/drv_usart_v2.c create mode 100644 bsp/n32/libraries/n32_drivers/drv_usart_v2.h create mode 100644 bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml diff --git a/bsp/n32/libraries/n32_drivers/drv_usart_v2.c b/bsp/n32/libraries/n32_drivers/drv_usart_v2.c new file mode 100644 index 00000000000..c58c6897e17 --- /dev/null +++ b/bsp/n32/libraries/n32_drivers/drv_usart_v2.c @@ -0,0 +1,1607 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-04-23 koudaiNEW first version + */ + +#include +#include +#include "board.h" +#include "drv_usart_v2.h" + +#ifdef RT_USING_SERIAL_V2 +#if !defined(BSP_USING_USART1) && !defined(BSP_USING_USART2) && !defined(BSP_USING_USART3) && !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1) +#error "Please define at least one BSP_USING_UARTx" +/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ +#endif + +/******************************* declare ****************************************************************************************** */ +enum +{ +#ifdef BSP_USING_USART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_USART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_USART3 + UART3_INDEX, +#endif +#ifdef BSP_USING_UART4 + UART4_INDEX, +#endif +#ifdef BSP_USING_UART5 + UART5_INDEX, +#endif +#ifdef BSP_USING_UART6 + UART6_INDEX, +#endif +#ifdef BSP_USING_UART7 + UART7_INDEX, +#endif +}; + +enum uart_afio_mode +{ +#ifdef BSP_USING_USART1 + USART1_AFIO_MODE_PA9_PA10, + USART1_AFIO_MODE_PB6_PB7, +#endif +#ifdef BSP_USING_USART2 + USART2_AFIO_MODE_PA2_PA3, + USART2_AFIO_MODE_PD5_PD6, + USART2_AFIO_MODE_PC8_PC9, + USART2_AFIO_MODE_PB4_PB5, +#endif +#ifdef BSP_USING_USART3 + USART3_AFIO_MODE_PB10_PB11, + USART3_AFIO_MODE_PC10_PC11, + USART3_AFIO_MODE_PD8_PD9, +#endif +#ifdef BSP_USING_UART4 + UART4_AFIO_MODE_PC10_PC11, + UART4_AFIO_MODE_PB2_PE7, + UART4_AFIO_MODE_PA13_PA14, + UART4_AFIO_MODE_PD0_PD1, +#endif +#ifdef BSP_USING_UART5 + UART5_AFIO_MODE_PC12_PD2, + UART5_AFIO_MODE_PB13_PB14, + UART5_AFIO_MODE_PE8_PE9, + UART5_AFIO_MODE_PB8_PB9, +#endif +#ifdef BSP_USING_UART6 + UART6_AFIO_MODE_PE2_PE3, + UART6_AFIO_MODE_PC0_PC1, + UART6_AFIO_MODE_PB0_PB1, +#endif +#ifdef BSP_USING_UART7 + UART7_AFIO_MODE_PC4_PC5, + UART7_AFIO_MODE_PC2_PC3, + UART7_AFIO_MODE_PG0_PG1, +#endif +}; + +struct DMA_HandleTypeDef +{ + DMA_ChannelType *Instance; /* DMA registers base address */ + struct UART_HandleTypeDef *Parent; + DMA_InitType Init; /* DMA initialization parameters */ + rt_uint32_t dma_rcc; + IRQn_Type dma_irq; + void (*DMA_ITC_Callback)(void); /* DMA transfer complete callback */ + void (*DMA_IE_Callback)(void); /* DMA error complete callback */ +}; + +struct UART_HandleTypeDef +{ + USART_Module *Instance; /*!< UART registers base address */ + USART_InitType Init; /*!< UART communication parameters */ + struct DMA_HandleTypeDef *HDMA_Tx; /*!< UART Tx DMA handle parameters */ + struct DMA_HandleTypeDef *HDMA_Rx; /*!< UART Rx DMA handle parameters */ +}; + +struct n32_uart_config +{ + const char *name; + USART_Module *Instance; + IRQn_Type irq_type; + GPIO_Module *tx_port; + uint16_t tx_pin; + GPIO_Module *rx_port; + uint16_t rx_pin; + unsigned char use_afio_mode; +}; + +struct n32_uart +{ + struct UART_HandleTypeDef handle; + struct n32_uart_config *config; +#ifdef RT_SERIAL_USING_DMA + struct + { + struct DMA_HandleTypeDef handle; + rt_size_t remaining_cnt; + } dma_rx; + struct + { + struct DMA_HandleTypeDef handle; + } dma_tx; +#endif + rt_uint16_t uart_dma_flag; + struct rt_serial_device serial; +}; +/********************************************************************************************************************************** */ +/******************************* funtion ****************************************************************************************** */ +static void n32_uart_mode_set(struct n32_uart_config *uart); +static void n32_uart_get_config(void); +static rt_err_t n32_configure(struct rt_serial_device *serial, struct serial_configure *cfg); +static void NVIC_Set(IRQn_Type irq, FunctionalState state); +/********************************************************************************************************************************** */ +/******************************** value ******************************************************************************************* */ +static struct n32_uart_config uart_config[] = + { +#ifdef BSP_USING_USART1 + { + .name = "usart1", +#if defined BSP_USART1_AFIO_MODE_PA9_PA10 + .use_afio_mode = USART1_AFIO_MODE_PA9_PA10, +#elif defined BSP_USART1_AFIO_MODE_PB6_PB7 + .use_afio_mode = USART1_AFIO_MODE_PB6_PB7, +#endif + }, +#endif +#ifdef BSP_USING_USART2 + { + .name = "usart2", +#if defined BSP_USART2_AFIO_MODE_PA2_PA3 + .use_afio_mode = USART2_AFIO_MODE_PA2_PA3, +#elif defined BSP_USART2_AFIO_MODE_PD5_PD6 + .use_afio_mode = USART2_AFIO_MODE_PD5_PD6, +#elif defined BSP_USART2_AFIO_MODE_PC8_PC9 + .use_afio_mode = USART2_AFIO_MODE_PC8_PC9, +#elif defined BSP_USART2_AFIO_MODE_PB4_PB5 + .use_afio_mode = USART2_AFIO_MODE_PB4_PB5, +#endif + }, +#endif +#ifdef BSP_USING_USART3 + { + .name = "usart3", +#if defined BSP_USART3_AFIO_MODE_PB10_PB11 + .use_afio_mode = USART3_AFIO_MODE_PB10_PB11, +#elif defined BSP_USART3_AFIO_MODE_PC10_PC11 + .use_afio_mode = USART3_AFIO_MODE_PC10_PC11, +#elif defined BSP_USART3_AFIO_MODE_PD8_PD9 + .use_afio_mode = USART3_AFIO_MODE_PD8_PD9, +#endif + }, +#endif +#ifdef BSP_USING_UART4 + { + .name = "uart4", +#if defined BSP_UART4_AFIO_MODE_PC10_PC11 + .use_afio_mode = UART4_AFIO_MODE_PC10_PC11, +#elif defined BSP_UART4_AFIO_MODE_PB2_PE7 + .use_afio_mode = UART4_AFIO_MODE_PB2_PE7, +#elif defined BSP_UART4_AFIO_MODE_PA13_PA14 + .use_afio_mode = UART4_AFIO_MODE_PA13_PA14, +#elif defined BSP_UART4_AFIO_MODE_PD0_PD1 + .use_afio_mode = UART4_AFIO_MODE_PD0_PD1, +#endif + }, +#endif +#ifdef BSP_USING_UART5 + { + .name = "uart5", +#if defined BSP_UART5_AFIO_MODE_PC12_PD2 + .use_afio_mode = UART5_AFIO_MODE_PC12_PD2, +#elif defined BSP_UART5_AFIO_MODE_PB13_PB14 + .use_afio_mode = UART5_AFIO_MODE_PB13_PB14, +#elif defined BSP_UART5_AFIO_MODE_PE8_PE9 + .use_afio_mode = UART5_AFIO_MODE_PE8_PE9, +#elif defined BSP_UART5_AFIO_MODE_PB8_PB9 + .use_afio_mode = UART5_AFIO_MODE_PB8_PB9, +#endif + }, +#endif +#ifdef BSP_USING_UART6 + { + .name = "uart6", +#if defined BSP_UART6_AFIO_MODE_PE2_PE3 + .use_afio_mode = UART6_AFIO_MODE_PE2_PE3, +#elif defined BSP_UART6_AFIO_MODE_PC0_PC1 + .use_afio_mode = UART6_AFIO_MODE_PC0_PC1, +#elif defined BSP_UART6_AFIO_MODE_PB0_PB1 + .use_afio_mode = UART6_AFIO_MODE_PB0_PB1, +#endif + }, +#endif +#ifdef BSP_USING_UART7 + { + .name = "uart7", +#if defined BSP_UART7_AFIO_MODE_PC4_PC5 + .use_afio_mode = UART7_AFIO_MODE_PC4_PC5, +#elif defined BSP_UART7_AFIO_MODE_PC2_PC3 + .use_afio_mode = UART7_AFIO_MODE_PC2_PC3, +#elif defined BSP_UART6_AFIO_MODE_PG0_PG1 + .use_afio_mode = UART7_AFIO_MODE_PG0_PG1, +#endif + }, +#endif +}; + +static struct n32_uart uart_obj[sizeof(uart_config) / sizeof(struct n32_uart_config)]; +/********************************************************************************************************************************** */ + +#ifdef RT_SERIAL_USING_DMA +static void n32_uart_dma_config(struct rt_serial_device *serial, rt_ubase_t flag); +#endif + +void HAL_UART_TxCpltCallback(struct UART_HandleTypeDef *huart); + +static void n32_uart_mode_set(struct n32_uart_config *uart) +{ + switch (uart->use_afio_mode) + { +#if defined BSP_USING_USART1 + /* usart1 */ + case USART1_AFIO_MODE_PA9_PA10: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_USART1 | RCC_APB2_PERIPH_GPIOA | RCC_APB2_PERIPH_AFIO, ENABLE); + GPIOInit(GPIOA, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_9); + GPIOInit(GPIOA, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_10); + NVIC_SetPriority(USART1_IRQn, 0); + /* save gpio data */ + uart->Instance = USART1; + uart->irq_type = USART1_IRQn; + uart->tx_port = GPIOA; + uart->tx_pin = GPIO_PIN_9; + uart->rx_port = GPIOA; + uart->rx_pin = GPIO_PIN_10; + break; + + case USART1_AFIO_MODE_PB6_PB7: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_USART1 | RCC_APB2_PERIPH_GPIOB | RCC_APB2_PERIPH_AFIO, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP_USART1, ENABLE); + GPIOInit(GPIOB, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_6); + GPIOInit(GPIOB, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_7); + NVIC_SetPriority(USART1_IRQn, 0); + /* save gpio data */ + uart->Instance = USART1; + uart->irq_type = USART1_IRQn; + uart->tx_port = GPIOB; + uart->tx_pin = GPIO_PIN_6; + uart->rx_port = GPIOB; + uart->rx_pin = GPIO_PIN_7; + break; +#endif + +#if defined BSP_USING_USART2 + /* usart2 */ + case USART2_AFIO_MODE_PA2_PA3: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA | RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART2, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP_USART2, DISABLE); + GPIO_ConfigPinRemap(GPIO_RMP1_USART2, DISABLE); + GPIOInit(GPIOA, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_2); + GPIOInit(GPIOA, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_3); + NVIC_SetPriority(USART2_IRQn, 0); + /* save gpio data */ + uart->Instance = USART2; + uart->irq_type = USART2_IRQn; + uart->tx_port = GPIOA; + uart->tx_pin = GPIO_PIN_2; + uart->rx_port = GPIOA; + uart->rx_pin = GPIO_PIN_3; + break; + + case USART2_AFIO_MODE_PD5_PD6: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOD | RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART2, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP_USART2, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP1_USART2, ENABLE); + GPIOInit(GPIOD, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_5); + GPIOInit(GPIOD, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_6); + NVIC_SetPriority(USART2_IRQn, 0); + /* save gpio data */ + uart->Instance = USART2; + uart->irq_type = USART2_IRQn; + uart->tx_port = GPIOD; + uart->tx_pin = GPIO_PIN_5; + uart->rx_port = GPIOD; + uart->rx_pin = GPIO_PIN_6; + break; + + case USART2_AFIO_MODE_PC8_PC9: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC | RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART2, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP_USART2, DISABLE); + GPIO_ConfigPinRemap(GPIO_RMP1_USART2, ENABLE); + GPIOInit(GPIOC, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_8); + GPIOInit(GPIOC, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_9); + NVIC_SetPriority(USART2_IRQn, 0); + /* save gpio data */ + uart->Instance = USART2; + uart->irq_type = USART2_IRQn; + uart->tx_port = GPIOC; + uart->tx_pin = GPIO_PIN_8; + uart->rx_port = GPIOC; + uart->rx_pin = GPIO_PIN_9; + break; + + case USART2_AFIO_MODE_PB4_PB5: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB | RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART2, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP_USART2, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP1_USART2, ENABLE); + GPIOInit(GPIOB, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_4); + GPIOInit(GPIOB, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_5); + NVIC_SetPriority(USART2_IRQn, 0); + /* save gpio data */ + uart->Instance = USART2; + uart->irq_type = USART2_IRQn; + uart->tx_port = GPIOB; + uart->tx_pin = GPIO_PIN_4; + uart->rx_port = GPIOB; + uart->rx_pin = GPIO_PIN_5; + break; +#endif + +#if defined BSP_USING_USART3 + /* usart3 */ + case USART3_AFIO_MODE_PB10_PB11: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB | RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART3, ENABLE); + GPIO_ConfigPinRemap(GPIO_ALL_RMP_USART3, DISABLE); + GPIOInit(GPIOB, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_10); + GPIOInit(GPIOB, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_11); + NVIC_SetPriority(USART3_IRQn, 0); + /* save gpio data */ + uart->Instance = USART3; + uart->irq_type = USART3_IRQn; + uart->tx_port = GPIOB; + uart->tx_pin = GPIO_PIN_10; + uart->rx_port = GPIOB; + uart->rx_pin = GPIO_PIN_11; + break; + + case USART3_AFIO_MODE_PC10_PC11: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC | RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART3, ENABLE); + GPIO_ConfigPinRemap(GPIO_PART_RMP_USART3, ENABLE); + GPIOInit(GPIOC, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_10); + GPIOInit(GPIOC, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_11); + NVIC_SetPriority(USART3_IRQn, 0); + /* save gpio data */ + uart->Instance = USART3; + uart->irq_type = USART3_IRQn; + uart->tx_port = GPIOC; + uart->tx_pin = GPIO_PIN_10; + uart->rx_port = GPIOC; + uart->rx_pin = GPIO_PIN_11; + break; + + case USART3_AFIO_MODE_PD8_PD9: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOD | RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART3, ENABLE); + GPIO_ConfigPinRemap(GPIO_ALL_RMP_USART3, ENABLE); + GPIOInit(GPIOD, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_8); + GPIOInit(GPIOD, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_9); + NVIC_SetPriority(USART3_IRQn, 0); + /* save gpio data */ + uart->Instance = USART3; + uart->irq_type = USART3_IRQn; + uart->tx_port = GPIOD; + uart->tx_pin = GPIO_PIN_8; + uart->rx_port = GPIOD; + uart->rx_pin = GPIO_PIN_9; + break; +#endif + +#if defined BSP_USING_UART4 + /* uart4 */ + case UART4_AFIO_MODE_PC10_PC11: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC | RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART4, ENABLE); + AFIO->RMP_CFG3 &= ~0x300000; + GPIOInit(GPIOC, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_10); + GPIOInit(GPIOC, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_11); + NVIC_SetPriority(UART4_IRQn, 0); + /* save gpio data */ + uart->Instance = UART4; + uart->irq_type = UART4_IRQn; + uart->tx_port = GPIOC; + uart->tx_pin = GPIO_PIN_10; + uart->rx_port = GPIOC; + uart->rx_pin = GPIO_PIN_11; + break; + + case UART4_AFIO_MODE_PB2_PE7: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB | RCC_APB2_PERIPH_GPIOE | RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART4, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP1_UART4, ENABLE); + GPIOInit(GPIOB, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_2); + GPIOInit(GPIOE, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_7); + NVIC_SetPriority(UART4_IRQn, 0); + /* save gpio data */ + uart->Instance = UART4; + uart->irq_type = UART4_IRQn; + uart->tx_port = GPIOB; + uart->tx_pin = GPIO_PIN_2; + uart->rx_port = GPIOE; + uart->rx_pin = GPIO_PIN_7; + break; + + case UART4_AFIO_MODE_PA13_PA14: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA | RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART4, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP2_UART4, ENABLE); + GPIOInit(GPIOA, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_13); + GPIOInit(GPIOA, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_14); + NVIC_SetPriority(UART4_IRQn, 0); + /* save gpio data */ + uart->Instance = UART4; + uart->irq_type = UART4_IRQn; + uart->tx_port = GPIOA; + uart->tx_pin = GPIO_PIN_13; + uart->rx_port = GPIOA; + uart->rx_pin = GPIO_PIN_14; + break; + + case UART4_AFIO_MODE_PD0_PD1: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOD | RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART4, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP3_UART4, ENABLE); + GPIOInit(GPIOD, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_0); + GPIOInit(GPIOD, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_1); + NVIC_SetPriority(UART4_IRQn, 0); + /* save gpio data */ + uart->Instance = UART4; + uart->irq_type = UART4_IRQn; + uart->tx_port = GPIOD; + uart->tx_pin = GPIO_PIN_0; + uart->rx_port = GPIOD; + uart->rx_pin = GPIO_PIN_1; + break; +#endif + +#if defined BSP_USING_UART5 + /* uart5 */ + case UART5_AFIO_MODE_PC12_PD2: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC | RCC_APB2_PERIPH_GPIOD | RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART5, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP3_UART5, DISABLE); + GPIOInit(GPIOC, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_12); + GPIOInit(GPIOD, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_2); + NVIC_SetPriority(UART5_IRQn, 0); + /* save gpio data */ + uart->Instance = UART5; + uart->irq_type = UART5_IRQn; + uart->tx_port = GPIOC; + uart->tx_pin = GPIO_PIN_12; + uart->rx_port = GPIOD; + uart->rx_pin = GPIO_PIN_2; + break; + + case UART5_AFIO_MODE_PB13_PB14: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB | RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART5, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP1_UART5, ENABLE); + GPIOInit(GPIOB, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_13); + GPIOInit(GPIOB, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_14); + NVIC_SetPriority(UART5_IRQn, 0); + /* save gpio data */ + uart->Instance = UART5; + uart->irq_type = UART5_IRQn; + uart->tx_port = GPIOB; + uart->tx_pin = GPIO_PIN_13; + uart->rx_port = GPIOB; + uart->rx_pin = GPIO_PIN_14; + break; + + case UART5_AFIO_MODE_PE8_PE9: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOE | RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART5, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP2_UART5, ENABLE); + GPIOInit(GPIOE, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_8); + GPIOInit(GPIOE, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_9); + NVIC_SetPriority(UART5_IRQn, 0); + /* save gpio data */ + uart->Instance = UART5; + uart->irq_type = UART5_IRQn; + uart->tx_port = GPIOE; + uart->tx_pin = GPIO_PIN_8; + uart->rx_port = GPIOE; + uart->rx_pin = GPIO_PIN_9; + break; + + case UART5_AFIO_MODE_PB8_PB9: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB | RCC_APB2_PERIPH_AFIO, ENABLE); + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART5, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP3_UART5, ENABLE); + GPIOInit(GPIOB, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_8); + GPIOInit(GPIOB, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_9); + NVIC_SetPriority(UART5_IRQn, 0); + /* save gpio data */ + uart->Instance = UART5; + uart->irq_type = UART5_IRQn; + uart->tx_port = GPIOB; + uart->tx_pin = GPIO_PIN_8; + uart->rx_port = GPIOB; + uart->rx_pin = GPIO_PIN_9; + break; +#endif + +#if defined BSP_USING_UART6 + /* uart6 */ + case UART6_AFIO_MODE_PE2_PE3: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOE | RCC_APB2_PERIPH_UART6 | RCC_APB2_PERIPH_AFIO, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP3_UART6, DISABLE); + GPIOInit(GPIOE, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_2); + GPIOInit(GPIOE, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_3); + NVIC_SetPriority(UART6_IRQn, 0); + /* save gpio data */ + uart->Instance = UART6; + uart->irq_type = UART6_IRQn; + uart->tx_port = GPIOE; + uart->tx_pin = GPIO_PIN_2; + uart->rx_port = GPIOE; + uart->rx_pin = GPIO_PIN_3; + break; + + case UART6_AFIO_MODE_PC0_PC1: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC | RCC_APB2_PERIPH_UART6 | RCC_APB2_PERIPH_AFIO, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP2_UART6, ENABLE); + GPIOInit(GPIOC, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_0); + GPIOInit(GPIOC, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_1); + NVIC_SetPriority(UART6_IRQn, 0); + /* save gpio data */ + uart->Instance = UART6; + uart->irq_type = UART6_IRQn; + uart->tx_port = GPIOC; + uart->tx_pin = GPIO_PIN_0; + uart->rx_port = GPIOC; + uart->rx_pin = GPIO_PIN_1; + break; + + case UART6_AFIO_MODE_PB0_PB1: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB | RCC_APB2_PERIPH_UART6 | RCC_APB2_PERIPH_AFIO, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP3_UART6, ENABLE); + GPIOInit(GPIOB, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_0); + GPIOInit(GPIOB, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_1); + NVIC_SetPriority(UART6_IRQn, 0); + /* save gpio data */ + uart->Instance = UART6; + uart->irq_type = UART6_IRQn; + uart->tx_port = GPIOB; + uart->tx_pin = GPIO_PIN_0; + uart->rx_port = GPIOB; + uart->rx_pin = GPIO_PIN_1; + break; +#endif + +#if defined BSP_USING_UART7 + /* uart7 */ + case UART7_AFIO_MODE_PC4_PC5: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC | RCC_APB2_PERIPH_UART7 | RCC_APB2_PERIPH_AFIO, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP3_UART7, DISABLE); + GPIOInit(GPIOC, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_4); + GPIOInit(GPIOC, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_5); + NVIC_SetPriority(UART7_IRQn, 0); + /* save gpio data */ + uart->Instance = UART7; + uart->irq_type = UART7_IRQn; + uart->tx_port = GPIOC; + uart->tx_pin = GPIO_PIN_4; + uart->rx_port = GPIOC; + uart->rx_pin = GPIO_PIN_5; + break; + + case UART7_AFIO_MODE_PC2_PC3: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC | RCC_APB2_PERIPH_UART7 | RCC_APB2_PERIPH_AFIO, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP1_UART7, ENABLE); + GPIOInit(GPIOC, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_2); + GPIOInit(GPIOC, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_3); + NVIC_SetPriority(UART7_IRQn, 0); + /* save gpio data */ + uart->Instance = UART7; + uart->irq_type = UART7_IRQn; + uart->tx_port = GPIOC; + uart->tx_pin = GPIO_PIN_2; + uart->rx_port = GPIOC; + uart->rx_pin = GPIO_PIN_3; + break; + + case UART7_AFIO_MODE_PG0_PG1: + /* enable GPIO USART AFIO clock */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOG | RCC_APB2_PERIPH_UART7 | RCC_APB2_PERIPH_AFIO, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP3_UART7, ENABLE); + GPIOInit(GPIOG, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, GPIO_PIN_0); + GPIOInit(GPIOG, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, GPIO_PIN_1); + NVIC_SetPriority(UART7_IRQn, 0); + /* save gpio data */ + uart->Instance = UART7; + uart->irq_type = UART7_IRQn; + uart->tx_port = GPIOG; + uart->tx_pin = GPIO_PIN_0; + uart->rx_port = GPIOG; + uart->rx_pin = GPIO_PIN_1; + break; +#endif + default: + break; + } +} + + +static rt_err_t n32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct n32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + uart = rt_container_of(serial, struct n32_uart, serial); + n32_uart_mode_set(uart->config); + uart->handle.Init.BaudRate = cfg->baud_rate; + + switch (cfg->data_bits) + { + case DATA_BITS_9: + uart->handle.Init.WordLength = USART_WL_9B; + break; + + default: + uart->handle.Init.WordLength = USART_WL_8B; + ; + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart->handle.Init.StopBits = USART_STPB_1; + break; + case STOP_BITS_2: + uart->handle.Init.StopBits = USART_STPB_0_5; + break; + case STOP_BITS_3: + uart->handle.Init.StopBits = USART_STPB_2; + break; + case STOP_BITS_4: + uart->handle.Init.StopBits = USART_STPB_1_5; + break; + default: + break; + } + + switch (cfg->parity) + { + case PARITY_ODD: + uart->handle.Init.Parity = USART_PE_ODD; + break; + case PARITY_EVEN: + uart->handle.Init.Parity = USART_PE_EVEN; + break; + case PARITY_NONE: + uart->handle.Init.Parity = USART_PE_NO; + break; + default: + break; + } + + switch (cfg->flowcontrol) + { + case RT_SERIAL_FLOWCONTROL_NONE: + uart->handle.Init.HardwareFlowControl = USART_HFCTRL_NONE; + break; + case RT_SERIAL_FLOWCONTROL_CTSRTS: + uart->handle.Init.HardwareFlowControl = USART_HFCTRL_RTS_CTS; + break; + default: + uart->handle.Init.HardwareFlowControl = USART_HFCTRL_NONE; + break; + } + uart->handle.Init.Mode = USART_MODE_TX | USART_MODE_RX; + USART_DeInit(uart->handle.Instance); + USART_Init(uart->handle.Instance, &uart->handle.Init); + USART_Enable(uart->handle.Instance, ENABLE); +#ifdef RT_SERIAL_USING_DMA + uart->dma_rx.remaining_cnt = serial->config.rx_bufsz; +#endif + + return RT_EOK; +} + +/** + * @brief Configures the nested vectored interrupt controller. + */ +static void NVIC_Set(IRQn_Type irq, FunctionalState state) +{ + if (state == ENABLE) + { + NVIC_SetPriority(irq, 0); + NVIC_EnableIRQ(irq); + } + else if (state == DISABLE) + { + NVIC_DisableIRQ(irq); + } +} + +static rt_err_t n32_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct n32_uart *uart; + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct n32_uart, serial); + if (ctrl_arg & (RT_DEVICE_FLAG_RX_BLOCKING | RT_DEVICE_FLAG_RX_NON_BLOCKING)) + { + if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_RX) + ctrl_arg = RT_DEVICE_FLAG_DMA_RX; + else + ctrl_arg = RT_DEVICE_FLAG_INT_RX; + } + else if (ctrl_arg & (RT_DEVICE_FLAG_TX_BLOCKING | RT_DEVICE_FLAG_TX_NON_BLOCKING)) + { + if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX) + ctrl_arg = RT_DEVICE_FLAG_DMA_TX; + else + ctrl_arg = RT_DEVICE_FLAG_INT_TX; + } + + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + // NVIC_DisableIRQ(uart->config->irq_type); + NVIC_Set(uart->config->irq_type, DISABLE); + if (ctrl_arg & RT_DEVICE_FLAG_INT_RX) + { + USART_ConfigInt(uart->handle.Instance, USART_INT_RXDNE, DISABLE); + USART_ClrFlag(uart->handle.Instance, USART_FLAG_RXDNE); + } + if (ctrl_arg & RT_DEVICE_FLAG_INT_TX) + { + USART_ConfigInt(uart->handle.Instance, USART_INT_TXDE, DISABLE); + USART_ConfigInt(uart->handle.Instance, USART_INT_TXC, DISABLE); + USART_ClrFlag(uart->handle.Instance, USART_FLAG_TXDE); + } +#ifdef RT_SERIAL_USING_DMA + if (ctrl_arg & RT_DEVICE_FLAG_DMA_RX) + { + USART_ConfigInt(uart->handle.Instance, USART_FLAG_RXDNE, DISABLE); + USART_ConfigInt(uart->handle.Instance, USART_FLAG_IDLEF, DISABLE); + USART_ClrFlag(uart->handle.Instance, USART_FLAG_RXDNE); + DMA_DeInit(uart->dma_rx.handle.Instance); + } + if (ctrl_arg & RT_DEVICE_FLAG_DMA_TX) + { + USART_ConfigInt(uart->handle.Instance, USART_INT_TXC, DISABLE); + USART_ClrFlag(uart->handle.Instance, USART_FLAG_TXC); + DMA_DeInit(uart->dma_tx.handle.Instance); + } +#endif + break; + + case RT_DEVICE_CTRL_CONFIG: +#ifdef RT_SERIAL_USING_DMA + if (ctrl_arg & (RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_DMA_TX)) + { + n32_uart_dma_config(serial, ctrl_arg); + break; + } +#endif + case RT_DEVICE_CTRL_SET_INT: + if (ctrl_arg & RT_DEVICE_FLAG_INT_RX) + { + USART_ClrFlag(uart->handle.Instance, USART_INT_RXDNE); + USART_ConfigInt(uart->handle.Instance, USART_INT_RXDNE, ENABLE); + } + if (ctrl_arg & RT_DEVICE_FLAG_INT_TX) + { + USART_ClrFlag(uart->handle.Instance, USART_INT_TXC); + USART_ConfigInt(uart->handle.Instance, USART_INT_TXC, ENABLE); + } + NVIC_Set(uart->config->irq_type, ENABLE); + break; + + case RT_DEVICE_CHECK_OPTMODE: { + if (ctrl_arg & RT_DEVICE_FLAG_DMA_TX) + return RT_SERIAL_TX_BLOCKING_NO_BUFFER; + else + return RT_SERIAL_TX_BLOCKING_BUFFER; + } + + case RT_DEVICE_CTRL_CLOSE: + DMA_EnableChannel(uart->dma_tx.handle.Instance, DISABLE); + DMA_EnableChannel(uart->dma_rx.handle.Instance, DISABLE); + USART_DeInit(uart->handle.Instance); + GPIOInit(uart->config->tx_port, GPIO_Mode_AIN, GPIO_INPUT, uart->config->tx_pin); + GPIOInit(uart->config->rx_port, GPIO_Mode_AIN, GPIO_INPUT, uart->config->rx_pin); + NVIC_DisableIRQ(uart->config->irq_type); + NVIC_ClearPendingIRQ(uart->config->irq_type); + break; + } + + return RT_EOK; +} + +static int n32_putc(struct rt_serial_device *serial, char c) +{ + struct n32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct n32_uart, serial); + /* Transmit Data */ + uart->handle.Instance->DAT = (c & (uint16_t)0x01FF); + while ((USART_GetFlagStatus(uart->handle.Instance, USART_FLAG_TXDE) == RESET)); + + return 1; +} + +static int n32_getc(struct rt_serial_device *serial) +{ + struct n32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct n32_uart, serial); + + return (int)(uart->handle.Instance->DAT & (uint16_t)0xFF); +} + +static rt_size_t n32_transmit(struct rt_serial_device *serial, + rt_uint8_t *buf, + rt_size_t size, + rt_uint32_t tx_flag) +{ + struct n32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(buf != RT_NULL); + uart = rt_container_of(serial, struct n32_uart, serial); + + if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX) + { + DMA_EnableChannel(uart->dma_tx.handle.Instance, DISABLE); + uart->dma_tx.handle.Instance->MADDR = (unsigned int)buf; + uart->dma_tx.handle.Instance->TXNUM = size & 0xFFFF; + DMA_EnableChannel(uart->dma_tx.handle.Instance, ENABLE); + + return size & 0xFFFF; + } + + return size; +} + +#ifdef RT_SERIAL_USING_DMA +static void dma_recv_isr(struct rt_serial_device *serial, rt_uint8_t isr_flag) +{ + struct n32_uart *uart; + rt_base_t level; + rt_size_t recv_len, counter; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct n32_uart, serial); + level = rt_hw_interrupt_disable(); + recv_len = 0; + counter = uart->dma_rx.handle.Instance->TXNUM; + + switch (isr_flag) + { + case UART_RX_DMA_IT_IDLE_FLAG: + if (counter <= uart->dma_rx.remaining_cnt) + recv_len = uart->dma_rx.remaining_cnt - counter; + else + recv_len = serial->config.rx_bufsz + uart->dma_rx.remaining_cnt - counter; + break; + + case UART_RX_DMA_IT_HT_FLAG: + if (counter < uart->dma_rx.remaining_cnt) + recv_len = uart->dma_rx.remaining_cnt - counter; + break; + + case UART_RX_DMA_IT_TC_FLAG: + if (counter >= uart->dma_rx.remaining_cnt) + recv_len = serial->config.rx_bufsz + uart->dma_rx.remaining_cnt - counter; + + default: + break; + } + + if (recv_len) + { + uart->dma_rx.remaining_cnt = counter; + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } + rt_hw_interrupt_enable(level); +} +#endif /* RT_SERIAL_USING_DMA */ + +/** + * Uart common interrupt process. This need add to uart ISR. + * + * @param serial serial device + */ +static void uart_isr(struct rt_serial_device *serial) +{ + struct n32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct n32_uart, serial); + /* If the Read data register is not empty and the RXNE interrupt is enabled （RDR） */ + if (USART_GetIntStatus(uart->handle.Instance, USART_INT_RXDNE) != RESET && USART_GetFlagStatus(uart->handle.Instance, USART_FLAG_RXDNE) != RESET) + { + struct rt_serial_rx_fifo *rx_fifo; + + rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + RT_ASSERT(rx_fifo != RT_NULL); + rt_ringbuffer_putchar(&(rx_fifo->rb), (rt_uint8_t)(uart->handle.Instance->DAT & (rt_uint16_t)0x01FF)); + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + } + /* If the Transmit data register is empty and the TXE interrupt enable is enabled （TDR）*/ + else if (USART_GetIntStatus(uart->handle.Instance, USART_INT_TXDE) != RESET && USART_GetFlagStatus(uart->handle.Instance, USART_FLAG_TXDE) != RESET) + { + struct rt_serial_tx_fifo *tx_fifo; + + tx_fifo = (struct rt_serial_tx_fifo *)serial->serial_tx; + RT_ASSERT(tx_fifo != RT_NULL); + rt_uint8_t put_char = 0; + if (rt_ringbuffer_getchar(&(tx_fifo->rb), &put_char)) + { + USART_SendData(uart->handle.Instance, put_char); + } + } + else if (USART_GetIntStatus(uart->handle.Instance, USART_INT_TXC) != RESET && USART_GetFlagStatus(uart->handle.Instance, USART_FLAG_TXC)) + { + /* Clear Transmission complete interrupt flag ( ISR Register ) */ + USART_ClrFlag(uart->handle.Instance, USART_INT_TXC); + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); + } + +#ifdef RT_SERIAL_USING_DMA + else if ((uart->uart_dma_flag) && (USART_GetFlagStatus(uart->handle.Instance, USART_FLAG_IDLEF) != RESET) + && (USART_GetIntStatus(uart->handle.Instance, USART_INT_IDLEF) != RESET)) + { + /* clean IDLEF flag */ + USART_ReceiveData(uart->handle.Instance); + dma_recv_isr(serial, UART_RX_DMA_IT_IDLE_FLAG); + USART_ClrIntPendingBit(uart->handle.Instance, USART_INT_TXC); + USART_ClrIntPendingBit(uart->handle.Instance, USART_INT_LINBD); + USART_ClrIntPendingBit(uart->handle.Instance, USART_INT_RXDNE); + } +#endif + else + { + if (USART_GetIntStatus(uart->handle.Instance, USART_INT_OREF) != RESET) + { + } + if (USART_GetIntStatus(uart->handle.Instance, USART_INT_NEF) != RESET) + { + } + if (USART_GetIntStatus(uart->handle.Instance, USART_INT_FEF) != RESET) + { + } + if (USART_GetIntStatus(uart->handle.Instance, USART_INT_PEF) != RESET) + { + } + if (USART_GetFlagStatus(uart->handle.Instance, USART_FLAG_TXC) != RESET) + { + USART_ClrFlag(uart->handle.Instance, USART_FLAG_TXC); + } + if (USART_GetFlagStatus(uart->handle.Instance, USART_FLAG_RXDNE) != RESET) + { + USART_ClrFlag(uart->handle.Instance, USART_FLAG_RXDNE); + } + USART_ReceiveData(uart->handle.Instance); + } +} + +/** + * @brief Handle DMA interrupt request. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +static void HAL_DMA_IRQHandler(struct DMA_HandleTypeDef *hdma) +{ + DMA_Module *dmax = RT_NULL; + + /* get offset */ + if ((unsigned int)hdma->Instance < DMA2_BASE) + { + dmax = DMA1; + } + else + { + dmax = DMA2; + } + unsigned int flag_it = dmax->INTSTS; + unsigned int channel_offset = ((unsigned int)hdma->Instance - (unsigned int)dmax - 8) / 20; + + /* Transfer Complete Interrupt management ***********************************/ + if ((flag_it & 2u << (4 * channel_offset))) + { + /* Clear the transfer complete flag */ + dmax->INTCLR |= 3u << (4 * channel_offset); + HAL_UART_TxCpltCallback(hdma->Parent); + } + /* Transfer Error Interrupt management **************************************/ + if ((flag_it & 8u << (4 * channel_offset))) + { + dmax->INTCLR |= 9u << (4 * channel_offset); + DMA_EnableChannel(hdma->Instance, DISABLE); + } +} + + +#if defined(BSP_USING_USART1) +void USART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART1_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) +void DMA1_Channel5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) +void DMA1_Channel4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */ +#endif /* BSP_USING_USART1 */ + +#if defined(BSP_USING_USART2) +void USART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART2_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) +void DMA1_Channel6_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) +void DMA1_Channel7_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */ +#endif /* BSP_USING_USART2 */ + +#if defined(BSP_USING_USART3) +void USART3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART3_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA) +void DMA1_Channel3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA) +void DMA1_Channel2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART3_TX_USING_DMA) */ +#endif /* BSP_USING_USART3*/ + +#if defined(BSP_USING_UART4) +void UART4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART4_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA) +void DMA2_Channel3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */ + +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA) +void DMA2_Channel5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART4_TX_USING_DMA) */ +#endif /* BSP_USING_UART4*/ + +#if defined(BSP_USING_UART5) +void UART5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART5_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) +void DMA1_Channel8_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) +void DMA1_Channel1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) */ +#endif /* BSP_USING_UART5*/ + +#if defined(BSP_USING_UART6) +void UART6_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART6_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) +void DMA2_Channel1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) +void DMA2_Channel2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) */ +#endif /* BSP_USING_UART6*/ + +#if defined(BSP_USING_UART7) +void UART7_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART7_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) +void DMA2_Channel6_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_rx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) +void DMA2_Channel7_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_tx.handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) */ +#endif /* BSP_USING_UART7*/ + + +static void n32_uart_get_config(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + +#ifdef BSP_USING_USART1 + uart_obj[UART1_INDEX].serial.config = config; + uart_obj[UART1_INDEX].serial.config.rx_bufsz = BSP_UART1_RX_BUFSIZE; + uart_obj[UART1_INDEX].serial.config.tx_bufsz = BSP_UART1_TX_BUFSIZE; + uart_obj[UART1_INDEX].handle.Instance = USART1; + uart_obj[UART1_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART1_RX_USING_DMA + uart_obj[UART1_INDEX].handle.HDMA_Rx = &uart_obj[UART1_INDEX].dma_rx.handle; + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_obj[UART1_INDEX].dma_rx.handle.Parent = &uart_obj[UART1_INDEX].handle; + uart_obj[UART1_INDEX].dma_rx.handle.Instance = DMA1_CH5; + uart_obj[UART1_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPCLKEN_DMA1EN; + uart_obj[UART1_INDEX].dma_rx.handle.dma_irq = DMA1_Channel5_IRQn; +#endif +#ifdef BSP_UART1_TX_USING_DMA + uart_obj[UART1_INDEX].handle.HDMA_Tx = &uart_obj[UART1_INDEX].dma_tx.handle; + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_obj[UART1_INDEX].dma_tx.handle.Parent = &uart_obj[UART1_INDEX].handle; + uart_obj[UART1_INDEX].dma_tx.handle.Instance = DMA1_CH4; + uart_obj[UART1_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPCLKEN_DMA1EN; + uart_obj[UART1_INDEX].dma_tx.handle.dma_irq = DMA1_Channel4_IRQn; +#endif +#endif + +#ifdef BSP_USING_USART2 + uart_obj[UART2_INDEX].serial.config = config; + uart_obj[UART2_INDEX].serial.config.rx_bufsz = BSP_UART2_RX_BUFSIZE; + uart_obj[UART2_INDEX].serial.config.tx_bufsz = BSP_UART2_TX_BUFSIZE; + uart_obj[UART2_INDEX].handle.Instance = USART2; + uart_obj[UART2_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART2_RX_USING_DMA + uart_obj[UART2_INDEX].handle.HDMA_Rx = &uart_obj[UART2_INDEX].dma_rx.handle; + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_obj[UART2_INDEX].dma_rx.handle.Parent = &uart_obj[UART2_INDEX].handle; + uart_obj[UART2_INDEX].dma_rx.handle.Instance = DMA1_CH6; + uart_obj[UART2_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPCLKEN_DMA1EN; + uart_obj[UART2_INDEX].dma_rx.handle.dma_irq = DMA1_Channel6_IRQn; +#endif +#ifdef BSP_UART2_TX_USING_DMA + uart_obj[UART2_INDEX].handle.HDMA_Tx = &uart_obj[UART2_INDEX].dma_tx.handle; + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_obj[UART2_INDEX].dma_tx.handle.Parent = &uart_obj[UART2_INDEX].handle; + uart_obj[UART2_INDEX].dma_tx.handle.Instance = DMA1_CH7; + uart_obj[UART2_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPCLKEN_DMA1EN; + uart_obj[UART2_INDEX].dma_tx.handle.dma_irq = DMA1_Channel7_IRQn; +#endif +#endif + +#ifdef BSP_USING_USART3 + uart_obj[UART3_INDEX].serial.config = config; + uart_obj[UART3_INDEX].serial.config.rx_bufsz = BSP_UART3_RX_BUFSIZE; + uart_obj[UART3_INDEX].serial.config.tx_bufsz = BSP_UART3_TX_BUFSIZE; + uart_obj[UART3_INDEX].handle.Instance = USART3; + uart_obj[UART3_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART3_RX_USING_DMA + uart_obj[UART3_INDEX].handle.HDMA_Rx = &uart_obj[UART3_INDEX].dma_rx.handle; + uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_obj[UART3_INDEX].dma_rx.handle.Parent = &uart_obj[UART3_INDEX].handle; + uart_obj[UART3_INDEX].dma_rx.handle.Instance = DMA1_CH3; + uart_obj[UART3_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPCLKEN_DMA1EN; + uart_obj[UART3_INDEX].dma_rx.handle.dma_irq = DMA1_Channel3_IRQn; +#endif +#ifdef BSP_UART3_TX_USING_DMA + uart_obj[UART3_INDEX].handle.HDMA_Tx = &uart_obj[UART3_INDEX].dma_tx.handle; + uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_obj[UART3_INDEX].dma_tx.handle.Parent = &uart_obj[UART3_INDEX].handle; + uart_obj[UART3_INDEX].dma_tx.handle.Instance = DMA1_CH2; + uart_obj[UART3_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPCLKEN_DMA1EN; + uart_obj[UART3_INDEX].dma_tx.handle.dma_irq = DMA1_Channel2_IRQn; +#endif +#endif + +#ifdef BSP_USING_UART4 + uart_obj[UART4_INDEX].serial.config = config; + uart_obj[UART4_INDEX].serial.config.rx_bufsz = BSP_UART4_RX_BUFSIZE; + uart_obj[UART4_INDEX].serial.config.tx_bufsz = BSP_UART4_TX_BUFSIZE; + uart_obj[UART4_INDEX].handle.Instance = UART4; + uart_obj[UART4_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART4_RX_USING_DMA + uart_obj[UART4_INDEX].handle.HDMA_Rx = &uart_obj[UART4_INDEX].dma_rx.handle; + uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_obj[UART4_INDEX].dma_rx.handle.Parent = &uart_obj[UART4_INDEX].handle; + uart_obj[UART4_INDEX].dma_rx.handle.Instance = DMA2_CH3; + uart_obj[UART4_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPCLKEN_DMA2EN; + uart_obj[UART4_INDEX].dma_rx.handle.dma_irq = DMA2_Channel3_IRQn; +#endif +#ifdef BSP_UART4_TX_USING_DMA + uart_obj[UART4_INDEX].handle.HDMA_Tx = &uart_obj[UART4_INDEX].dma_tx.handle; + uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_obj[UART4_INDEX].dma_tx.handle.Parent = &uart_obj[UART4_INDEX].handle; + uart_obj[UART4_INDEX].dma_tx.handle.Instance = DMA2_CH5; + uart_obj[UART4_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPCLKEN_DMA2EN; + uart_obj[UART4_INDEX].dma_tx.handle.dma_irq = DMA2_Channel5_IRQn; +#endif +#endif + +#ifdef BSP_USING_UART5 + uart_obj[UART5_INDEX].serial.config = config; + uart_obj[UART5_INDEX].serial.config.rx_bufsz = BSP_UART5_RX_BUFSIZE; + uart_obj[UART5_INDEX].serial.config.tx_bufsz = BSP_UART5_TX_BUFSIZE; + uart_obj[UART5_INDEX].handle.Instance = UART5; + uart_obj[UART5_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART5_RX_USING_DMA + uart_obj[UART5_INDEX].handle.HDMA_Rx = &uart_obj[UART5_INDEX].dma_rx.handle; + uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_obj[UART5_INDEX].dma_rx.handle.Parent = &uart_obj[UART5_INDEX].handle; + uart_obj[UART5_INDEX].dma_rx.handle.Instance = DMA1_CH8; + uart_obj[UART5_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPCLKEN_DMA1EN; + uart_obj[UART5_INDEX].dma_rx.handle.dma_irq = DMA1_Channel8_IRQn; +#endif +#ifdef BSP_UART5_TX_USING_DMA + uart_obj[UART5_INDEX].handle.HDMA_Tx = &uart_obj[UART5_INDEX].dma_tx.handle; + uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_obj[UART5_INDEX].dma_tx.handle.Parent = &uart_obj[UART5_INDEX].handle; + uart_obj[UART5_INDEX].dma_tx.handle.Instance = DMA1_CH1; + uart_obj[UART5_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPCLKEN_DMA1EN; + uart_obj[UART5_INDEX].dma_tx.handle.dma_irq = DMA1_Channel1_IRQn; +#endif +#endif + +#ifdef BSP_USING_UART6 + uart_obj[UART6_INDEX].serial.config = config; + uart_obj[UART6_INDEX].serial.config.rx_bufsz = BSP_UART6_RX_BUFSIZE; + uart_obj[UART6_INDEX].serial.config.tx_bufsz = BSP_UART6_TX_BUFSIZE; + uart_obj[UART6_INDEX].handle.Instance = UART6; + uart_obj[UART6_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART6_RX_USING_DMA + uart_obj[UART6_INDEX].handle.HDMA_Rx = &uart_obj[UART6_INDEX].dma_rx.handle; + uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_obj[UART6_INDEX].dma_rx.handle.Parent = &uart_obj[UART6_INDEX].handle; + uart_obj[UART6_INDEX].dma_rx.handle.Instance = DMA2_CH1; + uart_obj[UART6_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPCLKEN_DMA2EN; + uart_obj[UART6_INDEX].dma_rx.handle.dma_irq = DMA2_Channel1_IRQn; +#endif +#ifdef BSP_UART6_TX_USING_DMA + uart_obj[UART6_INDEX].handle.HDMA_Tx = &uart_obj[UART6_INDEX].dma_tx.handle; + uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_obj[UART6_INDEX].dma_tx.handle.Parent = &uart_obj[UART6_INDEX].handle; + uart_obj[UART6_INDEX].dma_tx.handle.Instance = DMA2_CH2; + uart_obj[UART6_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPCLKEN_DMA2EN; + uart_obj[UART6_INDEX].dma_tx.handle.dma_irq = DMA2_Channel2_IRQn; +#endif +#endif + +#ifdef BSP_USING_UART7 + uart_obj[UART7_INDEX].serial.config = config; + uart_obj[UART7_INDEX].serial.config.rx_bufsz = BSP_UART7_RX_BUFSIZE; + uart_obj[UART7_INDEX].serial.config.tx_bufsz = BSP_UART7_TX_BUFSIZE; + uart_obj[UART7_INDEX].handle.Instance = UART7; + uart_obj[UART7_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART7_RX_USING_DMA + uart_obj[UART7_INDEX].handle.HDMA_Rx = &uart_obj[UART7_INDEX].dma_rx.handle; + uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_obj[UART7_INDEX].dma_rx.handle.Parent = &uart_obj[UART7_INDEX].handle; + uart_obj[UART7_INDEX].dma_rx.handle.Instance = DMA2_CH6; + uart_obj[UART7_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPCLKEN_DMA2EN; + uart_obj[UART7_INDEX].dma_rx.handle.dma_irq = DMA2_Channel6_IRQn; +#endif +#ifdef BSP_UART7_TX_USING_DMA + uart_obj[UART7_INDEX].handle.HDMA_Tx = &uart_obj[UART7_INDEX].dma_tx.handle; + uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_obj[UART7_INDEX].dma_tx.handle.Parent = &uart_obj[UART7_INDEX].handle; + uart_obj[UART7_INDEX].dma_tx.handle.Instance = DMA2_CH7; + uart_obj[UART7_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPCLKEN_DMA2EN; + uart_obj[UART7_INDEX].dma_tx.handle.dma_irq = DMA2_Channel7_IRQn; +#endif +#endif +} + +#ifdef RT_SERIAL_USING_DMA +static void n32_uart_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) +{ + struct rt_serial_rx_fifo *rx_fifo; + struct DMA_HandleTypeDef *DMA_Handle; + struct n32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX); + uart = rt_container_of(serial, struct n32_uart, serial); + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + DMA_Handle = &uart->dma_rx.handle; + rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + } + else /* RT_DEVICE_FLAG_DMA_TX == flag */ + { + DMA_Handle = &uart->dma_tx.handle; + } + + RCC_EnableAHBPeriphClk(DMA_Handle->dma_rcc, ENABLE); + DMA_DeInit(DMA_Handle->Instance); + DMA_Handle->Init.PeriphAddr = (unsigned int)uart->config->Instance + 0x4; + DMA_Handle->Init.PeriphInc = DMA_PERIPH_INC_DISABLE; + DMA_Handle->Init.DMA_MemoryInc = DMA_MEM_INC_ENABLE; + DMA_Handle->Init.PeriphDataSize = DMA_PERIPH_DATA_SIZE_BYTE; + DMA_Handle->Init.MemDataSize = DMA_MemoryDataSize_Byte; + DMA_Handle->Init.Mem2Mem = DMA_M2M_DISABLE; + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + DMA_Handle->Init.Direction = DMA_DIR_PERIPH_SRC; + DMA_Handle->Init.MemAddr = (unsigned int)rx_fifo->buffer; + DMA_Handle->Init.BufSize = serial->config.rx_bufsz; + DMA_Handle->Init.CircularMode = DMA_MODE_CIRCULAR; + DMA_Handle->Init.Priority = DMA_PRIORITY_VERY_HIGH; + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + DMA_Handle->Init.Direction = DMA_DIR_PERIPH_DST; + DMA_Handle->Init.MemAddr = (unsigned int)1; + DMA_Handle->Init.BufSize = 1; + DMA_Handle->Init.CircularMode = DMA_MODE_NORMAL; + DMA_Handle->Init.Priority = DMA_PRIORITY_HIGH; + } + DMA_Init(DMA_Handle->Instance, &DMA_Handle->Init); + NVIC_Set(DMA_Handle->dma_irq, ENABLE); + /* Enable USART DMA Rx or TX request */ + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + USART_EnableDMA(uart->handle.Instance, USART_DMAREQ_RX, ENABLE); + USART_ClrFlag(uart->handle.Instance, USART_INT_IDLEF); + USART_ConfigInt(uart->handle.Instance, USART_INT_IDLEF, ENABLE); + NVIC_Set(uart->config->irq_type, ENABLE); + DMA_EnableChannel(DMA_Handle->Instance, ENABLE); + } + if (RT_DEVICE_FLAG_DMA_TX == flag) + { + USART_EnableDMA(uart->handle.Instance, USART_DMAREQ_TX, ENABLE); + DMA_ConfigInt(DMA_Handle->Instance, DMA_INT_TXC, ENABLE); + } + USART_Enable(uart->handle.Instance, ENABLE); +} + +/** + * @brief HAL_UART_TxCpltCallback + * @param huart: UART handle + * @note This callback can be called by two functions, first in UART_EndTransmit_IT when + * UART Tx complete and second in UART_DMATransmitCplt function in DMA Circular mode. + * @retval None + */ +void HAL_UART_TxCpltCallback(struct UART_HandleTypeDef *huart) +{ + RT_ASSERT(huart != NULL); + struct n32_uart *uart = (struct n32_uart *)huart; + + rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DMADONE); +} +#endif /* RT_SERIAL_USING_DMA */ + +static const struct rt_uart_ops n32_uart_ops = + { + .configure = n32_configure, + .control = n32_control, + .putc = n32_putc, + .getc = n32_getc, + .transmit = n32_transmit}; + +int rt_hw_usart_init(void) +{ + rt_err_t result = 0; + rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct n32_uart); + + n32_uart_get_config(); + for (int i = 0; i < obj_num; i++) + { + uart_obj[i].config = &uart_config[i]; + /* init UART object */ + uart_obj[i].serial.ops = &n32_uart_ops; + /* register UART device */ + result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_DMA_TX, NULL); + RT_ASSERT(result == RT_EOK); + } + + return result; +} +INIT_BOARD_EXPORT(rt_hw_usart_init); + +#endif /* RT_USING_SERIAL_V2 */ diff --git a/bsp/n32/libraries/n32_drivers/drv_usart_v2.h b/bsp/n32/libraries/n32_drivers/drv_usart_v2.h new file mode 100644 index 00000000000..e9f62606a69 --- /dev/null +++ b/bsp/n32/libraries/n32_drivers/drv_usart_v2.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-04-23 koudaiNEW first version + */ + +#ifndef __DRV_USART_V2_H__ +#define __DRV_USART_V2_H__ + +#include +#include +#include + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0U) +#define UART_RX_DMA_IT_IDLE_FLAG 0x00 +#define UART_RX_DMA_IT_HT_FLAG 0x01 +#define UART_RX_DMA_IT_TC_FLAG 0x02 + +#endif /* __DRV_USART_H__ */ diff --git a/bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml b/bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml new file mode 100644 index 00000000000..4b46ba9ba1f --- /dev/null +++ b/bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml @@ -0,0 +1,42 @@ +CONFIG_RT_USING_SERIAL_V1=n +CONFIG_RT_USING_SERIAL_V2=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_BSP_USART1_AFIO_MODE_PA9_PA10=y +CONFIG_BSP_UART1_RX_BUFSIZE=1024 +CONFIG_BSP_UART1_TX_BUFSIZE=1024 +CONFIG_BSP_USING_USART2=y +CONFIG_BSP_USART2_AFIO_MODE_PD5_PD6=y +CONFIG_BSP_UART2_RX_USING_DMA=y +CONFIG_BSP_UART2_TX_USING_DMA=y +CONFIG_BSP_UART2_RX_BUFSIZE=1024 +CONFIG_BSP_UART2_TX_BUFSIZE=1024 +CONFIG_BSP_USING_USART3=y +CONFIG_BSP_USART3_AFIO_MODE_PB10_PB11=y +CONFIG_BSP_UART3_RX_USING_DMA=y +CONFIG_BSP_UART3_TX_USING_DMA=y +CONFIG_BSP_UART3_RX_BUFSIZE=1024 +CONFIG_BSP_UART3_TX_BUFSIZE=1024 +CONFIG_BSP_USING_UART4=y +CONFIG_BSP_UART4_AFIO_MODE_PC10_PC11=y +CONFIG_BSP_UART4_RX_USING_DMA=y +CONFIG_BSP_UART4_TX_USING_DMA=y +CONFIG_BSP_UART4_RX_BUFSIZE=1024 +CONFIG_BSP_UART4_TX_BUFSIZE=1024 +CONFIG_BSP_USING_UART5=y +CONFIG_BSP_UART5_AFIO_MODE_PC12_PD2=y +CONFIG_BSP_UART5_RX_USING_DMA=y +CONFIG_BSP_UART5_TX_USING_DMA=y +CONFIG_BSP_UART5_RX_BUFSIZE=4096 +CONFIG_BSP_UART5_TX_BUFSIZE=4096 +CONFIG_BSP_USING_UART6=y +CONFIG_BSP_UART6_AFIO_MODE_PB0_PB1=y +CONFIG_BSP_UART6_RX_USING_DMA=y +CONFIG_BSP_UART6_TX_USING_DMA=y +CONFIG_BSP_UART6_RX_BUFSIZE=1024 +CONFIG_BSP_UART6_TX_BUFSIZE=1024 +CONFIG_BSP_USING_UART7=y +CONFIG_BSP_UART7_AFIO_MODE_PC4_PC5=y +CONFIG_BSP_UART7_RX_USING_DMA=y +CONFIG_BSP_UART7_TX_USING_DMA=y +CONFIG_BSP_UART7_RX_BUFSIZE=2048 +CONFIG_BSP_UART7_TX_BUFSIZE=2048 diff --git a/bsp/n32/n32g45xvl-stb/board/Kconfig b/bsp/n32/n32g45xvl-stb/board/Kconfig index c9384f7f340..185679e2387 100644 --- a/bsp/n32/n32g45xvl-stb/board/Kconfig +++ b/bsp/n32/n32g45xvl-stb/board/Kconfig @@ -27,33 +27,321 @@ menu "On-chip Peripheral Drivers" default y select RT_USING_SERIAL if BSP_USING_UART - config BSP_USING_USART1 + menuconfig BSP_USING_USART1 bool "Enable USART1" default y - - config BSP_USING_USART2 + if BSP_USING_USART1 + choice + prompt "Set usart1 afio mode" + default BSP_USART1_AFIO_MODE_PA9_PA10 + + config BSP_USART1_AFIO_MODE_PA9_PA10 + bool + prompt "PA9 PA10" + + config BSP_USART1_AFIO_MODE_PB6_PB7 + bool + prompt "PB6 PB7" + endchoice + + config BSP_UART1_RX_USING_DMA + bool "Enable usart1 rx dma" + depends on BSP_USING_USART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable usart1 tx dma" + depends on BSP_USING_USART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_RX_BUFSIZE + int "Set rx buffer size" + range 0 16384 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART1_TX_BUFSIZE + int "Set tx buffer size" + range 0 16384 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_USART2 bool "Enable USART2" default n - - config BSP_USING_USART3 + if BSP_USING_USART2 + choice + prompt "Set usart2 afio mode" + default BSP_USART2_AFIO_MODE_PA2_PA3 + + config BSP_USART2_AFIO_MODE_PA2_PA3 + bool + prompt "PA2 PA3" + + config BSP_USART2_AFIO_MODE_PD5_PD6 + bool + prompt "PD5 PD6" + + config BSP_USART2_AFIO_MODE_PC8_PC9 + bool + prompt "PC8 PC9" + + config BSP_USART2_AFIO_MODE_PB4_PB5 + bool + prompt "PB4 PB5" + endchoice + + config BSP_UART2_RX_USING_DMA + bool "Enable usart2 rx dma" + depends on BSP_USING_USART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable usart2 tx dma" + depends on BSP_USING_USART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_RX_BUFSIZE + int "Set rx buffer size" + range 256 16384 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART2_TX_BUFSIZE + int "Set tx buffer size" + range 0 16384 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_USART3 bool "Enable USART3" default n - - config BSP_USING_UART4 + if BSP_USING_USART3 + choice + prompt "Set usart3 afio mode" + default BSP_USART3_AFIO_MODE_PB10_PB11 + + config BSP_USART3_AFIO_MODE_PB10_PB11 + bool + prompt "PB10 PB11" + + config BSP_USART3_AFIO_MODE_PC10_PC11 + bool + prompt "PC10 PC11" + + config BSP_USART3_AFIO_MODE_PD8_PD9 + bool + prompt "PD8 PD9" + endchoice + + config BSP_UART3_RX_USING_DMA + bool "Enable usart3 rx dma" + depends on BSP_USING_USART3 && RT_SERIAL_USING_DMA + default n + + config BSP_UART3_TX_USING_DMA + bool "Enable usart3 tx dma" + depends on BSP_USING_USART3 && RT_SERIAL_USING_DMA + default n + + config BSP_UART3_RX_BUFSIZE + int "Set rx buffer size" + range 256 16384 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART3_TX_BUFSIZE + int "Set tx buffer size" + range 0 16384 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART4 bool "Enable UART4" default n - - config BSP_USING_UART5 + if BSP_USING_UART4 + choice + prompt "Set uart4 afio mode" + default BSP_UART4_AFIO_MODE_PC10_PC11 + + config BSP_UART4_AFIO_MODE_PC10_PC11 + bool + prompt "PC10 PC11" + + config BSP_UART4_AFIO_MODE_PB2_PE7 + bool + prompt "PB2 PE7" + + config BSP_UART4_AFIO_MODE_PA13_PA14 + bool + prompt "PA13 PA14" + + config BSP_UART4_AFIO_MODE_PD0_PD1 + bool + prompt "PD0 PD1" + endchoice + + config BSP_UART4_RX_USING_DMA + bool "Enable uart4 rx dma" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + + config BSP_UART4_TX_USING_DMA + bool "Enable uart4 tx dma" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + + config BSP_UART4_RX_BUFSIZE + int "Set rx buffer size" + range 256 16384 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART4_TX_BUFSIZE + int "Set tx buffer size" + range 0 16384 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART5 bool "Enable UART5" default n - - config BSP_USING_UART6 + if BSP_USING_UART5 + choice + prompt "Set uart5 afio mode" + default BSP_UART5_AFIO_MODE_PC12_PD2 + + config BSP_UART5_AFIO_MODE_PC12_PD2 + bool + prompt "PC12 PD2" + + config BSP_UART5_AFIO_MODE_PB13_PB14 + bool + prompt "PB13 PB14" + + config BSP_UART5_AFIO_MODE_PE8_PE9 + bool + prompt "PE8 PE9" + + config BSP_UART5_AFIO_MODE_PB8_PB9 + bool + prompt "PB8 PB9" + endchoice + + config BSP_UART5_RX_USING_DMA + bool "Enable uart5 rx dma" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + + config BSP_UART5_TX_USING_DMA + bool "Enable uart5 tx dma" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + + config BSP_UART5_RX_BUFSIZE + int "Set rx buffer size" + range 256 16384 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART5_TX_BUFSIZE + int "Set tx buffer size" + range 0 16384 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART6 bool "Enable UART6" default n - - config BSP_USING_UART7 + if BSP_USING_UART6 + choice + prompt "Set uart6 afio mode" + default BSP_UART6_AFIO_MODE_PE2_PE3 + + config BSP_UART6_AFIO_MODE_PE2_PE3 + bool + prompt "PE2 PE3" + + config BSP_UART6_AFIO_MODE_PC0_PC1 + bool + prompt "PC0 PC1" + + config BSP_UART6_AFIO_MODE_PB0_PB1 + bool + prompt "PB0 PB1" + endchoice + + config BSP_UART6_RX_USING_DMA + bool "Enable uart6 rx dma" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_TX_USING_DMA + bool "Enable uart6 tx dma" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_RX_BUFSIZE + int "Set rx buffer size" + range 256 16384 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART6_TX_BUFSIZE + int "Set tx buffer size" + range 0 16384 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART7 bool "Enable UART7" default n + if BSP_USING_UART7 + choice + prompt "Set uart7 afio mode" + default BSP_UART7_AFIO_MODE_PC4_PC5 + + config BSP_UART7_AFIO_MODE_PC4_PC5 + bool + prompt "PC4 PC5" + + config BSP_UART7_AFIO_MODE_PC2_PC3 + bool + prompt "PC2 PC3" + + config BSP_UART6_AFIO_MODE_PG0_PG1 + bool + prompt "PG0 PG1" + endchoice + + config BSP_UART7_RX_USING_DMA + bool "Enable uart7 rx dma" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + + config BSP_UART7_TX_USING_DMA + bool "Enable uart7 tx dma" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + + config BSP_UART7_RX_BUFSIZE + int "Set rx buffer size" + range 256 16384 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART7_TX_BUFSIZE + int "Set tx buffer size" + range 0 16384 + depends on RT_USING_SERIAL_V2 + default 0 + endif endif menuconfig BSP_USING_SPI From 89d3879d713bd07cac6c0d2f4551dc2c5725c580 Mon Sep 17 00:00:00 2001 From: koudai <786410175@qq.com> Date: Thu, 24 Apr 2025 09:06:09 +0800 Subject: [PATCH 2/6] =?UTF-8?q?=E4=BF=AE=E6=94=B9N32G45XVL=20yml?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../.ci/attachconfig/ci.attachconfig.yml | 86 ++++++++++--------- bsp/n32/n32g45xvl-stb/defconfig | 13 +++ 2 files changed, 57 insertions(+), 42 deletions(-) create mode 100644 bsp/n32/n32g45xvl-stb/defconfig diff --git a/bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml b/bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml index 4b46ba9ba1f..4970808fdc7 100644 --- a/bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml @@ -1,42 +1,44 @@ -CONFIG_RT_USING_SERIAL_V1=n -CONFIG_RT_USING_SERIAL_V2=y -CONFIG_RT_SERIAL_USING_DMA=y -CONFIG_BSP_USART1_AFIO_MODE_PA9_PA10=y -CONFIG_BSP_UART1_RX_BUFSIZE=1024 -CONFIG_BSP_UART1_TX_BUFSIZE=1024 -CONFIG_BSP_USING_USART2=y -CONFIG_BSP_USART2_AFIO_MODE_PD5_PD6=y -CONFIG_BSP_UART2_RX_USING_DMA=y -CONFIG_BSP_UART2_TX_USING_DMA=y -CONFIG_BSP_UART2_RX_BUFSIZE=1024 -CONFIG_BSP_UART2_TX_BUFSIZE=1024 -CONFIG_BSP_USING_USART3=y -CONFIG_BSP_USART3_AFIO_MODE_PB10_PB11=y -CONFIG_BSP_UART3_RX_USING_DMA=y -CONFIG_BSP_UART3_TX_USING_DMA=y -CONFIG_BSP_UART3_RX_BUFSIZE=1024 -CONFIG_BSP_UART3_TX_BUFSIZE=1024 -CONFIG_BSP_USING_UART4=y -CONFIG_BSP_UART4_AFIO_MODE_PC10_PC11=y -CONFIG_BSP_UART4_RX_USING_DMA=y -CONFIG_BSP_UART4_TX_USING_DMA=y -CONFIG_BSP_UART4_RX_BUFSIZE=1024 -CONFIG_BSP_UART4_TX_BUFSIZE=1024 -CONFIG_BSP_USING_UART5=y -CONFIG_BSP_UART5_AFIO_MODE_PC12_PD2=y -CONFIG_BSP_UART5_RX_USING_DMA=y -CONFIG_BSP_UART5_TX_USING_DMA=y -CONFIG_BSP_UART5_RX_BUFSIZE=4096 -CONFIG_BSP_UART5_TX_BUFSIZE=4096 -CONFIG_BSP_USING_UART6=y -CONFIG_BSP_UART6_AFIO_MODE_PB0_PB1=y -CONFIG_BSP_UART6_RX_USING_DMA=y -CONFIG_BSP_UART6_TX_USING_DMA=y -CONFIG_BSP_UART6_RX_BUFSIZE=1024 -CONFIG_BSP_UART6_TX_BUFSIZE=1024 -CONFIG_BSP_USING_UART7=y -CONFIG_BSP_UART7_AFIO_MODE_PC4_PC5=y -CONFIG_BSP_UART7_RX_USING_DMA=y -CONFIG_BSP_UART7_TX_USING_DMA=y -CONFIG_BSP_UART7_RX_BUFSIZE=2048 -CONFIG_BSP_UART7_TX_BUFSIZE=2048 +peripheral.UARTv2: + kconfig: + - CONFIG_RT_USING_SERIAL_V1=n + - CONFIG_RT_USING_SERIAL_V2=y + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_USART1_AFIO_MODE_PA9_PA10=y + - CONFIG_BSP_UART1_RX_BUFSIZE=1024 + - CONFIG_BSP_UART1_TX_BUFSIZE=1024 + - CONFIG_BSP_USING_USART2=y + - CONFIG_BSP_USART2_AFIO_MODE_PD5_PD6=y + - CONFIG_BSP_UART2_RX_USING_DMA=y + - CONFIG_BSP_UART2_TX_USING_DMA=y + - CONFIG_BSP_UART2_RX_BUFSIZE=1024 + - CONFIG_BSP_UART2_TX_BUFSIZE=1024 + - CONFIG_BSP_USING_USART3=y + - CONFIG_BSP_USART3_AFIO_MODE_PB10_PB11=y + - CONFIG_BSP_UART3_RX_USING_DMA=y + - CONFIG_BSP_UART3_TX_USING_DMA=y + - CONFIG_BSP_UART3_RX_BUFSIZE=1024 + - CONFIG_BSP_UART3_TX_BUFSIZE=1024 + - CONFIG_BSP_USING_UART4=y + - CONFIG_BSP_UART4_AFIO_MODE_PC10_PC11=y + - CONFIG_BSP_UART4_RX_USING_DMA=y + - CONFIG_BSP_UART4_TX_USING_DMA=y + - CONFIG_BSP_UART4_RX_BUFSIZE=1024 + - CONFIG_BSP_UART4_TX_BUFSIZE=1024 + - CONFIG_BSP_USING_UART5=y + - CONFIG_BSP_UART5_AFIO_MODE_PC12_PD2=y + - CONFIG_BSP_UART5_RX_USING_DMA=y + - CONFIG_BSP_UART5_TX_USING_DMA=y + - CONFIG_BSP_UART5_RX_BUFSIZE=4096 + - CONFIG_BSP_UART5_TX_BUFSIZE=4096 + - CONFIG_BSP_USING_UART6=y + - CONFIG_BSP_UART6_AFIO_MODE_PB0_PB1=y + - CONFIG_BSP_UART6_RX_USING_DMA=y + - CONFIG_BSP_UART6_TX_USING_DMA=y + - CONFIG_BSP_UART6_RX_BUFSIZE=1024 + - CONFIG_BSP_UART6_TX_BUFSIZE=1024 + - CONFIG_BSP_USING_UART7=y + - CONFIG_BSP_UART7_AFIO_MODE_PC4_PC5=y + - CONFIG_BSP_UART7_RX_USING_DMA=y + - CONFIG_BSP_UART7_TX_USING_DMA=y + - CONFIG_BSP_UART7_RX_BUFSIZE=2048 + - CONFIG_BSP_UART7_TX_BUFSIZE=2048 diff --git a/bsp/n32/n32g45xvl-stb/defconfig b/bsp/n32/n32g45xvl-stb/defconfig new file mode 100644 index 00000000000..1e7baf028e3 --- /dev/null +++ b/bsp/n32/n32g45xvl-stb/defconfig @@ -0,0 +1,13 @@ +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_CONSOLE_DEVICE_NAME="usart1" +# CONFIG_RT_USING_DFS is not set +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_USING_CAN=y +CONFIG_RT_USING_I2C=y +CONFIG_RT_USING_ADC=y +CONFIG_RT_USING_DAC=y +CONFIG_RT_USING_RTC=y +CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_WDT=y +CONFIG_RT_USING_HWTIMER=y From 9ccb9559f17299f971afd81e69ad87718157fa66 Mon Sep 17 00:00:00 2001 From: koudai <786410175@qq.com> Date: Thu, 24 Apr 2025 11:01:51 +0800 Subject: [PATCH 3/6] =?UTF-8?q?[bsp]=E8=A1=A5=E5=85=85=E5=A4=B4=E6=96=87?= =?UTF-8?q?=E4=BB=B6=EF=BC=8C=E5=B7=A5=E7=A8=8B=E8=84=9A=E6=9C=AC=E5=A2=9E?= =?UTF-8?q?=E5=8A=A0dma=E6=96=87=E4=BB=B6=EF=BC=8C=E4=BF=AE=E6=94=B9yml?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../N32G45x_Firmware_Library/SConscript | 2 + bsp/n32/libraries/n32_drivers/drv_usart_v2.c | 55 +++- .../.ci/attachconfig/ci.attachconfig.yml | 244 +++++++++++++++--- bsp/n32/n32g45xvl-stb/defconfig | 13 - 4 files changed, 259 insertions(+), 55 deletions(-) delete mode 100644 bsp/n32/n32g45xvl-stb/defconfig diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/SConscript b/bsp/n32/libraries/N32G45x_Firmware_Library/SConscript index f3bce0e0304..fc0934459fa 100644 --- a/bsp/n32/libraries/N32G45x_Firmware_Library/SConscript +++ b/bsp/n32/libraries/N32G45x_Firmware_Library/SConscript @@ -17,6 +17,8 @@ n32g45x_std_periph_driver/src/misc.c if GetDepend(['RT_USING_SERIAL']): src += ['n32g45x_std_periph_driver/src/n32g45x_usart.c'] + if GetDepend(['RT_SERIAL_USING_DMA']): + src += ['n32g45x_std_periph_driver/src/n32g45x_dma.c'] if GetDepend(['RT_USING_I2C']): src += ['n32g45x_std_periph_driver/src/n32g45x_i2c.c'] diff --git a/bsp/n32/libraries/n32_drivers/drv_usart_v2.c b/bsp/n32/libraries/n32_drivers/drv_usart_v2.c index c58c6897e17..7f70b2c7192 100644 --- a/bsp/n32/libraries/n32_drivers/drv_usart_v2.c +++ b/bsp/n32/libraries/n32_drivers/drv_usart_v2.c @@ -11,6 +11,8 @@ #include #include #include "board.h" +#include "n32g45x_gpio.h" +#include "n32g45x_dma.h" #include "drv_usart_v2.h" #ifdef RT_USING_SERIAL_V2 @@ -141,6 +143,11 @@ static void n32_uart_mode_set(struct n32_uart_config *uart); static void n32_uart_get_config(void); static rt_err_t n32_configure(struct rt_serial_device *serial, struct serial_configure *cfg); static void NVIC_Set(IRQn_Type irq, FunctionalState state); +#ifdef RT_SERIAL_USING_DMA +static void n32_uart_dma_config(struct rt_serial_device *serial, rt_ubase_t flag); +#endif +void HAL_UART_TxCpltCallback(struct UART_HandleTypeDef *huart); +static void GPIOInit(GPIO_Module* GPIOx, GPIO_ModeType mode, GPIO_SpeedType speed, uint16_t Pin); /********************************************************************************************************************************** */ /******************************** value ******************************************************************************************* */ static struct n32_uart_config uart_config[] = @@ -238,11 +245,49 @@ static struct n32_uart_config uart_config[] = static struct n32_uart uart_obj[sizeof(uart_config) / sizeof(struct n32_uart_config)]; /********************************************************************************************************************************** */ -#ifdef RT_SERIAL_USING_DMA -static void n32_uart_dma_config(struct rt_serial_device *serial, rt_ubase_t flag); -#endif - -void HAL_UART_TxCpltCallback(struct UART_HandleTypeDef *huart); +static void GPIOInit(GPIO_Module* GPIOx, GPIO_ModeType mode, GPIO_SpeedType speed, uint16_t Pin) +{ + GPIO_InitType GPIO_InitStructure; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + /* Enable the GPIO Clock */ + if (GPIOx == GPIOA) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); + } + else if (GPIOx == GPIOB) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE); + } + else if (GPIOx == GPIOC) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE); + } + else if (GPIOx == GPIOD) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOD, ENABLE); + } + else if (GPIOx == GPIOE) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOE, ENABLE); + } + else if (GPIOx == GPIOF) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOF, ENABLE); + } + else + { + if (GPIOx == GPIOG) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOG, ENABLE); + } + } + /* Configure the GPIO pin */ + GPIO_InitStructure.Pin = Pin; + GPIO_InitStructure.GPIO_Mode = mode; + GPIO_InitStructure.GPIO_Speed = speed; + GPIO_InitPeripheral(GPIOx, &GPIO_InitStructure); +} static void n32_uart_mode_set(struct n32_uart_config *uart) { diff --git a/bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml b/bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml index 4970808fdc7..6a21e471c9b 100644 --- a/bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml @@ -1,44 +1,214 @@ -peripheral.UARTv2: +scons.args: &scons + scons_arg: + - '--strict' +# ------ nano CI ------ +nano: + <<: *scons + kconfig: + - CONFIG_RT_USING_NANO=y +# ------ kernel CI ------ +kernel.klibc-stdlib: + <<: *scons + kconfig: + - CONFIG_RT_KLIBC_USING_STDLIB=y + - CONFIG_RT_KLIBC_USING_STDLIB_MEMORY=y +kernel.klibc-tinysize: + <<: *scons + kconfig: + - CONFIG_RT_KLIBC_USING_TINY_SIZE=y +kernel.klibc-vsnprintf-std: + <<: *scons + kconfig: + - CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y + - CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG=y + - CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y + - CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y + - CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y + - CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER=y + - CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS=y +# ------ online-packages CI ------ +online-packages.iot.at_devices: + <<: *scons + kconfig: + - CONFIG_PKG_USING_AT_DEVICE=y + # Quectel M26/MC20 + - CONFIG_AT_DEVICE_USING_M26=y + - CONFIG_AT_DEVICE_M26_INIT_ASYN=y + # Quectel EC20 + - CONFIG_AT_DEVICE_USING_EC20=y + - CONFIG_AT_DEVICE_EC20_INIT_ASYN=y + # Espressif ESP32 + - CONFIG_AT_DEVICE_USING_ESP32=y + - CONFIG_AT_DEVICE_ESP32_INIT_ASYN=y + # Espressif ESP8266 + - CONFIG_AT_DEVICE_USING_ESP8266=y + - CONFIG_AT_DEVICE_ESP8266_INIT_ASYN=y + # Realthread RW007 + - CONFIG_AT_DEVICE_USING_RW007=y + - CONFIG_AT_DEVICE_RW007_INIT_ASYN=y + # SIMCom SIM800C + - CONFIG_AT_DEVICE_USING_SIM800C=y + - CONFIG_AT_DEVICE_SIM800C_INIT_ASYN=y + # SIMCom SIM76XX + - CONFIG_AT_DEVICE_USING_SIM76XX=y + - CONFIG_AT_DEVICE_SIM76XX_INIT_ASYN=y + # Notion MW31 + - CONFIG_AT_DEVICE_USING_MW31=y + - CONFIG_AT_DEVICE_MW31_INIT_ASYN=y + # WinnerMicro W60X + - CONFIG_AT_DEVICE_USING_W60X=y + - CONFIG_AT_DEVICE_W60X_INIT_ASYN=y + # Ai-Think A9G + - CONFIG_AT_DEVICE_USING_A9G=y + - CONFIG_AT_DEVICE_A9G_INIT_ASYN=y + # Quectel BC26 + - CONFIG_AT_DEVICE_USING_BC26=y + - CONFIG_AT_DEVICE_BC26_INIT_ASYN=y + # luat Air720 + - CONFIG_AT_DEVICE_USING_AIR720=y + - CONFIG_AT_DEVICE_AIR720_INIT_ASYN=y + # Gosuncn ME3616 + - CONFIG_AT_DEVICE_USING_ME3616=y + - CONFIG_AT_DEVICE_ME3616_INIT_ASYN=y + # ChinaMobile M6315 + - CONFIG_AT_DEVICE_USING_M6315=y + - CONFIG_AT_DEVICE_M6315_INIT_ASYN=y + # Quectel BC28 + - CONFIG_AT_DEVICE_USING_BC28=y + - CONFIG_AT_DEVICE_BC28_INIT_ASYN=y + # Quectel EC200T/EC200S + - CONFIG_AT_DEVICE_USING_EC200X=y + - CONFIG_AT_DEVICE_EC200X_INIT_ASYN=y + # Neoway N21 + - CONFIG_AT_DEVICE_USING_N21=y + - CONFIG_AT_DEVICE_N21_INIT_ASYN=y + # Neoway N58 + - CONFIG_AT_DEVICE_USING_N58=y + - CONFIG_AT_DEVICE_N58_INIT_ASYN=y + # ChinaMobile M5311 + - CONFIG_AT_DEVICE_USING_M5311=y + - CONFIG_AT_DEVICE_M5311_INIT_ASYN=y + # Fibocom L610 + - CONFIG_AT_DEVICE_USING_L610=y + - CONFIG_AT_DEVICE_L610_INIT_ASYN=y + # Neoway N720 + - CONFIG_AT_DEVICE_USING_N720=y + - CONFIG_AT_DEVICE_N720_INIT_ASYN=y + # Gosuncn ML305 + - CONFIG_AT_DEVICE_USING_ML305=y + - CONFIG_AT_DEVICE_ML305_INIT_ASYN=y +online-packages.misc.misc: + <<: *scons + kconfig: + - CONFIG_PKG_USING_MULTIBUTTON=y +online-packages.misc.vi: + <<: *scons + kconfig: + - CONFIG_PKG_USING_VI=y + # - CONFIG_VI_ENABLE_8BIT=y + - CONFIG_VI_ENABLE_COLON=y + - CONFIG_VI_ENABLE_COLON_EXPAND=y + - CONFIG_VI_ENABLE_YANKMARK=y + - CONFIG_VI_ENABLE_SEARCH=y + - CONFIG_VI_ENABLE_DOT_CMD=y + - CONFIG_VI_ENABLE_READONLY=y + - CONFIG_VI_ENABLE_SETOPTS=y + - CONFIG_VI_ENABLE_SET=y + - CONFIG_VI_ENABLE_WIN_RESIZE=y + - CONFIG_VI_ENABLE_VI_ASK_TERMINAL=y + - CONFIG_VI_ENABLE_UNDO=y + - CONFIG_VI_ENABLE_UNDO_QUEUE=y + - CONFIG_VI_ENABLE_VERBOSE_STATUS=y +online-packages.multimedia.lvgl-v8.3-latest: + <<: *scons + kconfig: + - CONFIG_BSP_USING_LVGL=y + - CONFIG_BSP_USING_LVGL_DEMO=y + - CONFIG_PKG_LVGL_USING_V8_3_LATEST=y +online-packages.multimedia.lvgl-v8.3.11: + <<: *scons + kconfig: + - CONFIG_BSP_USING_LVGL=y + - CONFIG_BSP_USING_LVGL_DEMO=y + - CONFIG_PKG_LVGL_USING_V080311=y +online-packages.multimedia.lvgl-v8.4-latest: + <<: *scons + kconfig: + - CONFIG_BSP_USING_LVGL=y + - CONFIG_BSP_USING_LVGL_DEMO=y + - CONFIG_PKG_LVGL_USING_V8_4_LATEST=y +online-packages.system.enhanced-kservice: + <<: *scons + kconfig: + - CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE=y + - CONFIG_PKG_USING_RT_MEMCPY_CM=y +online-packages.system.os-wrappers: + <<: *scons + kconfig: + - CONFIG_PKG_USING_FREERTOS_WRAPPER=y +online-packages.ai.llmchat: + <<: *scons + kconfig: + - CONFIG_BSP_USING_RW007_WLAN=y + - CONFIG_WEBCLIENT_USING_MBED_TLS=y + - CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=6144 + - CONFIG_PKG_USING_LLMCHAT=y + - CONFIG_PKG_USING_LLMCHAT_LATEST_VERSION=y +# ------ peripheral CI ------ +peripheral.aht21: + kconfig: + - CONFIG_BSP_USING_AHT21=y +peripheral.ap3216c: + kconfig: + - CONFIG_BSP_USING_AP3216C=y +peripheral.ethernet_28j60: + kconfig: + - CONFIG_BSP_USING_ENC28j60=y +peripheral.fal_easyflash: + kconfig: + - CONFIG_BSP_USING_EASYFLASH=y +peripheral.filesystem: + kconfig: + - CONFIG_BSP_USING_FS=y + - CONFIG_BSP_USING_FLASH_FATFS=y +peripheral.icm20608: + kconfig: + - CONFIG_BSP_USING_ICM20608=y +peripheral.lcd_st7787: + kconfig: + - CONFIG_BSP_USING_ONBOARD_LCD=y +peripheral.led_matrix: + kconfig: + - CONFIG_BSP_USING_ONBOARD_LED_MATRIX=y +peripheral.rs485: + kconfig: + - CONFIG_BSP_USING_RS485=y +peripheral.rw007: + kconfig: + - CONFIG_BSP_USING_RW007_WLAN=y +peripheral.spi_flash_w25q64: + kconfig: + - CONFIG_BSP_USING_SPI_FLASH=y +peripheral.sram: + kconfig: + - CONFIG_BSP_USING_SRAM=y +peripheral.usb_mouse: + kconfig: + - CONFIG_BSP_USING_USB_MOUSE=y +peripheral.uartv2: kconfig: - CONFIG_RT_USING_SERIAL_V1=n - CONFIG_RT_USING_SERIAL_V2=y - CONFIG_RT_SERIAL_USING_DMA=y - - CONFIG_BSP_USART1_AFIO_MODE_PA9_PA10=y - - CONFIG_BSP_UART1_RX_BUFSIZE=1024 - - CONFIG_BSP_UART1_TX_BUFSIZE=1024 - - CONFIG_BSP_USING_USART2=y - CONFIG_BSP_USART2_AFIO_MODE_PD5_PD6=y - CONFIG_BSP_UART2_RX_USING_DMA=y - CONFIG_BSP_UART2_TX_USING_DMA=y - - CONFIG_BSP_UART2_RX_BUFSIZE=1024 - - CONFIG_BSP_UART2_TX_BUFSIZE=1024 - - CONFIG_BSP_USING_USART3=y - - CONFIG_BSP_USART3_AFIO_MODE_PB10_PB11=y - - CONFIG_BSP_UART3_RX_USING_DMA=y - - CONFIG_BSP_UART3_TX_USING_DMA=y - - CONFIG_BSP_UART3_RX_BUFSIZE=1024 - - CONFIG_BSP_UART3_TX_BUFSIZE=1024 - - CONFIG_BSP_USING_UART4=y - - CONFIG_BSP_UART4_AFIO_MODE_PC10_PC11=y - - CONFIG_BSP_UART4_RX_USING_DMA=y - - CONFIG_BSP_UART4_TX_USING_DMA=y - - CONFIG_BSP_UART4_RX_BUFSIZE=1024 - - CONFIG_BSP_UART4_TX_BUFSIZE=1024 - - CONFIG_BSP_USING_UART5=y - - CONFIG_BSP_UART5_AFIO_MODE_PC12_PD2=y - - CONFIG_BSP_UART5_RX_USING_DMA=y - - CONFIG_BSP_UART5_TX_USING_DMA=y - - CONFIG_BSP_UART5_RX_BUFSIZE=4096 - - CONFIG_BSP_UART5_TX_BUFSIZE=4096 - - CONFIG_BSP_USING_UART6=y - - CONFIG_BSP_UART6_AFIO_MODE_PB0_PB1=y - - CONFIG_BSP_UART6_RX_USING_DMA=y - - CONFIG_BSP_UART6_TX_USING_DMA=y - - CONFIG_BSP_UART6_RX_BUFSIZE=1024 - - CONFIG_BSP_UART6_TX_BUFSIZE=1024 - - CONFIG_BSP_USING_UART7=y - - CONFIG_BSP_UART7_AFIO_MODE_PC4_PC5=y - - CONFIG_BSP_UART7_RX_USING_DMA=y - - CONFIG_BSP_UART7_TX_USING_DMA=y - - CONFIG_BSP_UART7_RX_BUFSIZE=2048 - - CONFIG_BSP_UART7_TX_BUFSIZE=2048 +# ------ component CI ------ +component.cherryusb_cdc: + kconfig: + - CONFIG_RT_USING_CHERRYUSB=y + - CONFIG_RT_CHERRYUSB_DEVICE=y + - CONFIG_RT_CHERRYUSB_DEVICE_DWC2_ST=y + - CONFIG_RT_CHERRYUSB_DEVICE_CDC_ACM=y + - CONFIG_RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM=y + diff --git a/bsp/n32/n32g45xvl-stb/defconfig b/bsp/n32/n32g45xvl-stb/defconfig deleted file mode 100644 index 1e7baf028e3..00000000000 --- a/bsp/n32/n32g45xvl-stb/defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# CONFIG_RT_USING_TIMER_SOFT is not set -CONFIG_RT_USING_MEMHEAP=y -CONFIG_RT_CONSOLE_DEVICE_NAME="usart1" -# CONFIG_RT_USING_DFS is not set -CONFIG_RT_USING_SYSTEM_WORKQUEUE=y -CONFIG_RT_USING_CAN=y -CONFIG_RT_USING_I2C=y -CONFIG_RT_USING_ADC=y -CONFIG_RT_USING_DAC=y -CONFIG_RT_USING_RTC=y -CONFIG_RT_USING_SPI=y -CONFIG_RT_USING_WDT=y -CONFIG_RT_USING_HWTIMER=y From f8e1e27eef0518ecd9af8b12630963bdbbce3e6e Mon Sep 17 00:00:00 2001 From: koudai <125535506+koudaiNEW@users.noreply.github.com> Date: Thu, 24 Apr 2025 11:09:59 +0800 Subject: [PATCH 4/6] Update ci.attachconfig.yml --- bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml b/bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml index 6a21e471c9b..1b86bbdd943 100644 --- a/bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml @@ -200,9 +200,14 @@ peripheral.uartv2: - CONFIG_RT_USING_SERIAL_V1=n - CONFIG_RT_USING_SERIAL_V2=y - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_USART1_AFIO_MODE_PA9_PA10=y + - CONFIG_BSP_UART1_RX_BUFSIZE=1024 + - CONFIG_BSP_UART1_TX_BUFSIZE=1024 - CONFIG_BSP_USART2_AFIO_MODE_PD5_PD6=y - CONFIG_BSP_UART2_RX_USING_DMA=y - CONFIG_BSP_UART2_TX_USING_DMA=y + - CONFIG_BSP_UART2_RX_BUFSIZE=1024 + - CONFIG_BSP_UART2_TX_BUFSIZE=1024 # ------ component CI ------ component.cherryusb_cdc: kconfig: From 24c4ab2463760f0c7b14927ed2967aeb6ae08207 Mon Sep 17 00:00:00 2001 From: koudai <786410175@qq.com> Date: Thu, 24 Apr 2025 11:41:38 +0800 Subject: [PATCH 5/6] =?UTF-8?q?=E4=BF=AE=E6=94=B9yml?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../.ci/attachconfig/ci.attachconfig.yml | 202 +----------------- 1 file changed, 3 insertions(+), 199 deletions(-) diff --git a/bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml b/bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml index 1b86bbdd943..d63beb299e2 100644 --- a/bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml @@ -1,200 +1,11 @@ scons.args: &scons scons_arg: - '--strict' -# ------ nano CI ------ -nano: - <<: *scons - kconfig: - - CONFIG_RT_USING_NANO=y # ------ kernel CI ------ -kernel.klibc-stdlib: - <<: *scons - kconfig: - - CONFIG_RT_KLIBC_USING_STDLIB=y - - CONFIG_RT_KLIBC_USING_STDLIB_MEMORY=y -kernel.klibc-tinysize: - <<: *scons - kconfig: - - CONFIG_RT_KLIBC_USING_TINY_SIZE=y -kernel.klibc-vsnprintf-std: - <<: *scons - kconfig: - - CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y - - CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG=y - - CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y - - CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y - - CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y - - CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER=y - - CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS=y + # ------ online-packages CI ------ -online-packages.iot.at_devices: - <<: *scons - kconfig: - - CONFIG_PKG_USING_AT_DEVICE=y - # Quectel M26/MC20 - - CONFIG_AT_DEVICE_USING_M26=y - - CONFIG_AT_DEVICE_M26_INIT_ASYN=y - # Quectel EC20 - - CONFIG_AT_DEVICE_USING_EC20=y - - CONFIG_AT_DEVICE_EC20_INIT_ASYN=y - # Espressif ESP32 - - CONFIG_AT_DEVICE_USING_ESP32=y - - CONFIG_AT_DEVICE_ESP32_INIT_ASYN=y - # Espressif ESP8266 - - CONFIG_AT_DEVICE_USING_ESP8266=y - - CONFIG_AT_DEVICE_ESP8266_INIT_ASYN=y - # Realthread RW007 - - CONFIG_AT_DEVICE_USING_RW007=y - - CONFIG_AT_DEVICE_RW007_INIT_ASYN=y - # SIMCom SIM800C - - CONFIG_AT_DEVICE_USING_SIM800C=y - - CONFIG_AT_DEVICE_SIM800C_INIT_ASYN=y - # SIMCom SIM76XX - - CONFIG_AT_DEVICE_USING_SIM76XX=y - - CONFIG_AT_DEVICE_SIM76XX_INIT_ASYN=y - # Notion MW31 - - CONFIG_AT_DEVICE_USING_MW31=y - - CONFIG_AT_DEVICE_MW31_INIT_ASYN=y - # WinnerMicro W60X - - CONFIG_AT_DEVICE_USING_W60X=y - - CONFIG_AT_DEVICE_W60X_INIT_ASYN=y - # Ai-Think A9G - - CONFIG_AT_DEVICE_USING_A9G=y - - CONFIG_AT_DEVICE_A9G_INIT_ASYN=y - # Quectel BC26 - - CONFIG_AT_DEVICE_USING_BC26=y - - CONFIG_AT_DEVICE_BC26_INIT_ASYN=y - # luat Air720 - - CONFIG_AT_DEVICE_USING_AIR720=y - - CONFIG_AT_DEVICE_AIR720_INIT_ASYN=y - # Gosuncn ME3616 - - CONFIG_AT_DEVICE_USING_ME3616=y - - CONFIG_AT_DEVICE_ME3616_INIT_ASYN=y - # ChinaMobile M6315 - - CONFIG_AT_DEVICE_USING_M6315=y - - CONFIG_AT_DEVICE_M6315_INIT_ASYN=y - # Quectel BC28 - - CONFIG_AT_DEVICE_USING_BC28=y - - CONFIG_AT_DEVICE_BC28_INIT_ASYN=y - # Quectel EC200T/EC200S - - CONFIG_AT_DEVICE_USING_EC200X=y - - CONFIG_AT_DEVICE_EC200X_INIT_ASYN=y - # Neoway N21 - - CONFIG_AT_DEVICE_USING_N21=y - - CONFIG_AT_DEVICE_N21_INIT_ASYN=y - # Neoway N58 - - CONFIG_AT_DEVICE_USING_N58=y - - CONFIG_AT_DEVICE_N58_INIT_ASYN=y - # ChinaMobile M5311 - - CONFIG_AT_DEVICE_USING_M5311=y - - CONFIG_AT_DEVICE_M5311_INIT_ASYN=y - # Fibocom L610 - - CONFIG_AT_DEVICE_USING_L610=y - - CONFIG_AT_DEVICE_L610_INIT_ASYN=y - # Neoway N720 - - CONFIG_AT_DEVICE_USING_N720=y - - CONFIG_AT_DEVICE_N720_INIT_ASYN=y - # Gosuncn ML305 - - CONFIG_AT_DEVICE_USING_ML305=y - - CONFIG_AT_DEVICE_ML305_INIT_ASYN=y -online-packages.misc.misc: - <<: *scons - kconfig: - - CONFIG_PKG_USING_MULTIBUTTON=y -online-packages.misc.vi: - <<: *scons - kconfig: - - CONFIG_PKG_USING_VI=y - # - CONFIG_VI_ENABLE_8BIT=y - - CONFIG_VI_ENABLE_COLON=y - - CONFIG_VI_ENABLE_COLON_EXPAND=y - - CONFIG_VI_ENABLE_YANKMARK=y - - CONFIG_VI_ENABLE_SEARCH=y - - CONFIG_VI_ENABLE_DOT_CMD=y - - CONFIG_VI_ENABLE_READONLY=y - - CONFIG_VI_ENABLE_SETOPTS=y - - CONFIG_VI_ENABLE_SET=y - - CONFIG_VI_ENABLE_WIN_RESIZE=y - - CONFIG_VI_ENABLE_VI_ASK_TERMINAL=y - - CONFIG_VI_ENABLE_UNDO=y - - CONFIG_VI_ENABLE_UNDO_QUEUE=y - - CONFIG_VI_ENABLE_VERBOSE_STATUS=y -online-packages.multimedia.lvgl-v8.3-latest: - <<: *scons - kconfig: - - CONFIG_BSP_USING_LVGL=y - - CONFIG_BSP_USING_LVGL_DEMO=y - - CONFIG_PKG_LVGL_USING_V8_3_LATEST=y -online-packages.multimedia.lvgl-v8.3.11: - <<: *scons - kconfig: - - CONFIG_BSP_USING_LVGL=y - - CONFIG_BSP_USING_LVGL_DEMO=y - - CONFIG_PKG_LVGL_USING_V080311=y -online-packages.multimedia.lvgl-v8.4-latest: - <<: *scons - kconfig: - - CONFIG_BSP_USING_LVGL=y - - CONFIG_BSP_USING_LVGL_DEMO=y - - CONFIG_PKG_LVGL_USING_V8_4_LATEST=y -online-packages.system.enhanced-kservice: - <<: *scons - kconfig: - - CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE=y - - CONFIG_PKG_USING_RT_MEMCPY_CM=y -online-packages.system.os-wrappers: - <<: *scons - kconfig: - - CONFIG_PKG_USING_FREERTOS_WRAPPER=y -online-packages.ai.llmchat: - <<: *scons - kconfig: - - CONFIG_BSP_USING_RW007_WLAN=y - - CONFIG_WEBCLIENT_USING_MBED_TLS=y - - CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=6144 - - CONFIG_PKG_USING_LLMCHAT=y - - CONFIG_PKG_USING_LLMCHAT_LATEST_VERSION=y + # ------ peripheral CI ------ -peripheral.aht21: - kconfig: - - CONFIG_BSP_USING_AHT21=y -peripheral.ap3216c: - kconfig: - - CONFIG_BSP_USING_AP3216C=y -peripheral.ethernet_28j60: - kconfig: - - CONFIG_BSP_USING_ENC28j60=y -peripheral.fal_easyflash: - kconfig: - - CONFIG_BSP_USING_EASYFLASH=y -peripheral.filesystem: - kconfig: - - CONFIG_BSP_USING_FS=y - - CONFIG_BSP_USING_FLASH_FATFS=y -peripheral.icm20608: - kconfig: - - CONFIG_BSP_USING_ICM20608=y -peripheral.lcd_st7787: - kconfig: - - CONFIG_BSP_USING_ONBOARD_LCD=y -peripheral.led_matrix: - kconfig: - - CONFIG_BSP_USING_ONBOARD_LED_MATRIX=y -peripheral.rs485: - kconfig: - - CONFIG_BSP_USING_RS485=y -peripheral.rw007: - kconfig: - - CONFIG_BSP_USING_RW007_WLAN=y -peripheral.spi_flash_w25q64: - kconfig: - - CONFIG_BSP_USING_SPI_FLASH=y -peripheral.sram: - kconfig: - - CONFIG_BSP_USING_SRAM=y -peripheral.usb_mouse: - kconfig: - - CONFIG_BSP_USING_USB_MOUSE=y peripheral.uartv2: kconfig: - CONFIG_RT_USING_SERIAL_V1=n @@ -208,12 +19,5 @@ peripheral.uartv2: - CONFIG_BSP_UART2_TX_USING_DMA=y - CONFIG_BSP_UART2_RX_BUFSIZE=1024 - CONFIG_BSP_UART2_TX_BUFSIZE=1024 -# ------ component CI ------ -component.cherryusb_cdc: - kconfig: - - CONFIG_RT_USING_CHERRYUSB=y - - CONFIG_RT_CHERRYUSB_DEVICE=y - - CONFIG_RT_CHERRYUSB_DEVICE_DWC2_ST=y - - CONFIG_RT_CHERRYUSB_DEVICE_CDC_ACM=y - - CONFIG_RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM=y + From 9dcfad73b326ba0320e85c5ce6afe55caef1f09e Mon Sep 17 00:00:00 2001 From: koudai <786410175@qq.com> Date: Thu, 24 Apr 2025 15:35:35 +0800 Subject: [PATCH 6/6] =?UTF-8?q?=E4=BF=AE=E6=94=B9=E5=AE=8F=E6=B3=A8?= =?UTF-8?q?=E9=87=8A?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/n32/libraries/n32_drivers/drv_usart_v2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsp/n32/libraries/n32_drivers/drv_usart_v2.h b/bsp/n32/libraries/n32_drivers/drv_usart_v2.h index e9f62606a69..0a068452a9d 100644 --- a/bsp/n32/libraries/n32_drivers/drv_usart_v2.h +++ b/bsp/n32/libraries/n32_drivers/drv_usart_v2.h @@ -24,4 +24,4 @@ #define UART_RX_DMA_IT_HT_FLAG 0x01 #define UART_RX_DMA_IT_TC_FLAG 0x02 -#endif /* __DRV_USART_H__ */ +#endif /* __DRV_USART_V2_H__ */