From 1fafa3fcf5d2b4e363a81cf45539e7c7ee74b242 Mon Sep 17 00:00:00 2001 From: Yaochenger <1516081466@qq.com> Date: Thu, 29 May 2025 14:37:34 +0800 Subject: [PATCH 1/8] =?UTF-8?q?[xuantie]=20=E7=B2=BE=E7=AE=80libraries?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../libraries/device_drivers/drv_usart.c | 18 +- .../libraries/device_drivers/drv_usart.h | 2 +- .../chip_riscv_dummy/gcc_flash_xiaohui.ld | 2 +- .../include/asm/riscv_asm_macro.h | 2 +- .../chip_riscv_dummy/include/asm/riscv_csr.h | 26 +- .../chip_riscv_dummy/include/drv/dev_tag.h | 2 +- .../chip_riscv_dummy/include/dw_timer_ll.h | 10 +- .../src/arch/{e906fd => c906}/SConscript | 0 .../chip_riscv_dummy/src/arch/c906/startup.S | 7 +- .../src/arch/c906fd/startup.S | 128 --- .../chip_riscv_dummy/src/arch/c906fd/system.c | 274 ----- .../chip_riscv_dummy/src/arch/c906fd/trap_c.c | 64 -- .../src/arch/c906fd/vectors.S | 412 -------- .../src/arch/c906fdv/startup.S | 128 --- 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--------------- .../src/arch/c907fdv/startup.S | 188 ---- .../src/arch/c907fdv/system.c | 326 ------ .../src/arch/c907fdv/trap_c.c | 64 -- .../src/arch/c907fdv/vectors.S | 842 --------------- .../src/arch/c907fdvm-rv32/startup.S | 188 ---- .../src/arch/c907fdvm-rv32/system.c | 326 ------ .../src/arch/c907fdvm-rv32/trap_c.c | 64 -- .../src/arch/c907fdvm-rv32/vectors.S | 842 --------------- .../src/arch/c907fdvm/startup.S | 188 ---- .../src/arch/c907fdvm/system.c | 326 ------ .../src/arch/c907fdvm/trap_c.c | 64 -- .../src/arch/c907fdvm/vectors.S | 842 --------------- .../chip_riscv_dummy/src/arch/c908/SConscript | 13 + .../chip_riscv_dummy/src/arch/c908/startup.S | 7 +- .../chip_riscv_dummy/src/arch/c908i/startup.S | 188 ---- .../chip_riscv_dummy/src/arch/c908i/system.c | 316 ------ .../chip_riscv_dummy/src/arch/c908i/trap_c.c | 64 -- .../chip_riscv_dummy/src/arch/c908i/vectors.S | 527 ---------- .../chip_riscv_dummy/src/arch/c908v/startup.S | 188 ---- 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bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv/system.c delete mode 100644 bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv/trap_c.c delete mode 100644 bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv/vectors.S create mode 100644 bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r910/SConscript create mode 100644 bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r920/SConscript rename bsp/xuantie/libraries/xuantie_libraries/pre_main/{sub_libcpu.S => libcpu.S} (100%) diff --git a/bsp/xuantie/libraries/device_drivers/drv_usart.c b/bsp/xuantie/libraries/device_drivers/drv_usart.c index 677ba579d61..277f04ba67f 100644 --- a/bsp/xuantie/libraries/device_drivers/drv_usart.c +++ b/bsp/xuantie/libraries/device_drivers/drv_usart.c @@ -27,7 +27,7 @@ #include #if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) \ - && !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && !defined(BSP_USING_UART7) + && !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && !defined(BSP_USING_UART7) #error "Please define at least one BSP_USING_UARTx" /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ #endif @@ -62,7 +62,7 @@ static rt_err_t xuantie_configure(struct rt_serial_device *serial, struct serial ret = csi_uart_baud(&uart->uart, cfg->baud_rate); if (ret != CSI_OK) { - return -RT_ERROR; + return RT_ERROR; } csi_uart_data_bits_t data_bits; @@ -123,7 +123,7 @@ static rt_err_t xuantie_configure(struct rt_serial_device *serial, struct serial ret = csi_uart_format(&uart->uart, data_bits, parity, stop_bits); if (ret != CSI_OK) { - return -RT_ERROR; + return RT_ERROR; } return RT_EOK; @@ -136,7 +136,7 @@ static rt_err_t xuantie_control(struct rt_serial_device *serial, int cmd, void * case RT_DEVICE_CTRL_CONFIG: return xuantie_configure(serial, (struct serial_configure *)arg); default: - return -RT_ERROR; + return RT_ERROR; } } @@ -148,8 +148,8 @@ static int xuantie_putc(struct rt_serial_device *serial, char c) ret = csi_uart_send(&uart->uart, &c, 1, 50); if (ret == 1) return RT_EOK; - - return -RT_ERROR; + + return RT_ERROR; } static int xuantie_getc(struct rt_serial_device *serial) @@ -160,7 +160,7 @@ static int xuantie_getc(struct rt_serial_device *serial) csi_uart_receive(&uart->uart, &c, 1, 0x5); dw_uart_enable_recv_irq(uart_base); - return c; + return c; } static const struct rt_uart_ops xuantie_uart_ops = @@ -192,7 +192,7 @@ int rt_hw_usart_init(void) if (result != CSI_OK) { LOG_E("Failed to initialize UART %d", uart_obj[i].config->idx); - return -RT_ERROR; + return RT_ERROR; } /* Init UART object */ @@ -210,7 +210,7 @@ int rt_hw_usart_init(void) { LOG_E("Failed to register UART device %s", uart_obj[i].config->name); csi_uart_uninit(&uart_obj[i].uart); - return -RT_ERROR; + return RT_ERROR; } } return result; diff --git a/bsp/xuantie/libraries/device_drivers/drv_usart.h b/bsp/xuantie/libraries/device_drivers/drv_usart.h index f18fd544688..b0c0741931e 100644 --- a/bsp/xuantie/libraries/device_drivers/drv_usart.h +++ b/bsp/xuantie/libraries/device_drivers/drv_usart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2025, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_xiaohui.ld b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_xiaohui.ld index ea255d2035b..2bbd86b3853 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_xiaohui.ld +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_xiaohui.ld @@ -21,7 +21,7 @@ MEMORY DRAM : ORIGIN = 0x50000000, LENGTH = 0x100000 /* on-chip DRAM 1*1MB */ } -__min_heap_size = 0x200; +__min_heap_size = 0x20000; PROVIDE (__ram_end = 0x50100000 - 0x8); PROVIDE (__heap_end = __ram_end); diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_asm_macro.h b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_asm_macro.h index 4eeded81677..d71c7ec7a2e 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_asm_macro.h +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_asm_macro.h @@ -19,7 +19,7 @@ /* * attention: don't modify this file as a suggest * you should copy from chip_riscv_dummy/include/asm/riscv_asm_macro.h and keep it newer - * please contact xuantie-rtos os team if have question + * please contact xuantie-rtos os team if have question */ #ifndef __RISCV_ASM_MACRO_H__ diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_csr.h b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_csr.h index 423db93afa2..bc41bbe8b5a 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_csr.h +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_csr.h @@ -19,30 +19,30 @@ /* * attention: don't modify this file as a suggest * you should copy from chip_riscv_dummy/include/asm/riscv_csr.h and keep it newer - * please contact xuantie-rtos os team if have question + * please contact xuantie-rtos os team if have question */ #ifndef __RISCV_CSR_H__ #define __RISCV_CSR_H__ #if __riscv_xlen == 64 - #define portWORD_SIZE 8 - #define store_x sd - #define load_x ld + #define portWORD_SIZE 8 + #define store_x sd + #define load_x ld #elif __riscv_xlen == 32 - #define store_x sw - #define load_x lw - #define portWORD_SIZE 4 + #define store_x sw + #define load_x lw + #define portWORD_SIZE 4 #else - #error Assembler did not define __riscv_xlen + #error Assembler did not define __riscv_xlen #endif #if __riscv_flen == 64 - #define fstore_x fsd - #define fload_x fld + #define fstore_x fsd + #define fload_x fld #elif __riscv_flen == 32 - #define fstore_x fsw - #define fload_x flw + #define fstore_x fsw + #define fload_x flw #endif #if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE @@ -136,7 +136,7 @@ #define MSTATUS_FS_SHIFT 13 #define MSTATUS_MS_SHIFT 25 -#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) #if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V ||CONFIG_CPU_XUANTIE_C908I || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 #define ATTR_SO (1ull << 4) diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/drv/dev_tag.h b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/drv/dev_tag.h index 80150c85cd8..f9e3146a69c 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/drv/dev_tag.h +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/drv/dev_tag.h @@ -90,7 +90,7 @@ typedef enum { DEV_RAMBUS_120SI_TAG, DEV_RAMBUS_120SII_TAG, DEV_RAMBUS_120SIII_TAG, - DEV_WJ_AVFS_TAG, + DEV_WJ_AVFS_TAG, DEV_WJ_BMU_TAG, } csi_dev_tag_t; diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/dw_timer_ll.h b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/dw_timer_ll.h index c2289d97706..cb7bf108362 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/dw_timer_ll.h +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/dw_timer_ll.h @@ -1,12 +1,12 @@ /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * Copyright (C) 2017-2024 Alibaba Group Holding Limited */ /******************************************************* - * @file dw_timer_ll.h - * @brief header file for timer ll driver + * @file dw_timer_ll.h + * @brief header file for timer ll driver * @version V1.0 - * @date 9. April 2020 + * @date 9. April 2020 * ******************************************************/ #ifndef _DW_TIMER_LL_H_ @@ -21,7 +21,7 @@ extern "C" { #endif -/*! Timer1 Control Reg, offset: 0x08 */ +/*! Timer1 Control Reg, offset: 0x08 */ #define DW_TIMER_CTL_ENABLE_SEL_Pos (0U) #define DW_TIMER_CTL_ENABLE_SEL_Msk (0x1U << DW_TIMER_CTL_ENABLE_SEL_Pos) #define DW_TIMER_CTL_ENABLE_SEL_EN DW_TIMER_CTL_ENABLE_SEL_Msk diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fd/SConscript b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906/SConscript similarity index 100% rename from bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fd/SConscript rename to bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906/SConscript diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906/startup.S index 745487ab6d3..e8d56eb6346 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906/startup.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906/startup.S @@ -19,7 +19,9 @@ #include .globl Reset_Handler - +.global __rt_rvstack +.equ Mcoret_Handler, SW_handler +.equ Mirq_Handler, SW_handler .section .vectors .align 6 .globl __Vectors @@ -102,7 +104,7 @@ Reset_Handler: #endif #endif - la a0, pre_main + la a0, rtthread_startup jalr a0 .size Reset_Handler, . - Reset_Handler @@ -118,6 +120,7 @@ __exit: g_base_irqstack: .space CONFIG_ARCH_INTERRUPTSTACK g_top_irqstack: +__rt_rvstack: #ifdef CONFIG_KERNEL_NONE .align 4 .global g_base_mainstack diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/startup.S deleted file mode 100644 index 745487ab6d3..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/startup.S +++ /dev/null @@ -1,128 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -.globl Reset_Handler - -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler - j Default_Handler - j Default_Handler - j Default_Handler - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 - -#ifdef CONFIG_KERNEL_NONE - la sp, g_top_mainstack -#else - la sp, g_top_irqstack -#endif - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, pre_main - jalr a0 - - .size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_irqstack: -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK -g_top_mainstack: -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/system.c deleted file mode 100644 index ba5e05f515a..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/system.c +++ /dev/null @@ -1,274 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(MMU_MODE_32); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void interrupt_init(void) -{ - int i; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); - __set_MIE(mie); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); - -#if __riscv_flen == 64 - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); -#endif - - cache_init(); - section_init(); - pmp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/vectors.S deleted file mode 100644 index 2f728ddc35d..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/vectors.S +++ /dev/null @@ -1,412 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw sstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - csrw mscratch, sp - la sp, g_top_irqstack - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - mret - - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw sstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - sd s0, (sp) -#endif - csrw mscratch, sp - la sp, g_top_irqstack - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -(140+140) - sd x1, ( 0 + 0 )(sp) - sd x3, ( 8 + 8 )(sp) - sd x4, ( 12+ 12)(sp) - sd x5, ( 16+ 16)(sp) - sd x6, ( 20+ 20)(sp) - sd x7, ( 24+ 24)(sp) - sd x8, ( 28+ 28)(sp) - sd x9, ( 32+ 32)(sp) - sd x10,( 36+ 36)(sp) - sd x11,( 40+ 40)(sp) - sd x12,( 44+ 44)(sp) - sd x13,( 48+ 48)(sp) - sd x14,( 52+ 52)(sp) - sd x15,( 56+ 56)(sp) - sd x16,( 60+ 60)(sp) - sd x17,( 64+ 64)(sp) - sd x18,( 68+ 68)(sp) - sd x19,( 72+ 72)(sp) - sd x20,( 76+ 76)(sp) - sd x21,( 80+ 80)(sp) - sd x22,( 84+ 84)(sp) - sd x23,( 88+ 88)(sp) - sd x24,( 92+ 92)(sp) - sd x25,( 96+ 96)(sp) - sd x26,(100+100)(sp) - sd x27,(104+104)(sp) - sd x28,(108+108)(sp) - sd x29,(112+112)(sp) - sd x30,(116+116)(sp) - sd x31,(120+120)(sp) - csrr a0, mepc - sd a0, (124+124)(sp) - csrr a0, mstatus - sd a0, (128+128)(sp) - csrr a0, mcause - sd a0, (132+132)(sp) - csrr a0, mtval - sd a0, (136+136)(sp) - csrr a0, mscratch - sd a0, ( 4 + 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fdv/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fdv/startup.S deleted file mode 100644 index 745487ab6d3..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fdv/startup.S +++ /dev/null @@ -1,128 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -.globl Reset_Handler - -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler - j Default_Handler - j Default_Handler - j Default_Handler - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 - -#ifdef CONFIG_KERNEL_NONE - la sp, g_top_mainstack -#else - la sp, g_top_irqstack -#endif - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, pre_main - jalr a0 - - .size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_irqstack: -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK -g_top_mainstack: -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fdv/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fdv/system.c deleted file mode 100644 index ba5e05f515a..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fdv/system.c +++ /dev/null @@ -1,274 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(MMU_MODE_32); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void interrupt_init(void) -{ - int i; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); - __set_MIE(mie); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); - -#if __riscv_flen == 64 - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); -#endif - - cache_init(); - section_init(); - pmp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fdv/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fdv/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fdv/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fdv/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fdv/vectors.S deleted file mode 100644 index 2f728ddc35d..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fdv/vectors.S +++ /dev/null @@ -1,412 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw sstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - csrw mscratch, sp - la sp, g_top_irqstack - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - mret - - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw sstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - sd s0, (sp) -#endif - csrw mscratch, sp - la sp, g_top_irqstack - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -(140+140) - sd x1, ( 0 + 0 )(sp) - sd x3, ( 8 + 8 )(sp) - sd x4, ( 12+ 12)(sp) - sd x5, ( 16+ 16)(sp) - sd x6, ( 20+ 20)(sp) - sd x7, ( 24+ 24)(sp) - sd x8, ( 28+ 28)(sp) - sd x9, ( 32+ 32)(sp) - sd x10,( 36+ 36)(sp) - sd x11,( 40+ 40)(sp) - sd x12,( 44+ 44)(sp) - sd x13,( 48+ 48)(sp) - sd x14,( 52+ 52)(sp) - sd x15,( 56+ 56)(sp) - sd x16,( 60+ 60)(sp) - sd x17,( 64+ 64)(sp) - sd x18,( 68+ 68)(sp) - sd x19,( 72+ 72)(sp) - sd x20,( 76+ 76)(sp) - sd x21,( 80+ 80)(sp) - sd x22,( 84+ 84)(sp) - sd x23,( 88+ 88)(sp) - sd x24,( 92+ 92)(sp) - sd x25,( 96+ 96)(sp) - sd x26,(100+100)(sp) - sd x27,(104+104)(sp) - sd x28,(108+108)(sp) - sd x29,(112+112)(sp) - sd x30,(116+116)(sp) - sd x31,(120+120)(sp) - csrr a0, mepc - sd a0, (124+124)(sp) - csrr a0, mstatus - sd a0, (128+128)(sp) - csrr a0, mcause - sd a0, (132+132)(sp) - csrr a0, mtval - sd a0, (136+136)(sp) - csrr a0, mscratch - sd a0, ( 4 + 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907-rv32/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907-rv32/startup.S deleted file mode 100644 index 38a84acde3f..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907-rv32/startup.S +++ /dev/null @@ -1,188 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.globl Reset_Handler - -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler /* 12 */ - j Default_Handler /* 13 */ - j Default_Handler /* 14 */ - j Default_Handler /* 15 */ -#if CONFIG_ECC_L1_ENABLE - j ECC_L1_Handler /* 16 */ -#else - j Default_Handler /* 16 */ -#endif - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 - - /* get cpu id */ - csrr a0, mhartid - -#if defined(CONFIG_SMP) && CONFIG_SMP - /* check if hart is within range */ - /* tp: hart id */ - li t0, CONFIG_NR_CPUS - bge a0, t0, hart_out_of_bounds_loop -#endif - -#ifdef CONFIG_KERNEL_NONE - la sp, g_base_mainstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_MAINSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */ -#else - la sp, g_base_irqstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ -#endif - - /* other cpu core, jump to cpu entry directly */ - bnez a0, secondary_cpu_entry - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, pre_main - jalr a0 - -.size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - .type secondary_cpu_entry, %function -secondary_cpu_entry: -#if defined(CONFIG_SMP) && CONFIG_SMP - la a0, secondary_boot_flag - lw a0, 0(a0) - li a1, 0xa55a - beq a0, a1, 1f -#endif - j secondary_cpu_entry - -#if defined(CONFIG_SMP) && CONFIG_SMP -1: - jal secondary_cpu_c_start - -.size secondary_cpu_entry, . - secondary_cpu_entry - -hart_out_of_bounds_loop: - /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ - wfi - j hart_out_of_bounds_loop -#endif - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS -g_top_irqstack: - -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS -g_top_mainstack: -#endif - -#if defined(CONFIG_SMP) && CONFIG_SMP -.data -.global secondary_boot_flag -.align 3 -secondary_boot_flag: - .dword 0 -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907-rv32/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907-rv32/system.c deleted file mode 100644 index cccef03fd16..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907-rv32/system.c +++ /dev/null @@ -1,326 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP) -#if CONFIG_NR_CPUS > 1 -#error "Please define CONFIG_NR_CPUS as 1 or do not need define." -#endif -#endif - -#if CONFIG_ECC_L2_ENABLE -static csi_dev_t ecc_l2_dev; -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void interrupt_init(void) -{ - int i; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); -#if CONFIG_ECC_L1_ENABLE - mie |= (1 << 16); -#endif - __set_MIE(mie); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); -#if __riscv_matrix || __riscv_xtheadmatrix - /* enable matrix */ - status &= ~(1ul << 0); -#endif /* __riscv_matrix || __riscv_xtheadmatrix */ - __set_MXSTATUS(status); - -#if __riscv_flen - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif -#if __riscv_matrix || __riscv_xtheadmatrix - /* enable matrix ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_MS_SHIFT); - __set_MSTATUS(status); -#endif - -#if CONFIG_ECC_L1_ENABLE - /* enable L1 cache ecc */ - uint64_t mhint = __get_MHINT(); - mhint |= (0x1 << 19); - __set_MHINT(mhint); -#endif - -#if CONFIG_ECC_L2_ENABLE - /* enable L2 cache ecc */ - uint64_t mccr2 = __get_MCCR2(); - mccr2 |= (0x1 << 1); - __set_MCCR2(mccr2); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); - -#if CBO_INSN_SUPPORT - unsigned long envcfg = __get_MENVCFG(); - /* enable CBIE & CBCFE & CBZE on lower priviledge */ - envcfg |= (3 << 4 | 1 << 6 | 1 << 7); - __set_MENVCFG(envcfg); -#endif -#endif - - cache_init(); - section_init(); - pmp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); - -#if CONFIG_ECC_L2_ENABLE - extern void ecc_l2_irqhandler(void *arg); - /* l2 cache ecc interrupt register */ - ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn; - csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev); - csi_irq_enable(ecc_l2_dev.irq_num); -#endif -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907-rv32/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907-rv32/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907-rv32/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907-rv32/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907-rv32/vectors.S deleted file mode 100644 index ef32af346ff..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907-rv32/vectors.S +++ /dev/null @@ -1,842 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, sepc - store_x t0, (68+68)(sp) - csrr t0, sstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, sepc - store_x t0, (68)(sp) - csrr t0, sstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw sepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68)(sp) - csrw sepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret - - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, sepc - store_x t0, (68+68)(sp) - csrr t0, sstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, sepc - store_x t0, (68)(sp) - csrr t0, sstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, do_irq - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - load_x t0, (72+72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw sepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - load_x t0, (72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68)(sp) - csrw sepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, sscratch - sret - -#if CONFIG_ECC_L1_ENABLE - .align 3 - .weak ECC_L1_Handler - .type ECC_L1_Handler, %function -ECC_L1_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, ECC_L1_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret -#endif - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - store_x s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - -#if __riscv_xlen == 64 - addi sp, sp, -(140+140) - store_x x1, ( 0 + 0 )(sp) - store_x x3, ( 8 + 8 )(sp) - store_x x4, ( 12+ 12)(sp) - store_x x5, ( 16+ 16)(sp) - store_x x6, ( 20+ 20)(sp) - store_x x7, ( 24+ 24)(sp) - store_x x8, ( 28+ 28)(sp) - store_x x9, ( 32+ 32)(sp) - store_x x10,( 36+ 36)(sp) - store_x x11,( 40+ 40)(sp) - store_x x12,( 44+ 44)(sp) - store_x x13,( 48+ 48)(sp) - store_x x14,( 52+ 52)(sp) - store_x x15,( 56+ 56)(sp) - store_x x16,( 60+ 60)(sp) - store_x x17,( 64+ 64)(sp) - store_x x18,( 68+ 68)(sp) - store_x x19,( 72+ 72)(sp) - store_x x20,( 76+ 76)(sp) - store_x x21,( 80+ 80)(sp) - store_x x22,( 84+ 84)(sp) - store_x x23,( 88+ 88)(sp) - store_x x24,( 92+ 92)(sp) - store_x x25,( 96+ 96)(sp) - store_x x26,(100+100)(sp) - store_x x27,(104+104)(sp) - store_x x28,(108+108)(sp) - store_x x29,(112+112)(sp) - store_x x30,(116+116)(sp) - store_x x31,(120+120)(sp) - csrr a0, mepc - store_x a0, (124+124)(sp) - csrr a0, mstatus - store_x a0, (128+128)(sp) - csrr a0, mcause - store_x a0, (132+132)(sp) - csrr a0, mtval - store_x a0, (136+136)(sp) - csrr a0, mscratch - store_x a0, ( 4 + 4 )(sp) -#else - addi sp, sp, -140 - store_x x1, ( 0 )(sp) - store_x x3, ( 8 )(sp) - store_x x4, ( 12)(sp) - store_x x5, ( 16)(sp) - store_x x6, ( 20)(sp) - store_x x7, ( 24)(sp) - store_x x8, ( 28)(sp) - store_x x9, ( 32)(sp) - store_x x10,( 36)(sp) - store_x x11,( 40)(sp) - store_x x12,( 44)(sp) - store_x x13,( 48)(sp) - store_x x14,( 52)(sp) - store_x x15,( 56)(sp) - store_x x16,( 60)(sp) - store_x x17,( 64)(sp) - store_x x18,( 68)(sp) - store_x x19,( 72)(sp) - store_x x20,( 76)(sp) - store_x x21,( 80)(sp) - store_x x22,( 84)(sp) - store_x x23,( 88)(sp) - store_x x24,( 92)(sp) - store_x x25,( 96)(sp) - store_x x26,(100)(sp) - store_x x27,(104)(sp) - store_x x28,(108)(sp) - store_x x29,(112)(sp) - store_x x30,(116)(sp) - store_x x31,(120)(sp) - csrr a0, mepc - store_x a0, (124)(sp) - csrr a0, mstatus - store_x a0, (128)(sp) - csrr a0, mcause - store_x a0, (132)(sp) - csrr a0, mtval - store_x a0, (136)(sp) - csrr a0, mscratch - store_x a0, ( 4 )(sp) -#endif - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907/SConscript b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907/SConscript new file mode 100644 index 00000000000..7c13ee46652 --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907/SConscript @@ -0,0 +1,13 @@ +from building import * +import os + +cwd = GetCurrentDir() +CPPPATH = [cwd] +src = ['startup.S'] +src += ['system.c'] +src += ['trap_c.c'] +src += ['vectors.S'] + +group = DefineGroup('sys', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907/startup.S index 92ba69989b2..43feba91add 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907/startup.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907/startup.S @@ -23,7 +23,9 @@ #endif .globl Reset_Handler - +.global __rt_rvstack +.equ Mcoret_Handler, SW_handler +.equ Mirq_Handler, SW_handler .section .vectors .align 6 .globl __Vectors @@ -132,7 +134,7 @@ Reset_Handler: #endif #endif - la a0, pre_main + la a0, rtthread_startup jalr a0 .size Reset_Handler, . - Reset_Handler @@ -169,6 +171,7 @@ hart_out_of_bounds_loop: g_base_irqstack: .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS g_top_irqstack: +__rt_rvstack: #ifdef CONFIG_KERNEL_NONE .align 4 @@ -177,6 +180,7 @@ g_top_irqstack: g_base_mainstack: .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS g_top_mainstack: + #endif #if defined(CONFIG_SMP) && CONFIG_SMP diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd-rv32/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd-rv32/startup.S deleted file mode 100644 index 38a84acde3f..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd-rv32/startup.S +++ /dev/null @@ -1,188 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.globl Reset_Handler - -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler /* 12 */ - j Default_Handler /* 13 */ - j Default_Handler /* 14 */ - j Default_Handler /* 15 */ -#if CONFIG_ECC_L1_ENABLE - j ECC_L1_Handler /* 16 */ -#else - j Default_Handler /* 16 */ -#endif - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 - - /* get cpu id */ - csrr a0, mhartid - -#if defined(CONFIG_SMP) && CONFIG_SMP - /* check if hart is within range */ - /* tp: hart id */ - li t0, CONFIG_NR_CPUS - bge a0, t0, hart_out_of_bounds_loop -#endif - -#ifdef CONFIG_KERNEL_NONE - la sp, g_base_mainstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_MAINSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */ -#else - la sp, g_base_irqstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ -#endif - - /* other cpu core, jump to cpu entry directly */ - bnez a0, secondary_cpu_entry - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, pre_main - jalr a0 - -.size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - .type secondary_cpu_entry, %function -secondary_cpu_entry: -#if defined(CONFIG_SMP) && CONFIG_SMP - la a0, secondary_boot_flag - lw a0, 0(a0) - li a1, 0xa55a - beq a0, a1, 1f -#endif - j secondary_cpu_entry - -#if defined(CONFIG_SMP) && CONFIG_SMP -1: - jal secondary_cpu_c_start - -.size secondary_cpu_entry, . - secondary_cpu_entry - -hart_out_of_bounds_loop: - /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ - wfi - j hart_out_of_bounds_loop -#endif - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS -g_top_irqstack: - -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS -g_top_mainstack: -#endif - -#if defined(CONFIG_SMP) && CONFIG_SMP -.data -.global secondary_boot_flag -.align 3 -secondary_boot_flag: - .dword 0 -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd-rv32/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd-rv32/system.c deleted file mode 100644 index cccef03fd16..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd-rv32/system.c +++ /dev/null @@ -1,326 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP) -#if CONFIG_NR_CPUS > 1 -#error "Please define CONFIG_NR_CPUS as 1 or do not need define." -#endif -#endif - -#if CONFIG_ECC_L2_ENABLE -static csi_dev_t ecc_l2_dev; -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void interrupt_init(void) -{ - int i; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); -#if CONFIG_ECC_L1_ENABLE - mie |= (1 << 16); -#endif - __set_MIE(mie); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); -#if __riscv_matrix || __riscv_xtheadmatrix - /* enable matrix */ - status &= ~(1ul << 0); -#endif /* __riscv_matrix || __riscv_xtheadmatrix */ - __set_MXSTATUS(status); - -#if __riscv_flen - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif -#if __riscv_matrix || __riscv_xtheadmatrix - /* enable matrix ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_MS_SHIFT); - __set_MSTATUS(status); -#endif - -#if CONFIG_ECC_L1_ENABLE - /* enable L1 cache ecc */ - uint64_t mhint = __get_MHINT(); - mhint |= (0x1 << 19); - __set_MHINT(mhint); -#endif - -#if CONFIG_ECC_L2_ENABLE - /* enable L2 cache ecc */ - uint64_t mccr2 = __get_MCCR2(); - mccr2 |= (0x1 << 1); - __set_MCCR2(mccr2); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); - -#if CBO_INSN_SUPPORT - unsigned long envcfg = __get_MENVCFG(); - /* enable CBIE & CBCFE & CBZE on lower priviledge */ - envcfg |= (3 << 4 | 1 << 6 | 1 << 7); - __set_MENVCFG(envcfg); -#endif -#endif - - cache_init(); - section_init(); - pmp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); - -#if CONFIG_ECC_L2_ENABLE - extern void ecc_l2_irqhandler(void *arg); - /* l2 cache ecc interrupt register */ - ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn; - csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev); - csi_irq_enable(ecc_l2_dev.irq_num); -#endif -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd-rv32/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd-rv32/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd-rv32/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd-rv32/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd-rv32/vectors.S deleted file mode 100644 index ef32af346ff..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd-rv32/vectors.S +++ /dev/null @@ -1,842 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, sepc - store_x t0, (68+68)(sp) - csrr t0, sstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, sepc - store_x t0, (68)(sp) - csrr t0, sstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw sepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68)(sp) - csrw sepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret - - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, sepc - store_x t0, (68+68)(sp) - csrr t0, sstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, sepc - store_x t0, (68)(sp) - csrr t0, sstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, do_irq - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - load_x t0, (72+72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw sepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - load_x t0, (72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68)(sp) - csrw sepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, sscratch - sret - -#if CONFIG_ECC_L1_ENABLE - .align 3 - .weak ECC_L1_Handler - .type ECC_L1_Handler, %function -ECC_L1_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, ECC_L1_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret -#endif - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - store_x s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - -#if __riscv_xlen == 64 - addi sp, sp, -(140+140) - store_x x1, ( 0 + 0 )(sp) - store_x x3, ( 8 + 8 )(sp) - store_x x4, ( 12+ 12)(sp) - store_x x5, ( 16+ 16)(sp) - store_x x6, ( 20+ 20)(sp) - store_x x7, ( 24+ 24)(sp) - store_x x8, ( 28+ 28)(sp) - store_x x9, ( 32+ 32)(sp) - store_x x10,( 36+ 36)(sp) - store_x x11,( 40+ 40)(sp) - store_x x12,( 44+ 44)(sp) - store_x x13,( 48+ 48)(sp) - store_x x14,( 52+ 52)(sp) - store_x x15,( 56+ 56)(sp) - store_x x16,( 60+ 60)(sp) - store_x x17,( 64+ 64)(sp) - store_x x18,( 68+ 68)(sp) - store_x x19,( 72+ 72)(sp) - store_x x20,( 76+ 76)(sp) - store_x x21,( 80+ 80)(sp) - store_x x22,( 84+ 84)(sp) - store_x x23,( 88+ 88)(sp) - store_x x24,( 92+ 92)(sp) - store_x x25,( 96+ 96)(sp) - store_x x26,(100+100)(sp) - store_x x27,(104+104)(sp) - store_x x28,(108+108)(sp) - store_x x29,(112+112)(sp) - store_x x30,(116+116)(sp) - store_x x31,(120+120)(sp) - csrr a0, mepc - store_x a0, (124+124)(sp) - csrr a0, mstatus - store_x a0, (128+128)(sp) - csrr a0, mcause - store_x a0, (132+132)(sp) - csrr a0, mtval - store_x a0, (136+136)(sp) - csrr a0, mscratch - store_x a0, ( 4 + 4 )(sp) -#else - addi sp, sp, -140 - store_x x1, ( 0 )(sp) - store_x x3, ( 8 )(sp) - store_x x4, ( 12)(sp) - store_x x5, ( 16)(sp) - store_x x6, ( 20)(sp) - store_x x7, ( 24)(sp) - store_x x8, ( 28)(sp) - store_x x9, ( 32)(sp) - store_x x10,( 36)(sp) - store_x x11,( 40)(sp) - store_x x12,( 44)(sp) - store_x x13,( 48)(sp) - store_x x14,( 52)(sp) - store_x x15,( 56)(sp) - store_x x16,( 60)(sp) - store_x x17,( 64)(sp) - store_x x18,( 68)(sp) - store_x x19,( 72)(sp) - store_x x20,( 76)(sp) - store_x x21,( 80)(sp) - store_x x22,( 84)(sp) - store_x x23,( 88)(sp) - store_x x24,( 92)(sp) - store_x x25,( 96)(sp) - store_x x26,(100)(sp) - store_x x27,(104)(sp) - store_x x28,(108)(sp) - store_x x29,(112)(sp) - store_x x30,(116)(sp) - store_x x31,(120)(sp) - csrr a0, mepc - store_x a0, (124)(sp) - csrr a0, mstatus - store_x a0, (128)(sp) - csrr a0, mcause - store_x a0, (132)(sp) - csrr a0, mtval - store_x a0, (136)(sp) - csrr a0, mscratch - store_x a0, ( 4 )(sp) -#endif - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd/startup.S deleted file mode 100644 index 92ba69989b2..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd/startup.S +++ /dev/null @@ -1,188 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.globl Reset_Handler - -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler /* 12 */ - j Default_Handler /* 13 */ - j Default_Handler /* 14 */ - j Default_Handler /* 15 */ -#if CONFIG_ECC_L1_ENABLE - j ECC_L1_Handler /* 16 */ -#else - j Default_Handler /* 16 */ -#endif - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 - - /* get cpu id */ - csrr a0, mhartid - -#if defined(CONFIG_SMP) && CONFIG_SMP - /* check if hart is within range */ - /* tp: hart id */ - li t0, CONFIG_NR_CPUS - bge a0, t0, hart_out_of_bounds_loop -#endif - -#ifdef CONFIG_KERNEL_NONE - la sp, g_base_mainstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_MAINSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */ -#else - la sp, g_base_irqstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ -#endif - - /* other cpu core, jump to cpu entry directly */ - bnez a0, secondary_cpu_entry - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, pre_main - jalr a0 - -.size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - .type secondary_cpu_entry, %function -secondary_cpu_entry: -#if defined(CONFIG_SMP) && CONFIG_SMP - la a0, secondary_boot_flag - ld a0, 0(a0) - li a1, 0xa55a - beq a0, a1, 1f -#endif - j secondary_cpu_entry - -#if defined(CONFIG_SMP) && CONFIG_SMP -1: - jal secondary_cpu_c_start - -.size secondary_cpu_entry, . - secondary_cpu_entry - -hart_out_of_bounds_loop: - /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ - wfi - j hart_out_of_bounds_loop -#endif - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS -g_top_irqstack: - -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS -g_top_mainstack: -#endif - -#if defined(CONFIG_SMP) && CONFIG_SMP -.data -.global secondary_boot_flag -.align 3 -secondary_boot_flag: - .dword 0 -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd/system.c deleted file mode 100644 index cccef03fd16..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd/system.c +++ /dev/null @@ -1,326 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP) -#if CONFIG_NR_CPUS > 1 -#error "Please define CONFIG_NR_CPUS as 1 or do not need define." -#endif -#endif - -#if CONFIG_ECC_L2_ENABLE -static csi_dev_t ecc_l2_dev; -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void interrupt_init(void) -{ - int i; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); -#if CONFIG_ECC_L1_ENABLE - mie |= (1 << 16); -#endif - __set_MIE(mie); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); -#if __riscv_matrix || __riscv_xtheadmatrix - /* enable matrix */ - status &= ~(1ul << 0); -#endif /* __riscv_matrix || __riscv_xtheadmatrix */ - __set_MXSTATUS(status); - -#if __riscv_flen - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif -#if __riscv_matrix || __riscv_xtheadmatrix - /* enable matrix ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_MS_SHIFT); - __set_MSTATUS(status); -#endif - -#if CONFIG_ECC_L1_ENABLE - /* enable L1 cache ecc */ - uint64_t mhint = __get_MHINT(); - mhint |= (0x1 << 19); - __set_MHINT(mhint); -#endif - -#if CONFIG_ECC_L2_ENABLE - /* enable L2 cache ecc */ - uint64_t mccr2 = __get_MCCR2(); - mccr2 |= (0x1 << 1); - __set_MCCR2(mccr2); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); - -#if CBO_INSN_SUPPORT - unsigned long envcfg = __get_MENVCFG(); - /* enable CBIE & CBCFE & CBZE on lower priviledge */ - envcfg |= (3 << 4 | 1 << 6 | 1 << 7); - __set_MENVCFG(envcfg); -#endif -#endif - - cache_init(); - section_init(); - pmp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); - -#if CONFIG_ECC_L2_ENABLE - extern void ecc_l2_irqhandler(void *arg); - /* l2 cache ecc interrupt register */ - ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn; - csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev); - csi_irq_enable(ecc_l2_dev.irq_num); -#endif -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd/vectors.S deleted file mode 100644 index ef32af346ff..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fd/vectors.S +++ /dev/null @@ -1,842 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, sepc - store_x t0, (68+68)(sp) - csrr t0, sstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, sepc - store_x t0, (68)(sp) - csrr t0, sstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw sepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68)(sp) - csrw sepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret - - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, sepc - store_x t0, (68+68)(sp) - csrr t0, sstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, sepc - store_x t0, (68)(sp) - csrr t0, sstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, do_irq - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - load_x t0, (72+72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw sepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - load_x t0, (72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68)(sp) - csrw sepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, sscratch - sret - -#if CONFIG_ECC_L1_ENABLE - .align 3 - .weak ECC_L1_Handler - .type ECC_L1_Handler, %function -ECC_L1_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, ECC_L1_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret -#endif - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - store_x s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - -#if __riscv_xlen == 64 - addi sp, sp, -(140+140) - store_x x1, ( 0 + 0 )(sp) - store_x x3, ( 8 + 8 )(sp) - store_x x4, ( 12+ 12)(sp) - store_x x5, ( 16+ 16)(sp) - store_x x6, ( 20+ 20)(sp) - store_x x7, ( 24+ 24)(sp) - store_x x8, ( 28+ 28)(sp) - store_x x9, ( 32+ 32)(sp) - store_x x10,( 36+ 36)(sp) - store_x x11,( 40+ 40)(sp) - store_x x12,( 44+ 44)(sp) - store_x x13,( 48+ 48)(sp) - store_x x14,( 52+ 52)(sp) - store_x x15,( 56+ 56)(sp) - store_x x16,( 60+ 60)(sp) - store_x x17,( 64+ 64)(sp) - store_x x18,( 68+ 68)(sp) - store_x x19,( 72+ 72)(sp) - store_x x20,( 76+ 76)(sp) - store_x x21,( 80+ 80)(sp) - store_x x22,( 84+ 84)(sp) - store_x x23,( 88+ 88)(sp) - store_x x24,( 92+ 92)(sp) - store_x x25,( 96+ 96)(sp) - store_x x26,(100+100)(sp) - store_x x27,(104+104)(sp) - store_x x28,(108+108)(sp) - store_x x29,(112+112)(sp) - store_x x30,(116+116)(sp) - store_x x31,(120+120)(sp) - csrr a0, mepc - store_x a0, (124+124)(sp) - csrr a0, mstatus - store_x a0, (128+128)(sp) - csrr a0, mcause - store_x a0, (132+132)(sp) - csrr a0, mtval - store_x a0, (136+136)(sp) - csrr a0, mscratch - store_x a0, ( 4 + 4 )(sp) -#else - addi sp, sp, -140 - store_x x1, ( 0 )(sp) - store_x x3, ( 8 )(sp) - store_x x4, ( 12)(sp) - store_x x5, ( 16)(sp) - store_x x6, ( 20)(sp) - store_x x7, ( 24)(sp) - store_x x8, ( 28)(sp) - store_x x9, ( 32)(sp) - store_x x10,( 36)(sp) - store_x x11,( 40)(sp) - store_x x12,( 44)(sp) - store_x x13,( 48)(sp) - store_x x14,( 52)(sp) - store_x x15,( 56)(sp) - store_x x16,( 60)(sp) - store_x x17,( 64)(sp) - store_x x18,( 68)(sp) - store_x x19,( 72)(sp) - store_x x20,( 76)(sp) - store_x x21,( 80)(sp) - store_x x22,( 84)(sp) - store_x x23,( 88)(sp) - store_x x24,( 92)(sp) - store_x x25,( 96)(sp) - store_x x26,(100)(sp) - store_x x27,(104)(sp) - store_x x28,(108)(sp) - store_x x29,(112)(sp) - store_x x30,(116)(sp) - store_x x31,(120)(sp) - csrr a0, mepc - store_x a0, (124)(sp) - csrr a0, mstatus - store_x a0, (128)(sp) - csrr a0, mcause - store_x a0, (132)(sp) - csrr a0, mtval - store_x a0, (136)(sp) - csrr a0, mscratch - store_x a0, ( 4 )(sp) -#endif - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv-rv32/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv-rv32/startup.S deleted file mode 100644 index 38a84acde3f..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv-rv32/startup.S +++ /dev/null @@ -1,188 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.globl Reset_Handler - -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler /* 12 */ - j Default_Handler /* 13 */ - j Default_Handler /* 14 */ - j Default_Handler /* 15 */ -#if CONFIG_ECC_L1_ENABLE - j ECC_L1_Handler /* 16 */ -#else - j Default_Handler /* 16 */ -#endif - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 - - /* get cpu id */ - csrr a0, mhartid - -#if defined(CONFIG_SMP) && CONFIG_SMP - /* check if hart is within range */ - /* tp: hart id */ - li t0, CONFIG_NR_CPUS - bge a0, t0, hart_out_of_bounds_loop -#endif - -#ifdef CONFIG_KERNEL_NONE - la sp, g_base_mainstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_MAINSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */ -#else - la sp, g_base_irqstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ -#endif - - /* other cpu core, jump to cpu entry directly */ - bnez a0, secondary_cpu_entry - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, pre_main - jalr a0 - -.size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - .type secondary_cpu_entry, %function -secondary_cpu_entry: -#if defined(CONFIG_SMP) && CONFIG_SMP - la a0, secondary_boot_flag - lw a0, 0(a0) - li a1, 0xa55a - beq a0, a1, 1f -#endif - j secondary_cpu_entry - -#if defined(CONFIG_SMP) && CONFIG_SMP -1: - jal secondary_cpu_c_start - -.size secondary_cpu_entry, . - secondary_cpu_entry - -hart_out_of_bounds_loop: - /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ - wfi - j hart_out_of_bounds_loop -#endif - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS -g_top_irqstack: - -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS -g_top_mainstack: -#endif - -#if defined(CONFIG_SMP) && CONFIG_SMP -.data -.global secondary_boot_flag -.align 3 -secondary_boot_flag: - .dword 0 -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv-rv32/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv-rv32/system.c deleted file mode 100644 index cccef03fd16..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv-rv32/system.c +++ /dev/null @@ -1,326 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP) -#if CONFIG_NR_CPUS > 1 -#error "Please define CONFIG_NR_CPUS as 1 or do not need define." -#endif -#endif - -#if CONFIG_ECC_L2_ENABLE -static csi_dev_t ecc_l2_dev; -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void interrupt_init(void) -{ - int i; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); -#if CONFIG_ECC_L1_ENABLE - mie |= (1 << 16); -#endif - __set_MIE(mie); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); -#if __riscv_matrix || __riscv_xtheadmatrix - /* enable matrix */ - status &= ~(1ul << 0); -#endif /* __riscv_matrix || __riscv_xtheadmatrix */ - __set_MXSTATUS(status); - -#if __riscv_flen - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif -#if __riscv_matrix || __riscv_xtheadmatrix - /* enable matrix ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_MS_SHIFT); - __set_MSTATUS(status); -#endif - -#if CONFIG_ECC_L1_ENABLE - /* enable L1 cache ecc */ - uint64_t mhint = __get_MHINT(); - mhint |= (0x1 << 19); - __set_MHINT(mhint); -#endif - -#if CONFIG_ECC_L2_ENABLE - /* enable L2 cache ecc */ - uint64_t mccr2 = __get_MCCR2(); - mccr2 |= (0x1 << 1); - __set_MCCR2(mccr2); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); - -#if CBO_INSN_SUPPORT - unsigned long envcfg = __get_MENVCFG(); - /* enable CBIE & CBCFE & CBZE on lower priviledge */ - envcfg |= (3 << 4 | 1 << 6 | 1 << 7); - __set_MENVCFG(envcfg); -#endif -#endif - - cache_init(); - section_init(); - pmp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); - -#if CONFIG_ECC_L2_ENABLE - extern void ecc_l2_irqhandler(void *arg); - /* l2 cache ecc interrupt register */ - ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn; - csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev); - csi_irq_enable(ecc_l2_dev.irq_num); -#endif -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv-rv32/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv-rv32/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv-rv32/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv-rv32/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv-rv32/vectors.S deleted file mode 100644 index ef32af346ff..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv-rv32/vectors.S +++ /dev/null @@ -1,842 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, sepc - store_x t0, (68+68)(sp) - csrr t0, sstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, sepc - store_x t0, (68)(sp) - csrr t0, sstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw sepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68)(sp) - csrw sepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret - - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, sepc - store_x t0, (68+68)(sp) - csrr t0, sstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, sepc - store_x t0, (68)(sp) - csrr t0, sstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, do_irq - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - load_x t0, (72+72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw sepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - load_x t0, (72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68)(sp) - csrw sepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, sscratch - sret - -#if CONFIG_ECC_L1_ENABLE - .align 3 - .weak ECC_L1_Handler - .type ECC_L1_Handler, %function -ECC_L1_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, ECC_L1_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret -#endif - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - store_x s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - -#if __riscv_xlen == 64 - addi sp, sp, -(140+140) - store_x x1, ( 0 + 0 )(sp) - store_x x3, ( 8 + 8 )(sp) - store_x x4, ( 12+ 12)(sp) - store_x x5, ( 16+ 16)(sp) - store_x x6, ( 20+ 20)(sp) - store_x x7, ( 24+ 24)(sp) - store_x x8, ( 28+ 28)(sp) - store_x x9, ( 32+ 32)(sp) - store_x x10,( 36+ 36)(sp) - store_x x11,( 40+ 40)(sp) - store_x x12,( 44+ 44)(sp) - store_x x13,( 48+ 48)(sp) - store_x x14,( 52+ 52)(sp) - store_x x15,( 56+ 56)(sp) - store_x x16,( 60+ 60)(sp) - store_x x17,( 64+ 64)(sp) - store_x x18,( 68+ 68)(sp) - store_x x19,( 72+ 72)(sp) - store_x x20,( 76+ 76)(sp) - store_x x21,( 80+ 80)(sp) - store_x x22,( 84+ 84)(sp) - store_x x23,( 88+ 88)(sp) - store_x x24,( 92+ 92)(sp) - store_x x25,( 96+ 96)(sp) - store_x x26,(100+100)(sp) - store_x x27,(104+104)(sp) - store_x x28,(108+108)(sp) - store_x x29,(112+112)(sp) - store_x x30,(116+116)(sp) - store_x x31,(120+120)(sp) - csrr a0, mepc - store_x a0, (124+124)(sp) - csrr a0, mstatus - store_x a0, (128+128)(sp) - csrr a0, mcause - store_x a0, (132+132)(sp) - csrr a0, mtval - store_x a0, (136+136)(sp) - csrr a0, mscratch - store_x a0, ( 4 + 4 )(sp) -#else - addi sp, sp, -140 - store_x x1, ( 0 )(sp) - store_x x3, ( 8 )(sp) - store_x x4, ( 12)(sp) - store_x x5, ( 16)(sp) - store_x x6, ( 20)(sp) - store_x x7, ( 24)(sp) - store_x x8, ( 28)(sp) - store_x x9, ( 32)(sp) - store_x x10,( 36)(sp) - store_x x11,( 40)(sp) - store_x x12,( 44)(sp) - store_x x13,( 48)(sp) - store_x x14,( 52)(sp) - store_x x15,( 56)(sp) - store_x x16,( 60)(sp) - store_x x17,( 64)(sp) - store_x x18,( 68)(sp) - store_x x19,( 72)(sp) - store_x x20,( 76)(sp) - store_x x21,( 80)(sp) - store_x x22,( 84)(sp) - store_x x23,( 88)(sp) - store_x x24,( 92)(sp) - store_x x25,( 96)(sp) - store_x x26,(100)(sp) - store_x x27,(104)(sp) - store_x x28,(108)(sp) - store_x x29,(112)(sp) - store_x x30,(116)(sp) - store_x x31,(120)(sp) - csrr a0, mepc - store_x a0, (124)(sp) - csrr a0, mstatus - store_x a0, (128)(sp) - csrr a0, mcause - store_x a0, (132)(sp) - csrr a0, mtval - store_x a0, (136)(sp) - csrr a0, mscratch - store_x a0, ( 4 )(sp) -#endif - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv/startup.S deleted file mode 100644 index 92ba69989b2..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv/startup.S +++ /dev/null @@ -1,188 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.globl Reset_Handler - -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler /* 12 */ - j Default_Handler /* 13 */ - j Default_Handler /* 14 */ - j Default_Handler /* 15 */ -#if CONFIG_ECC_L1_ENABLE - j ECC_L1_Handler /* 16 */ -#else - j Default_Handler /* 16 */ -#endif - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 - - /* get cpu id */ - csrr a0, mhartid - -#if defined(CONFIG_SMP) && CONFIG_SMP - /* check if hart is within range */ - /* tp: hart id */ - li t0, CONFIG_NR_CPUS - bge a0, t0, hart_out_of_bounds_loop -#endif - -#ifdef CONFIG_KERNEL_NONE - la sp, g_base_mainstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_MAINSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */ -#else - la sp, g_base_irqstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ -#endif - - /* other cpu core, jump to cpu entry directly */ - bnez a0, secondary_cpu_entry - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, pre_main - jalr a0 - -.size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - .type secondary_cpu_entry, %function -secondary_cpu_entry: -#if defined(CONFIG_SMP) && CONFIG_SMP - la a0, secondary_boot_flag - ld a0, 0(a0) - li a1, 0xa55a - beq a0, a1, 1f -#endif - j secondary_cpu_entry - -#if defined(CONFIG_SMP) && CONFIG_SMP -1: - jal secondary_cpu_c_start - -.size secondary_cpu_entry, . - secondary_cpu_entry - -hart_out_of_bounds_loop: - /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ - wfi - j hart_out_of_bounds_loop -#endif - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS -g_top_irqstack: - -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS -g_top_mainstack: -#endif - -#if defined(CONFIG_SMP) && CONFIG_SMP -.data -.global secondary_boot_flag -.align 3 -secondary_boot_flag: - .dword 0 -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv/system.c deleted file mode 100644 index cccef03fd16..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv/system.c +++ /dev/null @@ -1,326 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP) -#if CONFIG_NR_CPUS > 1 -#error "Please define CONFIG_NR_CPUS as 1 or do not need define." -#endif -#endif - -#if CONFIG_ECC_L2_ENABLE -static csi_dev_t ecc_l2_dev; -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void interrupt_init(void) -{ - int i; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); -#if CONFIG_ECC_L1_ENABLE - mie |= (1 << 16); -#endif - __set_MIE(mie); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); -#if __riscv_matrix || __riscv_xtheadmatrix - /* enable matrix */ - status &= ~(1ul << 0); -#endif /* __riscv_matrix || __riscv_xtheadmatrix */ - __set_MXSTATUS(status); - -#if __riscv_flen - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif -#if __riscv_matrix || __riscv_xtheadmatrix - /* enable matrix ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_MS_SHIFT); - __set_MSTATUS(status); -#endif - -#if CONFIG_ECC_L1_ENABLE - /* enable L1 cache ecc */ - uint64_t mhint = __get_MHINT(); - mhint |= (0x1 << 19); - __set_MHINT(mhint); -#endif - -#if CONFIG_ECC_L2_ENABLE - /* enable L2 cache ecc */ - uint64_t mccr2 = __get_MCCR2(); - mccr2 |= (0x1 << 1); - __set_MCCR2(mccr2); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); - -#if CBO_INSN_SUPPORT - unsigned long envcfg = __get_MENVCFG(); - /* enable CBIE & CBCFE & CBZE on lower priviledge */ - envcfg |= (3 << 4 | 1 << 6 | 1 << 7); - __set_MENVCFG(envcfg); -#endif -#endif - - cache_init(); - section_init(); - pmp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); - -#if CONFIG_ECC_L2_ENABLE - extern void ecc_l2_irqhandler(void *arg); - /* l2 cache ecc interrupt register */ - ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn; - csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev); - csi_irq_enable(ecc_l2_dev.irq_num); -#endif -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv/vectors.S deleted file mode 100644 index ef32af346ff..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdv/vectors.S +++ /dev/null @@ -1,842 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, sepc - store_x t0, (68+68)(sp) - csrr t0, sstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, sepc - store_x t0, (68)(sp) - csrr t0, sstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw sepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68)(sp) - csrw sepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret - - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, sepc - store_x t0, (68+68)(sp) - csrr t0, sstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, sepc - store_x t0, (68)(sp) - csrr t0, sstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, do_irq - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - load_x t0, (72+72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw sepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - load_x t0, (72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68)(sp) - csrw sepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, sscratch - sret - -#if CONFIG_ECC_L1_ENABLE - .align 3 - .weak ECC_L1_Handler - .type ECC_L1_Handler, %function -ECC_L1_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, ECC_L1_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret -#endif - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - store_x s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - -#if __riscv_xlen == 64 - addi sp, sp, -(140+140) - store_x x1, ( 0 + 0 )(sp) - store_x x3, ( 8 + 8 )(sp) - store_x x4, ( 12+ 12)(sp) - store_x x5, ( 16+ 16)(sp) - store_x x6, ( 20+ 20)(sp) - store_x x7, ( 24+ 24)(sp) - store_x x8, ( 28+ 28)(sp) - store_x x9, ( 32+ 32)(sp) - store_x x10,( 36+ 36)(sp) - store_x x11,( 40+ 40)(sp) - store_x x12,( 44+ 44)(sp) - store_x x13,( 48+ 48)(sp) - store_x x14,( 52+ 52)(sp) - store_x x15,( 56+ 56)(sp) - store_x x16,( 60+ 60)(sp) - store_x x17,( 64+ 64)(sp) - store_x x18,( 68+ 68)(sp) - store_x x19,( 72+ 72)(sp) - store_x x20,( 76+ 76)(sp) - store_x x21,( 80+ 80)(sp) - store_x x22,( 84+ 84)(sp) - store_x x23,( 88+ 88)(sp) - store_x x24,( 92+ 92)(sp) - store_x x25,( 96+ 96)(sp) - store_x x26,(100+100)(sp) - store_x x27,(104+104)(sp) - store_x x28,(108+108)(sp) - store_x x29,(112+112)(sp) - store_x x30,(116+116)(sp) - store_x x31,(120+120)(sp) - csrr a0, mepc - store_x a0, (124+124)(sp) - csrr a0, mstatus - store_x a0, (128+128)(sp) - csrr a0, mcause - store_x a0, (132+132)(sp) - csrr a0, mtval - store_x a0, (136+136)(sp) - csrr a0, mscratch - store_x a0, ( 4 + 4 )(sp) -#else - addi sp, sp, -140 - store_x x1, ( 0 )(sp) - store_x x3, ( 8 )(sp) - store_x x4, ( 12)(sp) - store_x x5, ( 16)(sp) - store_x x6, ( 20)(sp) - store_x x7, ( 24)(sp) - store_x x8, ( 28)(sp) - store_x x9, ( 32)(sp) - store_x x10,( 36)(sp) - store_x x11,( 40)(sp) - store_x x12,( 44)(sp) - store_x x13,( 48)(sp) - store_x x14,( 52)(sp) - store_x x15,( 56)(sp) - store_x x16,( 60)(sp) - store_x x17,( 64)(sp) - store_x x18,( 68)(sp) - store_x x19,( 72)(sp) - store_x x20,( 76)(sp) - store_x x21,( 80)(sp) - store_x x22,( 84)(sp) - store_x x23,( 88)(sp) - store_x x24,( 92)(sp) - store_x x25,( 96)(sp) - store_x x26,(100)(sp) - store_x x27,(104)(sp) - store_x x28,(108)(sp) - store_x x29,(112)(sp) - store_x x30,(116)(sp) - store_x x31,(120)(sp) - csrr a0, mepc - store_x a0, (124)(sp) - csrr a0, mstatus - store_x a0, (128)(sp) - csrr a0, mcause - store_x a0, (132)(sp) - csrr a0, mtval - store_x a0, (136)(sp) - csrr a0, mscratch - store_x a0, ( 4 )(sp) -#endif - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm-rv32/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm-rv32/startup.S deleted file mode 100644 index 38a84acde3f..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm-rv32/startup.S +++ /dev/null @@ -1,188 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.globl Reset_Handler - -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler /* 12 */ - j Default_Handler /* 13 */ - j Default_Handler /* 14 */ - j Default_Handler /* 15 */ -#if CONFIG_ECC_L1_ENABLE - j ECC_L1_Handler /* 16 */ -#else - j Default_Handler /* 16 */ -#endif - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 - - /* get cpu id */ - csrr a0, mhartid - -#if defined(CONFIG_SMP) && CONFIG_SMP - /* check if hart is within range */ - /* tp: hart id */ - li t0, CONFIG_NR_CPUS - bge a0, t0, hart_out_of_bounds_loop -#endif - -#ifdef CONFIG_KERNEL_NONE - la sp, g_base_mainstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_MAINSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */ -#else - la sp, g_base_irqstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ -#endif - - /* other cpu core, jump to cpu entry directly */ - bnez a0, secondary_cpu_entry - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, pre_main - jalr a0 - -.size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - .type secondary_cpu_entry, %function -secondary_cpu_entry: -#if defined(CONFIG_SMP) && CONFIG_SMP - la a0, secondary_boot_flag - lw a0, 0(a0) - li a1, 0xa55a - beq a0, a1, 1f -#endif - j secondary_cpu_entry - -#if defined(CONFIG_SMP) && CONFIG_SMP -1: - jal secondary_cpu_c_start - -.size secondary_cpu_entry, . - secondary_cpu_entry - -hart_out_of_bounds_loop: - /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ - wfi - j hart_out_of_bounds_loop -#endif - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS -g_top_irqstack: - -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS -g_top_mainstack: -#endif - -#if defined(CONFIG_SMP) && CONFIG_SMP -.data -.global secondary_boot_flag -.align 3 -secondary_boot_flag: - .dword 0 -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm-rv32/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm-rv32/system.c deleted file mode 100644 index cccef03fd16..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm-rv32/system.c +++ /dev/null @@ -1,326 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP) -#if CONFIG_NR_CPUS > 1 -#error "Please define CONFIG_NR_CPUS as 1 or do not need define." -#endif -#endif - -#if CONFIG_ECC_L2_ENABLE -static csi_dev_t ecc_l2_dev; -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void interrupt_init(void) -{ - int i; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); -#if CONFIG_ECC_L1_ENABLE - mie |= (1 << 16); -#endif - __set_MIE(mie); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); -#if __riscv_matrix || __riscv_xtheadmatrix - /* enable matrix */ - status &= ~(1ul << 0); -#endif /* __riscv_matrix || __riscv_xtheadmatrix */ - __set_MXSTATUS(status); - -#if __riscv_flen - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif -#if __riscv_matrix || __riscv_xtheadmatrix - /* enable matrix ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_MS_SHIFT); - __set_MSTATUS(status); -#endif - -#if CONFIG_ECC_L1_ENABLE - /* enable L1 cache ecc */ - uint64_t mhint = __get_MHINT(); - mhint |= (0x1 << 19); - __set_MHINT(mhint); -#endif - -#if CONFIG_ECC_L2_ENABLE - /* enable L2 cache ecc */ - uint64_t mccr2 = __get_MCCR2(); - mccr2 |= (0x1 << 1); - __set_MCCR2(mccr2); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); - -#if CBO_INSN_SUPPORT - unsigned long envcfg = __get_MENVCFG(); - /* enable CBIE & CBCFE & CBZE on lower priviledge */ - envcfg |= (3 << 4 | 1 << 6 | 1 << 7); - __set_MENVCFG(envcfg); -#endif -#endif - - cache_init(); - section_init(); - pmp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); - -#if CONFIG_ECC_L2_ENABLE - extern void ecc_l2_irqhandler(void *arg); - /* l2 cache ecc interrupt register */ - ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn; - csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev); - csi_irq_enable(ecc_l2_dev.irq_num); -#endif -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm-rv32/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm-rv32/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm-rv32/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm-rv32/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm-rv32/vectors.S deleted file mode 100644 index ef32af346ff..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm-rv32/vectors.S +++ /dev/null @@ -1,842 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, sepc - store_x t0, (68+68)(sp) - csrr t0, sstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, sepc - store_x t0, (68)(sp) - csrr t0, sstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw sepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68)(sp) - csrw sepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret - - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, sepc - store_x t0, (68+68)(sp) - csrr t0, sstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, sepc - store_x t0, (68)(sp) - csrr t0, sstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, do_irq - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - load_x t0, (72+72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw sepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - load_x t0, (72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68)(sp) - csrw sepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, sscratch - sret - -#if CONFIG_ECC_L1_ENABLE - .align 3 - .weak ECC_L1_Handler - .type ECC_L1_Handler, %function -ECC_L1_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, ECC_L1_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret -#endif - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - store_x s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - -#if __riscv_xlen == 64 - addi sp, sp, -(140+140) - store_x x1, ( 0 + 0 )(sp) - store_x x3, ( 8 + 8 )(sp) - store_x x4, ( 12+ 12)(sp) - store_x x5, ( 16+ 16)(sp) - store_x x6, ( 20+ 20)(sp) - store_x x7, ( 24+ 24)(sp) - store_x x8, ( 28+ 28)(sp) - store_x x9, ( 32+ 32)(sp) - store_x x10,( 36+ 36)(sp) - store_x x11,( 40+ 40)(sp) - store_x x12,( 44+ 44)(sp) - store_x x13,( 48+ 48)(sp) - store_x x14,( 52+ 52)(sp) - store_x x15,( 56+ 56)(sp) - store_x x16,( 60+ 60)(sp) - store_x x17,( 64+ 64)(sp) - store_x x18,( 68+ 68)(sp) - store_x x19,( 72+ 72)(sp) - store_x x20,( 76+ 76)(sp) - store_x x21,( 80+ 80)(sp) - store_x x22,( 84+ 84)(sp) - store_x x23,( 88+ 88)(sp) - store_x x24,( 92+ 92)(sp) - store_x x25,( 96+ 96)(sp) - store_x x26,(100+100)(sp) - store_x x27,(104+104)(sp) - store_x x28,(108+108)(sp) - store_x x29,(112+112)(sp) - store_x x30,(116+116)(sp) - store_x x31,(120+120)(sp) - csrr a0, mepc - store_x a0, (124+124)(sp) - csrr a0, mstatus - store_x a0, (128+128)(sp) - csrr a0, mcause - store_x a0, (132+132)(sp) - csrr a0, mtval - store_x a0, (136+136)(sp) - csrr a0, mscratch - store_x a0, ( 4 + 4 )(sp) -#else - addi sp, sp, -140 - store_x x1, ( 0 )(sp) - store_x x3, ( 8 )(sp) - store_x x4, ( 12)(sp) - store_x x5, ( 16)(sp) - store_x x6, ( 20)(sp) - store_x x7, ( 24)(sp) - store_x x8, ( 28)(sp) - store_x x9, ( 32)(sp) - store_x x10,( 36)(sp) - store_x x11,( 40)(sp) - store_x x12,( 44)(sp) - store_x x13,( 48)(sp) - store_x x14,( 52)(sp) - store_x x15,( 56)(sp) - store_x x16,( 60)(sp) - store_x x17,( 64)(sp) - store_x x18,( 68)(sp) - store_x x19,( 72)(sp) - store_x x20,( 76)(sp) - store_x x21,( 80)(sp) - store_x x22,( 84)(sp) - store_x x23,( 88)(sp) - store_x x24,( 92)(sp) - store_x x25,( 96)(sp) - store_x x26,(100)(sp) - store_x x27,(104)(sp) - store_x x28,(108)(sp) - store_x x29,(112)(sp) - store_x x30,(116)(sp) - store_x x31,(120)(sp) - csrr a0, mepc - store_x a0, (124)(sp) - csrr a0, mstatus - store_x a0, (128)(sp) - csrr a0, mcause - store_x a0, (132)(sp) - csrr a0, mtval - store_x a0, (136)(sp) - csrr a0, mscratch - store_x a0, ( 4 )(sp) -#endif - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm/startup.S deleted file mode 100644 index 92ba69989b2..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm/startup.S +++ /dev/null @@ -1,188 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.globl Reset_Handler - -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler /* 12 */ - j Default_Handler /* 13 */ - j Default_Handler /* 14 */ - j Default_Handler /* 15 */ -#if CONFIG_ECC_L1_ENABLE - j ECC_L1_Handler /* 16 */ -#else - j Default_Handler /* 16 */ -#endif - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 - - /* get cpu id */ - csrr a0, mhartid - -#if defined(CONFIG_SMP) && CONFIG_SMP - /* check if hart is within range */ - /* tp: hart id */ - li t0, CONFIG_NR_CPUS - bge a0, t0, hart_out_of_bounds_loop -#endif - -#ifdef CONFIG_KERNEL_NONE - la sp, g_base_mainstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_MAINSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */ -#else - la sp, g_base_irqstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ -#endif - - /* other cpu core, jump to cpu entry directly */ - bnez a0, secondary_cpu_entry - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, pre_main - jalr a0 - -.size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - .type secondary_cpu_entry, %function -secondary_cpu_entry: -#if defined(CONFIG_SMP) && CONFIG_SMP - la a0, secondary_boot_flag - ld a0, 0(a0) - li a1, 0xa55a - beq a0, a1, 1f -#endif - j secondary_cpu_entry - -#if defined(CONFIG_SMP) && CONFIG_SMP -1: - jal secondary_cpu_c_start - -.size secondary_cpu_entry, . - secondary_cpu_entry - -hart_out_of_bounds_loop: - /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ - wfi - j hart_out_of_bounds_loop -#endif - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS -g_top_irqstack: - -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS -g_top_mainstack: -#endif - -#if defined(CONFIG_SMP) && CONFIG_SMP -.data -.global secondary_boot_flag -.align 3 -secondary_boot_flag: - .dword 0 -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm/system.c deleted file mode 100644 index cccef03fd16..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm/system.c +++ /dev/null @@ -1,326 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP) -#if CONFIG_NR_CPUS > 1 -#error "Please define CONFIG_NR_CPUS as 1 or do not need define." -#endif -#endif - -#if CONFIG_ECC_L2_ENABLE -static csi_dev_t ecc_l2_dev; -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void interrupt_init(void) -{ - int i; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); -#if CONFIG_ECC_L1_ENABLE - mie |= (1 << 16); -#endif - __set_MIE(mie); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); -#if __riscv_matrix || __riscv_xtheadmatrix - /* enable matrix */ - status &= ~(1ul << 0); -#endif /* __riscv_matrix || __riscv_xtheadmatrix */ - __set_MXSTATUS(status); - -#if __riscv_flen - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif -#if __riscv_matrix || __riscv_xtheadmatrix - /* enable matrix ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_MS_SHIFT); - __set_MSTATUS(status); -#endif - -#if CONFIG_ECC_L1_ENABLE - /* enable L1 cache ecc */ - uint64_t mhint = __get_MHINT(); - mhint |= (0x1 << 19); - __set_MHINT(mhint); -#endif - -#if CONFIG_ECC_L2_ENABLE - /* enable L2 cache ecc */ - uint64_t mccr2 = __get_MCCR2(); - mccr2 |= (0x1 << 1); - __set_MCCR2(mccr2); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); - -#if CBO_INSN_SUPPORT - unsigned long envcfg = __get_MENVCFG(); - /* enable CBIE & CBCFE & CBZE on lower priviledge */ - envcfg |= (3 << 4 | 1 << 6 | 1 << 7); - __set_MENVCFG(envcfg); -#endif -#endif - - cache_init(); - section_init(); - pmp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); - -#if CONFIG_ECC_L2_ENABLE - extern void ecc_l2_irqhandler(void *arg); - /* l2 cache ecc interrupt register */ - ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn; - csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev); - csi_irq_enable(ecc_l2_dev.irq_num); -#endif -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm/vectors.S deleted file mode 100644 index ef32af346ff..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907fdvm/vectors.S +++ /dev/null @@ -1,842 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, sepc - store_x t0, (68+68)(sp) - csrr t0, sstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, sepc - store_x t0, (68)(sp) - csrr t0, sstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw sepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68)(sp) - csrw sepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret - - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, sepc - store_x t0, (68+68)(sp) - csrr t0, sstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, sepc - store_x t0, (68)(sp) - csrr t0, sstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, do_irq - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - load_x t0, (72+72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw sepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - load_x t0, (72)(sp) - csrw sstatus, t0 -#endif - load_x t0, (68)(sp) - csrw sepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, sscratch - sret - -#if CONFIG_ECC_L1_ENABLE - .align 3 - .weak ECC_L1_Handler - .type ECC_L1_Handler, %function -ECC_L1_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, ECC_L1_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret -#endif - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: - addi sp, sp, -16 - store_x t0, (0)(sp) - store_x t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - store_x s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if __riscv_xlen == 64 - addi sp, sp, -(76+76) - store_x t0, (4+4)(sp) - store_x t1, (8+8)(sp) - store_x t2, (12+12)(sp) - - csrr t0, mepc - store_x t0, (68+68)(sp) - csrr t0, mstatus - store_x t0, (72+72)(sp) - - store_x ra, (0 +0 )(sp) - store_x a0, (16+16)(sp) - store_x a1, (20+20)(sp) - store_x a2, (24+24)(sp) - store_x a3, (28+28)(sp) - store_x a4, (32+32)(sp) - store_x a5, (36+36)(sp) - store_x a6, (40+40)(sp) - store_x a7, (44+44)(sp) - store_x t3, (48+48)(sp) - store_x t4, (52+52)(sp) - store_x t5, (56+56)(sp) - store_x t6, (60+60)(sp) -#else - addi sp, sp, -76 - store_x t0, (4)(sp) - store_x t1, (8)(sp) - store_x t2, (12)(sp) - - csrr t0, mepc - store_x t0, (68)(sp) - csrr t0, mstatus - store_x t0, (72)(sp) - - store_x ra, (0)(sp) - store_x a0, (16)(sp) - store_x a1, (20)(sp) - store_x a2, (24)(sp) - store_x a3, (28)(sp) - store_x a4, (32)(sp) - store_x a5, (36)(sp) - store_x a6, (40)(sp) - store_x a7, (44)(sp) - store_x t3, (48)(sp) - store_x t4, (52)(sp) - store_x t5, (56)(sp) - store_x t6, (60)(sp) -#endif - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - SAVE_MATRIX_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_MATRIX_REGISTERS - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if __riscv_xlen == 64 -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72+72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68+68)(sp) - csrw mepc, t0 - - load_x ra, (0 +0 )(sp) - load_x t0, (4 +4 )(sp) - load_x t1, (8 +8 )(sp) - load_x t2, (12+12)(sp) - load_x a0, (16+16)(sp) - load_x a1, (20+20)(sp) - load_x a2, (24+24)(sp) - load_x a3, (28+28)(sp) - load_x a4, (32+32)(sp) - load_x a5, (36+36)(sp) - load_x a6, (40+40)(sp) - load_x a7, (44+44)(sp) - load_x t3, (48+48)(sp) - load_x t4, (52+52)(sp) - load_x t5, (56+56)(sp) - load_x t6, (60+60)(sp) - addi sp, sp, (76+76) -#else -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) && (!CONFIG_CHECK_MATRIX_DIRTY) - load_x t0, (72)(sp) - csrw mstatus, t0 -#endif - load_x t0, (68)(sp) - csrw mepc, t0 - - load_x ra, (0)(sp) - load_x t0, (4)(sp) - load_x t1, (8)(sp) - load_x t2, (12)(sp) - load_x a0, (16)(sp) - load_x a1, (20)(sp) - load_x a2, (24)(sp) - load_x a3, (28)(sp) - load_x a4, (32)(sp) - load_x a5, (36)(sp) - load_x a6, (40)(sp) - load_x a7, (44)(sp) - load_x t3, (48)(sp) - load_x t4, (52)(sp) - load_x t5, (56)(sp) - load_x t6, (60)(sp) - addi sp, sp, (76) -#endif - csrr sp, mscratch - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - load_x t0, (0)(sp) - load_x t1, (8)(sp) - addi sp, sp, 16 - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - -#if __riscv_xlen == 64 - addi sp, sp, -(140+140) - store_x x1, ( 0 + 0 )(sp) - store_x x3, ( 8 + 8 )(sp) - store_x x4, ( 12+ 12)(sp) - store_x x5, ( 16+ 16)(sp) - store_x x6, ( 20+ 20)(sp) - store_x x7, ( 24+ 24)(sp) - store_x x8, ( 28+ 28)(sp) - store_x x9, ( 32+ 32)(sp) - store_x x10,( 36+ 36)(sp) - store_x x11,( 40+ 40)(sp) - store_x x12,( 44+ 44)(sp) - store_x x13,( 48+ 48)(sp) - store_x x14,( 52+ 52)(sp) - store_x x15,( 56+ 56)(sp) - store_x x16,( 60+ 60)(sp) - store_x x17,( 64+ 64)(sp) - store_x x18,( 68+ 68)(sp) - store_x x19,( 72+ 72)(sp) - store_x x20,( 76+ 76)(sp) - store_x x21,( 80+ 80)(sp) - store_x x22,( 84+ 84)(sp) - store_x x23,( 88+ 88)(sp) - store_x x24,( 92+ 92)(sp) - store_x x25,( 96+ 96)(sp) - store_x x26,(100+100)(sp) - store_x x27,(104+104)(sp) - store_x x28,(108+108)(sp) - store_x x29,(112+112)(sp) - store_x x30,(116+116)(sp) - store_x x31,(120+120)(sp) - csrr a0, mepc - store_x a0, (124+124)(sp) - csrr a0, mstatus - store_x a0, (128+128)(sp) - csrr a0, mcause - store_x a0, (132+132)(sp) - csrr a0, mtval - store_x a0, (136+136)(sp) - csrr a0, mscratch - store_x a0, ( 4 + 4 )(sp) -#else - addi sp, sp, -140 - store_x x1, ( 0 )(sp) - store_x x3, ( 8 )(sp) - store_x x4, ( 12)(sp) - store_x x5, ( 16)(sp) - store_x x6, ( 20)(sp) - store_x x7, ( 24)(sp) - store_x x8, ( 28)(sp) - store_x x9, ( 32)(sp) - store_x x10,( 36)(sp) - store_x x11,( 40)(sp) - store_x x12,( 44)(sp) - store_x x13,( 48)(sp) - store_x x14,( 52)(sp) - store_x x15,( 56)(sp) - store_x x16,( 60)(sp) - store_x x17,( 64)(sp) - store_x x18,( 68)(sp) - store_x x19,( 72)(sp) - store_x x20,( 76)(sp) - store_x x21,( 80)(sp) - store_x x22,( 84)(sp) - store_x x23,( 88)(sp) - store_x x24,( 92)(sp) - store_x x25,( 96)(sp) - store_x x26,(100)(sp) - store_x x27,(104)(sp) - store_x x28,(108)(sp) - store_x x29,(112)(sp) - store_x x30,(116)(sp) - store_x x31,(120)(sp) - csrr a0, mepc - store_x a0, (124)(sp) - csrr a0, mstatus - store_x a0, (128)(sp) - csrr a0, mcause - store_x a0, (132)(sp) - csrr a0, mtval - store_x a0, (136)(sp) - csrr a0, mscratch - store_x a0, ( 4 )(sp) -#endif - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908/SConscript b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908/SConscript new file mode 100644 index 00000000000..7c13ee46652 --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908/SConscript @@ -0,0 +1,13 @@ +from building import * +import os + +cwd = GetCurrentDir() +CPPPATH = [cwd] +src = ['startup.S'] +src += ['system.c'] +src += ['trap_c.c'] +src += ['vectors.S'] + +group = DefineGroup('sys', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908/startup.S index 92ba69989b2..5877d711f25 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908/startup.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908/startup.S @@ -23,7 +23,9 @@ #endif .globl Reset_Handler - +.global __rt_rvstack +.equ Mcoret_Handler, SW_handler +.equ Mirq_Handler, SW_handler .section .vectors .align 6 .globl __Vectors @@ -132,7 +134,7 @@ Reset_Handler: #endif #endif - la a0, pre_main + la a0, rtthread_startup jalr a0 .size Reset_Handler, . - Reset_Handler @@ -169,6 +171,7 @@ hart_out_of_bounds_loop: g_base_irqstack: .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS g_top_irqstack: +__rt_rvstack: #ifdef CONFIG_KERNEL_NONE .align 4 diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908i/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908i/startup.S deleted file mode 100644 index 92ba69989b2..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908i/startup.S +++ /dev/null @@ -1,188 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.globl Reset_Handler - -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler /* 12 */ - j Default_Handler /* 13 */ - j Default_Handler /* 14 */ - j Default_Handler /* 15 */ -#if CONFIG_ECC_L1_ENABLE - j ECC_L1_Handler /* 16 */ -#else - j Default_Handler /* 16 */ -#endif - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 - - /* get cpu id */ - csrr a0, mhartid - -#if defined(CONFIG_SMP) && CONFIG_SMP - /* check if hart is within range */ - /* tp: hart id */ - li t0, CONFIG_NR_CPUS - bge a0, t0, hart_out_of_bounds_loop -#endif - -#ifdef CONFIG_KERNEL_NONE - la sp, g_base_mainstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_MAINSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */ -#else - la sp, g_base_irqstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ -#endif - - /* other cpu core, jump to cpu entry directly */ - bnez a0, secondary_cpu_entry - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, pre_main - jalr a0 - -.size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - .type secondary_cpu_entry, %function -secondary_cpu_entry: -#if defined(CONFIG_SMP) && CONFIG_SMP - la a0, secondary_boot_flag - ld a0, 0(a0) - li a1, 0xa55a - beq a0, a1, 1f -#endif - j secondary_cpu_entry - -#if defined(CONFIG_SMP) && CONFIG_SMP -1: - jal secondary_cpu_c_start - -.size secondary_cpu_entry, . - secondary_cpu_entry - -hart_out_of_bounds_loop: - /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ - wfi - j hart_out_of_bounds_loop -#endif - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS -g_top_irqstack: - -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS -g_top_mainstack: -#endif - -#if defined(CONFIG_SMP) && CONFIG_SMP -.data -.global secondary_boot_flag -.align 3 -secondary_boot_flag: - .dword 0 -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908i/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908i/system.c deleted file mode 100644 index dfa4b9bfb9a..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908i/system.c +++ /dev/null @@ -1,316 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP) -#if CONFIG_NR_CPUS > 1 -#error "Please define CONFIG_NR_CPUS as 1 or do not need define." -#endif -#endif - -#if CONFIG_ECC_L2_ENABLE -static csi_dev_t ecc_l2_dev; -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void interrupt_init(void) -{ - int i; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); -#if CONFIG_ECC_L1_ENABLE - mie |= (1 << 16); -#endif - __set_MIE(mie); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); - -#if __riscv_flen == 64 - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif - -#if CONFIG_ECC_L1_ENABLE - /* enable L1 cache ecc */ - uint64_t mhint = __get_MHINT(); - mhint |= (0x1 << 19); - __set_MHINT(mhint); -#endif - -#if CONFIG_ECC_L2_ENABLE - /* enable L2 cache ecc */ - uint64_t mccr2 = __get_MCCR2(); - mccr2 |= (0x1 << 1); - __set_MCCR2(mccr2); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); - -#if CBO_INSN_SUPPORT - unsigned long envcfg = __get_MENVCFG(); - /* enable CBIE & CBCFE & CBZE on lower priviledge */ - envcfg |= (3 << 4 | 1 << 6 | 1 << 7); - __set_MENVCFG(envcfg); -#endif -#endif - - cache_init(); - section_init(); - pmp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); - -#if CONFIG_ECC_L2_ENABLE - extern void ecc_l2_irqhandler(void *arg); - /* l2 cache ecc interrupt register */ - ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn; - csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev); - csi_irq_enable(ecc_l2_dev.irq_num); -#endif -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908i/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908i/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908i/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908i/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908i/vectors.S deleted file mode 100644 index 317c7d4e93d..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908i/vectors.S +++ /dev/null @@ -1,527 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw sstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - -#if CONFIG_ECC_L1_ENABLE - .align 3 - .weak ECC_L1_Handler - .type ECC_L1_Handler, %function -ECC_L1_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, ECC_L1_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret -#endif - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw sstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - sd s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -(140+140) - sd x1, ( 0 + 0 )(sp) - sd x3, ( 8 + 8 )(sp) - sd x4, ( 12+ 12)(sp) - sd x5, ( 16+ 16)(sp) - sd x6, ( 20+ 20)(sp) - sd x7, ( 24+ 24)(sp) - sd x8, ( 28+ 28)(sp) - sd x9, ( 32+ 32)(sp) - sd x10,( 36+ 36)(sp) - sd x11,( 40+ 40)(sp) - sd x12,( 44+ 44)(sp) - sd x13,( 48+ 48)(sp) - sd x14,( 52+ 52)(sp) - sd x15,( 56+ 56)(sp) - sd x16,( 60+ 60)(sp) - sd x17,( 64+ 64)(sp) - sd x18,( 68+ 68)(sp) - sd x19,( 72+ 72)(sp) - sd x20,( 76+ 76)(sp) - sd x21,( 80+ 80)(sp) - sd x22,( 84+ 84)(sp) - sd x23,( 88+ 88)(sp) - sd x24,( 92+ 92)(sp) - sd x25,( 96+ 96)(sp) - sd x26,(100+100)(sp) - sd x27,(104+104)(sp) - sd x28,(108+108)(sp) - sd x29,(112+112)(sp) - sd x30,(116+116)(sp) - sd x31,(120+120)(sp) - csrr a0, mepc - sd a0, (124+124)(sp) - csrr a0, mstatus - sd a0, (128+128)(sp) - csrr a0, mcause - sd a0, (132+132)(sp) - csrr a0, mtval - sd a0, (136+136)(sp) - csrr a0, mscratch - sd a0, ( 4 + 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/startup.S deleted file mode 100644 index 92ba69989b2..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/startup.S +++ /dev/null @@ -1,188 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.globl Reset_Handler - -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler /* 12 */ - j Default_Handler /* 13 */ - j Default_Handler /* 14 */ - j Default_Handler /* 15 */ -#if CONFIG_ECC_L1_ENABLE - j ECC_L1_Handler /* 16 */ -#else - j Default_Handler /* 16 */ -#endif - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 - - /* get cpu id */ - csrr a0, mhartid - -#if defined(CONFIG_SMP) && CONFIG_SMP - /* check if hart is within range */ - /* tp: hart id */ - li t0, CONFIG_NR_CPUS - bge a0, t0, hart_out_of_bounds_loop -#endif - -#ifdef CONFIG_KERNEL_NONE - la sp, g_base_mainstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_MAINSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */ -#else - la sp, g_base_irqstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ -#endif - - /* other cpu core, jump to cpu entry directly */ - bnez a0, secondary_cpu_entry - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, pre_main - jalr a0 - -.size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - .type secondary_cpu_entry, %function -secondary_cpu_entry: -#if defined(CONFIG_SMP) && CONFIG_SMP - la a0, secondary_boot_flag - ld a0, 0(a0) - li a1, 0xa55a - beq a0, a1, 1f -#endif - j secondary_cpu_entry - -#if defined(CONFIG_SMP) && CONFIG_SMP -1: - jal secondary_cpu_c_start - -.size secondary_cpu_entry, . - secondary_cpu_entry - -hart_out_of_bounds_loop: - /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ - wfi - j hart_out_of_bounds_loop -#endif - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS -g_top_irqstack: - -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS -g_top_mainstack: -#endif - -#if defined(CONFIG_SMP) && CONFIG_SMP -.data -.global secondary_boot_flag -.align 3 -secondary_boot_flag: - .dword 0 -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/system.c deleted file mode 100644 index dfa4b9bfb9a..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/system.c +++ /dev/null @@ -1,316 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP) -#if CONFIG_NR_CPUS > 1 -#error "Please define CONFIG_NR_CPUS as 1 or do not need define." -#endif -#endif - -#if CONFIG_ECC_L2_ENABLE -static csi_dev_t ecc_l2_dev; -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void interrupt_init(void) -{ - int i; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); -#if CONFIG_ECC_L1_ENABLE - mie |= (1 << 16); -#endif - __set_MIE(mie); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); - -#if __riscv_flen == 64 - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif - -#if CONFIG_ECC_L1_ENABLE - /* enable L1 cache ecc */ - uint64_t mhint = __get_MHINT(); - mhint |= (0x1 << 19); - __set_MHINT(mhint); -#endif - -#if CONFIG_ECC_L2_ENABLE - /* enable L2 cache ecc */ - uint64_t mccr2 = __get_MCCR2(); - mccr2 |= (0x1 << 1); - __set_MCCR2(mccr2); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); - -#if CBO_INSN_SUPPORT - unsigned long envcfg = __get_MENVCFG(); - /* enable CBIE & CBCFE & CBZE on lower priviledge */ - envcfg |= (3 << 4 | 1 << 6 | 1 << 7); - __set_MENVCFG(envcfg); -#endif -#endif - - cache_init(); - section_init(); - pmp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); - -#if CONFIG_ECC_L2_ENABLE - extern void ecc_l2_irqhandler(void *arg); - /* l2 cache ecc interrupt register */ - ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn; - csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev); - csi_irq_enable(ecc_l2_dev.irq_num); -#endif -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/vectors.S deleted file mode 100644 index 317c7d4e93d..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/vectors.S +++ /dev/null @@ -1,527 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw sstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - -#if CONFIG_ECC_L1_ENABLE - .align 3 - .weak ECC_L1_Handler - .type ECC_L1_Handler, %function -ECC_L1_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, ECC_L1_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret -#endif - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw sstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - sd s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -(140+140) - sd x1, ( 0 + 0 )(sp) - sd x3, ( 8 + 8 )(sp) - sd x4, ( 12+ 12)(sp) - sd x5, ( 16+ 16)(sp) - sd x6, ( 20+ 20)(sp) - sd x7, ( 24+ 24)(sp) - sd x8, ( 28+ 28)(sp) - sd x9, ( 32+ 32)(sp) - sd x10,( 36+ 36)(sp) - sd x11,( 40+ 40)(sp) - sd x12,( 44+ 44)(sp) - sd x13,( 48+ 48)(sp) - sd x14,( 52+ 52)(sp) - sd x15,( 56+ 56)(sp) - sd x16,( 60+ 60)(sp) - sd x17,( 64+ 64)(sp) - sd x18,( 68+ 68)(sp) - sd x19,( 72+ 72)(sp) - sd x20,( 76+ 76)(sp) - sd x21,( 80+ 80)(sp) - sd x22,( 84+ 84)(sp) - sd x23,( 88+ 88)(sp) - sd x24,( 92+ 92)(sp) - sd x25,( 96+ 96)(sp) - sd x26,(100+100)(sp) - sd x27,(104+104)(sp) - sd x28,(108+108)(sp) - sd x29,(112+112)(sp) - sd x30,(116+116)(sp) - sd x31,(120+120)(sp) - csrr a0, mepc - sd a0, (124+124)(sp) - csrr a0, mstatus - sd a0, (128+128)(sp) - csrr a0, mcause - sd a0, (132+132)(sp) - csrr a0, mtval - sd a0, (136+136)(sp) - csrr a0, mscratch - sd a0, ( 4 + 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v2/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v2/startup.S deleted file mode 100644 index 92ba69989b2..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v2/startup.S +++ /dev/null @@ -1,188 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.globl Reset_Handler - -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler /* 12 */ - j Default_Handler /* 13 */ - j Default_Handler /* 14 */ - j Default_Handler /* 15 */ -#if CONFIG_ECC_L1_ENABLE - j ECC_L1_Handler /* 16 */ -#else - j Default_Handler /* 16 */ -#endif - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 - - /* get cpu id */ - csrr a0, mhartid - -#if defined(CONFIG_SMP) && CONFIG_SMP - /* check if hart is within range */ - /* tp: hart id */ - li t0, CONFIG_NR_CPUS - bge a0, t0, hart_out_of_bounds_loop -#endif - -#ifdef CONFIG_KERNEL_NONE - la sp, g_base_mainstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_MAINSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */ -#else - la sp, g_base_irqstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ -#endif - - /* other cpu core, jump to cpu entry directly */ - bnez a0, secondary_cpu_entry - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, pre_main - jalr a0 - -.size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - .type secondary_cpu_entry, %function -secondary_cpu_entry: -#if defined(CONFIG_SMP) && CONFIG_SMP - la a0, secondary_boot_flag - ld a0, 0(a0) - li a1, 0xa55a - beq a0, a1, 1f -#endif - j secondary_cpu_entry - -#if defined(CONFIG_SMP) && CONFIG_SMP -1: - jal secondary_cpu_c_start - -.size secondary_cpu_entry, . - secondary_cpu_entry - -hart_out_of_bounds_loop: - /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ - wfi - j hart_out_of_bounds_loop -#endif - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS -g_top_irqstack: - -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS -g_top_mainstack: -#endif - -#if defined(CONFIG_SMP) && CONFIG_SMP -.data -.global secondary_boot_flag -.align 3 -secondary_boot_flag: - .dword 0 -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v2/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v2/system.c deleted file mode 100644 index dfa4b9bfb9a..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v2/system.c +++ /dev/null @@ -1,316 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP) -#if CONFIG_NR_CPUS > 1 -#error "Please define CONFIG_NR_CPUS as 1 or do not need define." -#endif -#endif - -#if CONFIG_ECC_L2_ENABLE -static csi_dev_t ecc_l2_dev; -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void interrupt_init(void) -{ - int i; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); -#if CONFIG_ECC_L1_ENABLE - mie |= (1 << 16); -#endif - __set_MIE(mie); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); - -#if __riscv_flen == 64 - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif - -#if CONFIG_ECC_L1_ENABLE - /* enable L1 cache ecc */ - uint64_t mhint = __get_MHINT(); - mhint |= (0x1 << 19); - __set_MHINT(mhint); -#endif - -#if CONFIG_ECC_L2_ENABLE - /* enable L2 cache ecc */ - uint64_t mccr2 = __get_MCCR2(); - mccr2 |= (0x1 << 1); - __set_MCCR2(mccr2); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); - -#if CBO_INSN_SUPPORT - unsigned long envcfg = __get_MENVCFG(); - /* enable CBIE & CBCFE & CBZE on lower priviledge */ - envcfg |= (3 << 4 | 1 << 6 | 1 << 7); - __set_MENVCFG(envcfg); -#endif -#endif - - cache_init(); - section_init(); - pmp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); - -#if CONFIG_ECC_L2_ENABLE - extern void ecc_l2_irqhandler(void *arg); - /* l2 cache ecc interrupt register */ - ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn; - csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev); - csi_irq_enable(ecc_l2_dev.irq_num); -#endif -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v2/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v2/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v2/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v2/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v2/vectors.S deleted file mode 100644 index b49028d1903..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v2/vectors.S +++ /dev/null @@ -1,521 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw sstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - -#if CONFIG_ECC_L1_ENABLE - .align 3 - .weak ECC_L1_Handler - .type ECC_L1_Handler, %function -ECC_L1_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, ECC_L1_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret -#endif - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw sstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - sd s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -(140+140) - sd x1, ( 0 + 0 )(sp) - sd x3, ( 8 + 8 )(sp) - sd x4, ( 12+ 12)(sp) - sd x5, ( 16+ 16)(sp) - sd x6, ( 20+ 20)(sp) - sd x7, ( 24+ 24)(sp) - sd x8, ( 28+ 28)(sp) - sd x9, ( 32+ 32)(sp) - sd x10,( 36+ 36)(sp) - sd x11,( 40+ 40)(sp) - sd x12,( 44+ 44)(sp) - sd x13,( 48+ 48)(sp) - sd x14,( 52+ 52)(sp) - sd x15,( 56+ 56)(sp) - sd x16,( 60+ 60)(sp) - sd x17,( 64+ 64)(sp) - sd x18,( 68+ 68)(sp) - sd x19,( 72+ 72)(sp) - sd x20,( 76+ 76)(sp) - sd x21,( 80+ 80)(sp) - sd x22,( 84+ 84)(sp) - sd x23,( 88+ 88)(sp) - sd x24,( 92+ 92)(sp) - sd x25,( 96+ 96)(sp) - sd x26,(100+100)(sp) - sd x27,(104+104)(sp) - sd x28,(108+108)(sp) - sd x29,(112+112)(sp) - sd x30,(116+116)(sp) - sd x31,(120+120)(sp) - csrr a0, mepc - sd a0, (124+124)(sp) - csrr a0, mstatus - sd a0, (128+128)(sp) - csrr a0, mcause - sd a0, (132+132)(sp) - csrr a0, mtval - sd a0, (136+136)(sp) - csrr a0, mscratch - sd a0, ( 4 + 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3-cp/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3-cp/startup.S deleted file mode 100644 index 92ba69989b2..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3-cp/startup.S +++ /dev/null @@ -1,188 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.globl Reset_Handler - -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler /* 12 */ - j Default_Handler /* 13 */ - j Default_Handler /* 14 */ - j Default_Handler /* 15 */ -#if CONFIG_ECC_L1_ENABLE - j ECC_L1_Handler /* 16 */ -#else - j Default_Handler /* 16 */ -#endif - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 - - /* get cpu id */ - csrr a0, mhartid - -#if defined(CONFIG_SMP) && CONFIG_SMP - /* check if hart is within range */ - /* tp: hart id */ - li t0, CONFIG_NR_CPUS - bge a0, t0, hart_out_of_bounds_loop -#endif - -#ifdef CONFIG_KERNEL_NONE - la sp, g_base_mainstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_MAINSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */ -#else - la sp, g_base_irqstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ -#endif - - /* other cpu core, jump to cpu entry directly */ - bnez a0, secondary_cpu_entry - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, pre_main - jalr a0 - -.size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - .type secondary_cpu_entry, %function -secondary_cpu_entry: -#if defined(CONFIG_SMP) && CONFIG_SMP - la a0, secondary_boot_flag - ld a0, 0(a0) - li a1, 0xa55a - beq a0, a1, 1f -#endif - j secondary_cpu_entry - -#if defined(CONFIG_SMP) && CONFIG_SMP -1: - jal secondary_cpu_c_start - -.size secondary_cpu_entry, . - secondary_cpu_entry - -hart_out_of_bounds_loop: - /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ - wfi - j hart_out_of_bounds_loop -#endif - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS -g_top_irqstack: - -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS -g_top_mainstack: -#endif - -#if defined(CONFIG_SMP) && CONFIG_SMP -.data -.global secondary_boot_flag -.align 3 -secondary_boot_flag: - .dword 0 -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3-cp/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3-cp/system.c deleted file mode 100644 index 8157f81729d..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3-cp/system.c +++ /dev/null @@ -1,324 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP) -#if CONFIG_NR_CPUS > 1 -#error "Please define CONFIG_NR_CPUS as 1 or do not need define." -#endif -#endif - -#if CONFIG_ECC_L2_ENABLE -static csi_dev_t ecc_l2_dev; -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void interrupt_init(void) -{ - int i; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); -#if CONFIG_ECC_L1_ENABLE - mie |= (1 << 16); -#endif - __set_MIE(mie); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ -#if CONFIG_CPU_XUANTIE_C910V3_CP || CONFIG_CPU_XUANTIE_C920V3_CP - /* disable theadisaee & enable MM */ - unsigned long status = __get_MXSTATUS(); - status &= ~(1 << 22); - status |= (1 << 24 | 1 << 15); - __set_MXSTATUS(status); -#else - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); -#endif - -#if __riscv_flen == 64 - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif - -#if CONFIG_ECC_L1_ENABLE - /* enable L1 cache ecc */ - uint64_t mhint = __get_MHINT(); - mhint |= (0x1 << 19); - __set_MHINT(mhint); -#endif - -#if CONFIG_ECC_L2_ENABLE - /* enable L2 cache ecc */ - uint64_t mccr2 = __get_MCCR2(); - mccr2 |= (0x1 << 1); - __set_MCCR2(mccr2); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); - -#if CBO_INSN_SUPPORT - unsigned long envcfg = __get_MENVCFG(); - /* enable CBIE & CBCFE & CBZE on lower priviledge */ - envcfg |= (3 << 4 | 1 << 6 | 1 << 7); - __set_MENVCFG(envcfg); -#endif -#endif - - cache_init(); - section_init(); - pmp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); - -#if CONFIG_ECC_L2_ENABLE - extern void ecc_l2_irqhandler(void *arg); - /* l2 cache ecc interrupt register */ - ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn; - csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev); - csi_irq_enable(ecc_l2_dev.irq_num); -#endif -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3-cp/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3-cp/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3-cp/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3-cp/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3-cp/vectors.S deleted file mode 100644 index b49028d1903..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3-cp/vectors.S +++ /dev/null @@ -1,521 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw sstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - -#if CONFIG_ECC_L1_ENABLE - .align 3 - .weak ECC_L1_Handler - .type ECC_L1_Handler, %function -ECC_L1_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, ECC_L1_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret -#endif - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw sstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - sd s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -(140+140) - sd x1, ( 0 + 0 )(sp) - sd x3, ( 8 + 8 )(sp) - sd x4, ( 12+ 12)(sp) - sd x5, ( 16+ 16)(sp) - sd x6, ( 20+ 20)(sp) - sd x7, ( 24+ 24)(sp) - sd x8, ( 28+ 28)(sp) - sd x9, ( 32+ 32)(sp) - sd x10,( 36+ 36)(sp) - sd x11,( 40+ 40)(sp) - sd x12,( 44+ 44)(sp) - sd x13,( 48+ 48)(sp) - sd x14,( 52+ 52)(sp) - sd x15,( 56+ 56)(sp) - sd x16,( 60+ 60)(sp) - sd x17,( 64+ 64)(sp) - sd x18,( 68+ 68)(sp) - sd x19,( 72+ 72)(sp) - sd x20,( 76+ 76)(sp) - sd x21,( 80+ 80)(sp) - sd x22,( 84+ 84)(sp) - sd x23,( 88+ 88)(sp) - sd x24,( 92+ 92)(sp) - sd x25,( 96+ 96)(sp) - sd x26,(100+100)(sp) - sd x27,(104+104)(sp) - sd x28,(108+108)(sp) - sd x29,(112+112)(sp) - sd x30,(116+116)(sp) - sd x31,(120+120)(sp) - csrr a0, mepc - sd a0, (124+124)(sp) - csrr a0, mstatus - sd a0, (128+128)(sp) - csrr a0, mcause - sd a0, (132+132)(sp) - csrr a0, mtval - sd a0, (136+136)(sp) - csrr a0, mscratch - sd a0, ( 4 + 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/SConscript b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/SConscript new file mode 100644 index 00000000000..7c13ee46652 --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/SConscript @@ -0,0 +1,13 @@ +from building import * +import os + +cwd = GetCurrentDir() +CPPPATH = [cwd] +src = ['startup.S'] +src += ['system.c'] +src += ['trap_c.c'] +src += ['vectors.S'] + +group = DefineGroup('sys', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/startup.S index 92ba69989b2..5877d711f25 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/startup.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/startup.S @@ -23,7 +23,9 @@ #endif .globl Reset_Handler - +.global __rt_rvstack +.equ Mcoret_Handler, SW_handler +.equ Mirq_Handler, SW_handler .section .vectors .align 6 .globl __Vectors @@ -132,7 +134,7 @@ Reset_Handler: #endif #endif - la a0, pre_main + la a0, rtthread_startup jalr a0 .size Reset_Handler, . - Reset_Handler @@ -169,6 +171,7 @@ hart_out_of_bounds_loop: g_base_irqstack: .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS g_top_irqstack: +__rt_rvstack: #ifdef CONFIG_KERNEL_NONE .align 4 diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v2/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v2/startup.S deleted file mode 100644 index 92ba69989b2..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v2/startup.S +++ /dev/null @@ -1,188 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.globl Reset_Handler - -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler /* 12 */ - j Default_Handler /* 13 */ - j Default_Handler /* 14 */ - j Default_Handler /* 15 */ -#if CONFIG_ECC_L1_ENABLE - j ECC_L1_Handler /* 16 */ -#else - j Default_Handler /* 16 */ -#endif - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 - - /* get cpu id */ - csrr a0, mhartid - -#if defined(CONFIG_SMP) && CONFIG_SMP - /* check if hart is within range */ - /* tp: hart id */ - li t0, CONFIG_NR_CPUS - bge a0, t0, hart_out_of_bounds_loop -#endif - -#ifdef CONFIG_KERNEL_NONE - la sp, g_base_mainstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_MAINSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */ -#else - la sp, g_base_irqstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ -#endif - - /* other cpu core, jump to cpu entry directly */ - bnez a0, secondary_cpu_entry - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, pre_main - jalr a0 - -.size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - .type secondary_cpu_entry, %function -secondary_cpu_entry: -#if defined(CONFIG_SMP) && CONFIG_SMP - la a0, secondary_boot_flag - ld a0, 0(a0) - li a1, 0xa55a - beq a0, a1, 1f -#endif - j secondary_cpu_entry - -#if defined(CONFIG_SMP) && CONFIG_SMP -1: - jal secondary_cpu_c_start - -.size secondary_cpu_entry, . - secondary_cpu_entry - -hart_out_of_bounds_loop: - /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ - wfi - j hart_out_of_bounds_loop -#endif - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS -g_top_irqstack: - -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS -g_top_mainstack: -#endif - -#if defined(CONFIG_SMP) && CONFIG_SMP -.data -.global secondary_boot_flag -.align 3 -secondary_boot_flag: - .dword 0 -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v2/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v2/system.c deleted file mode 100644 index dfa4b9bfb9a..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v2/system.c +++ /dev/null @@ -1,316 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP) -#if CONFIG_NR_CPUS > 1 -#error "Please define CONFIG_NR_CPUS as 1 or do not need define." -#endif -#endif - -#if CONFIG_ECC_L2_ENABLE -static csi_dev_t ecc_l2_dev; -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void interrupt_init(void) -{ - int i; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); -#if CONFIG_ECC_L1_ENABLE - mie |= (1 << 16); -#endif - __set_MIE(mie); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); - -#if __riscv_flen == 64 - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif - -#if CONFIG_ECC_L1_ENABLE - /* enable L1 cache ecc */ - uint64_t mhint = __get_MHINT(); - mhint |= (0x1 << 19); - __set_MHINT(mhint); -#endif - -#if CONFIG_ECC_L2_ENABLE - /* enable L2 cache ecc */ - uint64_t mccr2 = __get_MCCR2(); - mccr2 |= (0x1 << 1); - __set_MCCR2(mccr2); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); - -#if CBO_INSN_SUPPORT - unsigned long envcfg = __get_MENVCFG(); - /* enable CBIE & CBCFE & CBZE on lower priviledge */ - envcfg |= (3 << 4 | 1 << 6 | 1 << 7); - __set_MENVCFG(envcfg); -#endif -#endif - - cache_init(); - section_init(); - pmp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); - -#if CONFIG_ECC_L2_ENABLE - extern void ecc_l2_irqhandler(void *arg); - /* l2 cache ecc interrupt register */ - ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn; - csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev); - csi_irq_enable(ecc_l2_dev.irq_num); -#endif -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v2/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v2/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v2/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v2/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v2/vectors.S deleted file mode 100644 index b49028d1903..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v2/vectors.S +++ /dev/null @@ -1,521 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw sstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - -#if CONFIG_ECC_L1_ENABLE - .align 3 - .weak ECC_L1_Handler - .type ECC_L1_Handler, %function -ECC_L1_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, ECC_L1_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret -#endif - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw sstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - sd s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -(140+140) - sd x1, ( 0 + 0 )(sp) - sd x3, ( 8 + 8 )(sp) - sd x4, ( 12+ 12)(sp) - sd x5, ( 16+ 16)(sp) - sd x6, ( 20+ 20)(sp) - sd x7, ( 24+ 24)(sp) - sd x8, ( 28+ 28)(sp) - sd x9, ( 32+ 32)(sp) - sd x10,( 36+ 36)(sp) - sd x11,( 40+ 40)(sp) - sd x12,( 44+ 44)(sp) - sd x13,( 48+ 48)(sp) - sd x14,( 52+ 52)(sp) - sd x15,( 56+ 56)(sp) - sd x16,( 60+ 60)(sp) - sd x17,( 64+ 64)(sp) - sd x18,( 68+ 68)(sp) - sd x19,( 72+ 72)(sp) - sd x20,( 76+ 76)(sp) - sd x21,( 80+ 80)(sp) - sd x22,( 84+ 84)(sp) - sd x23,( 88+ 88)(sp) - sd x24,( 92+ 92)(sp) - sd x25,( 96+ 96)(sp) - sd x26,(100+100)(sp) - sd x27,(104+104)(sp) - sd x28,(108+108)(sp) - sd x29,(112+112)(sp) - sd x30,(116+116)(sp) - sd x31,(120+120)(sp) - csrr a0, mepc - sd a0, (124+124)(sp) - csrr a0, mstatus - sd a0, (128+128)(sp) - csrr a0, mcause - sd a0, (132+132)(sp) - csrr a0, mtval - sd a0, (136+136)(sp) - csrr a0, mscratch - sd a0, ( 4 + 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3-cp/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3-cp/startup.S deleted file mode 100644 index 92ba69989b2..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3-cp/startup.S +++ /dev/null @@ -1,188 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.globl Reset_Handler - -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler /* 12 */ - j Default_Handler /* 13 */ - j Default_Handler /* 14 */ - j Default_Handler /* 15 */ -#if CONFIG_ECC_L1_ENABLE - j ECC_L1_Handler /* 16 */ -#else - j Default_Handler /* 16 */ -#endif - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 - - /* get cpu id */ - csrr a0, mhartid - -#if defined(CONFIG_SMP) && CONFIG_SMP - /* check if hart is within range */ - /* tp: hart id */ - li t0, CONFIG_NR_CPUS - bge a0, t0, hart_out_of_bounds_loop -#endif - -#ifdef CONFIG_KERNEL_NONE - la sp, g_base_mainstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_MAINSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */ -#else - la sp, g_base_irqstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ -#endif - - /* other cpu core, jump to cpu entry directly */ - bnez a0, secondary_cpu_entry - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, pre_main - jalr a0 - -.size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - .type secondary_cpu_entry, %function -secondary_cpu_entry: -#if defined(CONFIG_SMP) && CONFIG_SMP - la a0, secondary_boot_flag - ld a0, 0(a0) - li a1, 0xa55a - beq a0, a1, 1f -#endif - j secondary_cpu_entry - -#if defined(CONFIG_SMP) && CONFIG_SMP -1: - jal secondary_cpu_c_start - -.size secondary_cpu_entry, . - secondary_cpu_entry - -hart_out_of_bounds_loop: - /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ - wfi - j hart_out_of_bounds_loop -#endif - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS -g_top_irqstack: - -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS -g_top_mainstack: -#endif - -#if defined(CONFIG_SMP) && CONFIG_SMP -.data -.global secondary_boot_flag -.align 3 -secondary_boot_flag: - .dword 0 -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3-cp/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3-cp/system.c deleted file mode 100644 index 8157f81729d..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3-cp/system.c +++ /dev/null @@ -1,324 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP) -#if CONFIG_NR_CPUS > 1 -#error "Please define CONFIG_NR_CPUS as 1 or do not need define." -#endif -#endif - -#if CONFIG_ECC_L2_ENABLE -static csi_dev_t ecc_l2_dev; -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void interrupt_init(void) -{ - int i; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); -#if CONFIG_ECC_L1_ENABLE - mie |= (1 << 16); -#endif - __set_MIE(mie); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ -#if CONFIG_CPU_XUANTIE_C910V3_CP || CONFIG_CPU_XUANTIE_C920V3_CP - /* disable theadisaee & enable MM */ - unsigned long status = __get_MXSTATUS(); - status &= ~(1 << 22); - status |= (1 << 24 | 1 << 15); - __set_MXSTATUS(status); -#else - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); -#endif - -#if __riscv_flen == 64 - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif - -#if CONFIG_ECC_L1_ENABLE - /* enable L1 cache ecc */ - uint64_t mhint = __get_MHINT(); - mhint |= (0x1 << 19); - __set_MHINT(mhint); -#endif - -#if CONFIG_ECC_L2_ENABLE - /* enable L2 cache ecc */ - uint64_t mccr2 = __get_MCCR2(); - mccr2 |= (0x1 << 1); - __set_MCCR2(mccr2); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); - -#if CBO_INSN_SUPPORT - unsigned long envcfg = __get_MENVCFG(); - /* enable CBIE & CBCFE & CBZE on lower priviledge */ - envcfg |= (3 << 4 | 1 << 6 | 1 << 7); - __set_MENVCFG(envcfg); -#endif -#endif - - cache_init(); - section_init(); - pmp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); - -#if CONFIG_ECC_L2_ENABLE - extern void ecc_l2_irqhandler(void *arg); - /* l2 cache ecc interrupt register */ - ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn; - csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev); - csi_irq_enable(ecc_l2_dev.irq_num); -#endif -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3-cp/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3-cp/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3-cp/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3-cp/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3-cp/vectors.S deleted file mode 100644 index b49028d1903..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3-cp/vectors.S +++ /dev/null @@ -1,521 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw sstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - -#if CONFIG_ECC_L1_ENABLE - .align 3 - .weak ECC_L1_Handler - .type ECC_L1_Handler, %function -ECC_L1_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, ECC_L1_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret -#endif - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw sstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - sd s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -(140+140) - sd x1, ( 0 + 0 )(sp) - sd x3, ( 8 + 8 )(sp) - sd x4, ( 12+ 12)(sp) - sd x5, ( 16+ 16)(sp) - sd x6, ( 20+ 20)(sp) - sd x7, ( 24+ 24)(sp) - sd x8, ( 28+ 28)(sp) - sd x9, ( 32+ 32)(sp) - sd x10,( 36+ 36)(sp) - sd x11,( 40+ 40)(sp) - sd x12,( 44+ 44)(sp) - sd x13,( 48+ 48)(sp) - sd x14,( 52+ 52)(sp) - sd x15,( 56+ 56)(sp) - sd x16,( 60+ 60)(sp) - sd x17,( 64+ 64)(sp) - sd x18,( 68+ 68)(sp) - sd x19,( 72+ 72)(sp) - sd x20,( 76+ 76)(sp) - sd x21,( 80+ 80)(sp) - sd x22,( 84+ 84)(sp) - sd x23,( 88+ 88)(sp) - sd x24,( 92+ 92)(sp) - sd x25,( 96+ 96)(sp) - sd x26,(100+100)(sp) - sd x27,(104+104)(sp) - sd x28,(108+108)(sp) - sd x29,(112+112)(sp) - sd x30,(116+116)(sp) - sd x31,(120+120)(sp) - csrr a0, mepc - sd a0, (124+124)(sp) - csrr a0, mstatus - sd a0, (128+128)(sp) - csrr a0, mcause - sd a0, (132+132)(sp) - csrr a0, mtval - sd a0, (136+136)(sp) - csrr a0, mscratch - sd a0, ( 4 + 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902m/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902m/startup.S deleted file mode 100644 index d092d3388c2..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902m/startup.S +++ /dev/null @@ -1,134 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -.section .vectors, "aw", @progbits - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long tspend_handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_IRQHandler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - - /* External interrupts */ - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - - .globl Reset_Handler - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 -_start: - .text - .long Reset_Handler - .align 2 - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - la gp, __global_pointer$ -.option pop - la a0, Default_Handler - ori a0, a0, 3 - csrw mtvec, a0 - - la a0, __Vectors - csrw mtvt, a0 - - la sp, g_top_irqstack - csrw mscratch, sp -#ifdef CONFIG_KERNEL_NONE - la sp, g_top_mainstack -#endif - -#ifndef __NO_SYSTEM_INIT - jal SystemInit -#endif - - jal pre_main - - .size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - -.section .stack - .align 3 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_irqstack: -#ifdef CONFIG_KERNEL_NONE - .align 3 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK -g_top_mainstack: -#endif - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902m/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902m/system.c deleted file mode 100644 index b4ed4130b52..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902m/system.c +++ /dev/null @@ -1,100 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -static void cache_init(void) -{ - csi_icache_enable(); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); -#endif - - section_bss_clear(); -} - -static void clic_init(void) -{ - int i; - - /* get interrupt level from info */ - CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); - - for (i = 0; i < 64; i++) { - CLIC->CLICINT[i].IP = 0; - CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - csi_vic_set_prio(i, 1); - } - -#ifndef CONFIG_KERNEL_NONE - /* tspend use lower priority */ - csi_vic_set_prio(Machine_Software_IRQn, 0); - /* tspend use positive interrupt */ - CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; - csi_irq_enable(Machine_Software_IRQn); -#endif -} - -static void interrupt_init(void) -{ - clic_init(); -#ifdef CONFIG_KERNEL_NONE - __enable_excp_irq(); -#endif -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee */ - uint32_t status = __get_MXSTATUS(); - status |= (1 << 22); - __set_MXSTATUS(status); - cache_init(); - section_init(); - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902m/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902m/trap_c.c deleted file mode 100644 index 78ae4585da0..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902m/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 15; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[15]); - printk("mstatus: %p\n", (void *)regs[16]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902m/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902m/vectors.S deleted file mode 100644 index 48c6060a86e..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902m/vectors.S +++ /dev/null @@ -1,383 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 - -.section .stack - .align 2 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -#if CONFIG_SUPPORT_IRQ_NESTED -#define IRQ_NESTED_MAX (6) -.section .bss -irq_nested_level: -.long 0 - -irq_nested_mcause: -.long 0, 0, 0, 0, 0, 0 -#endif - -.text - -#if !CONFIG_SUPPORT_IRQ_NESTED - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - csrw mscratch, sp - la sp, g_top_irqstack - addi sp, sp, -48 - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 40(sp) - sw t0, 44(sp) - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - - la t0, do_irq - jalr t0 - - lw a1, 40(sp) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - lw t0, 44(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - - addi sp, sp, 48 - csrr sp, mscratch - mret -#else - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -8 - sw t0, 0(sp) - sw t1, 4(sp) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, 1 - sw t1, (t0) - - li t0, IRQ_NESTED_MAX - /* nested too deeply, may be error happens */ - bgt t1, t0, Default_Handler - - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t0, t0, t1 - csrr t1, mcause - sw t1, (t0) - - la t0, irq_nested_level - lw t1, (t0) - li t0, 1 - bgt t1, t0, .Lnested1 - - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 - - csrw mscratch, sp - la sp, g_top_irqstack - j .Lnested2 -.Lnested1: - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 -.Lnested2: - addi sp, sp, -48 - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 40(sp) - sw t0, 44(sp) - - csrs mstatus, 8 - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - - la t0, do_irq - jalr t0 - - csrc mstatus, 8 - - - lw a1, 40(sp) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, -1 - sw t1, (t0) - bgt t1, zero, .Lnested3 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - lw t0, 44(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - - addi sp, sp, 48 - csrr sp, mscratch - mret - -.Lnested3: - /* keep mpil in current mcause & load exception code before */ - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t1, t0, t1 - lw t0, (t1) - andi t0, t0, 0x3FF - andi a0, a1, 0xFFFFFC00 - or t0, a0, t0 - csrw mcause, t0 - lw t0, 44(sp) - csrw mepc, t0 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - - addi sp, sp, 48 - mret -#endif - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 2 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -76 - sw x1, (0 )(sp) - sw x3, (8 )(sp) - sw x4, (12)(sp) - sw x5, (16)(sp) - sw x6, (20)(sp) - sw x7, (24)(sp) - sw x8, (28)(sp) - sw x9, (32)(sp) - sw x10,(36)(sp) - sw x11,(40)(sp) - sw x12,(44)(sp) - sw x13,(48)(sp) - sw x14,(52)(sp) - sw x15,(56)(sp) - csrr a0, mepc - sw a0, (60)(sp) - csrr a0, mstatus - sw a0, (64)(sp) - csrr a0, mcause - sw a0, (68)(sp) - csrr a0, mtval - sw a0, (72)(sp) - csrr a0, mscratch - sw a0, (4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - - .align 6 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - /* Check for nmi */ - addi sp, sp, -8 - sw t0, 0x0(sp) - sw t1, 0x4(sp) - csrr t0, mcause - andi t0, t0, 0x3FF - li t1, 24 - beq t0, t1, .NMI_Handler - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - j trap -.NMI_Handler: - /* mscratch may be used before */ - addi sp, sp, -4 - csrr t0, mscratch - sw t0, 0x0(sp) - - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -48 - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 40(sp) - sw t0, 44(sp) - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - - la t0, handle_nmi_exception - jalr t0 - - lw a1, 40(sp) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - lw t0, 44(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - - addi sp, sp, 48 - csrr sp, mscratch - - /* restore mscratch */ - lw t0, 0x0(sp) - csrw mscratch, t0 - addi sp, sp, 4 - - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - - mret - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler tspend_handler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902mt/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902mt/startup.S deleted file mode 100644 index d092d3388c2..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902mt/startup.S +++ /dev/null @@ -1,134 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -.section .vectors, "aw", @progbits - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long tspend_handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_IRQHandler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - - /* External interrupts */ - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - - .globl Reset_Handler - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 -_start: - .text - .long Reset_Handler - .align 2 - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - la gp, __global_pointer$ -.option pop - la a0, Default_Handler - ori a0, a0, 3 - csrw mtvec, a0 - - la a0, __Vectors - csrw mtvt, a0 - - la sp, g_top_irqstack - csrw mscratch, sp -#ifdef CONFIG_KERNEL_NONE - la sp, g_top_mainstack -#endif - -#ifndef __NO_SYSTEM_INIT - jal SystemInit -#endif - - jal pre_main - - .size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - -.section .stack - .align 3 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_irqstack: -#ifdef CONFIG_KERNEL_NONE - .align 3 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK -g_top_mainstack: -#endif - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902mt/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902mt/system.c deleted file mode 100644 index b4ed4130b52..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902mt/system.c +++ /dev/null @@ -1,100 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -static void cache_init(void) -{ - csi_icache_enable(); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); -#endif - - section_bss_clear(); -} - -static void clic_init(void) -{ - int i; - - /* get interrupt level from info */ - CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); - - for (i = 0; i < 64; i++) { - CLIC->CLICINT[i].IP = 0; - CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - csi_vic_set_prio(i, 1); - } - -#ifndef CONFIG_KERNEL_NONE - /* tspend use lower priority */ - csi_vic_set_prio(Machine_Software_IRQn, 0); - /* tspend use positive interrupt */ - CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; - csi_irq_enable(Machine_Software_IRQn); -#endif -} - -static void interrupt_init(void) -{ - clic_init(); -#ifdef CONFIG_KERNEL_NONE - __enable_excp_irq(); -#endif -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee */ - uint32_t status = __get_MXSTATUS(); - status |= (1 << 22); - __set_MXSTATUS(status); - cache_init(); - section_init(); - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902mt/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902mt/trap_c.c deleted file mode 100644 index 78ae4585da0..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902mt/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 15; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[15]); - printk("mstatus: %p\n", (void *)regs[16]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902mt/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902mt/vectors.S deleted file mode 100644 index 48c6060a86e..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902mt/vectors.S +++ /dev/null @@ -1,383 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 - -.section .stack - .align 2 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -#if CONFIG_SUPPORT_IRQ_NESTED -#define IRQ_NESTED_MAX (6) -.section .bss -irq_nested_level: -.long 0 - -irq_nested_mcause: -.long 0, 0, 0, 0, 0, 0 -#endif - -.text - -#if !CONFIG_SUPPORT_IRQ_NESTED - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - csrw mscratch, sp - la sp, g_top_irqstack - addi sp, sp, -48 - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 40(sp) - sw t0, 44(sp) - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - - la t0, do_irq - jalr t0 - - lw a1, 40(sp) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - lw t0, 44(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - - addi sp, sp, 48 - csrr sp, mscratch - mret -#else - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -8 - sw t0, 0(sp) - sw t1, 4(sp) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, 1 - sw t1, (t0) - - li t0, IRQ_NESTED_MAX - /* nested too deeply, may be error happens */ - bgt t1, t0, Default_Handler - - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t0, t0, t1 - csrr t1, mcause - sw t1, (t0) - - la t0, irq_nested_level - lw t1, (t0) - li t0, 1 - bgt t1, t0, .Lnested1 - - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 - - csrw mscratch, sp - la sp, g_top_irqstack - j .Lnested2 -.Lnested1: - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 -.Lnested2: - addi sp, sp, -48 - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 40(sp) - sw t0, 44(sp) - - csrs mstatus, 8 - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - - la t0, do_irq - jalr t0 - - csrc mstatus, 8 - - - lw a1, 40(sp) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, -1 - sw t1, (t0) - bgt t1, zero, .Lnested3 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - lw t0, 44(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - - addi sp, sp, 48 - csrr sp, mscratch - mret - -.Lnested3: - /* keep mpil in current mcause & load exception code before */ - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t1, t0, t1 - lw t0, (t1) - andi t0, t0, 0x3FF - andi a0, a1, 0xFFFFFC00 - or t0, a0, t0 - csrw mcause, t0 - lw t0, 44(sp) - csrw mepc, t0 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - - addi sp, sp, 48 - mret -#endif - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 2 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -76 - sw x1, (0 )(sp) - sw x3, (8 )(sp) - sw x4, (12)(sp) - sw x5, (16)(sp) - sw x6, (20)(sp) - sw x7, (24)(sp) - sw x8, (28)(sp) - sw x9, (32)(sp) - sw x10,(36)(sp) - sw x11,(40)(sp) - sw x12,(44)(sp) - sw x13,(48)(sp) - sw x14,(52)(sp) - sw x15,(56)(sp) - csrr a0, mepc - sw a0, (60)(sp) - csrr a0, mstatus - sw a0, (64)(sp) - csrr a0, mcause - sw a0, (68)(sp) - csrr a0, mtval - sw a0, (72)(sp) - csrr a0, mscratch - sw a0, (4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - - .align 6 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - /* Check for nmi */ - addi sp, sp, -8 - sw t0, 0x0(sp) - sw t1, 0x4(sp) - csrr t0, mcause - andi t0, t0, 0x3FF - li t1, 24 - beq t0, t1, .NMI_Handler - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - j trap -.NMI_Handler: - /* mscratch may be used before */ - addi sp, sp, -4 - csrr t0, mscratch - sw t0, 0x0(sp) - - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -48 - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 40(sp) - sw t0, 44(sp) - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - - la t0, handle_nmi_exception - jalr t0 - - lw a1, 40(sp) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - lw t0, 44(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - - addi sp, sp, 48 - csrr sp, mscratch - - /* restore mscratch */ - lw t0, 0x0(sp) - csrw mscratch, t0 - addi sp, sp, 4 - - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - - mret - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler tspend_handler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902t/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902t/startup.S deleted file mode 100644 index d092d3388c2..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902t/startup.S +++ /dev/null @@ -1,134 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -.section .vectors, "aw", @progbits - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long tspend_handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_IRQHandler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - - /* External interrupts */ - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - - .globl Reset_Handler - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 -_start: - .text - .long Reset_Handler - .align 2 - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - la gp, __global_pointer$ -.option pop - la a0, Default_Handler - ori a0, a0, 3 - csrw mtvec, a0 - - la a0, __Vectors - csrw mtvt, a0 - - la sp, g_top_irqstack - csrw mscratch, sp -#ifdef CONFIG_KERNEL_NONE - la sp, g_top_mainstack -#endif - -#ifndef __NO_SYSTEM_INIT - jal SystemInit -#endif - - jal pre_main - - .size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - -.section .stack - .align 3 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_irqstack: -#ifdef CONFIG_KERNEL_NONE - .align 3 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK -g_top_mainstack: -#endif - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902t/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902t/system.c deleted file mode 100644 index b4ed4130b52..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902t/system.c +++ /dev/null @@ -1,100 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -static void cache_init(void) -{ - csi_icache_enable(); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); -#endif - - section_bss_clear(); -} - -static void clic_init(void) -{ - int i; - - /* get interrupt level from info */ - CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); - - for (i = 0; i < 64; i++) { - CLIC->CLICINT[i].IP = 0; - CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - csi_vic_set_prio(i, 1); - } - -#ifndef CONFIG_KERNEL_NONE - /* tspend use lower priority */ - csi_vic_set_prio(Machine_Software_IRQn, 0); - /* tspend use positive interrupt */ - CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; - csi_irq_enable(Machine_Software_IRQn); -#endif -} - -static void interrupt_init(void) -{ - clic_init(); -#ifdef CONFIG_KERNEL_NONE - __enable_excp_irq(); -#endif -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee */ - uint32_t status = __get_MXSTATUS(); - status |= (1 << 22); - __set_MXSTATUS(status); - cache_init(); - section_init(); - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902t/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902t/trap_c.c deleted file mode 100644 index 78ae4585da0..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902t/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 15; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[15]); - printk("mstatus: %p\n", (void *)regs[16]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902t/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902t/vectors.S deleted file mode 100644 index 48c6060a86e..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902t/vectors.S +++ /dev/null @@ -1,383 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 - -.section .stack - .align 2 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -#if CONFIG_SUPPORT_IRQ_NESTED -#define IRQ_NESTED_MAX (6) -.section .bss -irq_nested_level: -.long 0 - -irq_nested_mcause: -.long 0, 0, 0, 0, 0, 0 -#endif - -.text - -#if !CONFIG_SUPPORT_IRQ_NESTED - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - csrw mscratch, sp - la sp, g_top_irqstack - addi sp, sp, -48 - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 40(sp) - sw t0, 44(sp) - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - - la t0, do_irq - jalr t0 - - lw a1, 40(sp) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - lw t0, 44(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - - addi sp, sp, 48 - csrr sp, mscratch - mret -#else - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -8 - sw t0, 0(sp) - sw t1, 4(sp) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, 1 - sw t1, (t0) - - li t0, IRQ_NESTED_MAX - /* nested too deeply, may be error happens */ - bgt t1, t0, Default_Handler - - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t0, t0, t1 - csrr t1, mcause - sw t1, (t0) - - la t0, irq_nested_level - lw t1, (t0) - li t0, 1 - bgt t1, t0, .Lnested1 - - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 - - csrw mscratch, sp - la sp, g_top_irqstack - j .Lnested2 -.Lnested1: - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 -.Lnested2: - addi sp, sp, -48 - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 40(sp) - sw t0, 44(sp) - - csrs mstatus, 8 - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - - la t0, do_irq - jalr t0 - - csrc mstatus, 8 - - - lw a1, 40(sp) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, -1 - sw t1, (t0) - bgt t1, zero, .Lnested3 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - lw t0, 44(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - - addi sp, sp, 48 - csrr sp, mscratch - mret - -.Lnested3: - /* keep mpil in current mcause & load exception code before */ - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t1, t0, t1 - lw t0, (t1) - andi t0, t0, 0x3FF - andi a0, a1, 0xFFFFFC00 - or t0, a0, t0 - csrw mcause, t0 - lw t0, 44(sp) - csrw mepc, t0 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - - addi sp, sp, 48 - mret -#endif - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 2 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -76 - sw x1, (0 )(sp) - sw x3, (8 )(sp) - sw x4, (12)(sp) - sw x5, (16)(sp) - sw x6, (20)(sp) - sw x7, (24)(sp) - sw x8, (28)(sp) - sw x9, (32)(sp) - sw x10,(36)(sp) - sw x11,(40)(sp) - sw x12,(44)(sp) - sw x13,(48)(sp) - sw x14,(52)(sp) - sw x15,(56)(sp) - csrr a0, mepc - sw a0, (60)(sp) - csrr a0, mstatus - sw a0, (64)(sp) - csrr a0, mcause - sw a0, (68)(sp) - csrr a0, mtval - sw a0, (72)(sp) - csrr a0, mscratch - sw a0, (4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - - .align 6 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - /* Check for nmi */ - addi sp, sp, -8 - sw t0, 0x0(sp) - sw t1, 0x4(sp) - csrr t0, mcause - andi t0, t0, 0x3FF - li t1, 24 - beq t0, t1, .NMI_Handler - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - j trap -.NMI_Handler: - /* mscratch may be used before */ - addi sp, sp, -4 - csrr t0, mscratch - sw t0, 0x0(sp) - - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -48 - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 40(sp) - sw t0, 44(sp) - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - - la t0, handle_nmi_exception - jalr t0 - - lw a1, 40(sp) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - lw t0, 44(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - - addi sp, sp, 48 - csrr sp, mscratch - - /* restore mscratch */ - lw t0, 0x0(sp) - csrw mscratch, t0 - addi sp, sp, 4 - - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - - mret - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler tspend_handler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906f/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906f/startup.S deleted file mode 100644 index 65032fbbb7c..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906f/startup.S +++ /dev/null @@ -1,168 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -.section .vectors, "aw", @progbits - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long tspend_handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_IRQHandler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - - /* External interrupts */ - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - - .size __Vectors, . - __Vectors - - .globl Reset_Handler - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 -_start: - .text - .long Reset_Handler - .align 2 - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - la gp, __global_pointer$ -.option pop - la a0, Default_Handler - ori a0, a0, 3 - csrw mtvec, a0 - - la a0, __Vectors - csrw mtvt, a0 - - la sp, g_top_irqstack - csrw mscratch, sp -#ifdef CONFIG_KERNEL_NONE - la sp, g_top_mainstack -#endif - -#ifndef __NO_SYSTEM_INIT - jal SystemInit -#endif - - jal pre_main - - .size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_irqstack: -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK -g_top_mainstack: -#endif - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906f/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906f/system.c deleted file mode 100644 index 904523c669f..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906f/system.c +++ /dev/null @@ -1,113 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -static void cache_init(void) -{ - csi_dcache_enable(); - csi_icache_enable(); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - section_bss_clear(); -} - -static void clic_init(void) -{ - int i; - - /* get interrupt level from info */ - CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); - - for (i = 0; i < 64; i++) { - CLIC->CLICINT[i].IP = 0; - CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - } - - /* tspend use positive interrupt */ - CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; - csi_irq_enable(Machine_Software_IRQn); -} - -static void interrupt_init(void) -{ - clic_init(); -#ifdef CONFIG_KERNEL_NONE - __enable_excp_irq(); -#endif -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - uint32_t status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); - -#if __riscv_flen - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif - /* enable mexstatus SPUSHEN and disable SPSWAPEN */ -#if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP \ - || CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP - status = __get_MEXSTATUS(); - status |= (0x1 << 16); - status &= ~(0x2 << 16); - __set_MEXSTATUS(status); -#endif - - cache_init(); - section_init(); - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906f/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906f/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906f/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906f/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906f/vectors.S deleted file mode 100644 index 6bb2e9836c3..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906f/vectors.S +++ /dev/null @@ -1,591 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -#if CONFIG_SUPPORT_IRQ_NESTED -#define IRQ_NESTED_MAX (6) -.section .bss -irq_nested_level: -.long 0 - -irq_nested_mcause: -.long 0, 0, 0, 0, 0, 0 -#endif - -.text - -#if !CONFIG_SUPPORT_IRQ_NESTED - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - csrw mscratch, sp - la sp, g_top_irqstack -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, do_irq - jalr t0 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - mret -#else - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -8 - sw t0, 0(sp) - sw t1, 4(sp) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, 1 - sw t1, (t0) - - li t0, IRQ_NESTED_MAX - /* nested too deeply, may be error happens */ - bgt t1, t0, Default_Handler - - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t0, t0, t1 - csrr t1, mcause - sw t1, (t0) - - la t0, irq_nested_level - lw t1, (t0) - li t0, 1 - bgt t1, t0, .Lnested1 - - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 - - csrw mscratch, sp - la sp, g_top_irqstack - j .Lnested2 -.Lnested1: - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 -.Lnested2: -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - csrs mstatus, 8 - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, do_irq - jalr t0 - - csrc mstatus, 8 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, -1 - sw t1, (t0) - bgt t1, zero, .Lnested3 - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - mret - -.Lnested3: - /* keep mpil in current mcause & load exception code before */ - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t1, t0, t1 - lw t0, (t1) - andi t0, t0, 0x3FF - andi a0, a1, 0xFFFFFC00 - or t0, a0, t0 - csrw mcause, t0 - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - mret -#endif - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 2 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -140 - sw x1, ( 0 )(sp) - sw x3, ( 8 )(sp) - sw x4, ( 12)(sp) - sw x5, ( 16)(sp) - sw x6, ( 20)(sp) - sw x7, ( 24)(sp) - sw x8, ( 28)(sp) - sw x9, ( 32)(sp) - sw x10,( 36)(sp) - sw x11,( 40)(sp) - sw x12,( 44)(sp) - sw x13,( 48)(sp) - sw x14,( 52)(sp) - sw x15,( 56)(sp) - sw x16,( 60)(sp) - sw x17,( 64)(sp) - sw x18,( 68)(sp) - sw x19,( 72)(sp) - sw x20,( 76)(sp) - sw x21,( 80)(sp) - sw x22,( 84)(sp) - sw x23,( 88)(sp) - sw x24,( 92)(sp) - sw x25,( 96)(sp) - sw x26,(100)(sp) - sw x27,(104)(sp) - sw x28,(108)(sp) - sw x29,(112)(sp) - sw x30,(116)(sp) - sw x31,(120)(sp) - csrr a0, mepc - sw a0, (124)(sp) - csrr a0, mstatus - sw a0, (128)(sp) - csrr a0, mcause - sw a0, (132)(sp) - csrr a0, mtval - sw a0, (136)(sp) - csrr a0, mscratch - sw a0, ( 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - - .align 6 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - /* Check for nmi */ - addi sp, sp, -8 - sw t0, 0x0(sp) - sw t1, 0x4(sp) - csrr t0, mcause - andi t0, t0, 0x3FF - li t1, 24 - beq t0, t1, .NMI_Handler - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - j trap -.NMI_Handler: - /* mscratch may be used before */ - addi sp, sp, -4 - csrr t0, mscratch - sw t0, 0x0(sp) - - csrw mscratch, sp - la sp, g_top_trapstack -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, handle_nmi_exception - jalr t0 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 -#if CONFIG_CHECK_FPU_DIRTY - lw t0, 72(sp) - csrw mstatus, t0 -#endif - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - - /* restore mscratch */ - lw t0, 0x0(sp) - csrw mscratch, t0 - addi sp, sp, 4 - - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - - mret - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler tspend_handler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fd/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fd/startup.S deleted file mode 100644 index 8843b34fb0d..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fd/startup.S +++ /dev/null @@ -1,169 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -.global __rt_rvstack -.section .vectors, "aw", @progbits - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long tspend_handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_IRQHandler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - - /* External interrupts */ - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - - .size __Vectors, . - __Vectors - - .globl Reset_Handler - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 -_start: - .text - .long Reset_Handler - .align 2 - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - la gp, __global_pointer$ -.option pop - la a0, Default_Handler - ori a0, a0, 3 - csrw mtvec, a0 - - la a0, __Vectors - csrw mtvt, a0 - - la sp, g_top_irqstack - csrw mscratch, sp -#ifdef CONFIG_KERNEL_NONE - la sp, g_top_mainstack -#endif - -#ifndef __NO_SYSTEM_INIT - jal SystemInit -#endif - - jal rtthread_startup - - .size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_irqstack: -__rt_rvstack: -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK -g_top_mainstack: -#endif - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fd/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fd/system.c deleted file mode 100644 index 904523c669f..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fd/system.c +++ /dev/null @@ -1,113 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -static void cache_init(void) -{ - csi_dcache_enable(); - csi_icache_enable(); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - section_bss_clear(); -} - -static void clic_init(void) -{ - int i; - - /* get interrupt level from info */ - CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); - - for (i = 0; i < 64; i++) { - CLIC->CLICINT[i].IP = 0; - CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - } - - /* tspend use positive interrupt */ - CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; - csi_irq_enable(Machine_Software_IRQn); -} - -static void interrupt_init(void) -{ - clic_init(); -#ifdef CONFIG_KERNEL_NONE - __enable_excp_irq(); -#endif -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - uint32_t status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); - -#if __riscv_flen - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif - /* enable mexstatus SPUSHEN and disable SPSWAPEN */ -#if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP \ - || CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP - status = __get_MEXSTATUS(); - status |= (0x1 << 16); - status &= ~(0x2 << 16); - __set_MEXSTATUS(status); -#endif - - cache_init(); - section_init(); - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fd/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fd/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fd/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fd/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fd/vectors.S deleted file mode 100644 index 6bb2e9836c3..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fd/vectors.S +++ /dev/null @@ -1,591 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -#if CONFIG_SUPPORT_IRQ_NESTED -#define IRQ_NESTED_MAX (6) -.section .bss -irq_nested_level: -.long 0 - -irq_nested_mcause: -.long 0, 0, 0, 0, 0, 0 -#endif - -.text - -#if !CONFIG_SUPPORT_IRQ_NESTED - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - csrw mscratch, sp - la sp, g_top_irqstack -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, do_irq - jalr t0 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - mret -#else - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -8 - sw t0, 0(sp) - sw t1, 4(sp) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, 1 - sw t1, (t0) - - li t0, IRQ_NESTED_MAX - /* nested too deeply, may be error happens */ - bgt t1, t0, Default_Handler - - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t0, t0, t1 - csrr t1, mcause - sw t1, (t0) - - la t0, irq_nested_level - lw t1, (t0) - li t0, 1 - bgt t1, t0, .Lnested1 - - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 - - csrw mscratch, sp - la sp, g_top_irqstack - j .Lnested2 -.Lnested1: - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 -.Lnested2: -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - csrs mstatus, 8 - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, do_irq - jalr t0 - - csrc mstatus, 8 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, -1 - sw t1, (t0) - bgt t1, zero, .Lnested3 - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - mret - -.Lnested3: - /* keep mpil in current mcause & load exception code before */ - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t1, t0, t1 - lw t0, (t1) - andi t0, t0, 0x3FF - andi a0, a1, 0xFFFFFC00 - or t0, a0, t0 - csrw mcause, t0 - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - mret -#endif - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 2 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -140 - sw x1, ( 0 )(sp) - sw x3, ( 8 )(sp) - sw x4, ( 12)(sp) - sw x5, ( 16)(sp) - sw x6, ( 20)(sp) - sw x7, ( 24)(sp) - sw x8, ( 28)(sp) - sw x9, ( 32)(sp) - sw x10,( 36)(sp) - sw x11,( 40)(sp) - sw x12,( 44)(sp) - sw x13,( 48)(sp) - sw x14,( 52)(sp) - sw x15,( 56)(sp) - sw x16,( 60)(sp) - sw x17,( 64)(sp) - sw x18,( 68)(sp) - sw x19,( 72)(sp) - sw x20,( 76)(sp) - sw x21,( 80)(sp) - sw x22,( 84)(sp) - sw x23,( 88)(sp) - sw x24,( 92)(sp) - sw x25,( 96)(sp) - sw x26,(100)(sp) - sw x27,(104)(sp) - sw x28,(108)(sp) - sw x29,(112)(sp) - sw x30,(116)(sp) - sw x31,(120)(sp) - csrr a0, mepc - sw a0, (124)(sp) - csrr a0, mstatus - sw a0, (128)(sp) - csrr a0, mcause - sw a0, (132)(sp) - csrr a0, mtval - sw a0, (136)(sp) - csrr a0, mscratch - sw a0, ( 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - - .align 6 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - /* Check for nmi */ - addi sp, sp, -8 - sw t0, 0x0(sp) - sw t1, 0x4(sp) - csrr t0, mcause - andi t0, t0, 0x3FF - li t1, 24 - beq t0, t1, .NMI_Handler - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - j trap -.NMI_Handler: - /* mscratch may be used before */ - addi sp, sp, -4 - csrr t0, mscratch - sw t0, 0x0(sp) - - csrw mscratch, sp - la sp, g_top_trapstack -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, handle_nmi_exception - jalr t0 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 -#if CONFIG_CHECK_FPU_DIRTY - lw t0, 72(sp) - csrw mstatus, t0 -#endif - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - - /* restore mscratch */ - lw t0, 0x0(sp) - csrw mscratch, t0 - addi sp, sp, 4 - - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - - mret - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler tspend_handler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fdp/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fdp/startup.S deleted file mode 100644 index 65032fbbb7c..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fdp/startup.S +++ /dev/null @@ -1,168 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -.section .vectors, "aw", @progbits - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long tspend_handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_IRQHandler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - - /* External interrupts */ - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - - .size __Vectors, . - __Vectors - - .globl Reset_Handler - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 -_start: - .text - .long Reset_Handler - .align 2 - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - la gp, __global_pointer$ -.option pop - la a0, Default_Handler - ori a0, a0, 3 - csrw mtvec, a0 - - la a0, __Vectors - csrw mtvt, a0 - - la sp, g_top_irqstack - csrw mscratch, sp -#ifdef CONFIG_KERNEL_NONE - la sp, g_top_mainstack -#endif - -#ifndef __NO_SYSTEM_INIT - jal SystemInit -#endif - - jal pre_main - - .size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_irqstack: -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK -g_top_mainstack: -#endif - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fdp/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fdp/system.c deleted file mode 100644 index 904523c669f..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fdp/system.c +++ /dev/null @@ -1,113 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -static void cache_init(void) -{ - csi_dcache_enable(); - csi_icache_enable(); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - section_bss_clear(); -} - -static void clic_init(void) -{ - int i; - - /* get interrupt level from info */ - CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); - - for (i = 0; i < 64; i++) { - CLIC->CLICINT[i].IP = 0; - CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - } - - /* tspend use positive interrupt */ - CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; - csi_irq_enable(Machine_Software_IRQn); -} - -static void interrupt_init(void) -{ - clic_init(); -#ifdef CONFIG_KERNEL_NONE - __enable_excp_irq(); -#endif -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - uint32_t status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); - -#if __riscv_flen - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif - /* enable mexstatus SPUSHEN and disable SPSWAPEN */ -#if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP \ - || CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP - status = __get_MEXSTATUS(); - status |= (0x1 << 16); - status &= ~(0x2 << 16); - __set_MEXSTATUS(status); -#endif - - cache_init(); - section_init(); - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fdp/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fdp/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fdp/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fdp/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fdp/vectors.S deleted file mode 100644 index 6bb2e9836c3..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fdp/vectors.S +++ /dev/null @@ -1,591 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -#if CONFIG_SUPPORT_IRQ_NESTED -#define IRQ_NESTED_MAX (6) -.section .bss -irq_nested_level: -.long 0 - -irq_nested_mcause: -.long 0, 0, 0, 0, 0, 0 -#endif - -.text - -#if !CONFIG_SUPPORT_IRQ_NESTED - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - csrw mscratch, sp - la sp, g_top_irqstack -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, do_irq - jalr t0 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - mret -#else - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -8 - sw t0, 0(sp) - sw t1, 4(sp) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, 1 - sw t1, (t0) - - li t0, IRQ_NESTED_MAX - /* nested too deeply, may be error happens */ - bgt t1, t0, Default_Handler - - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t0, t0, t1 - csrr t1, mcause - sw t1, (t0) - - la t0, irq_nested_level - lw t1, (t0) - li t0, 1 - bgt t1, t0, .Lnested1 - - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 - - csrw mscratch, sp - la sp, g_top_irqstack - j .Lnested2 -.Lnested1: - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 -.Lnested2: -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - csrs mstatus, 8 - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, do_irq - jalr t0 - - csrc mstatus, 8 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, -1 - sw t1, (t0) - bgt t1, zero, .Lnested3 - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - mret - -.Lnested3: - /* keep mpil in current mcause & load exception code before */ - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t1, t0, t1 - lw t0, (t1) - andi t0, t0, 0x3FF - andi a0, a1, 0xFFFFFC00 - or t0, a0, t0 - csrw mcause, t0 - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - mret -#endif - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 2 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -140 - sw x1, ( 0 )(sp) - sw x3, ( 8 )(sp) - sw x4, ( 12)(sp) - sw x5, ( 16)(sp) - sw x6, ( 20)(sp) - sw x7, ( 24)(sp) - sw x8, ( 28)(sp) - sw x9, ( 32)(sp) - sw x10,( 36)(sp) - sw x11,( 40)(sp) - sw x12,( 44)(sp) - sw x13,( 48)(sp) - sw x14,( 52)(sp) - sw x15,( 56)(sp) - sw x16,( 60)(sp) - sw x17,( 64)(sp) - sw x18,( 68)(sp) - sw x19,( 72)(sp) - sw x20,( 76)(sp) - sw x21,( 80)(sp) - sw x22,( 84)(sp) - sw x23,( 88)(sp) - sw x24,( 92)(sp) - sw x25,( 96)(sp) - sw x26,(100)(sp) - sw x27,(104)(sp) - sw x28,(108)(sp) - sw x29,(112)(sp) - sw x30,(116)(sp) - sw x31,(120)(sp) - csrr a0, mepc - sw a0, (124)(sp) - csrr a0, mstatus - sw a0, (128)(sp) - csrr a0, mcause - sw a0, (132)(sp) - csrr a0, mtval - sw a0, (136)(sp) - csrr a0, mscratch - sw a0, ( 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - - .align 6 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - /* Check for nmi */ - addi sp, sp, -8 - sw t0, 0x0(sp) - sw t1, 0x4(sp) - csrr t0, mcause - andi t0, t0, 0x3FF - li t1, 24 - beq t0, t1, .NMI_Handler - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - j trap -.NMI_Handler: - /* mscratch may be used before */ - addi sp, sp, -4 - csrr t0, mscratch - sw t0, 0x0(sp) - - csrw mscratch, sp - la sp, g_top_trapstack -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, handle_nmi_exception - jalr t0 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 -#if CONFIG_CHECK_FPU_DIRTY - lw t0, 72(sp) - csrw mstatus, t0 -#endif - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - - /* restore mscratch */ - lw t0, 0x0(sp) - csrw mscratch, t0 - addi sp, sp, 4 - - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - - mret - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler tspend_handler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fp/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fp/startup.S deleted file mode 100644 index 65032fbbb7c..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fp/startup.S +++ /dev/null @@ -1,168 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -.section .vectors, "aw", @progbits - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long tspend_handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_IRQHandler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - - /* External interrupts */ - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - - .size __Vectors, . - __Vectors - - .globl Reset_Handler - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 -_start: - .text - .long Reset_Handler - .align 2 - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - la gp, __global_pointer$ -.option pop - la a0, Default_Handler - ori a0, a0, 3 - csrw mtvec, a0 - - la a0, __Vectors - csrw mtvt, a0 - - la sp, g_top_irqstack - csrw mscratch, sp -#ifdef CONFIG_KERNEL_NONE - la sp, g_top_mainstack -#endif - -#ifndef __NO_SYSTEM_INIT - jal SystemInit -#endif - - jal pre_main - - .size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_irqstack: -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK -g_top_mainstack: -#endif - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fp/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fp/system.c deleted file mode 100644 index 904523c669f..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fp/system.c +++ /dev/null @@ -1,113 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -static void cache_init(void) -{ - csi_dcache_enable(); - csi_icache_enable(); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - section_bss_clear(); -} - -static void clic_init(void) -{ - int i; - - /* get interrupt level from info */ - CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); - - for (i = 0; i < 64; i++) { - CLIC->CLICINT[i].IP = 0; - CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - } - - /* tspend use positive interrupt */ - CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; - csi_irq_enable(Machine_Software_IRQn); -} - -static void interrupt_init(void) -{ - clic_init(); -#ifdef CONFIG_KERNEL_NONE - __enable_excp_irq(); -#endif -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - uint32_t status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); - -#if __riscv_flen - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif - /* enable mexstatus SPUSHEN and disable SPSWAPEN */ -#if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP \ - || CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP - status = __get_MEXSTATUS(); - status |= (0x1 << 16); - status &= ~(0x2 << 16); - __set_MEXSTATUS(status); -#endif - - cache_init(); - section_init(); - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fp/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fp/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fp/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fp/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fp/vectors.S deleted file mode 100644 index 6bb2e9836c3..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906fp/vectors.S +++ /dev/null @@ -1,591 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -#if CONFIG_SUPPORT_IRQ_NESTED -#define IRQ_NESTED_MAX (6) -.section .bss -irq_nested_level: -.long 0 - -irq_nested_mcause: -.long 0, 0, 0, 0, 0, 0 -#endif - -.text - -#if !CONFIG_SUPPORT_IRQ_NESTED - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - csrw mscratch, sp - la sp, g_top_irqstack -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, do_irq - jalr t0 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - mret -#else - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -8 - sw t0, 0(sp) - sw t1, 4(sp) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, 1 - sw t1, (t0) - - li t0, IRQ_NESTED_MAX - /* nested too deeply, may be error happens */ - bgt t1, t0, Default_Handler - - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t0, t0, t1 - csrr t1, mcause - sw t1, (t0) - - la t0, irq_nested_level - lw t1, (t0) - li t0, 1 - bgt t1, t0, .Lnested1 - - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 - - csrw mscratch, sp - la sp, g_top_irqstack - j .Lnested2 -.Lnested1: - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 -.Lnested2: -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - csrs mstatus, 8 - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, do_irq - jalr t0 - - csrc mstatus, 8 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, -1 - sw t1, (t0) - bgt t1, zero, .Lnested3 - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - mret - -.Lnested3: - /* keep mpil in current mcause & load exception code before */ - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t1, t0, t1 - lw t0, (t1) - andi t0, t0, 0x3FF - andi a0, a1, 0xFFFFFC00 - or t0, a0, t0 - csrw mcause, t0 - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - mret -#endif - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 2 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -140 - sw x1, ( 0 )(sp) - sw x3, ( 8 )(sp) - sw x4, ( 12)(sp) - sw x5, ( 16)(sp) - sw x6, ( 20)(sp) - sw x7, ( 24)(sp) - sw x8, ( 28)(sp) - sw x9, ( 32)(sp) - sw x10,( 36)(sp) - sw x11,( 40)(sp) - sw x12,( 44)(sp) - sw x13,( 48)(sp) - sw x14,( 52)(sp) - sw x15,( 56)(sp) - sw x16,( 60)(sp) - sw x17,( 64)(sp) - sw x18,( 68)(sp) - sw x19,( 72)(sp) - sw x20,( 76)(sp) - sw x21,( 80)(sp) - sw x22,( 84)(sp) - sw x23,( 88)(sp) - sw x24,( 92)(sp) - sw x25,( 96)(sp) - sw x26,(100)(sp) - sw x27,(104)(sp) - sw x28,(108)(sp) - sw x29,(112)(sp) - sw x30,(116)(sp) - sw x31,(120)(sp) - csrr a0, mepc - sw a0, (124)(sp) - csrr a0, mstatus - sw a0, (128)(sp) - csrr a0, mcause - sw a0, (132)(sp) - csrr a0, mtval - sw a0, (136)(sp) - csrr a0, mscratch - sw a0, ( 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - - .align 6 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - /* Check for nmi */ - addi sp, sp, -8 - sw t0, 0x0(sp) - sw t1, 0x4(sp) - csrr t0, mcause - andi t0, t0, 0x3FF - li t1, 24 - beq t0, t1, .NMI_Handler - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - j trap -.NMI_Handler: - /* mscratch may be used before */ - addi sp, sp, -4 - csrr t0, mscratch - sw t0, 0x0(sp) - - csrw mscratch, sp - la sp, g_top_trapstack -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, handle_nmi_exception - jalr t0 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 -#if CONFIG_CHECK_FPU_DIRTY - lw t0, 72(sp) - csrw mstatus, t0 -#endif - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - - /* restore mscratch */ - lw t0, 0x0(sp) - csrw mscratch, t0 - addi sp, sp, 4 - - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - - mret - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler tspend_handler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906p/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906p/startup.S deleted file mode 100644 index 65032fbbb7c..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906p/startup.S +++ /dev/null @@ -1,168 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -.section .vectors, "aw", @progbits - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long tspend_handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_IRQHandler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - - /* External interrupts */ - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - - .size __Vectors, . - __Vectors - - .globl Reset_Handler - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 -_start: - .text - .long Reset_Handler - .align 2 - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - la gp, __global_pointer$ -.option pop - la a0, Default_Handler - ori a0, a0, 3 - csrw mtvec, a0 - - la a0, __Vectors - csrw mtvt, a0 - - la sp, g_top_irqstack - csrw mscratch, sp -#ifdef CONFIG_KERNEL_NONE - la sp, g_top_mainstack -#endif - -#ifndef __NO_SYSTEM_INIT - jal SystemInit -#endif - - jal pre_main - - .size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_irqstack: -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK -g_top_mainstack: -#endif - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906p/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906p/system.c deleted file mode 100644 index 904523c669f..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906p/system.c +++ /dev/null @@ -1,113 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -static void cache_init(void) -{ - csi_dcache_enable(); - csi_icache_enable(); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - section_bss_clear(); -} - -static void clic_init(void) -{ - int i; - - /* get interrupt level from info */ - CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); - - for (i = 0; i < 64; i++) { - CLIC->CLICINT[i].IP = 0; - CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - } - - /* tspend use positive interrupt */ - CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; - csi_irq_enable(Machine_Software_IRQn); -} - -static void interrupt_init(void) -{ - clic_init(); -#ifdef CONFIG_KERNEL_NONE - __enable_excp_irq(); -#endif -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - uint32_t status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); - -#if __riscv_flen - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif - /* enable mexstatus SPUSHEN and disable SPSWAPEN */ -#if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP \ - || CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP - status = __get_MEXSTATUS(); - status |= (0x1 << 16); - status &= ~(0x2 << 16); - __set_MEXSTATUS(status); -#endif - - cache_init(); - section_init(); - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906p/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906p/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906p/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906p/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906p/vectors.S deleted file mode 100644 index 6bb2e9836c3..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906p/vectors.S +++ /dev/null @@ -1,591 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -#if CONFIG_SUPPORT_IRQ_NESTED -#define IRQ_NESTED_MAX (6) -.section .bss -irq_nested_level: -.long 0 - -irq_nested_mcause: -.long 0, 0, 0, 0, 0, 0 -#endif - -.text - -#if !CONFIG_SUPPORT_IRQ_NESTED - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - csrw mscratch, sp - la sp, g_top_irqstack -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, do_irq - jalr t0 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - mret -#else - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -8 - sw t0, 0(sp) - sw t1, 4(sp) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, 1 - sw t1, (t0) - - li t0, IRQ_NESTED_MAX - /* nested too deeply, may be error happens */ - bgt t1, t0, Default_Handler - - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t0, t0, t1 - csrr t1, mcause - sw t1, (t0) - - la t0, irq_nested_level - lw t1, (t0) - li t0, 1 - bgt t1, t0, .Lnested1 - - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 - - csrw mscratch, sp - la sp, g_top_irqstack - j .Lnested2 -.Lnested1: - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 -.Lnested2: -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - csrs mstatus, 8 - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, do_irq - jalr t0 - - csrc mstatus, 8 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, -1 - sw t1, (t0) - bgt t1, zero, .Lnested3 - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - mret - -.Lnested3: - /* keep mpil in current mcause & load exception code before */ - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t1, t0, t1 - lw t0, (t1) - andi t0, t0, 0x3FF - andi a0, a1, 0xFFFFFC00 - or t0, a0, t0 - csrw mcause, t0 - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - mret -#endif - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 2 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -140 - sw x1, ( 0 )(sp) - sw x3, ( 8 )(sp) - sw x4, ( 12)(sp) - sw x5, ( 16)(sp) - sw x6, ( 20)(sp) - sw x7, ( 24)(sp) - sw x8, ( 28)(sp) - sw x9, ( 32)(sp) - sw x10,( 36)(sp) - sw x11,( 40)(sp) - sw x12,( 44)(sp) - sw x13,( 48)(sp) - sw x14,( 52)(sp) - sw x15,( 56)(sp) - sw x16,( 60)(sp) - sw x17,( 64)(sp) - sw x18,( 68)(sp) - sw x19,( 72)(sp) - sw x20,( 76)(sp) - sw x21,( 80)(sp) - sw x22,( 84)(sp) - sw x23,( 88)(sp) - sw x24,( 92)(sp) - sw x25,( 96)(sp) - sw x26,(100)(sp) - sw x27,(104)(sp) - sw x28,(108)(sp) - sw x29,(112)(sp) - sw x30,(116)(sp) - sw x31,(120)(sp) - csrr a0, mepc - sw a0, (124)(sp) - csrr a0, mstatus - sw a0, (128)(sp) - csrr a0, mcause - sw a0, (132)(sp) - csrr a0, mtval - sw a0, (136)(sp) - csrr a0, mscratch - sw a0, ( 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - - .align 6 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - /* Check for nmi */ - addi sp, sp, -8 - sw t0, 0x0(sp) - sw t1, 0x4(sp) - csrr t0, mcause - andi t0, t0, 0x3FF - li t1, 24 - beq t0, t1, .NMI_Handler - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - j trap -.NMI_Handler: - /* mscratch may be used before */ - addi sp, sp, -4 - csrr t0, mscratch - sw t0, 0x0(sp) - - csrw mscratch, sp - la sp, g_top_trapstack -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, handle_nmi_exception - jalr t0 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 -#if CONFIG_CHECK_FPU_DIRTY - lw t0, 72(sp) - csrw mstatus, t0 -#endif - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - - /* restore mscratch */ - lw t0, 0x0(sp) - csrw mscratch, t0 - addi sp, sp, 4 - - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - - mret - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler tspend_handler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907f/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907f/startup.S deleted file mode 100644 index b65fed1ed5c..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907f/startup.S +++ /dev/null @@ -1,172 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -.section .vectors, "aw", @progbits - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long tspend_handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_IRQHandler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - - /* External interrupts */ - .long Default_IRQHandler -#if CONFIG_IRQ_LATENCY - .long IRQ_LATENCY_IRQHandler -#else - .long Default_IRQHandler -#endif - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - - .size __Vectors, . - __Vectors - - .globl Reset_Handler - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 -_start: - .text - .long Reset_Handler - .align 2 - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - la gp, __global_pointer$ -.option pop - la a0, Default_Handler - ori a0, a0, 3 - csrw mtvec, a0 - - la a0, __Vectors - csrw mtvt, a0 - - la sp, g_top_irqstack - csrw mscratch, sp -#ifdef CONFIG_KERNEL_NONE - la sp, g_top_mainstack -#endif - -#ifndef __NO_SYSTEM_INIT - jal SystemInit -#endif - - jal pre_main - - .size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_irqstack: -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK -g_top_mainstack: -#endif - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907f/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907f/system.c deleted file mode 100644 index 904523c669f..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907f/system.c +++ /dev/null @@ -1,113 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -static void cache_init(void) -{ - csi_dcache_enable(); - csi_icache_enable(); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - section_bss_clear(); -} - -static void clic_init(void) -{ - int i; - - /* get interrupt level from info */ - CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); - - for (i = 0; i < 64; i++) { - CLIC->CLICINT[i].IP = 0; - CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - } - - /* tspend use positive interrupt */ - CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; - csi_irq_enable(Machine_Software_IRQn); -} - -static void interrupt_init(void) -{ - clic_init(); -#ifdef CONFIG_KERNEL_NONE - __enable_excp_irq(); -#endif -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - uint32_t status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); - -#if __riscv_flen - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif - /* enable mexstatus SPUSHEN and disable SPSWAPEN */ -#if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP \ - || CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP - status = __get_MEXSTATUS(); - status |= (0x1 << 16); - status &= ~(0x2 << 16); - __set_MEXSTATUS(status); -#endif - - cache_init(); - section_init(); - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907f/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907f/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907f/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907f/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907f/vectors.S deleted file mode 100644 index d1f896319f4..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907f/vectors.S +++ /dev/null @@ -1,588 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -#if CONFIG_SUPPORT_IRQ_NESTED -#define IRQ_NESTED_MAX (6) -.section .bss -irq_nested_level: -.long 0 - -irq_nested_mcause: -.long 0, 0, 0, 0, 0, 0 -#endif - -.text - -#if !CONFIG_SUPPORT_IRQ_NESTED - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - csrw mscratch, sp - la sp, g_top_irqstack -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, do_irq - jalr t0 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - mret -#else - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -8 - sw t0, 0(sp) - sw t1, 4(sp) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, 1 - sw t1, (t0) - - li t0, IRQ_NESTED_MAX - /* nested too deeply, may be error happens */ - bgt t1, t0, Default_Handler - - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t0, t0, t1 - csrr t1, mcause - sw t1, (t0) - - la t0, irq_nested_level - lw t1, (t0) - li t0, 1 - bgt t1, t0, .Lnested1 - - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 - - csrw mscratch, sp - la sp, g_top_irqstack - j .Lnested2 -.Lnested1: - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 -.Lnested2: -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) - -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - csrs mstatus, 8 - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, do_irq - jalr t0 - - csrc mstatus, 8 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, -1 - sw t1, (t0) - bgt t1, zero, .Lnested3 - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - mret - -.Lnested3: - /* keep mpil in current mcause & load exception code before */ - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t1, t0, t1 - lw t0, (t1) - andi t0, t0, 0x3FF - andi a0, a1, 0xFFFFFC00 - or t0, a0, t0 - csrw mcause, t0 - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - mret -#endif - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 2 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -140 - sw x1, ( 0 )(sp) - sw x3, ( 8 )(sp) - sw x4, ( 12)(sp) - sw x5, ( 16)(sp) - sw x6, ( 20)(sp) - sw x7, ( 24)(sp) - sw x8, ( 28)(sp) - sw x9, ( 32)(sp) - sw x10,( 36)(sp) - sw x11,( 40)(sp) - sw x12,( 44)(sp) - sw x13,( 48)(sp) - sw x14,( 52)(sp) - sw x15,( 56)(sp) - sw x16,( 60)(sp) - sw x17,( 64)(sp) - sw x18,( 68)(sp) - sw x19,( 72)(sp) - sw x20,( 76)(sp) - sw x21,( 80)(sp) - sw x22,( 84)(sp) - sw x23,( 88)(sp) - sw x24,( 92)(sp) - sw x25,( 96)(sp) - sw x26,(100)(sp) - sw x27,(104)(sp) - sw x28,(108)(sp) - sw x29,(112)(sp) - sw x30,(116)(sp) - sw x31,(120)(sp) - csrr a0, mepc - sw a0, (124)(sp) - csrr a0, mstatus - sw a0, (128)(sp) - csrr a0, mcause - sw a0, (132)(sp) - csrr a0, mtval - sw a0, (136)(sp) - csrr a0, mscratch - sw a0, ( 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - - .align 6 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - /* Check for nmi */ - addi sp, sp, -8 - sw t0, 0x0(sp) - sw t1, 0x4(sp) - csrr t0, mcause - andi t0, t0, 0x3FF - li t1, 24 - beq t0, t1, .NMI_Handler - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - j trap -.NMI_Handler: - /* mscratch may be used before */ - addi sp, sp, -4 - csrr t0, mscratch - sw t0, 0x0(sp) - - csrw mscratch, sp - la sp, g_top_trapstack -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) - -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, handle_nmi_exception - jalr t0 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - - /* restore mscratch */ - lw t0, 0x0(sp) - csrw mscratch, t0 - addi sp, sp, 4 - - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - - mret - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler tspend_handler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fd/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fd/startup.S deleted file mode 100644 index b65fed1ed5c..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fd/startup.S +++ /dev/null @@ -1,172 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -.section .vectors, "aw", @progbits - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long tspend_handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_IRQHandler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - - /* External interrupts */ - .long Default_IRQHandler -#if CONFIG_IRQ_LATENCY - .long IRQ_LATENCY_IRQHandler -#else - .long Default_IRQHandler -#endif - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - - .size __Vectors, . - __Vectors - - .globl Reset_Handler - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 -_start: - .text - .long Reset_Handler - .align 2 - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - la gp, __global_pointer$ -.option pop - la a0, Default_Handler - ori a0, a0, 3 - csrw mtvec, a0 - - la a0, __Vectors - csrw mtvt, a0 - - la sp, g_top_irqstack - csrw mscratch, sp -#ifdef CONFIG_KERNEL_NONE - la sp, g_top_mainstack -#endif - -#ifndef __NO_SYSTEM_INIT - jal SystemInit -#endif - - jal pre_main - - .size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_irqstack: -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK -g_top_mainstack: -#endif - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fd/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fd/system.c deleted file mode 100644 index 904523c669f..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fd/system.c +++ /dev/null @@ -1,113 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -static void cache_init(void) -{ - csi_dcache_enable(); - csi_icache_enable(); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - section_bss_clear(); -} - -static void clic_init(void) -{ - int i; - - /* get interrupt level from info */ - CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); - - for (i = 0; i < 64; i++) { - CLIC->CLICINT[i].IP = 0; - CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - } - - /* tspend use positive interrupt */ - CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; - csi_irq_enable(Machine_Software_IRQn); -} - -static void interrupt_init(void) -{ - clic_init(); -#ifdef CONFIG_KERNEL_NONE - __enable_excp_irq(); -#endif -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - uint32_t status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); - -#if __riscv_flen - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif - /* enable mexstatus SPUSHEN and disable SPSWAPEN */ -#if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP \ - || CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP - status = __get_MEXSTATUS(); - status |= (0x1 << 16); - status &= ~(0x2 << 16); - __set_MEXSTATUS(status); -#endif - - cache_init(); - section_init(); - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fd/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fd/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fd/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fd/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fd/vectors.S deleted file mode 100644 index d1f896319f4..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fd/vectors.S +++ /dev/null @@ -1,588 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -#if CONFIG_SUPPORT_IRQ_NESTED -#define IRQ_NESTED_MAX (6) -.section .bss -irq_nested_level: -.long 0 - -irq_nested_mcause: -.long 0, 0, 0, 0, 0, 0 -#endif - -.text - -#if !CONFIG_SUPPORT_IRQ_NESTED - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - csrw mscratch, sp - la sp, g_top_irqstack -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, do_irq - jalr t0 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - mret -#else - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -8 - sw t0, 0(sp) - sw t1, 4(sp) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, 1 - sw t1, (t0) - - li t0, IRQ_NESTED_MAX - /* nested too deeply, may be error happens */ - bgt t1, t0, Default_Handler - - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t0, t0, t1 - csrr t1, mcause - sw t1, (t0) - - la t0, irq_nested_level - lw t1, (t0) - li t0, 1 - bgt t1, t0, .Lnested1 - - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 - - csrw mscratch, sp - la sp, g_top_irqstack - j .Lnested2 -.Lnested1: - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 -.Lnested2: -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) - -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - csrs mstatus, 8 - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, do_irq - jalr t0 - - csrc mstatus, 8 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, -1 - sw t1, (t0) - bgt t1, zero, .Lnested3 - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - mret - -.Lnested3: - /* keep mpil in current mcause & load exception code before */ - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t1, t0, t1 - lw t0, (t1) - andi t0, t0, 0x3FF - andi a0, a1, 0xFFFFFC00 - or t0, a0, t0 - csrw mcause, t0 - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - mret -#endif - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 2 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -140 - sw x1, ( 0 )(sp) - sw x3, ( 8 )(sp) - sw x4, ( 12)(sp) - sw x5, ( 16)(sp) - sw x6, ( 20)(sp) - sw x7, ( 24)(sp) - sw x8, ( 28)(sp) - sw x9, ( 32)(sp) - sw x10,( 36)(sp) - sw x11,( 40)(sp) - sw x12,( 44)(sp) - sw x13,( 48)(sp) - sw x14,( 52)(sp) - sw x15,( 56)(sp) - sw x16,( 60)(sp) - sw x17,( 64)(sp) - sw x18,( 68)(sp) - sw x19,( 72)(sp) - sw x20,( 76)(sp) - sw x21,( 80)(sp) - sw x22,( 84)(sp) - sw x23,( 88)(sp) - sw x24,( 92)(sp) - sw x25,( 96)(sp) - sw x26,(100)(sp) - sw x27,(104)(sp) - sw x28,(108)(sp) - sw x29,(112)(sp) - sw x30,(116)(sp) - sw x31,(120)(sp) - csrr a0, mepc - sw a0, (124)(sp) - csrr a0, mstatus - sw a0, (128)(sp) - csrr a0, mcause - sw a0, (132)(sp) - csrr a0, mtval - sw a0, (136)(sp) - csrr a0, mscratch - sw a0, ( 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - - .align 6 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - /* Check for nmi */ - addi sp, sp, -8 - sw t0, 0x0(sp) - sw t1, 0x4(sp) - csrr t0, mcause - andi t0, t0, 0x3FF - li t1, 24 - beq t0, t1, .NMI_Handler - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - j trap -.NMI_Handler: - /* mscratch may be used before */ - addi sp, sp, -4 - csrr t0, mscratch - sw t0, 0x0(sp) - - csrw mscratch, sp - la sp, g_top_trapstack -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) - -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, handle_nmi_exception - jalr t0 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - - /* restore mscratch */ - lw t0, 0x0(sp) - csrw mscratch, t0 - addi sp, sp, 4 - - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - - mret - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler tspend_handler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fdp/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fdp/startup.S deleted file mode 100644 index b65fed1ed5c..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fdp/startup.S +++ /dev/null @@ -1,172 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -.section .vectors, "aw", @progbits - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long tspend_handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_IRQHandler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - - /* External interrupts */ - .long Default_IRQHandler -#if CONFIG_IRQ_LATENCY - .long IRQ_LATENCY_IRQHandler -#else - .long Default_IRQHandler -#endif - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - - .size __Vectors, . - __Vectors - - .globl Reset_Handler - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 -_start: - .text - .long Reset_Handler - .align 2 - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - la gp, __global_pointer$ -.option pop - la a0, Default_Handler - ori a0, a0, 3 - csrw mtvec, a0 - - la a0, __Vectors - csrw mtvt, a0 - - la sp, g_top_irqstack - csrw mscratch, sp -#ifdef CONFIG_KERNEL_NONE - la sp, g_top_mainstack -#endif - -#ifndef __NO_SYSTEM_INIT - jal SystemInit -#endif - - jal pre_main - - .size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_irqstack: -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK -g_top_mainstack: -#endif - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fdp/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fdp/system.c deleted file mode 100644 index 904523c669f..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fdp/system.c +++ /dev/null @@ -1,113 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -static void cache_init(void) -{ - csi_dcache_enable(); - csi_icache_enable(); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - section_bss_clear(); -} - -static void clic_init(void) -{ - int i; - - /* get interrupt level from info */ - CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); - - for (i = 0; i < 64; i++) { - CLIC->CLICINT[i].IP = 0; - CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - } - - /* tspend use positive interrupt */ - CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; - csi_irq_enable(Machine_Software_IRQn); -} - -static void interrupt_init(void) -{ - clic_init(); -#ifdef CONFIG_KERNEL_NONE - __enable_excp_irq(); -#endif -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - uint32_t status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); - -#if __riscv_flen - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif - /* enable mexstatus SPUSHEN and disable SPSWAPEN */ -#if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP \ - || CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP - status = __get_MEXSTATUS(); - status |= (0x1 << 16); - status &= ~(0x2 << 16); - __set_MEXSTATUS(status); -#endif - - cache_init(); - section_init(); - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fdp/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fdp/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fdp/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fdp/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fdp/vectors.S deleted file mode 100644 index d1f896319f4..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fdp/vectors.S +++ /dev/null @@ -1,588 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -#if CONFIG_SUPPORT_IRQ_NESTED -#define IRQ_NESTED_MAX (6) -.section .bss -irq_nested_level: -.long 0 - -irq_nested_mcause: -.long 0, 0, 0, 0, 0, 0 -#endif - -.text - -#if !CONFIG_SUPPORT_IRQ_NESTED - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - csrw mscratch, sp - la sp, g_top_irqstack -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, do_irq - jalr t0 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - mret -#else - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -8 - sw t0, 0(sp) - sw t1, 4(sp) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, 1 - sw t1, (t0) - - li t0, IRQ_NESTED_MAX - /* nested too deeply, may be error happens */ - bgt t1, t0, Default_Handler - - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t0, t0, t1 - csrr t1, mcause - sw t1, (t0) - - la t0, irq_nested_level - lw t1, (t0) - li t0, 1 - bgt t1, t0, .Lnested1 - - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 - - csrw mscratch, sp - la sp, g_top_irqstack - j .Lnested2 -.Lnested1: - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 -.Lnested2: -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) - -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - csrs mstatus, 8 - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, do_irq - jalr t0 - - csrc mstatus, 8 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, -1 - sw t1, (t0) - bgt t1, zero, .Lnested3 - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - mret - -.Lnested3: - /* keep mpil in current mcause & load exception code before */ - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t1, t0, t1 - lw t0, (t1) - andi t0, t0, 0x3FF - andi a0, a1, 0xFFFFFC00 - or t0, a0, t0 - csrw mcause, t0 - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - mret -#endif - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 2 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -140 - sw x1, ( 0 )(sp) - sw x3, ( 8 )(sp) - sw x4, ( 12)(sp) - sw x5, ( 16)(sp) - sw x6, ( 20)(sp) - sw x7, ( 24)(sp) - sw x8, ( 28)(sp) - sw x9, ( 32)(sp) - sw x10,( 36)(sp) - sw x11,( 40)(sp) - sw x12,( 44)(sp) - sw x13,( 48)(sp) - sw x14,( 52)(sp) - sw x15,( 56)(sp) - sw x16,( 60)(sp) - sw x17,( 64)(sp) - sw x18,( 68)(sp) - sw x19,( 72)(sp) - sw x20,( 76)(sp) - sw x21,( 80)(sp) - sw x22,( 84)(sp) - sw x23,( 88)(sp) - sw x24,( 92)(sp) - sw x25,( 96)(sp) - sw x26,(100)(sp) - sw x27,(104)(sp) - sw x28,(108)(sp) - sw x29,(112)(sp) - sw x30,(116)(sp) - sw x31,(120)(sp) - csrr a0, mepc - sw a0, (124)(sp) - csrr a0, mstatus - sw a0, (128)(sp) - csrr a0, mcause - sw a0, (132)(sp) - csrr a0, mtval - sw a0, (136)(sp) - csrr a0, mscratch - sw a0, ( 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - - .align 6 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - /* Check for nmi */ - addi sp, sp, -8 - sw t0, 0x0(sp) - sw t1, 0x4(sp) - csrr t0, mcause - andi t0, t0, 0x3FF - li t1, 24 - beq t0, t1, .NMI_Handler - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - j trap -.NMI_Handler: - /* mscratch may be used before */ - addi sp, sp, -4 - csrr t0, mscratch - sw t0, 0x0(sp) - - csrw mscratch, sp - la sp, g_top_trapstack -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) - -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, handle_nmi_exception - jalr t0 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - - /* restore mscratch */ - lw t0, 0x0(sp) - csrw mscratch, t0 - addi sp, sp, 4 - - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - - mret - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler tspend_handler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fp/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fp/startup.S deleted file mode 100644 index b65fed1ed5c..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fp/startup.S +++ /dev/null @@ -1,172 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -.section .vectors, "aw", @progbits - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long tspend_handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_IRQHandler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - - /* External interrupts */ - .long Default_IRQHandler -#if CONFIG_IRQ_LATENCY - .long IRQ_LATENCY_IRQHandler -#else - .long Default_IRQHandler -#endif - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - - .size __Vectors, . - __Vectors - - .globl Reset_Handler - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 -_start: - .text - .long Reset_Handler - .align 2 - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - la gp, __global_pointer$ -.option pop - la a0, Default_Handler - ori a0, a0, 3 - csrw mtvec, a0 - - la a0, __Vectors - csrw mtvt, a0 - - la sp, g_top_irqstack - csrw mscratch, sp -#ifdef CONFIG_KERNEL_NONE - la sp, g_top_mainstack -#endif - -#ifndef __NO_SYSTEM_INIT - jal SystemInit -#endif - - jal pre_main - - .size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_irqstack: -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK -g_top_mainstack: -#endif - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fp/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fp/system.c deleted file mode 100644 index 904523c669f..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fp/system.c +++ /dev/null @@ -1,113 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -static void cache_init(void) -{ - csi_dcache_enable(); - csi_icache_enable(); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - section_bss_clear(); -} - -static void clic_init(void) -{ - int i; - - /* get interrupt level from info */ - CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); - - for (i = 0; i < 64; i++) { - CLIC->CLICINT[i].IP = 0; - CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - } - - /* tspend use positive interrupt */ - CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; - csi_irq_enable(Machine_Software_IRQn); -} - -static void interrupt_init(void) -{ - clic_init(); -#ifdef CONFIG_KERNEL_NONE - __enable_excp_irq(); -#endif -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - uint32_t status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); - -#if __riscv_flen - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif - /* enable mexstatus SPUSHEN and disable SPSWAPEN */ -#if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP \ - || CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP - status = __get_MEXSTATUS(); - status |= (0x1 << 16); - status &= ~(0x2 << 16); - __set_MEXSTATUS(status); -#endif - - cache_init(); - section_init(); - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fp/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fp/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fp/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fp/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fp/vectors.S deleted file mode 100644 index d1f896319f4..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907fp/vectors.S +++ /dev/null @@ -1,588 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -#if CONFIG_SUPPORT_IRQ_NESTED -#define IRQ_NESTED_MAX (6) -.section .bss -irq_nested_level: -.long 0 - -irq_nested_mcause: -.long 0, 0, 0, 0, 0, 0 -#endif - -.text - -#if !CONFIG_SUPPORT_IRQ_NESTED - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - csrw mscratch, sp - la sp, g_top_irqstack -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, do_irq - jalr t0 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - mret -#else - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -8 - sw t0, 0(sp) - sw t1, 4(sp) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, 1 - sw t1, (t0) - - li t0, IRQ_NESTED_MAX - /* nested too deeply, may be error happens */ - bgt t1, t0, Default_Handler - - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t0, t0, t1 - csrr t1, mcause - sw t1, (t0) - - la t0, irq_nested_level - lw t1, (t0) - li t0, 1 - bgt t1, t0, .Lnested1 - - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 - - csrw mscratch, sp - la sp, g_top_irqstack - j .Lnested2 -.Lnested1: - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 -.Lnested2: -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) - -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - csrs mstatus, 8 - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, do_irq - jalr t0 - - csrc mstatus, 8 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, -1 - sw t1, (t0) - bgt t1, zero, .Lnested3 - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - mret - -.Lnested3: - /* keep mpil in current mcause & load exception code before */ - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t1, t0, t1 - lw t0, (t1) - andi t0, t0, 0x3FF - andi a0, a1, 0xFFFFFC00 - or t0, a0, t0 - csrw mcause, t0 - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - mret -#endif - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 2 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -140 - sw x1, ( 0 )(sp) - sw x3, ( 8 )(sp) - sw x4, ( 12)(sp) - sw x5, ( 16)(sp) - sw x6, ( 20)(sp) - sw x7, ( 24)(sp) - sw x8, ( 28)(sp) - sw x9, ( 32)(sp) - sw x10,( 36)(sp) - sw x11,( 40)(sp) - sw x12,( 44)(sp) - sw x13,( 48)(sp) - sw x14,( 52)(sp) - sw x15,( 56)(sp) - sw x16,( 60)(sp) - sw x17,( 64)(sp) - sw x18,( 68)(sp) - sw x19,( 72)(sp) - sw x20,( 76)(sp) - sw x21,( 80)(sp) - sw x22,( 84)(sp) - sw x23,( 88)(sp) - sw x24,( 92)(sp) - sw x25,( 96)(sp) - sw x26,(100)(sp) - sw x27,(104)(sp) - sw x28,(108)(sp) - sw x29,(112)(sp) - sw x30,(116)(sp) - sw x31,(120)(sp) - csrr a0, mepc - sw a0, (124)(sp) - csrr a0, mstatus - sw a0, (128)(sp) - csrr a0, mcause - sw a0, (132)(sp) - csrr a0, mtval - sw a0, (136)(sp) - csrr a0, mscratch - sw a0, ( 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - - .align 6 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - /* Check for nmi */ - addi sp, sp, -8 - sw t0, 0x0(sp) - sw t1, 0x4(sp) - csrr t0, mcause - andi t0, t0, 0x3FF - li t1, 24 - beq t0, t1, .NMI_Handler - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - j trap -.NMI_Handler: - /* mscratch may be used before */ - addi sp, sp, -4 - csrr t0, mscratch - sw t0, 0x0(sp) - - csrw mscratch, sp - la sp, g_top_trapstack -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) - -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, handle_nmi_exception - jalr t0 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - - /* restore mscratch */ - lw t0, 0x0(sp) - csrw mscratch, t0 - addi sp, sp, 4 - - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - - mret - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler tspend_handler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907p/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907p/startup.S deleted file mode 100644 index b65fed1ed5c..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907p/startup.S +++ /dev/null @@ -1,172 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -.section .vectors, "aw", @progbits - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long tspend_handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_IRQHandler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long Default_Handler - - /* External interrupts */ - .long Default_IRQHandler -#if CONFIG_IRQ_LATENCY - .long IRQ_LATENCY_IRQHandler -#else - .long Default_IRQHandler -#endif - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - .long Default_IRQHandler - - .size __Vectors, . - __Vectors - - .globl Reset_Handler - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 -_start: - .text - .long Reset_Handler - .align 2 - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - la gp, __global_pointer$ -.option pop - la a0, Default_Handler - ori a0, a0, 3 - csrw mtvec, a0 - - la a0, __Vectors - csrw mtvt, a0 - - la sp, g_top_irqstack - csrw mscratch, sp -#ifdef CONFIG_KERNEL_NONE - la sp, g_top_mainstack -#endif - -#ifndef __NO_SYSTEM_INIT - jal SystemInit -#endif - - jal pre_main - - .size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_irqstack: -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK -g_top_mainstack: -#endif - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907p/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907p/system.c deleted file mode 100644 index 904523c669f..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907p/system.c +++ /dev/null @@ -1,113 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -static void cache_init(void) -{ - csi_dcache_enable(); - csi_icache_enable(); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - section_bss_clear(); -} - -static void clic_init(void) -{ - int i; - - /* get interrupt level from info */ - CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); - - for (i = 0; i < 64; i++) { - CLIC->CLICINT[i].IP = 0; - CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - } - - /* tspend use positive interrupt */ - CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; - csi_irq_enable(Machine_Software_IRQn); -} - -static void interrupt_init(void) -{ - clic_init(); -#ifdef CONFIG_KERNEL_NONE - __enable_excp_irq(); -#endif -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ - /* enable theadisaee & MM */ - uint32_t status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); - -#if __riscv_flen - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif - /* enable mexstatus SPUSHEN and disable SPSWAPEN */ -#if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP \ - || CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP - status = __get_MEXSTATUS(); - status |= (0x1 << 16); - status &= ~(0x2 << 16); - __set_MEXSTATUS(status); -#endif - - cache_init(); - section_init(); - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907p/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907p/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907p/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907p/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907p/vectors.S deleted file mode 100644 index d1f896319f4..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907p/vectors.S +++ /dev/null @@ -1,588 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -#if CONFIG_SUPPORT_IRQ_NESTED -#define IRQ_NESTED_MAX (6) -.section .bss -irq_nested_level: -.long 0 - -irq_nested_mcause: -.long 0, 0, 0, 0, 0, 0 -#endif - -.text - -#if !CONFIG_SUPPORT_IRQ_NESTED - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - csrw mscratch, sp - la sp, g_top_irqstack -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, do_irq - jalr t0 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - mret -#else - .align 2 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -8 - sw t0, 0(sp) - sw t1, 4(sp) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, 1 - sw t1, (t0) - - li t0, IRQ_NESTED_MAX - /* nested too deeply, may be error happens */ - bgt t1, t0, Default_Handler - - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t0, t0, t1 - csrr t1, mcause - sw t1, (t0) - - la t0, irq_nested_level - lw t1, (t0) - li t0, 1 - bgt t1, t0, .Lnested1 - - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 - - csrw mscratch, sp - la sp, g_top_irqstack - j .Lnested2 -.Lnested1: - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 -.Lnested2: -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) - -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - csrs mstatus, 8 - - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, do_irq - jalr t0 - - csrc mstatus, 8 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - la t0, irq_nested_level - lw t1, (t0) - addi t1, t1, -1 - sw t1, (t0) - bgt t1, zero, .Lnested3 - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - mret - -.Lnested3: - /* keep mpil in current mcause & load exception code before */ - addi t1, t1, -1 - la t0, irq_nested_mcause - slli t1, t1, 2 - add t1, t0, t1 - lw t0, (t1) - andi t0, t0, 0x3FF - andi a0, a1, 0xFFFFFC00 - or t0, a0, t0 - csrw mcause, t0 - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - mret -#endif - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 2 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -140 - sw x1, ( 0 )(sp) - sw x3, ( 8 )(sp) - sw x4, ( 12)(sp) - sw x5, ( 16)(sp) - sw x6, ( 20)(sp) - sw x7, ( 24)(sp) - sw x8, ( 28)(sp) - sw x9, ( 32)(sp) - sw x10,( 36)(sp) - sw x11,( 40)(sp) - sw x12,( 44)(sp) - sw x13,( 48)(sp) - sw x14,( 52)(sp) - sw x15,( 56)(sp) - sw x16,( 60)(sp) - sw x17,( 64)(sp) - sw x18,( 68)(sp) - sw x19,( 72)(sp) - sw x20,( 76)(sp) - sw x21,( 80)(sp) - sw x22,( 84)(sp) - sw x23,( 88)(sp) - sw x24,( 92)(sp) - sw x25,( 96)(sp) - sw x26,(100)(sp) - sw x27,(104)(sp) - sw x28,(108)(sp) - sw x29,(112)(sp) - sw x30,(116)(sp) - sw x31,(120)(sp) - csrr a0, mepc - sw a0, (124)(sp) - csrr a0, mstatus - sw a0, (128)(sp) - csrr a0, mcause - sw a0, (132)(sp) - csrr a0, mtval - sw a0, (136)(sp) - csrr a0, mscratch - sw a0, ( 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - - .align 6 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - /* Check for nmi */ - addi sp, sp, -8 - sw t0, 0x0(sp) - sw t1, 0x4(sp) - csrr t0, mcause - andi t0, t0, 0x3FF - li t1, 24 - beq t0, t1, .NMI_Handler - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - j trap -.NMI_Handler: - /* mscratch may be used before */ - addi sp, sp, -4 - csrr t0, mscratch - sw t0, 0x0(sp) - - csrw mscratch, sp - la sp, g_top_trapstack -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif - sw t0, 4(sp) - sw t1, 8(sp) - csrr t0, mepc - csrr t1, mcause - sw t1, 64(sp) - sw t0, 68(sp) - -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif - sw ra, 0(sp) - sw t2, 12(sp) - sw a0, 16(sp) - sw a1, 20(sp) - sw a2, 24(sp) - sw a3, 28(sp) - sw a4, 32(sp) - sw a5, 36(sp) - sw a6, 40(sp) - sw a7, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - -#if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - - la t0, handle_nmi_exception - jalr t0 - - /* get mcause from sp */ - addi t0, sp, 64 -#if __riscv_dsp - addi t0, t0, 4 -#endif /*__riscv_dsp */ -#if __riscv_flen == 64 - addi t0, t0, 164 -#elif __riscv_flen == 32 - addi t0, t0, 84 -#endif - lw a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clear pending */ - li a2, 0xE0801000 - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_FLOAT_REGISTERS - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - - lw t0, 68(sp) - csrw mepc, t0 - lw ra, 0(sp) - lw t0, 4(sp) - lw t1, 8(sp) - lw t2, 12(sp) - lw a0, 16(sp) - lw a1, 20(sp) - lw a2, 24(sp) - lw a3, 28(sp) - lw a4, 32(sp) - lw a5, 36(sp) - lw a6, 40(sp) - lw a7, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - -#if CONFIG_CHECK_FPU_DIRTY - addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif - csrr sp, mscratch - - /* restore mscratch */ - lw t0, 0x0(sp) - csrw mscratch, t0 - addi sp, sp, 4 - - lw t0, 0x0(sp) - lw t1, 0x4(sp) - addi sp, sp, 8 - - mret - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler tspend_handler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908-cp/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908-cp/startup.S deleted file mode 100644 index f6cd7865859..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908-cp/startup.S +++ /dev/null @@ -1,292 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.globl Reset_Handler - -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: -#if CONFIG_INTC_CLIC_PLIC - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - .dword tspend_handler /* 3 */ - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - .dword Mcoret_Handler /* 7 */ - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - .dword Default_IRQHandler /* 11 */ - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - - /* External interrupts */ -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE - .dword ECC_L1_Handler /* 16 */ -#else - .dword Default_IRQHandler /* 16 */ -#endif -#if CONFIG_IRQ_LATENCY - .dword IRQ_LATENCY_IRQHandler -#else - .dword Default_IRQHandler -#endif - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler -#else - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler /* 12 */ - j Default_Handler /* 13 */ - j Default_Handler /* 14 */ - j Default_Handler /* 15 */ -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE - j ECC_L1_Handler /* 16 */ -#else - j Default_Handler /* 16 */ -#endif -#endif - - .size __Vectors, . - __Vectors - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop -#if CONFIG_INTC_CLIC_PLIC - la a0, Default_Handler - ori a0, a0, 3 - csrw mtvec, a0 - - la a0, __Vectors - csrw mtvt, a0 -#else - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 -#endif - - /* get cpu id */ - csrr a0, mhartid - -#if defined(CONFIG_SMP) && CONFIG_SMP - /* check if hart is within range */ - /* tp: hart id */ - li t0, CONFIG_NR_CPUS - bge a0, t0, hart_out_of_bounds_loop -#endif - -#ifdef CONFIG_KERNEL_NONE - la sp, g_base_mainstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_MAINSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */ -#else - la sp, g_base_irqstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ -#endif - - /* other cpu core, jump to cpu entry directly */ - bnez a0, secondary_cpu_entry - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, pre_main - jalr a0 - -.size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - .type secondary_cpu_entry, %function -secondary_cpu_entry: -#if defined(CONFIG_SMP) && CONFIG_SMP - la a0, secondary_boot_flag - ld a0, 0(a0) - li a1, 0xa55a - beq a0, a1, 1f -#endif - j secondary_cpu_entry - -#if defined(CONFIG_SMP) && CONFIG_SMP -1: - jal secondary_cpu_c_start - -.size secondary_cpu_entry, . - secondary_cpu_entry - -hart_out_of_bounds_loop: - /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ - wfi - j hart_out_of_bounds_loop -#endif - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS -g_top_irqstack: - -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS -g_top_mainstack: -#endif - -#if defined(CONFIG_SMP) && CONFIG_SMP -.data -.global secondary_boot_flag -.align 3 -secondary_boot_flag: - .dword 0 -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908-cp/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908-cp/system.c deleted file mode 100644 index 6b9b5b4d028..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908-cp/system.c +++ /dev/null @@ -1,406 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP) -#if CONFIG_NR_CPUS > 1 -#error "Please define CONFIG_NR_CPUS as 1 or do not need define." -#endif -#endif - -#if !CONFIG_INTC_CLIC_PLIC && CONFIG_SUPPORT_IRQ_NESTED -#error "Please disable CONFIG_SUPPORT_IRQ_NESTED in package.yaml when use PLIC." -#endif - -#if CONFIG_ECC_L2_ENABLE -static csi_dev_t ecc_l2_dev; -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void fpp_init(void) -{ -#if CONFIG_FPP_ENABLE - csi_fpp_set_base_addr(0x19000000); - csi_fpp_enable(); -#endif -} - -#if CONFIG_INTC_CLIC_PLIC -static void clic_init(void) -{ - int i; - - /* get interrupt level from info */ - CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); - - for (i = 0; i < 64; i++) { - uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos; - CLIC->CLICINT[i].CTL = (CLIC->CLICINT[i].CTL & (~CLIC_INTCFG_PRIO_Msk)) | (0x1 << (8 - nlbits)); - CLIC->CLICINT[i].IP = 0; - CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - } - - /* tspend use positive interrupt */ - CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; - csi_irq_enable(Machine_Software_IRQn); - - /* enable external plic interrupt */ - csi_irq_enable(Machine_External_IRQn); - -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE - CLIC->CLICINT[L1_CACHE_ECC_IRQn].ATTR = 0x3; - csi_irq_enable(L1_CACHE_ECC_IRQn); -#endif -} -#endif - -static void interrupt_init(void) -{ - int i; - -#if CONFIG_INTC_CLIC_PLIC - clic_init(); - for (i = 0; i < CONFIG_IRQ_NUM - PLIC_IRQ_OFFSET; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM - PLIC_IRQ_OFFSET + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM - PLIC_IRQ_OFFSET + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM - PLIC_IRQ_OFFSET; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; -#else - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE - mie |= (1 << 16); -#endif - __set_MIE(mie); -#endif -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ -#if CONFIG_CPU_XUANTIE_R908_CP || CONFIG_CPU_XUANTIE_R908FD_CP || CONFIG_CPU_XUANTIE_R908FDV_CP - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status &= ~(1 << 22); - status |= (1 << 24 | 1 << 15); - __set_MXSTATUS(status); -#else - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); -#endif - -#if __riscv_flen == 64 - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif - -#if CONFIG_ECC_L1_ENABLE - /* enable L1 cache ecc */ - uint64_t mhint = __get_MHINT(); - mhint |= (0x1 << 19); - __set_MHINT(mhint); -#endif - -#if CONFIG_ECC_L2_ENABLE - /* enable L2 cache ecc */ - uint64_t mccr2 = __get_MCCR2(); - mccr2 |= (0x1 << 1); - __set_MCCR2(mccr2); -#endif - -#if CONFIG_ECC_ITCM_ENABLE - uint64_t mitcmcr = __get_MITCMCR(); - mitcmcr |= MITCMCR_ECC_EN_Msk; - __set_MITCMCR(mitcmcr); -#endif - -#if CONFIG_ECC_DTCM_ENABLE - uint64_t mdtcmcr = __get_MDTCMCR(); - mdtcmcr |= MDTCMCR_ECC_EN_Msk; - __set_MDTCMCR(mdtcmcr); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); - -#if CBO_INSN_SUPPORT - unsigned long envcfg = __get_MENVCFG(); - /* enable CBIE & CBCFE & CBZE on lower priviledge */ - envcfg |= (3 << 4 | 1 << 6 | 1 << 7); - __set_MENVCFG(envcfg); -#endif -#endif - - cache_init(); - section_init(); - pmp_init(); - fpp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); - -#if CONFIG_ECC_L2_ENABLE - extern void ecc_l2_irqhandler(void *arg); - /* l2 cache ecc interrupt register */ - ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn; - csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev); - csi_irq_enable(ecc_l2_dev.irq_num); -#endif -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908-cp/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908-cp/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908-cp/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908-cp/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908-cp/vectors.S deleted file mode 100644 index e5417cc677a..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908-cp/vectors.S +++ /dev/null @@ -1,983 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -#if CONFIG_INTC_CLIC_PLIC - -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 - -#if CONFIG_SUPPORT_IRQ_NESTED -#define IRQ_NESTED_MAX (6) - -.section .bss -.align 3 -.global irq_nested_level -irq_nested_level: - .space 8 * CONFIG_NR_CPUS -irq_nested_level_end: - -irq_nested_mcause: - .space 8 * CONFIG_NR_CPUS * IRQ_NESTED_MAX -irq_nested_mcause_end: -#endif - -.text - -#if !CONFIG_SUPPORT_IRQ_NESTED - .align 3 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - sd s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, -(76+76) -#else - addi sp, sp, -(72+72) -#endif - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - csrr t0, mepc - sd t1, (64+64)(sp) - sd t0, (68+68)(sp) -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t0, mstatus - sd t0, (72+72)(sp) -#endif - sd ra, (0)(sp) - sd t2, (12+12)(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t0, do_irq - jalr t0 - - csrr a1, mcause - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clic clear pending */ - li a2, 0x0c011000 /* clic base address */ - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (68+68)(sp) - csrw mepc, t0 - ld ra, (0)(sp) - ld t0, (4+4)(sp) - ld t1, (8+8)(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, (76+76) -#else - addi sp, sp, (72+72) -#endif - csrr sp, mscratch -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret -#else /* CONFIG_SUPPORT_IRQ_NESTED */ - .align 3 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -(8+8+8+8) - sd t0, 0(sp) - sd t1, (4+4)(sp) - sd t2, (8+8)(sp) - sd t3, (12+12)(sp) - - csrr t3, mhartid - - la t0, irq_nested_level - slli t2, t3, 3 /* mhartid * 8 */ - add t0, t0, t2 - ld t1, (t0) - addi t1, t1, 1 - sd t1, (t0) - - li t0, IRQ_NESTED_MAX - /* nested too deeply, may be error happens */ - bgt t1, t0, Default_Handler - - addi t1, t1, -1 - la t0, irq_nested_mcause - li t2, 8 * IRQ_NESTED_MAX - mul t2, t2, t3 - slli t1, t1, 3 - add t2, t2, t1 - add t0, t0, t2 - - csrr t1, mcause - sd t1, (t0) - - la t0, irq_nested_level - slli t2, t3, 3 /* mhartid * 8 */ - add t0, t0, t2 - ld t1, (t0) - li t0, 1 - bgt t1, t0, .Lnested1 - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -16 - sd s0, (sp) - csrr t0, mepc - sd t0, 8(sp) -#endif - csrw mscratch, sp - la sp, g_base_irqstack - addi t1, t3, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - j .Lnested2 -.Lnested1: - ld t0, 0(sp) - ld t1, (4+4)(sp) - ld t2, (8+8)(sp) - ld t3, (12+12)(sp) - addi sp, sp, (8+8+8+8) -.Lnested2: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, -(76+76) -#else - addi sp, sp, -(72+72) -#endif - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - csrr t0, mepc - sd t1, (64+64)(sp) - sd t0, (68+68)(sp) -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t0, mstatus - sd t0, (72+72)(sp) -#endif - csrs mstatus, 8 - - sd ra, 0(sp) - sd t2, (12+12)(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t0, do_irq - jalr t0 - - csrc mstatus, 8 - - /* get mcause from irq_nested_mcause */ - csrr t3, mhartid - la t0, irq_nested_level - slli t2, t3, 3 /* mhartid * 8 */ - add t0, t0, t2 - ld t1, (t0) - addi t1, t1, -1 - la t0, irq_nested_mcause - li t2, 8 * IRQ_NESTED_MAX - mul t2, t2, t3 - slli t1, t1, 3 - add t2, t2, t1 - add t0, t0, t2 - - ld a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clic clear pending */ - li a2, 0x0c011000 /* clic base address */ - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - la t0, irq_nested_level - slli t2, t3, 3 /* mhartid * 8 */ - add t0, t0, t2 - ld t1, (t0) - addi t1, t1, -1 - sd t1, (t0) - bgt t1, zero, .Lnested3 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (68+68)(sp) - csrw mepc, t0 - ld ra, 0(sp) - ld t0, (4+4)(sp) - ld t1, (8+8)(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, (76+76) -#else - addi sp, sp, (72+72) -#endif - csrr sp, mscratch -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 16 -#endif - ld t0, 0(sp) - ld t1, (4+4)(sp) - ld t2, (8+8)(sp) - ld t3, (12+12)(sp) - addi sp, sp, (8+8+8+8) - mret - -.Lnested3: - /* keep mpil in current mcause & load exception code before */ - addi t1, t1, -1 - la t0, irq_nested_mcause - li t2, 8 * IRQ_NESTED_MAX - mul t2, t2, t3 - slli t1, t1, 3 - add t2, t2, t1 - add t0, t0, t2 - mv t1, t0 - - ld t0, (t1) - andi t0, t0, 0x3FF - srli a0, a1, 11 - slli a0, a0, 11 - or t0, a0, t0 - csrw mcause, t0 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (68+68)(sp) - csrw mepc, t0 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - ld ra, 0(sp) - ld t0, (4+4)(sp) - ld t1, (8+8)(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, (76+76) -#else - addi sp, sp, (72+72) -#endif - mret -#endif /* CONFIG_SUPPORT_IRQ_NESTED */ - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - j Default_IRQHandler - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -(140+140) - sd x1, ( 0 )(sp) - sd x3, ( 8+8)(sp) - sd x4, ( 12+12)(sp) - sd x5, ( 16+16)(sp) - sd x6, ( 20+20)(sp) - sd x7, ( 24+24)(sp) - sd x8, ( 28+28)(sp) - sd x9, ( 32+32)(sp) - sd x10,( 36+36)(sp) - sd x11,( 40+40)(sp) - sd x12,( 44+44)(sp) - sd x13,( 48+48)(sp) - sd x14,( 52+52)(sp) - sd x15,( 56+56)(sp) - sd x16,( 60+60)(sp) - sd x17,( 64+64)(sp) - sd x18,( 68+68)(sp) - sd x19,( 72+72)(sp) - sd x20,( 76+76)(sp) - sd x21,( 80+80)(sp) - sd x22,( 84+84)(sp) - sd x23,( 88+88)(sp) - sd x24,( 92+92)(sp) - sd x25,( 96+96)(sp) - sd x26,(100+100)(sp) - sd x27,(104+104)(sp) - sd x28,(108+108)(sp) - sd x29,(112+112)(sp) - sd x30,(116+116)(sp) - sd x31,(120+120)(sp) - csrr a0, mepc - sd a0, (124+124)(sp) - csrr a0, mstatus - sd a0, (128+128)(sp) - csrr a0, mcause - sd a0, (132+132)(sp) - csrr a0, mtval - sd a0, (136+136)(sp) - csrr a0, mscratch - sd a0, ( 4+4)(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - - .align 6 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler tspend_handler - -#else /* !CONFIG_INTC_CLIC_PLIC */ - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw sstatus, t0 - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw mstatus, t0 - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw sstatus, t0 - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - sd s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw mstatus, t0 - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -(140+140) - sd x1, ( 0 + 0 )(sp) - sd x3, ( 8 + 8 )(sp) - sd x4, ( 12+ 12)(sp) - sd x5, ( 16+ 16)(sp) - sd x6, ( 20+ 20)(sp) - sd x7, ( 24+ 24)(sp) - sd x8, ( 28+ 28)(sp) - sd x9, ( 32+ 32)(sp) - sd x10,( 36+ 36)(sp) - sd x11,( 40+ 40)(sp) - sd x12,( 44+ 44)(sp) - sd x13,( 48+ 48)(sp) - sd x14,( 52+ 52)(sp) - sd x15,( 56+ 56)(sp) - sd x16,( 60+ 60)(sp) - sd x17,( 64+ 64)(sp) - sd x18,( 68+ 68)(sp) - sd x19,( 72+ 72)(sp) - sd x20,( 76+ 76)(sp) - sd x21,( 80+ 80)(sp) - sd x22,( 84+ 84)(sp) - sd x23,( 88+ 88)(sp) - sd x24,( 92+ 92)(sp) - sd x25,( 96+ 96)(sp) - sd x26,(100+100)(sp) - sd x27,(104+104)(sp) - sd x28,(108+108)(sp) - sd x29,(112+112)(sp) - sd x30,(116+116)(sp) - sd x31,(120+120)(sp) - csrr a0, mepc - sd a0, (124+124)(sp) - csrr a0, mstatus - sd a0, (128+128)(sp) - csrr a0, mcause - sd a0, (132+132)(sp) - csrr a0, mtval - sd a0, (136+136)(sp) - csrr a0, mscratch - sd a0, ( 4 + 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler -#endif - -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE -.text - .align 3 - .weak ECC_L1_Handler - .type ECC_L1_Handler, %function -ECC_L1_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, ECC_L1_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw mstatus, t0 - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - .size ECC_L1_Handler, . - ECC_L1_Handler -#endif /* CONFIG_INTC_CLIC_PLIC */ diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908/SConscript b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908/SConscript new file mode 100644 index 00000000000..7c13ee46652 --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908/SConscript @@ -0,0 +1,13 @@ +from building import * +import os + +cwd = GetCurrentDir() +CPPPATH = [cwd] +src = ['startup.S'] +src += ['system.c'] +src += ['trap_c.c'] +src += ['vectors.S'] + +group = DefineGroup('sys', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908/startup.S index f6cd7865859..14c3bf68ccf 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908/startup.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908/startup.S @@ -21,7 +21,7 @@ #ifndef CONFIG_NR_CPUS #define CONFIG_NR_CPUS 1 #endif - +.global __rt_rvstack .globl Reset_Handler .section .vectors @@ -236,7 +236,7 @@ Reset_Handler: #endif #endif - la a0, pre_main + la a0, rtthread_startup jalr a0 .size Reset_Handler, . - Reset_Handler @@ -273,6 +273,7 @@ hart_out_of_bounds_loop: g_base_irqstack: .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS g_top_irqstack: +__rt_rvstack: #ifdef CONFIG_KERNEL_NONE .align 4 diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd-cp/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd-cp/startup.S deleted file mode 100644 index f6cd7865859..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd-cp/startup.S +++ /dev/null @@ -1,292 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.globl Reset_Handler - -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: -#if CONFIG_INTC_CLIC_PLIC - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - .dword tspend_handler /* 3 */ - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - .dword Mcoret_Handler /* 7 */ - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - .dword Default_IRQHandler /* 11 */ - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - - /* External interrupts */ -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE - .dword ECC_L1_Handler /* 16 */ -#else - .dword Default_IRQHandler /* 16 */ -#endif -#if CONFIG_IRQ_LATENCY - .dword IRQ_LATENCY_IRQHandler -#else - .dword Default_IRQHandler -#endif - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler -#else - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler /* 12 */ - j Default_Handler /* 13 */ - j Default_Handler /* 14 */ - j Default_Handler /* 15 */ -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE - j ECC_L1_Handler /* 16 */ -#else - j Default_Handler /* 16 */ -#endif -#endif - - .size __Vectors, . - __Vectors - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop -#if CONFIG_INTC_CLIC_PLIC - la a0, Default_Handler - ori a0, a0, 3 - csrw mtvec, a0 - - la a0, __Vectors - csrw mtvt, a0 -#else - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 -#endif - - /* get cpu id */ - csrr a0, mhartid - -#if defined(CONFIG_SMP) && CONFIG_SMP - /* check if hart is within range */ - /* tp: hart id */ - li t0, CONFIG_NR_CPUS - bge a0, t0, hart_out_of_bounds_loop -#endif - -#ifdef CONFIG_KERNEL_NONE - la sp, g_base_mainstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_MAINSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */ -#else - la sp, g_base_irqstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ -#endif - - /* other cpu core, jump to cpu entry directly */ - bnez a0, secondary_cpu_entry - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, pre_main - jalr a0 - -.size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - .type secondary_cpu_entry, %function -secondary_cpu_entry: -#if defined(CONFIG_SMP) && CONFIG_SMP - la a0, secondary_boot_flag - ld a0, 0(a0) - li a1, 0xa55a - beq a0, a1, 1f -#endif - j secondary_cpu_entry - -#if defined(CONFIG_SMP) && CONFIG_SMP -1: - jal secondary_cpu_c_start - -.size secondary_cpu_entry, . - secondary_cpu_entry - -hart_out_of_bounds_loop: - /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ - wfi - j hart_out_of_bounds_loop -#endif - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS -g_top_irqstack: - -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS -g_top_mainstack: -#endif - -#if defined(CONFIG_SMP) && CONFIG_SMP -.data -.global secondary_boot_flag -.align 3 -secondary_boot_flag: - .dword 0 -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd-cp/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd-cp/system.c deleted file mode 100644 index 6b9b5b4d028..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd-cp/system.c +++ /dev/null @@ -1,406 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP) -#if CONFIG_NR_CPUS > 1 -#error "Please define CONFIG_NR_CPUS as 1 or do not need define." -#endif -#endif - -#if !CONFIG_INTC_CLIC_PLIC && CONFIG_SUPPORT_IRQ_NESTED -#error "Please disable CONFIG_SUPPORT_IRQ_NESTED in package.yaml when use PLIC." -#endif - -#if CONFIG_ECC_L2_ENABLE -static csi_dev_t ecc_l2_dev; -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void fpp_init(void) -{ -#if CONFIG_FPP_ENABLE - csi_fpp_set_base_addr(0x19000000); - csi_fpp_enable(); -#endif -} - -#if CONFIG_INTC_CLIC_PLIC -static void clic_init(void) -{ - int i; - - /* get interrupt level from info */ - CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); - - for (i = 0; i < 64; i++) { - uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos; - CLIC->CLICINT[i].CTL = (CLIC->CLICINT[i].CTL & (~CLIC_INTCFG_PRIO_Msk)) | (0x1 << (8 - nlbits)); - CLIC->CLICINT[i].IP = 0; - CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - } - - /* tspend use positive interrupt */ - CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; - csi_irq_enable(Machine_Software_IRQn); - - /* enable external plic interrupt */ - csi_irq_enable(Machine_External_IRQn); - -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE - CLIC->CLICINT[L1_CACHE_ECC_IRQn].ATTR = 0x3; - csi_irq_enable(L1_CACHE_ECC_IRQn); -#endif -} -#endif - -static void interrupt_init(void) -{ - int i; - -#if CONFIG_INTC_CLIC_PLIC - clic_init(); - for (i = 0; i < CONFIG_IRQ_NUM - PLIC_IRQ_OFFSET; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM - PLIC_IRQ_OFFSET + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM - PLIC_IRQ_OFFSET + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM - PLIC_IRQ_OFFSET; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; -#else - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE - mie |= (1 << 16); -#endif - __set_MIE(mie); -#endif -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ -#if CONFIG_CPU_XUANTIE_R908_CP || CONFIG_CPU_XUANTIE_R908FD_CP || CONFIG_CPU_XUANTIE_R908FDV_CP - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status &= ~(1 << 22); - status |= (1 << 24 | 1 << 15); - __set_MXSTATUS(status); -#else - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); -#endif - -#if __riscv_flen == 64 - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif - -#if CONFIG_ECC_L1_ENABLE - /* enable L1 cache ecc */ - uint64_t mhint = __get_MHINT(); - mhint |= (0x1 << 19); - __set_MHINT(mhint); -#endif - -#if CONFIG_ECC_L2_ENABLE - /* enable L2 cache ecc */ - uint64_t mccr2 = __get_MCCR2(); - mccr2 |= (0x1 << 1); - __set_MCCR2(mccr2); -#endif - -#if CONFIG_ECC_ITCM_ENABLE - uint64_t mitcmcr = __get_MITCMCR(); - mitcmcr |= MITCMCR_ECC_EN_Msk; - __set_MITCMCR(mitcmcr); -#endif - -#if CONFIG_ECC_DTCM_ENABLE - uint64_t mdtcmcr = __get_MDTCMCR(); - mdtcmcr |= MDTCMCR_ECC_EN_Msk; - __set_MDTCMCR(mdtcmcr); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); - -#if CBO_INSN_SUPPORT - unsigned long envcfg = __get_MENVCFG(); - /* enable CBIE & CBCFE & CBZE on lower priviledge */ - envcfg |= (3 << 4 | 1 << 6 | 1 << 7); - __set_MENVCFG(envcfg); -#endif -#endif - - cache_init(); - section_init(); - pmp_init(); - fpp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); - -#if CONFIG_ECC_L2_ENABLE - extern void ecc_l2_irqhandler(void *arg); - /* l2 cache ecc interrupt register */ - ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn; - csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev); - csi_irq_enable(ecc_l2_dev.irq_num); -#endif -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd-cp/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd-cp/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd-cp/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd-cp/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd-cp/vectors.S deleted file mode 100644 index e5417cc677a..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd-cp/vectors.S +++ /dev/null @@ -1,983 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -#if CONFIG_INTC_CLIC_PLIC - -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 - -#if CONFIG_SUPPORT_IRQ_NESTED -#define IRQ_NESTED_MAX (6) - -.section .bss -.align 3 -.global irq_nested_level -irq_nested_level: - .space 8 * CONFIG_NR_CPUS -irq_nested_level_end: - -irq_nested_mcause: - .space 8 * CONFIG_NR_CPUS * IRQ_NESTED_MAX -irq_nested_mcause_end: -#endif - -.text - -#if !CONFIG_SUPPORT_IRQ_NESTED - .align 3 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - sd s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, -(76+76) -#else - addi sp, sp, -(72+72) -#endif - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - csrr t0, mepc - sd t1, (64+64)(sp) - sd t0, (68+68)(sp) -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t0, mstatus - sd t0, (72+72)(sp) -#endif - sd ra, (0)(sp) - sd t2, (12+12)(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t0, do_irq - jalr t0 - - csrr a1, mcause - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clic clear pending */ - li a2, 0x0c011000 /* clic base address */ - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (68+68)(sp) - csrw mepc, t0 - ld ra, (0)(sp) - ld t0, (4+4)(sp) - ld t1, (8+8)(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, (76+76) -#else - addi sp, sp, (72+72) -#endif - csrr sp, mscratch -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret -#else /* CONFIG_SUPPORT_IRQ_NESTED */ - .align 3 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -(8+8+8+8) - sd t0, 0(sp) - sd t1, (4+4)(sp) - sd t2, (8+8)(sp) - sd t3, (12+12)(sp) - - csrr t3, mhartid - - la t0, irq_nested_level - slli t2, t3, 3 /* mhartid * 8 */ - add t0, t0, t2 - ld t1, (t0) - addi t1, t1, 1 - sd t1, (t0) - - li t0, IRQ_NESTED_MAX - /* nested too deeply, may be error happens */ - bgt t1, t0, Default_Handler - - addi t1, t1, -1 - la t0, irq_nested_mcause - li t2, 8 * IRQ_NESTED_MAX - mul t2, t2, t3 - slli t1, t1, 3 - add t2, t2, t1 - add t0, t0, t2 - - csrr t1, mcause - sd t1, (t0) - - la t0, irq_nested_level - slli t2, t3, 3 /* mhartid * 8 */ - add t0, t0, t2 - ld t1, (t0) - li t0, 1 - bgt t1, t0, .Lnested1 - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -16 - sd s0, (sp) - csrr t0, mepc - sd t0, 8(sp) -#endif - csrw mscratch, sp - la sp, g_base_irqstack - addi t1, t3, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - j .Lnested2 -.Lnested1: - ld t0, 0(sp) - ld t1, (4+4)(sp) - ld t2, (8+8)(sp) - ld t3, (12+12)(sp) - addi sp, sp, (8+8+8+8) -.Lnested2: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, -(76+76) -#else - addi sp, sp, -(72+72) -#endif - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - csrr t0, mepc - sd t1, (64+64)(sp) - sd t0, (68+68)(sp) -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t0, mstatus - sd t0, (72+72)(sp) -#endif - csrs mstatus, 8 - - sd ra, 0(sp) - sd t2, (12+12)(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t0, do_irq - jalr t0 - - csrc mstatus, 8 - - /* get mcause from irq_nested_mcause */ - csrr t3, mhartid - la t0, irq_nested_level - slli t2, t3, 3 /* mhartid * 8 */ - add t0, t0, t2 - ld t1, (t0) - addi t1, t1, -1 - la t0, irq_nested_mcause - li t2, 8 * IRQ_NESTED_MAX - mul t2, t2, t3 - slli t1, t1, 3 - add t2, t2, t1 - add t0, t0, t2 - - ld a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clic clear pending */ - li a2, 0x0c011000 /* clic base address */ - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - la t0, irq_nested_level - slli t2, t3, 3 /* mhartid * 8 */ - add t0, t0, t2 - ld t1, (t0) - addi t1, t1, -1 - sd t1, (t0) - bgt t1, zero, .Lnested3 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (68+68)(sp) - csrw mepc, t0 - ld ra, 0(sp) - ld t0, (4+4)(sp) - ld t1, (8+8)(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, (76+76) -#else - addi sp, sp, (72+72) -#endif - csrr sp, mscratch -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 16 -#endif - ld t0, 0(sp) - ld t1, (4+4)(sp) - ld t2, (8+8)(sp) - ld t3, (12+12)(sp) - addi sp, sp, (8+8+8+8) - mret - -.Lnested3: - /* keep mpil in current mcause & load exception code before */ - addi t1, t1, -1 - la t0, irq_nested_mcause - li t2, 8 * IRQ_NESTED_MAX - mul t2, t2, t3 - slli t1, t1, 3 - add t2, t2, t1 - add t0, t0, t2 - mv t1, t0 - - ld t0, (t1) - andi t0, t0, 0x3FF - srli a0, a1, 11 - slli a0, a0, 11 - or t0, a0, t0 - csrw mcause, t0 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (68+68)(sp) - csrw mepc, t0 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - ld ra, 0(sp) - ld t0, (4+4)(sp) - ld t1, (8+8)(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, (76+76) -#else - addi sp, sp, (72+72) -#endif - mret -#endif /* CONFIG_SUPPORT_IRQ_NESTED */ - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - j Default_IRQHandler - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -(140+140) - sd x1, ( 0 )(sp) - sd x3, ( 8+8)(sp) - sd x4, ( 12+12)(sp) - sd x5, ( 16+16)(sp) - sd x6, ( 20+20)(sp) - sd x7, ( 24+24)(sp) - sd x8, ( 28+28)(sp) - sd x9, ( 32+32)(sp) - sd x10,( 36+36)(sp) - sd x11,( 40+40)(sp) - sd x12,( 44+44)(sp) - sd x13,( 48+48)(sp) - sd x14,( 52+52)(sp) - sd x15,( 56+56)(sp) - sd x16,( 60+60)(sp) - sd x17,( 64+64)(sp) - sd x18,( 68+68)(sp) - sd x19,( 72+72)(sp) - sd x20,( 76+76)(sp) - sd x21,( 80+80)(sp) - sd x22,( 84+84)(sp) - sd x23,( 88+88)(sp) - sd x24,( 92+92)(sp) - sd x25,( 96+96)(sp) - sd x26,(100+100)(sp) - sd x27,(104+104)(sp) - sd x28,(108+108)(sp) - sd x29,(112+112)(sp) - sd x30,(116+116)(sp) - sd x31,(120+120)(sp) - csrr a0, mepc - sd a0, (124+124)(sp) - csrr a0, mstatus - sd a0, (128+128)(sp) - csrr a0, mcause - sd a0, (132+132)(sp) - csrr a0, mtval - sd a0, (136+136)(sp) - csrr a0, mscratch - sd a0, ( 4+4)(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - - .align 6 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler tspend_handler - -#else /* !CONFIG_INTC_CLIC_PLIC */ - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw sstatus, t0 - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw mstatus, t0 - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw sstatus, t0 - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - sd s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw mstatus, t0 - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -(140+140) - sd x1, ( 0 + 0 )(sp) - sd x3, ( 8 + 8 )(sp) - sd x4, ( 12+ 12)(sp) - sd x5, ( 16+ 16)(sp) - sd x6, ( 20+ 20)(sp) - sd x7, ( 24+ 24)(sp) - sd x8, ( 28+ 28)(sp) - sd x9, ( 32+ 32)(sp) - sd x10,( 36+ 36)(sp) - sd x11,( 40+ 40)(sp) - sd x12,( 44+ 44)(sp) - sd x13,( 48+ 48)(sp) - sd x14,( 52+ 52)(sp) - sd x15,( 56+ 56)(sp) - sd x16,( 60+ 60)(sp) - sd x17,( 64+ 64)(sp) - sd x18,( 68+ 68)(sp) - sd x19,( 72+ 72)(sp) - sd x20,( 76+ 76)(sp) - sd x21,( 80+ 80)(sp) - sd x22,( 84+ 84)(sp) - sd x23,( 88+ 88)(sp) - sd x24,( 92+ 92)(sp) - sd x25,( 96+ 96)(sp) - sd x26,(100+100)(sp) - sd x27,(104+104)(sp) - sd x28,(108+108)(sp) - sd x29,(112+112)(sp) - sd x30,(116+116)(sp) - sd x31,(120+120)(sp) - csrr a0, mepc - sd a0, (124+124)(sp) - csrr a0, mstatus - sd a0, (128+128)(sp) - csrr a0, mcause - sd a0, (132+132)(sp) - csrr a0, mtval - sd a0, (136+136)(sp) - csrr a0, mscratch - sd a0, ( 4 + 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler -#endif - -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE -.text - .align 3 - .weak ECC_L1_Handler - .type ECC_L1_Handler, %function -ECC_L1_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, ECC_L1_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw mstatus, t0 - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - .size ECC_L1_Handler, . - ECC_L1_Handler -#endif /* CONFIG_INTC_CLIC_PLIC */ diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd/startup.S deleted file mode 100644 index f6cd7865859..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd/startup.S +++ /dev/null @@ -1,292 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.globl Reset_Handler - -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: -#if CONFIG_INTC_CLIC_PLIC - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - .dword tspend_handler /* 3 */ - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - .dword Mcoret_Handler /* 7 */ - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - .dword Default_IRQHandler /* 11 */ - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - - /* External interrupts */ -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE - .dword ECC_L1_Handler /* 16 */ -#else - .dword Default_IRQHandler /* 16 */ -#endif -#if CONFIG_IRQ_LATENCY - .dword IRQ_LATENCY_IRQHandler -#else - .dword Default_IRQHandler -#endif - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler -#else - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler /* 12 */ - j Default_Handler /* 13 */ - j Default_Handler /* 14 */ - j Default_Handler /* 15 */ -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE - j ECC_L1_Handler /* 16 */ -#else - j Default_Handler /* 16 */ -#endif -#endif - - .size __Vectors, . - __Vectors - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop -#if CONFIG_INTC_CLIC_PLIC - la a0, Default_Handler - ori a0, a0, 3 - csrw mtvec, a0 - - la a0, __Vectors - csrw mtvt, a0 -#else - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 -#endif - - /* get cpu id */ - csrr a0, mhartid - -#if defined(CONFIG_SMP) && CONFIG_SMP - /* check if hart is within range */ - /* tp: hart id */ - li t0, CONFIG_NR_CPUS - bge a0, t0, hart_out_of_bounds_loop -#endif - -#ifdef CONFIG_KERNEL_NONE - la sp, g_base_mainstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_MAINSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */ -#else - la sp, g_base_irqstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ -#endif - - /* other cpu core, jump to cpu entry directly */ - bnez a0, secondary_cpu_entry - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, pre_main - jalr a0 - -.size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - .type secondary_cpu_entry, %function -secondary_cpu_entry: -#if defined(CONFIG_SMP) && CONFIG_SMP - la a0, secondary_boot_flag - ld a0, 0(a0) - li a1, 0xa55a - beq a0, a1, 1f -#endif - j secondary_cpu_entry - -#if defined(CONFIG_SMP) && CONFIG_SMP -1: - jal secondary_cpu_c_start - -.size secondary_cpu_entry, . - secondary_cpu_entry - -hart_out_of_bounds_loop: - /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ - wfi - j hart_out_of_bounds_loop -#endif - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS -g_top_irqstack: - -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS -g_top_mainstack: -#endif - -#if defined(CONFIG_SMP) && CONFIG_SMP -.data -.global secondary_boot_flag -.align 3 -secondary_boot_flag: - .dword 0 -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd/system.c deleted file mode 100644 index 6b9b5b4d028..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd/system.c +++ /dev/null @@ -1,406 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP) -#if CONFIG_NR_CPUS > 1 -#error "Please define CONFIG_NR_CPUS as 1 or do not need define." -#endif -#endif - -#if !CONFIG_INTC_CLIC_PLIC && CONFIG_SUPPORT_IRQ_NESTED -#error "Please disable CONFIG_SUPPORT_IRQ_NESTED in package.yaml when use PLIC." -#endif - -#if CONFIG_ECC_L2_ENABLE -static csi_dev_t ecc_l2_dev; -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void fpp_init(void) -{ -#if CONFIG_FPP_ENABLE - csi_fpp_set_base_addr(0x19000000); - csi_fpp_enable(); -#endif -} - -#if CONFIG_INTC_CLIC_PLIC -static void clic_init(void) -{ - int i; - - /* get interrupt level from info */ - CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); - - for (i = 0; i < 64; i++) { - uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos; - CLIC->CLICINT[i].CTL = (CLIC->CLICINT[i].CTL & (~CLIC_INTCFG_PRIO_Msk)) | (0x1 << (8 - nlbits)); - CLIC->CLICINT[i].IP = 0; - CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - } - - /* tspend use positive interrupt */ - CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; - csi_irq_enable(Machine_Software_IRQn); - - /* enable external plic interrupt */ - csi_irq_enable(Machine_External_IRQn); - -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE - CLIC->CLICINT[L1_CACHE_ECC_IRQn].ATTR = 0x3; - csi_irq_enable(L1_CACHE_ECC_IRQn); -#endif -} -#endif - -static void interrupt_init(void) -{ - int i; - -#if CONFIG_INTC_CLIC_PLIC - clic_init(); - for (i = 0; i < CONFIG_IRQ_NUM - PLIC_IRQ_OFFSET; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM - PLIC_IRQ_OFFSET + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM - PLIC_IRQ_OFFSET + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM - PLIC_IRQ_OFFSET; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; -#else - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE - mie |= (1 << 16); -#endif - __set_MIE(mie); -#endif -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ -#if CONFIG_CPU_XUANTIE_R908_CP || CONFIG_CPU_XUANTIE_R908FD_CP || CONFIG_CPU_XUANTIE_R908FDV_CP - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status &= ~(1 << 22); - status |= (1 << 24 | 1 << 15); - __set_MXSTATUS(status); -#else - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); -#endif - -#if __riscv_flen == 64 - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif - -#if CONFIG_ECC_L1_ENABLE - /* enable L1 cache ecc */ - uint64_t mhint = __get_MHINT(); - mhint |= (0x1 << 19); - __set_MHINT(mhint); -#endif - -#if CONFIG_ECC_L2_ENABLE - /* enable L2 cache ecc */ - uint64_t mccr2 = __get_MCCR2(); - mccr2 |= (0x1 << 1); - __set_MCCR2(mccr2); -#endif - -#if CONFIG_ECC_ITCM_ENABLE - uint64_t mitcmcr = __get_MITCMCR(); - mitcmcr |= MITCMCR_ECC_EN_Msk; - __set_MITCMCR(mitcmcr); -#endif - -#if CONFIG_ECC_DTCM_ENABLE - uint64_t mdtcmcr = __get_MDTCMCR(); - mdtcmcr |= MDTCMCR_ECC_EN_Msk; - __set_MDTCMCR(mdtcmcr); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); - -#if CBO_INSN_SUPPORT - unsigned long envcfg = __get_MENVCFG(); - /* enable CBIE & CBCFE & CBZE on lower priviledge */ - envcfg |= (3 << 4 | 1 << 6 | 1 << 7); - __set_MENVCFG(envcfg); -#endif -#endif - - cache_init(); - section_init(); - pmp_init(); - fpp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); - -#if CONFIG_ECC_L2_ENABLE - extern void ecc_l2_irqhandler(void *arg); - /* l2 cache ecc interrupt register */ - ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn; - csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev); - csi_irq_enable(ecc_l2_dev.irq_num); -#endif -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd/vectors.S deleted file mode 100644 index e5417cc677a..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fd/vectors.S +++ /dev/null @@ -1,983 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -#if CONFIG_INTC_CLIC_PLIC - -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 - -#if CONFIG_SUPPORT_IRQ_NESTED -#define IRQ_NESTED_MAX (6) - -.section .bss -.align 3 -.global irq_nested_level -irq_nested_level: - .space 8 * CONFIG_NR_CPUS -irq_nested_level_end: - -irq_nested_mcause: - .space 8 * CONFIG_NR_CPUS * IRQ_NESTED_MAX -irq_nested_mcause_end: -#endif - -.text - -#if !CONFIG_SUPPORT_IRQ_NESTED - .align 3 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - sd s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, -(76+76) -#else - addi sp, sp, -(72+72) -#endif - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - csrr t0, mepc - sd t1, (64+64)(sp) - sd t0, (68+68)(sp) -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t0, mstatus - sd t0, (72+72)(sp) -#endif - sd ra, (0)(sp) - sd t2, (12+12)(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t0, do_irq - jalr t0 - - csrr a1, mcause - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clic clear pending */ - li a2, 0x0c011000 /* clic base address */ - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (68+68)(sp) - csrw mepc, t0 - ld ra, (0)(sp) - ld t0, (4+4)(sp) - ld t1, (8+8)(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, (76+76) -#else - addi sp, sp, (72+72) -#endif - csrr sp, mscratch -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret -#else /* CONFIG_SUPPORT_IRQ_NESTED */ - .align 3 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -(8+8+8+8) - sd t0, 0(sp) - sd t1, (4+4)(sp) - sd t2, (8+8)(sp) - sd t3, (12+12)(sp) - - csrr t3, mhartid - - la t0, irq_nested_level - slli t2, t3, 3 /* mhartid * 8 */ - add t0, t0, t2 - ld t1, (t0) - addi t1, t1, 1 - sd t1, (t0) - - li t0, IRQ_NESTED_MAX - /* nested too deeply, may be error happens */ - bgt t1, t0, Default_Handler - - addi t1, t1, -1 - la t0, irq_nested_mcause - li t2, 8 * IRQ_NESTED_MAX - mul t2, t2, t3 - slli t1, t1, 3 - add t2, t2, t1 - add t0, t0, t2 - - csrr t1, mcause - sd t1, (t0) - - la t0, irq_nested_level - slli t2, t3, 3 /* mhartid * 8 */ - add t0, t0, t2 - ld t1, (t0) - li t0, 1 - bgt t1, t0, .Lnested1 - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -16 - sd s0, (sp) - csrr t0, mepc - sd t0, 8(sp) -#endif - csrw mscratch, sp - la sp, g_base_irqstack - addi t1, t3, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - j .Lnested2 -.Lnested1: - ld t0, 0(sp) - ld t1, (4+4)(sp) - ld t2, (8+8)(sp) - ld t3, (12+12)(sp) - addi sp, sp, (8+8+8+8) -.Lnested2: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, -(76+76) -#else - addi sp, sp, -(72+72) -#endif - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - csrr t0, mepc - sd t1, (64+64)(sp) - sd t0, (68+68)(sp) -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t0, mstatus - sd t0, (72+72)(sp) -#endif - csrs mstatus, 8 - - sd ra, 0(sp) - sd t2, (12+12)(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t0, do_irq - jalr t0 - - csrc mstatus, 8 - - /* get mcause from irq_nested_mcause */ - csrr t3, mhartid - la t0, irq_nested_level - slli t2, t3, 3 /* mhartid * 8 */ - add t0, t0, t2 - ld t1, (t0) - addi t1, t1, -1 - la t0, irq_nested_mcause - li t2, 8 * IRQ_NESTED_MAX - mul t2, t2, t3 - slli t1, t1, 3 - add t2, t2, t1 - add t0, t0, t2 - - ld a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clic clear pending */ - li a2, 0x0c011000 /* clic base address */ - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - la t0, irq_nested_level - slli t2, t3, 3 /* mhartid * 8 */ - add t0, t0, t2 - ld t1, (t0) - addi t1, t1, -1 - sd t1, (t0) - bgt t1, zero, .Lnested3 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (68+68)(sp) - csrw mepc, t0 - ld ra, 0(sp) - ld t0, (4+4)(sp) - ld t1, (8+8)(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, (76+76) -#else - addi sp, sp, (72+72) -#endif - csrr sp, mscratch -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 16 -#endif - ld t0, 0(sp) - ld t1, (4+4)(sp) - ld t2, (8+8)(sp) - ld t3, (12+12)(sp) - addi sp, sp, (8+8+8+8) - mret - -.Lnested3: - /* keep mpil in current mcause & load exception code before */ - addi t1, t1, -1 - la t0, irq_nested_mcause - li t2, 8 * IRQ_NESTED_MAX - mul t2, t2, t3 - slli t1, t1, 3 - add t2, t2, t1 - add t0, t0, t2 - mv t1, t0 - - ld t0, (t1) - andi t0, t0, 0x3FF - srli a0, a1, 11 - slli a0, a0, 11 - or t0, a0, t0 - csrw mcause, t0 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (68+68)(sp) - csrw mepc, t0 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - ld ra, 0(sp) - ld t0, (4+4)(sp) - ld t1, (8+8)(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, (76+76) -#else - addi sp, sp, (72+72) -#endif - mret -#endif /* CONFIG_SUPPORT_IRQ_NESTED */ - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - j Default_IRQHandler - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -(140+140) - sd x1, ( 0 )(sp) - sd x3, ( 8+8)(sp) - sd x4, ( 12+12)(sp) - sd x5, ( 16+16)(sp) - sd x6, ( 20+20)(sp) - sd x7, ( 24+24)(sp) - sd x8, ( 28+28)(sp) - sd x9, ( 32+32)(sp) - sd x10,( 36+36)(sp) - sd x11,( 40+40)(sp) - sd x12,( 44+44)(sp) - sd x13,( 48+48)(sp) - sd x14,( 52+52)(sp) - sd x15,( 56+56)(sp) - sd x16,( 60+60)(sp) - sd x17,( 64+64)(sp) - sd x18,( 68+68)(sp) - sd x19,( 72+72)(sp) - sd x20,( 76+76)(sp) - sd x21,( 80+80)(sp) - sd x22,( 84+84)(sp) - sd x23,( 88+88)(sp) - sd x24,( 92+92)(sp) - sd x25,( 96+96)(sp) - sd x26,(100+100)(sp) - sd x27,(104+104)(sp) - sd x28,(108+108)(sp) - sd x29,(112+112)(sp) - sd x30,(116+116)(sp) - sd x31,(120+120)(sp) - csrr a0, mepc - sd a0, (124+124)(sp) - csrr a0, mstatus - sd a0, (128+128)(sp) - csrr a0, mcause - sd a0, (132+132)(sp) - csrr a0, mtval - sd a0, (136+136)(sp) - csrr a0, mscratch - sd a0, ( 4+4)(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - - .align 6 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler tspend_handler - -#else /* !CONFIG_INTC_CLIC_PLIC */ - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw sstatus, t0 - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw mstatus, t0 - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw sstatus, t0 - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - sd s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw mstatus, t0 - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -(140+140) - sd x1, ( 0 + 0 )(sp) - sd x3, ( 8 + 8 )(sp) - sd x4, ( 12+ 12)(sp) - sd x5, ( 16+ 16)(sp) - sd x6, ( 20+ 20)(sp) - sd x7, ( 24+ 24)(sp) - sd x8, ( 28+ 28)(sp) - sd x9, ( 32+ 32)(sp) - sd x10,( 36+ 36)(sp) - sd x11,( 40+ 40)(sp) - sd x12,( 44+ 44)(sp) - sd x13,( 48+ 48)(sp) - sd x14,( 52+ 52)(sp) - sd x15,( 56+ 56)(sp) - sd x16,( 60+ 60)(sp) - sd x17,( 64+ 64)(sp) - sd x18,( 68+ 68)(sp) - sd x19,( 72+ 72)(sp) - sd x20,( 76+ 76)(sp) - sd x21,( 80+ 80)(sp) - sd x22,( 84+ 84)(sp) - sd x23,( 88+ 88)(sp) - sd x24,( 92+ 92)(sp) - sd x25,( 96+ 96)(sp) - sd x26,(100+100)(sp) - sd x27,(104+104)(sp) - sd x28,(108+108)(sp) - sd x29,(112+112)(sp) - sd x30,(116+116)(sp) - sd x31,(120+120)(sp) - csrr a0, mepc - sd a0, (124+124)(sp) - csrr a0, mstatus - sd a0, (128+128)(sp) - csrr a0, mcause - sd a0, (132+132)(sp) - csrr a0, mtval - sd a0, (136+136)(sp) - csrr a0, mscratch - sd a0, ( 4 + 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler -#endif - -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE -.text - .align 3 - .weak ECC_L1_Handler - .type ECC_L1_Handler, %function -ECC_L1_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, ECC_L1_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw mstatus, t0 - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - .size ECC_L1_Handler, . - ECC_L1_Handler -#endif /* CONFIG_INTC_CLIC_PLIC */ diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv-cp/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv-cp/startup.S deleted file mode 100644 index f6cd7865859..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv-cp/startup.S +++ /dev/null @@ -1,292 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.globl Reset_Handler - -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: -#if CONFIG_INTC_CLIC_PLIC - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - .dword tspend_handler /* 3 */ - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - .dword Mcoret_Handler /* 7 */ - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - .dword Default_IRQHandler /* 11 */ - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - - /* External interrupts */ -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE - .dword ECC_L1_Handler /* 16 */ -#else - .dword Default_IRQHandler /* 16 */ -#endif -#if CONFIG_IRQ_LATENCY - .dword IRQ_LATENCY_IRQHandler -#else - .dword Default_IRQHandler -#endif - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler -#else - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler /* 12 */ - j Default_Handler /* 13 */ - j Default_Handler /* 14 */ - j Default_Handler /* 15 */ -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE - j ECC_L1_Handler /* 16 */ -#else - j Default_Handler /* 16 */ -#endif -#endif - - .size __Vectors, . - __Vectors - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop -#if CONFIG_INTC_CLIC_PLIC - la a0, Default_Handler - ori a0, a0, 3 - csrw mtvec, a0 - - la a0, __Vectors - csrw mtvt, a0 -#else - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 -#endif - - /* get cpu id */ - csrr a0, mhartid - -#if defined(CONFIG_SMP) && CONFIG_SMP - /* check if hart is within range */ - /* tp: hart id */ - li t0, CONFIG_NR_CPUS - bge a0, t0, hart_out_of_bounds_loop -#endif - -#ifdef CONFIG_KERNEL_NONE - la sp, g_base_mainstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_MAINSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */ -#else - la sp, g_base_irqstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ -#endif - - /* other cpu core, jump to cpu entry directly */ - bnez a0, secondary_cpu_entry - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, pre_main - jalr a0 - -.size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - .type secondary_cpu_entry, %function -secondary_cpu_entry: -#if defined(CONFIG_SMP) && CONFIG_SMP - la a0, secondary_boot_flag - ld a0, 0(a0) - li a1, 0xa55a - beq a0, a1, 1f -#endif - j secondary_cpu_entry - -#if defined(CONFIG_SMP) && CONFIG_SMP -1: - jal secondary_cpu_c_start - -.size secondary_cpu_entry, . - secondary_cpu_entry - -hart_out_of_bounds_loop: - /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ - wfi - j hart_out_of_bounds_loop -#endif - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS -g_top_irqstack: - -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS -g_top_mainstack: -#endif - -#if defined(CONFIG_SMP) && CONFIG_SMP -.data -.global secondary_boot_flag -.align 3 -secondary_boot_flag: - .dword 0 -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv-cp/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv-cp/system.c deleted file mode 100644 index 6b9b5b4d028..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv-cp/system.c +++ /dev/null @@ -1,406 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP) -#if CONFIG_NR_CPUS > 1 -#error "Please define CONFIG_NR_CPUS as 1 or do not need define." -#endif -#endif - -#if !CONFIG_INTC_CLIC_PLIC && CONFIG_SUPPORT_IRQ_NESTED -#error "Please disable CONFIG_SUPPORT_IRQ_NESTED in package.yaml when use PLIC." -#endif - -#if CONFIG_ECC_L2_ENABLE -static csi_dev_t ecc_l2_dev; -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void fpp_init(void) -{ -#if CONFIG_FPP_ENABLE - csi_fpp_set_base_addr(0x19000000); - csi_fpp_enable(); -#endif -} - -#if CONFIG_INTC_CLIC_PLIC -static void clic_init(void) -{ - int i; - - /* get interrupt level from info */ - CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); - - for (i = 0; i < 64; i++) { - uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos; - CLIC->CLICINT[i].CTL = (CLIC->CLICINT[i].CTL & (~CLIC_INTCFG_PRIO_Msk)) | (0x1 << (8 - nlbits)); - CLIC->CLICINT[i].IP = 0; - CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - } - - /* tspend use positive interrupt */ - CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; - csi_irq_enable(Machine_Software_IRQn); - - /* enable external plic interrupt */ - csi_irq_enable(Machine_External_IRQn); - -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE - CLIC->CLICINT[L1_CACHE_ECC_IRQn].ATTR = 0x3; - csi_irq_enable(L1_CACHE_ECC_IRQn); -#endif -} -#endif - -static void interrupt_init(void) -{ - int i; - -#if CONFIG_INTC_CLIC_PLIC - clic_init(); - for (i = 0; i < CONFIG_IRQ_NUM - PLIC_IRQ_OFFSET; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM - PLIC_IRQ_OFFSET + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM - PLIC_IRQ_OFFSET + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM - PLIC_IRQ_OFFSET; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; -#else - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE - mie |= (1 << 16); -#endif - __set_MIE(mie); -#endif -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ -#if CONFIG_CPU_XUANTIE_R908_CP || CONFIG_CPU_XUANTIE_R908FD_CP || CONFIG_CPU_XUANTIE_R908FDV_CP - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status &= ~(1 << 22); - status |= (1 << 24 | 1 << 15); - __set_MXSTATUS(status); -#else - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); -#endif - -#if __riscv_flen == 64 - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif - -#if CONFIG_ECC_L1_ENABLE - /* enable L1 cache ecc */ - uint64_t mhint = __get_MHINT(); - mhint |= (0x1 << 19); - __set_MHINT(mhint); -#endif - -#if CONFIG_ECC_L2_ENABLE - /* enable L2 cache ecc */ - uint64_t mccr2 = __get_MCCR2(); - mccr2 |= (0x1 << 1); - __set_MCCR2(mccr2); -#endif - -#if CONFIG_ECC_ITCM_ENABLE - uint64_t mitcmcr = __get_MITCMCR(); - mitcmcr |= MITCMCR_ECC_EN_Msk; - __set_MITCMCR(mitcmcr); -#endif - -#if CONFIG_ECC_DTCM_ENABLE - uint64_t mdtcmcr = __get_MDTCMCR(); - mdtcmcr |= MDTCMCR_ECC_EN_Msk; - __set_MDTCMCR(mdtcmcr); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); - -#if CBO_INSN_SUPPORT - unsigned long envcfg = __get_MENVCFG(); - /* enable CBIE & CBCFE & CBZE on lower priviledge */ - envcfg |= (3 << 4 | 1 << 6 | 1 << 7); - __set_MENVCFG(envcfg); -#endif -#endif - - cache_init(); - section_init(); - pmp_init(); - fpp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); - -#if CONFIG_ECC_L2_ENABLE - extern void ecc_l2_irqhandler(void *arg); - /* l2 cache ecc interrupt register */ - ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn; - csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev); - csi_irq_enable(ecc_l2_dev.irq_num); -#endif -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv-cp/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv-cp/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv-cp/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv-cp/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv-cp/vectors.S deleted file mode 100644 index e5417cc677a..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv-cp/vectors.S +++ /dev/null @@ -1,983 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -#if CONFIG_INTC_CLIC_PLIC - -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 - -#if CONFIG_SUPPORT_IRQ_NESTED -#define IRQ_NESTED_MAX (6) - -.section .bss -.align 3 -.global irq_nested_level -irq_nested_level: - .space 8 * CONFIG_NR_CPUS -irq_nested_level_end: - -irq_nested_mcause: - .space 8 * CONFIG_NR_CPUS * IRQ_NESTED_MAX -irq_nested_mcause_end: -#endif - -.text - -#if !CONFIG_SUPPORT_IRQ_NESTED - .align 3 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - sd s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, -(76+76) -#else - addi sp, sp, -(72+72) -#endif - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - csrr t0, mepc - sd t1, (64+64)(sp) - sd t0, (68+68)(sp) -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t0, mstatus - sd t0, (72+72)(sp) -#endif - sd ra, (0)(sp) - sd t2, (12+12)(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t0, do_irq - jalr t0 - - csrr a1, mcause - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clic clear pending */ - li a2, 0x0c011000 /* clic base address */ - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (68+68)(sp) - csrw mepc, t0 - ld ra, (0)(sp) - ld t0, (4+4)(sp) - ld t1, (8+8)(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, (76+76) -#else - addi sp, sp, (72+72) -#endif - csrr sp, mscratch -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret -#else /* CONFIG_SUPPORT_IRQ_NESTED */ - .align 3 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -(8+8+8+8) - sd t0, 0(sp) - sd t1, (4+4)(sp) - sd t2, (8+8)(sp) - sd t3, (12+12)(sp) - - csrr t3, mhartid - - la t0, irq_nested_level - slli t2, t3, 3 /* mhartid * 8 */ - add t0, t0, t2 - ld t1, (t0) - addi t1, t1, 1 - sd t1, (t0) - - li t0, IRQ_NESTED_MAX - /* nested too deeply, may be error happens */ - bgt t1, t0, Default_Handler - - addi t1, t1, -1 - la t0, irq_nested_mcause - li t2, 8 * IRQ_NESTED_MAX - mul t2, t2, t3 - slli t1, t1, 3 - add t2, t2, t1 - add t0, t0, t2 - - csrr t1, mcause - sd t1, (t0) - - la t0, irq_nested_level - slli t2, t3, 3 /* mhartid * 8 */ - add t0, t0, t2 - ld t1, (t0) - li t0, 1 - bgt t1, t0, .Lnested1 - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -16 - sd s0, (sp) - csrr t0, mepc - sd t0, 8(sp) -#endif - csrw mscratch, sp - la sp, g_base_irqstack - addi t1, t3, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - j .Lnested2 -.Lnested1: - ld t0, 0(sp) - ld t1, (4+4)(sp) - ld t2, (8+8)(sp) - ld t3, (12+12)(sp) - addi sp, sp, (8+8+8+8) -.Lnested2: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, -(76+76) -#else - addi sp, sp, -(72+72) -#endif - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - csrr t0, mepc - sd t1, (64+64)(sp) - sd t0, (68+68)(sp) -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t0, mstatus - sd t0, (72+72)(sp) -#endif - csrs mstatus, 8 - - sd ra, 0(sp) - sd t2, (12+12)(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t0, do_irq - jalr t0 - - csrc mstatus, 8 - - /* get mcause from irq_nested_mcause */ - csrr t3, mhartid - la t0, irq_nested_level - slli t2, t3, 3 /* mhartid * 8 */ - add t0, t0, t2 - ld t1, (t0) - addi t1, t1, -1 - la t0, irq_nested_mcause - li t2, 8 * IRQ_NESTED_MAX - mul t2, t2, t3 - slli t1, t1, 3 - add t2, t2, t1 - add t0, t0, t2 - - ld a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clic clear pending */ - li a2, 0x0c011000 /* clic base address */ - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - la t0, irq_nested_level - slli t2, t3, 3 /* mhartid * 8 */ - add t0, t0, t2 - ld t1, (t0) - addi t1, t1, -1 - sd t1, (t0) - bgt t1, zero, .Lnested3 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (68+68)(sp) - csrw mepc, t0 - ld ra, 0(sp) - ld t0, (4+4)(sp) - ld t1, (8+8)(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, (76+76) -#else - addi sp, sp, (72+72) -#endif - csrr sp, mscratch -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 16 -#endif - ld t0, 0(sp) - ld t1, (4+4)(sp) - ld t2, (8+8)(sp) - ld t3, (12+12)(sp) - addi sp, sp, (8+8+8+8) - mret - -.Lnested3: - /* keep mpil in current mcause & load exception code before */ - addi t1, t1, -1 - la t0, irq_nested_mcause - li t2, 8 * IRQ_NESTED_MAX - mul t2, t2, t3 - slli t1, t1, 3 - add t2, t2, t1 - add t0, t0, t2 - mv t1, t0 - - ld t0, (t1) - andi t0, t0, 0x3FF - srli a0, a1, 11 - slli a0, a0, 11 - or t0, a0, t0 - csrw mcause, t0 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (68+68)(sp) - csrw mepc, t0 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - ld ra, 0(sp) - ld t0, (4+4)(sp) - ld t1, (8+8)(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, (76+76) -#else - addi sp, sp, (72+72) -#endif - mret -#endif /* CONFIG_SUPPORT_IRQ_NESTED */ - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - j Default_IRQHandler - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -(140+140) - sd x1, ( 0 )(sp) - sd x3, ( 8+8)(sp) - sd x4, ( 12+12)(sp) - sd x5, ( 16+16)(sp) - sd x6, ( 20+20)(sp) - sd x7, ( 24+24)(sp) - sd x8, ( 28+28)(sp) - sd x9, ( 32+32)(sp) - sd x10,( 36+36)(sp) - sd x11,( 40+40)(sp) - sd x12,( 44+44)(sp) - sd x13,( 48+48)(sp) - sd x14,( 52+52)(sp) - sd x15,( 56+56)(sp) - sd x16,( 60+60)(sp) - sd x17,( 64+64)(sp) - sd x18,( 68+68)(sp) - sd x19,( 72+72)(sp) - sd x20,( 76+76)(sp) - sd x21,( 80+80)(sp) - sd x22,( 84+84)(sp) - sd x23,( 88+88)(sp) - sd x24,( 92+92)(sp) - sd x25,( 96+96)(sp) - sd x26,(100+100)(sp) - sd x27,(104+104)(sp) - sd x28,(108+108)(sp) - sd x29,(112+112)(sp) - sd x30,(116+116)(sp) - sd x31,(120+120)(sp) - csrr a0, mepc - sd a0, (124+124)(sp) - csrr a0, mstatus - sd a0, (128+128)(sp) - csrr a0, mcause - sd a0, (132+132)(sp) - csrr a0, mtval - sd a0, (136+136)(sp) - csrr a0, mscratch - sd a0, ( 4+4)(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - - .align 6 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler tspend_handler - -#else /* !CONFIG_INTC_CLIC_PLIC */ - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw sstatus, t0 - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw mstatus, t0 - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw sstatus, t0 - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - sd s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw mstatus, t0 - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -(140+140) - sd x1, ( 0 + 0 )(sp) - sd x3, ( 8 + 8 )(sp) - sd x4, ( 12+ 12)(sp) - sd x5, ( 16+ 16)(sp) - sd x6, ( 20+ 20)(sp) - sd x7, ( 24+ 24)(sp) - sd x8, ( 28+ 28)(sp) - sd x9, ( 32+ 32)(sp) - sd x10,( 36+ 36)(sp) - sd x11,( 40+ 40)(sp) - sd x12,( 44+ 44)(sp) - sd x13,( 48+ 48)(sp) - sd x14,( 52+ 52)(sp) - sd x15,( 56+ 56)(sp) - sd x16,( 60+ 60)(sp) - sd x17,( 64+ 64)(sp) - sd x18,( 68+ 68)(sp) - sd x19,( 72+ 72)(sp) - sd x20,( 76+ 76)(sp) - sd x21,( 80+ 80)(sp) - sd x22,( 84+ 84)(sp) - sd x23,( 88+ 88)(sp) - sd x24,( 92+ 92)(sp) - sd x25,( 96+ 96)(sp) - sd x26,(100+100)(sp) - sd x27,(104+104)(sp) - sd x28,(108+108)(sp) - sd x29,(112+112)(sp) - sd x30,(116+116)(sp) - sd x31,(120+120)(sp) - csrr a0, mepc - sd a0, (124+124)(sp) - csrr a0, mstatus - sd a0, (128+128)(sp) - csrr a0, mcause - sd a0, (132+132)(sp) - csrr a0, mtval - sd a0, (136+136)(sp) - csrr a0, mscratch - sd a0, ( 4 + 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler -#endif - -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE -.text - .align 3 - .weak ECC_L1_Handler - .type ECC_L1_Handler, %function -ECC_L1_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, ECC_L1_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw mstatus, t0 - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - .size ECC_L1_Handler, . - ECC_L1_Handler -#endif /* CONFIG_INTC_CLIC_PLIC */ diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv/startup.S deleted file mode 100644 index f6cd7865859..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv/startup.S +++ /dev/null @@ -1,292 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.globl Reset_Handler - -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: -#if CONFIG_INTC_CLIC_PLIC - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - .dword tspend_handler /* 3 */ - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - .dword Mcoret_Handler /* 7 */ - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - .dword Default_IRQHandler /* 11 */ - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - .dword Default_Handler - - /* External interrupts */ -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE - .dword ECC_L1_Handler /* 16 */ -#else - .dword Default_IRQHandler /* 16 */ -#endif -#if CONFIG_IRQ_LATENCY - .dword IRQ_LATENCY_IRQHandler -#else - .dword Default_IRQHandler -#endif - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler - .dword Default_IRQHandler -#else - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler /* 12 */ - j Default_Handler /* 13 */ - j Default_Handler /* 14 */ - j Default_Handler /* 15 */ -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE - j ECC_L1_Handler /* 16 */ -#else - j Default_Handler /* 16 */ -#endif -#endif - - .size __Vectors, . - __Vectors - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop -#if CONFIG_INTC_CLIC_PLIC - la a0, Default_Handler - ori a0, a0, 3 - csrw mtvec, a0 - - la a0, __Vectors - csrw mtvt, a0 -#else - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 -#endif - - /* get cpu id */ - csrr a0, mhartid - -#if defined(CONFIG_SMP) && CONFIG_SMP - /* check if hart is within range */ - /* tp: hart id */ - li t0, CONFIG_NR_CPUS - bge a0, t0, hart_out_of_bounds_loop -#endif - -#ifdef CONFIG_KERNEL_NONE - la sp, g_base_mainstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_MAINSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */ -#else - la sp, g_base_irqstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ -#endif - - /* other cpu core, jump to cpu entry directly */ - bnez a0, secondary_cpu_entry - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, pre_main - jalr a0 - -.size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - .type secondary_cpu_entry, %function -secondary_cpu_entry: -#if defined(CONFIG_SMP) && CONFIG_SMP - la a0, secondary_boot_flag - ld a0, 0(a0) - li a1, 0xa55a - beq a0, a1, 1f -#endif - j secondary_cpu_entry - -#if defined(CONFIG_SMP) && CONFIG_SMP -1: - jal secondary_cpu_c_start - -.size secondary_cpu_entry, . - secondary_cpu_entry - -hart_out_of_bounds_loop: - /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ - wfi - j hart_out_of_bounds_loop -#endif - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS -g_top_irqstack: - -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS -g_top_mainstack: -#endif - -#if defined(CONFIG_SMP) && CONFIG_SMP -.data -.global secondary_boot_flag -.align 3 -secondary_boot_flag: - .dword 0 -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv/system.c deleted file mode 100644 index 6b9b5b4d028..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv/system.c +++ /dev/null @@ -1,406 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP) -#if CONFIG_NR_CPUS > 1 -#error "Please define CONFIG_NR_CPUS as 1 or do not need define." -#endif -#endif - -#if !CONFIG_INTC_CLIC_PLIC && CONFIG_SUPPORT_IRQ_NESTED -#error "Please disable CONFIG_SUPPORT_IRQ_NESTED in package.yaml when use PLIC." -#endif - -#if CONFIG_ECC_L2_ENABLE -static csi_dev_t ecc_l2_dev; -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void fpp_init(void) -{ -#if CONFIG_FPP_ENABLE - csi_fpp_set_base_addr(0x19000000); - csi_fpp_enable(); -#endif -} - -#if CONFIG_INTC_CLIC_PLIC -static void clic_init(void) -{ - int i; - - /* get interrupt level from info */ - CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); - - for (i = 0; i < 64; i++) { - uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos; - CLIC->CLICINT[i].CTL = (CLIC->CLICINT[i].CTL & (~CLIC_INTCFG_PRIO_Msk)) | (0x1 << (8 - nlbits)); - CLIC->CLICINT[i].IP = 0; - CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - } - - /* tspend use positive interrupt */ - CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; - csi_irq_enable(Machine_Software_IRQn); - - /* enable external plic interrupt */ - csi_irq_enable(Machine_External_IRQn); - -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE - CLIC->CLICINT[L1_CACHE_ECC_IRQn].ATTR = 0x3; - csi_irq_enable(L1_CACHE_ECC_IRQn); -#endif -} -#endif - -static void interrupt_init(void) -{ - int i; - -#if CONFIG_INTC_CLIC_PLIC - clic_init(); - for (i = 0; i < CONFIG_IRQ_NUM - PLIC_IRQ_OFFSET; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM - PLIC_IRQ_OFFSET + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM - PLIC_IRQ_OFFSET + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM - PLIC_IRQ_OFFSET; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; -#else - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE - mie |= (1 << 16); -#endif - __set_MIE(mie); -#endif -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ -#if CONFIG_CPU_XUANTIE_R908_CP || CONFIG_CPU_XUANTIE_R908FD_CP || CONFIG_CPU_XUANTIE_R908FDV_CP - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status &= ~(1 << 22); - status |= (1 << 24 | 1 << 15); - __set_MXSTATUS(status); -#else - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); -#endif - -#if __riscv_flen == 64 - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif - -#if CONFIG_ECC_L1_ENABLE - /* enable L1 cache ecc */ - uint64_t mhint = __get_MHINT(); - mhint |= (0x1 << 19); - __set_MHINT(mhint); -#endif - -#if CONFIG_ECC_L2_ENABLE - /* enable L2 cache ecc */ - uint64_t mccr2 = __get_MCCR2(); - mccr2 |= (0x1 << 1); - __set_MCCR2(mccr2); -#endif - -#if CONFIG_ECC_ITCM_ENABLE - uint64_t mitcmcr = __get_MITCMCR(); - mitcmcr |= MITCMCR_ECC_EN_Msk; - __set_MITCMCR(mitcmcr); -#endif - -#if CONFIG_ECC_DTCM_ENABLE - uint64_t mdtcmcr = __get_MDTCMCR(); - mdtcmcr |= MDTCMCR_ECC_EN_Msk; - __set_MDTCMCR(mdtcmcr); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); - -#if CBO_INSN_SUPPORT - unsigned long envcfg = __get_MENVCFG(); - /* enable CBIE & CBCFE & CBZE on lower priviledge */ - envcfg |= (3 << 4 | 1 << 6 | 1 << 7); - __set_MENVCFG(envcfg); -#endif -#endif - - cache_init(); - section_init(); - pmp_init(); - fpp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); - -#if CONFIG_ECC_L2_ENABLE - extern void ecc_l2_irqhandler(void *arg); - /* l2 cache ecc interrupt register */ - ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn; - csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev); - csi_irq_enable(ecc_l2_dev.irq_num); -#endif -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv/vectors.S deleted file mode 100644 index e5417cc677a..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908fdv/vectors.S +++ /dev/null @@ -1,983 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -#if CONFIG_INTC_CLIC_PLIC - -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 - -#if CONFIG_SUPPORT_IRQ_NESTED -#define IRQ_NESTED_MAX (6) - -.section .bss -.align 3 -.global irq_nested_level -irq_nested_level: - .space 8 * CONFIG_NR_CPUS -irq_nested_level_end: - -irq_nested_mcause: - .space 8 * CONFIG_NR_CPUS * IRQ_NESTED_MAX -irq_nested_mcause_end: -#endif - -.text - -#if !CONFIG_SUPPORT_IRQ_NESTED - .align 3 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - sd s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, -(76+76) -#else - addi sp, sp, -(72+72) -#endif - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - csrr t0, mepc - sd t1, (64+64)(sp) - sd t0, (68+68)(sp) -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t0, mstatus - sd t0, (72+72)(sp) -#endif - sd ra, (0)(sp) - sd t2, (12+12)(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t0, do_irq - jalr t0 - - csrr a1, mcause - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clic clear pending */ - li a2, 0x0c011000 /* clic base address */ - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (68+68)(sp) - csrw mepc, t0 - ld ra, (0)(sp) - ld t0, (4+4)(sp) - ld t1, (8+8)(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, (76+76) -#else - addi sp, sp, (72+72) -#endif - csrr sp, mscratch -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret -#else /* CONFIG_SUPPORT_IRQ_NESTED */ - .align 3 - .weak Default_IRQHandler - .type Default_IRQHandler, %function -Default_IRQHandler: - addi sp, sp, -(8+8+8+8) - sd t0, 0(sp) - sd t1, (4+4)(sp) - sd t2, (8+8)(sp) - sd t3, (12+12)(sp) - - csrr t3, mhartid - - la t0, irq_nested_level - slli t2, t3, 3 /* mhartid * 8 */ - add t0, t0, t2 - ld t1, (t0) - addi t1, t1, 1 - sd t1, (t0) - - li t0, IRQ_NESTED_MAX - /* nested too deeply, may be error happens */ - bgt t1, t0, Default_Handler - - addi t1, t1, -1 - la t0, irq_nested_mcause - li t2, 8 * IRQ_NESTED_MAX - mul t2, t2, t3 - slli t1, t1, 3 - add t2, t2, t1 - add t0, t0, t2 - - csrr t1, mcause - sd t1, (t0) - - la t0, irq_nested_level - slli t2, t3, 3 /* mhartid * 8 */ - add t0, t0, t2 - ld t1, (t0) - li t0, 1 - bgt t1, t0, .Lnested1 - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -16 - sd s0, (sp) - csrr t0, mepc - sd t0, 8(sp) -#endif - csrw mscratch, sp - la sp, g_base_irqstack - addi t1, t3, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - j .Lnested2 -.Lnested1: - ld t0, 0(sp) - ld t1, (4+4)(sp) - ld t2, (8+8)(sp) - ld t3, (12+12)(sp) - addi sp, sp, (8+8+8+8) -.Lnested2: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, -(76+76) -#else - addi sp, sp, -(72+72) -#endif - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - csrr t0, mepc - sd t1, (64+64)(sp) - sd t0, (68+68)(sp) -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t0, mstatus - sd t0, (72+72)(sp) -#endif - csrs mstatus, 8 - - sd ra, 0(sp) - sd t2, (12+12)(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t0, do_irq - jalr t0 - - csrc mstatus, 8 - - /* get mcause from irq_nested_mcause */ - csrr t3, mhartid - la t0, irq_nested_level - slli t2, t3, 3 /* mhartid * 8 */ - add t0, t0, t2 - ld t1, (t0) - addi t1, t1, -1 - la t0, irq_nested_mcause - li t2, 8 * IRQ_NESTED_MAX - mul t2, t2, t3 - slli t1, t1, 3 - add t2, t2, t1 - add t0, t0, t2 - - ld a1, (t0) - andi a0, a1, 0x3FF - slli a0, a0, 2 - - /* clic clear pending */ - li a2, 0x0c011000 /* clic base address */ - add a2, a2, a0 - lb a3, 0(a2) - li a4, 1 - not a4, a4 - and a5, a4, a3 - sb a5, 0(a2) - - la t0, irq_nested_level - slli t2, t3, 3 /* mhartid * 8 */ - add t0, t0, t2 - ld t1, (t0) - addi t1, t1, -1 - sd t1, (t0) - bgt t1, zero, .Lnested3 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - csrw mcause, a1 - - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (68+68)(sp) - csrw mepc, t0 - ld ra, 0(sp) - ld t0, (4+4)(sp) - ld t1, (8+8)(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, (76+76) -#else - addi sp, sp, (72+72) -#endif - csrr sp, mscratch -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 16 -#endif - ld t0, 0(sp) - ld t1, (4+4)(sp) - ld t2, (8+8)(sp) - ld t3, (12+12)(sp) - addi sp, sp, (8+8+8+8) - mret - -.Lnested3: - /* keep mpil in current mcause & load exception code before */ - addi t1, t1, -1 - la t0, irq_nested_mcause - li t2, 8 * IRQ_NESTED_MAX - mul t2, t2, t3 - slli t1, t1, 3 - add t2, t2, t1 - add t0, t0, t2 - mv t1, t0 - - ld t0, (t1) - andi t0, t0, 0x3FF - srli a0, a1, 11 - slli a0, a0, 11 - or t0, a0, t0 - csrw mcause, t0 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (68+68)(sp) - csrw mepc, t0 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - - ld ra, 0(sp) - ld t0, (4+4)(sp) - ld t1, (8+8)(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - addi sp, sp, (76+76) -#else - addi sp, sp, (72+72) -#endif - mret -#endif /* CONFIG_SUPPORT_IRQ_NESTED */ - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - j Default_IRQHandler - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -(140+140) - sd x1, ( 0 )(sp) - sd x3, ( 8+8)(sp) - sd x4, ( 12+12)(sp) - sd x5, ( 16+16)(sp) - sd x6, ( 20+20)(sp) - sd x7, ( 24+24)(sp) - sd x8, ( 28+28)(sp) - sd x9, ( 32+32)(sp) - sd x10,( 36+36)(sp) - sd x11,( 40+40)(sp) - sd x12,( 44+44)(sp) - sd x13,( 48+48)(sp) - sd x14,( 52+52)(sp) - sd x15,( 56+56)(sp) - sd x16,( 60+60)(sp) - sd x17,( 64+64)(sp) - sd x18,( 68+68)(sp) - sd x19,( 72+72)(sp) - sd x20,( 76+76)(sp) - sd x21,( 80+80)(sp) - sd x22,( 84+84)(sp) - sd x23,( 88+88)(sp) - sd x24,( 92+92)(sp) - sd x25,( 96+96)(sp) - sd x26,(100+100)(sp) - sd x27,(104+104)(sp) - sd x28,(108+108)(sp) - sd x29,(112+112)(sp) - sd x30,(116+116)(sp) - sd x31,(120+120)(sp) - csrr a0, mepc - sd a0, (124+124)(sp) - csrr a0, mstatus - sd a0, (128+128)(sp) - csrr a0, mcause - sd a0, (132+132)(sp) - csrr a0, mtval - sd a0, (136+136)(sp) - csrr a0, mscratch - sd a0, ( 4+4)(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - - .align 6 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler tspend_handler - -#else /* !CONFIG_INTC_CLIC_PLIC */ - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw sstatus, t0 - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw mstatus, t0 - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw sstatus, t0 - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - sd s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw mstatus, t0 - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -(140+140) - sd x1, ( 0 + 0 )(sp) - sd x3, ( 8 + 8 )(sp) - sd x4, ( 12+ 12)(sp) - sd x5, ( 16+ 16)(sp) - sd x6, ( 20+ 20)(sp) - sd x7, ( 24+ 24)(sp) - sd x8, ( 28+ 28)(sp) - sd x9, ( 32+ 32)(sp) - sd x10,( 36+ 36)(sp) - sd x11,( 40+ 40)(sp) - sd x12,( 44+ 44)(sp) - sd x13,( 48+ 48)(sp) - sd x14,( 52+ 52)(sp) - sd x15,( 56+ 56)(sp) - sd x16,( 60+ 60)(sp) - sd x17,( 64+ 64)(sp) - sd x18,( 68+ 68)(sp) - sd x19,( 72+ 72)(sp) - sd x20,( 76+ 76)(sp) - sd x21,( 80+ 80)(sp) - sd x22,( 84+ 84)(sp) - sd x23,( 88+ 88)(sp) - sd x24,( 92+ 92)(sp) - sd x25,( 96+ 96)(sp) - sd x26,(100+100)(sp) - sd x27,(104+104)(sp) - sd x28,(108+108)(sp) - sd x29,(112+112)(sp) - sd x30,(116+116)(sp) - sd x31,(120+120)(sp) - csrr a0, mepc - sd a0, (124+124)(sp) - csrr a0, mstatus - sd a0, (128+128)(sp) - csrr a0, mcause - sd a0, (132+132)(sp) - csrr a0, mtval - sd a0, (136+136)(sp) - csrr a0, mscratch - sd a0, ( 4 + 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler -#endif - -#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_ITCM_ENABLE || CONFIG_ECC_DTCM_ENABLE -.text - .align 3 - .weak ECC_L1_Handler - .type ECC_L1_Handler, %function -ECC_L1_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, ECC_L1_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - - ld t0, (72+72)(sp) - csrw mstatus, t0 - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - .size ECC_L1_Handler, . - ECC_L1_Handler -#endif /* CONFIG_INTC_CLIC_PLIC */ diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r910/SConscript b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r910/SConscript new file mode 100644 index 00000000000..7c13ee46652 --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r910/SConscript @@ -0,0 +1,13 @@ +from building import * +import os + +cwd = GetCurrentDir() +CPPPATH = [cwd] +src = ['startup.S'] +src += ['system.c'] +src += ['trap_c.c'] +src += ['vectors.S'] + +group = DefineGroup('sys', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r910/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r910/startup.S index 92ba69989b2..5877d711f25 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r910/startup.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r910/startup.S @@ -23,7 +23,9 @@ #endif .globl Reset_Handler - +.global __rt_rvstack +.equ Mcoret_Handler, SW_handler +.equ Mirq_Handler, SW_handler .section .vectors .align 6 .globl __Vectors @@ -132,7 +134,7 @@ Reset_Handler: #endif #endif - la a0, pre_main + la a0, rtthread_startup jalr a0 .size Reset_Handler, . - Reset_Handler @@ -169,6 +171,7 @@ hart_out_of_bounds_loop: g_base_irqstack: .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS g_top_irqstack: +__rt_rvstack: #ifdef CONFIG_KERNEL_NONE .align 4 diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r920/SConscript b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r920/SConscript new file mode 100644 index 00000000000..7c13ee46652 --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r920/SConscript @@ -0,0 +1,13 @@ +from building import * +import os + +cwd = GetCurrentDir() +CPPPATH = [cwd] +src = ['startup.S'] +src += ['system.c'] +src += ['trap_c.c'] +src += ['vectors.S'] + +group = DefineGroup('sys', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r920/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r920/startup.S index 92ba69989b2..5877d711f25 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r920/startup.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r920/startup.S @@ -23,7 +23,9 @@ #endif .globl Reset_Handler - +.global __rt_rvstack +.equ Mcoret_Handler, SW_handler +.equ Mirq_Handler, SW_handler .section .vectors .align 6 .globl __Vectors @@ -132,7 +134,7 @@ Reset_Handler: #endif #endif - la a0, pre_main + la a0, rtthread_startup jalr a0 .size Reset_Handler, . - Reset_Handler @@ -169,6 +171,7 @@ hart_out_of_bounds_loop: g_base_irqstack: .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS g_top_irqstack: +__rt_rvstack: #ifdef CONFIG_KERNEL_NONE .align 4 diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/aes.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/aes.c index 2749501431e..ba9d0538386 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/aes.c +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/aes.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * Copyright (C) 2017-2024 Alibaba Group Holding Limited */ /******************************************************* diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/crc.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/crc.c index 6c15756eda0..d01704e883f 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/crc.c +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/crc.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include /** \brief CRC State @@ -124,7 +124,7 @@ csi_error_t csi_crc_config(csi_crc_t *crc, csi_crc_config_t *config) ///< TODO：设置模式 ///< TODO：设置极性 ///< TODO：设置初始值 - + break; case CRC_STANDARD_IBM: diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/i2s.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/i2s.c index e18e16d4a2c..306f81bdc83 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/i2s.c +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/i2s.c @@ -651,7 +651,7 @@ int32_t csi_i2s_send(csi_i2s_t *i2s, const void *data, uint32_t size) if ((uint8_t *)i2s->priv) { ///< if dma is stop, then start it soc_dcache_clean_invalid_range((unsigned long)(i2s->tx_buf->buffer + i2s->tx_buf->read), i2s->tx_period); - + ///< TODO：调用csi_dma_ch_start开启DMA通道发送数据 i2s->priv = (void *)0U; } diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/iic.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/iic.c index ca9b33944b2..761129f8688 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/iic.c +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/iic.c @@ -71,7 +71,7 @@ void dw_iic_slave_rx_handler(void *arg) ///< TODO：根据中断状态接收数据 ///< TODO：根据中断状态处理异常并执行用户回调函数 - + } /** @@ -121,7 +121,7 @@ csi_error_t csi_iic_init(csi_iic_t *iic, uint32_t idx) ///< TODO：关闭IIC所有的中断 ///< TODO：设置IIC从机在接收到来自主机的读取请求时不刷新FIFO中的数据 } - + iic->state.writeable = 1U; iic->state.readable = 1U; iic->state.error = 0U; @@ -158,8 +158,8 @@ void csi_iic_uninit(csi_iic_t *iic) ///< TODO：关闭IIC // 禁止中断控制器对应的中断，注销中断服务函数 - csi_irq_disable((uint32_t)iic->dev.irq_num); - csi_irq_detach((uint32_t)iic->dev.irq_num); + csi_irq_disable((uint32_t)iic->dev.irq_num); + csi_irq_detach((uint32_t)iic->dev.irq_num); } /** @@ -238,7 +238,7 @@ csi_error_t csi_iic_speed(csi_iic_t *iic, csi_iic_speed_t speed) ret = CSI_OK; } else if (speed == IIC_BUS_SPEED_FAST) { - + ///< TODO：设置IIC为快速模式,400KHz ///< TODO：获取IIC使用的频率 ///< TODO：快速模式设置SCL时钟的高周期计数 @@ -370,7 +370,7 @@ static csi_error_t iic_master_send_intr(csi_iic_t *iic, uint32_t devaddr, const ///< TODO：使能发送中断 ///< TODO：设置发送FIFO的触发级别 ///< TODO：打开IIC - + } } @@ -410,7 +410,7 @@ static csi_error_t iic_master_send_dma(csi_iic_t *iic, uint32_t devaddr, const v soc_dcache_clean_invalid_range((unsigned long)iic->data, iic->size); - ///< TODO：调用csi_dma_ch_start开启IIC使用的DMA通道 + ///< TODO：调用csi_dma_ch_start开启IIC使用的DMA通道 ///< TODO：打开IIC return ret; @@ -662,7 +662,7 @@ int32_t csi_iic_mem_receive(csi_iic_t *iic, uint32_t devaddr, uint16_t memaddr, ///< TODO：设置IIC为接收数据模式 } - ///< TODO：等待接收数据，超时则超时退出 + ///< TODO：等待接收数据，超时则超时退出 if (ret == CSI_OK) { for (read_count = 0; read_count < (int32_t)size; read_count++) { @@ -689,7 +689,7 @@ int32_t csi_iic_mem_receive(csi_iic_t *iic, uint32_t devaddr, uint16_t memaddr, } ///< TODO：IIC读数据寄存器接收数据 - + read_count ++; if (cmd_num > 0U) { @@ -874,7 +874,7 @@ csi_error_t csi_iic_slave_send_async(csi_iic_t *iic, const void *data, uint32_t ///< 注册发送中断服务函数、使能中断控制器对应的中断 csi_irq_attach((uint32_t)iic->dev.irq_num, &dw_iic_slave_tx_handler, &iic->dev); csi_irq_enable((uint32_t)iic->dev.irq_num); - + ///< 开始IIC从机模式以中断方式发送数据 iic_slave_send_intr(iic, data, size); } @@ -972,7 +972,7 @@ csi_error_t csi_iic_slave_receive_async(csi_iic_t *iic, void *data, uint32_t siz ///< 初始化接收中断服务函数、使能中断控制器对应的中断 csi_irq_attach((uint32_t)iic->dev.irq_num, &dw_iic_slave_rx_handler, &iic->dev); csi_irq_enable((uint32_t)iic->dev.irq_num); - + ///< TODO：开始IIC从机模式以中断方式发送数据 iic_slave_receive_intr(iic, data, size); } diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/mbox.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/mbox.c index f0b86d730cb..d0b9ac3e65d 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/mbox.c +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/mbox.c @@ -166,7 +166,7 @@ int32_t csi_mbox_receive(csi_mbox_t *mbox, uint32_t channel_id, void *data, uint ///< TODO：往指定的CPU以及该CPU的某个通道写数据（0） } - ///< TODO：禁止指定的CPU以及该CPU的某个通道的中断 + ///< TODO：禁止指定的CPU以及该CPU的某个通道的中断 memcpy(data, buf, size); ///< TODO：往指定的CPU以及该CPU的某个通道写数据（(MBOX_ACK << 16U) | 1U） diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/pwm.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/pwm.c index 9f073473c79..ebb596f659a 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/pwm.c +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/pwm.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * Copyright (C) 2017-2024 Alibaba Group Holding Limited */ /******************************************************* @@ -100,7 +100,7 @@ csi_error_t csi_pwm_out_start(csi_pwm_t *pwm, uint32_t channel) { CSI_PARAM_CHK(pwm, CSI_ERROR); - ///< TODO：打开输出使能 + ///< TODO：打开输出使能 return CSI_OK; } diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/qspi.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/qspi.c index 6f38dd93577..f0aeed631e9 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/qspi.c +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/qspi.c @@ -100,7 +100,7 @@ csi_error_t csi_qspi_mode(csi_qspi_t *qspi, csi_qspi_mode_t mode) case QSPI_CLOCK_MODE_2: ///< TODO：配置QSPI时钟的极性和相位 break; - + case QSPI_CLOCK_MODE_3: ///< TODO：配置QSPI时钟的极性和相位 break; diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/rsa.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/rsa.c index 8b9f6dea4bf..9e9e9af19fc 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/rsa.c +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/rsa.c @@ -36,9 +36,9 @@ #define GET_KEY_WORD(k) (k >> 5U) ///< TODO：RSA_KEY_LEN需要根据实际情况进行设置 -#define RSA_KEY_LEN 2048U ///< 支持RSA秘钥的最大长度 -#define RSA_KEY_BYTE (RSA_KEY_LEN >> 3U) -#define RSA_KEY_WORD (RSA_KEY_LEN >> 5U) +#define RSA_KEY_LEN 2048U ///< 支持RSA秘钥的最大长度 +#define RSA_KEY_BYTE (RSA_KEY_LEN >> 3U) +#define RSA_KEY_WORD (RSA_KEY_LEN >> 5U) #define BN_MAX_BITS ((RSA_KEY_LEN << 1U) + 32U) #define BN_MAX_BYTES ((BN_MAX_BITS + 7U) >> 3U) diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/sha.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/sha.c index d443096e8d1..71e29f497d3 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/sha.c +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/sha.c @@ -1,12 +1,12 @@ /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * Copyright (C) 2017-2024 Alibaba Group Holding Limited */ /******************************************************* - * @file wj_sha.c - * @brief source file for sha csi driver + * @file wj_sha.c + * @brief source file for sha csi driver * @version V2.0 - * @date 14. Sept 2020 + * @date 14. Sept 2020 * ******************************************************/ #include @@ -281,7 +281,7 @@ csi_error_t csi_sha_update(csi_sha_t *sha, csi_sha_context_t *context, const voi sha->state.busy = 1U; ///< TODO：设置SHA 模式 - ///< TODO：用context->state初始化HASH + ///< TODO：用context->state初始化HASH block_size = SHA_GET_BOLOCK_SIZE_BYTES(context->mode); @@ -378,7 +378,7 @@ csi_error_t csi_sha_finish(csi_sha_t *sha, csi_sha_context_t *context, void *out uint64_t pad_bit_len; ///< TODO：设置SHA 模式 - ///< TODO：用context->state初始化HASH + ///< TODO：用context->state初始化HASH block_size = SHA_GET_BOLOCK_SIZE_BYTES(context->mode); msg_length = SHA_GET_MSGLEN_TAIL_4BYTES(context->mode); diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/spiflash.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/spiflash.c index 82d99e29d4d..096ba5f3f24 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/spiflash.c +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/spiflash.c @@ -88,7 +88,7 @@ static int32_t flash_wait_ready(csi_spiflash_t *spiflash) uint8_t cmd; uint8_t status; int32_t ret = CSI_TIMEOUT; - int32_t check; + int32_t check; time_start = csi_tick_get_ms(); cmd = FLASH_CMD_READ_STATUS1; @@ -277,7 +277,7 @@ csi_error_t csi_spiflash_erase(csi_spiflash_t *spiflash, uint32_t offset, uint32 } else if (offset % param->sector_size) { ret = CSI_ERROR; break; - } + } if (( offset == 0U ) && ( size == param->flash_size )){ /* chip erase */ ret = spiflash->spi_send(spiflash, FLASH_CMD_WRITE_ENABLE, 0U, 0U, NULL, 0U); @@ -339,7 +339,7 @@ csi_error_t csi_spiflash_erase(csi_spiflash_t *spiflash, uint32_t offset, uint32 } while (addr < (offset + size)); } } while(0); - + return ( csi_error_t )ret; } @@ -650,8 +650,8 @@ int csi_spiflash_is_locked(csi_spiflash_t *spiflash, uint32_t offset, uint32_t s ret = spiflash->spi_receive(spiflash, FLASH_CMD_READ_STATUS1, 0U, 0U, &status, 1U); if (ret < 0) { ret = CSI_ERROR; - break; - } + break; + } /* Calculate bp msk and tb msk */ bp_bits = param->bp_bits; @@ -682,7 +682,7 @@ csi_error_t csi_spiflash_config_data_line(csi_spiflash_t *spiflash, csi_spiflash temp = status; do { - + /* config spiflash periphrial data line */ switch (line) { case SPIFLASH_DATA_1_LINE: @@ -695,18 +695,18 @@ csi_error_t csi_spiflash_config_data_line(csi_spiflash_t *spiflash, csi_spiflash if (ret < 0) { ret = CSI_ERROR; - break; - } + break; + } ret = spiflash->spi_receive(spiflash, FLASH_CMD_READ_STATUS2, 0U, 0U, &status[1], 1U); if (ret < 0) { ret = CSI_ERROR; - break; - } + break; + } if(param->qe_pos == 1U){ - // Used to adapte GDxxx series SPIFLASH + // Used to adapte GDxxx series SPIFLASH status[1] |= ((uint8_t)0x1U << param->qe_pos); ret = csi_spiflash_write_reg(spiflash, 0x31U, &status[1], 1U); } else { diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/trng.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/trng.c index 809c3d75acb..09f64df1f4b 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/trng.c +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/trng.c @@ -47,7 +47,7 @@ csi_error_t csi_rng_get_multi_word(uint32_t *data, uint32_t num) ///< TODO：使能trng 模块 ///< TODO：等待trng 模块有效 且未超时，超时设置ret并退出循环 - + ///< TODO：获取trng值到data[i] i++; num--; @@ -69,7 +69,7 @@ csi_error_t csi_rng_get_single_word(uint32_t* data) ///< TODO：等待trng 模块有效 且未超时，超时设置ret并退出循环 - ///< TODO：获取trng值到*data + ///< TODO：获取trng值到*data return ret; } diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/uart.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/uart.c index 32d393099c7..98382492bd7 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/uart.c +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/uart.c @@ -461,7 +461,7 @@ int32_t csi_uart_send(csi_uart_t *uart, const void *data, uint32_t size, uint32_ uint32_t send_start, timeout_flag = 0U; uint32_t intr_en_status; - uart_base = (dw_uart_regs_t *)uart->dev.reg_base; + uart_base = (dw_uart_regs_t *)uart->dev.reg_base; // 串口地址 0x1900d000 /* store the status of intr */ intr_en_status = dw_uart_get_intr_en_status(uart_base); dw_uart_disable_trans_irq(uart_base); diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/wdt.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/wdt.c index 36f9a47aae7..cb1eb6cbce9 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/wdt.c +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/drivers/wdt.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * Copyright (C) 2017-2024 Alibaba Group Holding Limited */ /******************************************************* @@ -14,7 +14,7 @@ void dw_wdt_irq_handler(void *arg) { - + ///< TODO：获取WDT的中断状态 ///< TODO：根据中断状态执行用户回调函数 @@ -33,7 +33,7 @@ csi_error_t csi_wdt_init(csi_wdt_t *wdt, uint32_t idx) ///< 获取中断号、基地址等相关信息 if (0 == target_get(DEV_DW_WDT_TAG, idx, &wdt->dev)) { - + ///< TODO：复位WDT的控制寄存器 ///< TODO：复位WDT的超时时间范围寄存器 ///< TODO：复位重启WDT计数器寄存器 diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/irq_port.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/irq_port.c index 7fa2ae9a0ee..89979d97408 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/irq_port.c +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/irq_port.c @@ -50,7 +50,7 @@ void soc_irq_priority(uint32_t irq_num, uint32_t priority) } /** - * @brief get external irq number only + * @brief get external irq number only * @return irq no */ uint32_t soc_irq_get_irq_num(void) diff --git a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/csi_rv64_gcc.h b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/csi_rv64_gcc.h index f9872d772ba..1c69a0415c2 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/csi_rv64_gcc.h +++ b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/csi_rv64_gcc.h @@ -1621,8 +1621,8 @@ __ALWAYS_STATIC_INLINE void __ICACHE_IALL(void) } /** - \brief Invalid all icache and broadcast to other cores - \details Invalid all icache and broadcast to other cores + \brief Invalid all icache and broadcast to other cores + \details Invalid all icache and broadcast to other cores */ __ALWAYS_STATIC_INLINE void __ICACHE_IALLS(void) { diff --git a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/csi_core.h b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/csi_core.h index 85fe3408211..e7e04c41cbe 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/csi_core.h +++ b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/csi_core.h @@ -85,96 +85,96 @@ extern "C" { __STATIC_INLINE const char* csi_get_cpu_name() { #if CONFIG_CPU_XUANTIE_C906 - return "c906"; + return "c906"; #elif CONFIG_CPU_XUANTIE_C906FD - return "c906fd"; + return "c906fd"; #elif CONFIG_CPU_XUANTIE_C906FDV - return "c906fdv"; + return "c906fdv"; #elif CONFIG_CPU_XUANTIE_C907 - return "c907"; + return "c907"; #elif CONFIG_CPU_XUANTIE_C907FD - return "c907fd"; + return "c907fd"; #elif CONFIG_CPU_XUANTIE_C907FDV - return "c907fdv"; + return "c907fdv"; #elif CONFIG_CPU_XUANTIE_C907FDVM - return "c907fdvm"; + return "c907fdvm"; #elif CONFIG_CPU_XUANTIE_C907_RV32 - return "c907-rv32"; + return "c907-rv32"; #elif CONFIG_CPU_XUANTIE_C907FD_RV32 - return "c907fd-rv32"; + return "c907fd-rv32"; #elif CONFIG_CPU_XUANTIE_C907FDV_RV32 - return "c907fdv-rv32"; + return "c907fdv-rv32"; #elif CONFIG_CPU_XUANTIE_C907FDVM_RV32 - return "c907fdvm-rv32"; + return "c907fdvm-rv32"; #elif CONFIG_CPU_XUANTIE_C908 - return "c908"; + return "c908"; #elif CONFIG_CPU_XUANTIE_C908V - return "c908v"; + return "c908v"; #elif CONFIG_CPU_XUANTIE_C908I - return "c908i"; + return "c908i"; #elif CONFIG_CPU_XUANTIE_C910V2 - return "c910v2"; + return "c910v2"; #elif CONFIG_CPU_XUANTIE_C910V3 - return "c910v3"; + return "c910v3"; #elif CONFIG_CPU_XUANTIE_C910V3_CP - return "c910v3-cp"; + return "c910v3-cp"; #elif CONFIG_CPU_XUANTIE_C920V2 - return "c920v2"; + return "c920v2"; #elif CONFIG_CPU_XUANTIE_C920V3 - return "c920v3"; + return "c920v3"; #elif CONFIG_CPU_XUANTIE_C920V3_CP - return "c920v3-cp"; + return "c920v3-cp"; #elif CONFIG_CPU_XUANTIE_R910 - return "r910"; + return "r910"; #elif CONFIG_CPU_XUANTIE_R920 - return "r920"; + return "r920"; #elif CONFIG_CPU_XUANTIE_R908 - return "r908"; + return "r908"; #elif CONFIG_CPU_XUANTIE_R908FD - return "r908fd"; + return "r908fd"; #elif CONFIG_CPU_XUANTIE_R908FDV - return "r908fdv"; + return "r908fdv"; #elif CONFIG_CPU_XUANTIE_R908_CP - return "r908-cp"; + return "r908-cp"; #elif CONFIG_CPU_XUANTIE_R908FD_CP - return "r908fd-cp"; + return "r908fd-cp"; #elif CONFIG_CPU_XUANTIE_R908FDV_CP - return "r908fdv-cp"; + return "r908fdv-cp"; #elif CONFIG_CPU_XUANTIE_E902 - return "e902"; + return "e902"; #elif CONFIG_CPU_XUANTIE_E902M - return "e902m"; + return "e902m"; #elif CONFIG_CPU_XUANTIE_E902T - return "e902t"; + return "e902t"; #elif CONFIG_CPU_XUANTIE_E902MT - return "e902mt"; + return "e902mt"; #elif CONFIG_CPU_XUANTIE_E906 - return "e906"; + return "e906"; #elif CONFIG_CPU_XUANTIE_E906F - return "e906f"; + return "e906f"; #elif CONFIG_CPU_XUANTIE_E906FD - return "e906fd"; + return "e906fd"; #elif CONFIG_CPU_XUANTIE_E906P - return "e906p"; + return "e906p"; #elif CONFIG_CPU_XUANTIE_E906FP - return "e906fp"; + return "e906fp"; #elif CONFIG_CPU_XUANTIE_E906FDP - return "e906fdp"; + return "e906fdp"; #elif CONFIG_CPU_XUANTIE_E907 - return "e907"; + return "e907"; #elif CONFIG_CPU_XUANTIE_E907F - return "e907f"; + return "e907f"; #elif CONFIG_CPU_XUANTIE_E907FD - return "e907fd"; + return "e907fd"; #elif CONFIG_CPU_XUANTIE_E907P - return "e907p"; + return "e907p"; #elif CONFIG_CPU_XUANTIE_E907FP - return "e907fp"; + return "e907fp"; #elif CONFIG_CPU_XUANTIE_E907FDP - return "e907fdp"; + return "e907fdp"; #else - return "unknown"; + return "unknown"; #endif } diff --git a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/adc.h b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/adc.h index 609fb851d59..4aa61783b2f 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/adc.h +++ b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/adc.h @@ -50,7 +50,7 @@ struct csi_adc { void (*callback)(csi_adc_t *adc, csi_adc_event_t event, void *arg); ///< User callback ,signaled by driver event void *arg; ///< User private param ,passed to user callback uint32_t *data; ///< Data buf - uint32_t num; ///< Data size by word + uint32_t num; ///< Data size by word csi_dma_ch_t *dma; ///< Dma channel handle csi_error_t (*start)(csi_adc_t *adc); ///< Start function csi_error_t (*stop)(csi_adc_t *adc); ///< Stop function @@ -69,7 +69,7 @@ csi_error_t csi_adc_init(csi_adc_t *adc, uint32_t idx); /** \brief De-initialize adc Interface. stops operation and releases the software resources used by the interface \param[in] handle ADC handle to operate - \return None + \return None */ void csi_adc_uninit(csi_adc_t *adc); @@ -119,7 +119,7 @@ csi_error_t csi_adc_stop_async(csi_adc_t *adc); csi_error_t csi_adc_channel_enable(csi_adc_t *adc, uint8_t ch_id, bool is_enable); /** - \brief Set the ADC sampling time for the selected channel + \brief Set the ADC sampling time for the selected channel \param[in] adc ADC handle to operate \param[in] ch_id ADC channel id \param[in] clock_num Channel sampling clock number @@ -179,7 +179,7 @@ csi_error_t csi_adc_attach_callback(csi_adc_t *adc, void *callback, void *arg); /** \brief Detach the callback handler \param[in] adc Operate handle - \return None + \return None */ void csi_adc_detach_callback(csi_adc_t *adc); @@ -201,7 +201,7 @@ csi_error_t csi_adc_enable_pm(csi_adc_t *adc); /** \brief Disable adc low power mode \param[in] adc ADC handle to operate - \return None + \return None */ void csi_adc_disable_pm(csi_adc_t *adc); diff --git a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/aes.h b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/aes.h index 4a56bc65357..a395fa7c0ce 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/aes.h +++ b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/aes.h @@ -83,7 +83,7 @@ csi_error_t csi_aes_set_encrypt_key(csi_aes_t *aes, void *key, csi_aes_key_bits_ csi_error_t csi_aes_set_decrypt_key(csi_aes_t *aes, void *key, csi_aes_key_bits_t key_len); /** \brief Set encrypt key2. This API is used for the algorithm which has two keys, - such as xts, used for the key of tweak + such as xts, used for the key of tweak \param[in] aes Handle to operate \param[in] key Pointer to the key buf \param[in] key_len Pointer to \ref csi_aes_key_bits_t @@ -93,7 +93,7 @@ csi_error_t csi_aes_set_encrypt_key2(csi_aes_t *aes, void *key, csi_aes_key_bits /** \brief Set decrypt key2. This API is used for the algorithm which has two keys, - such as xts, used for the key of tweak + such as xts, used for the key of tweak \param[in] aes Handle to operate \param[in] key Pointer to the key buf \param[in] key_len Pointer to \ref csi_aes_key_bits_t diff --git a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/drv_fft.h b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/drv_fft.h index 62bcc8176e9..76330849923 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/drv_fft.h +++ b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/drv_fft.h @@ -38,18 +38,18 @@ #endif typedef enum { - // 512-point FFT - CSKY_MCA_FFT_LEN_512 = 0x1, - // 256-point FFT - CSKY_MCA_FFT_LEN_256 = 0x2, - // 128-point FFT - CSKY_MCA_FFT_LEN_128 = 0x4, - // 64-point FFT - CSKY_MCA_FFT_LEN_64 = 0x8, - // 32-point FFT - CSKY_MCA_FFT_LEN_32 = 0x10, - // 16-point FFT - CSKY_MCA_FFT_LEN_16 = 0x20, + // 512-point FFT + CSKY_MCA_FFT_LEN_512 = 0x1, + // 256-point FFT + CSKY_MCA_FFT_LEN_256 = 0x2, + // 128-point FFT + CSKY_MCA_FFT_LEN_128 = 0x4, + // 64-point FFT + CSKY_MCA_FFT_LEN_64 = 0x8, + // 32-point FFT + CSKY_MCA_FFT_LEN_32 = 0x10, + // 16-point FFT + CSKY_MCA_FFT_LEN_16 = 0x20, } csky_mca_fft_len_t; /* 8-bit fixed-point numeric type in user-defined format */ diff --git a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/ecdsa.h b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/ecdsa.h index 0c034ebd208..4c6d91a65de 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/ecdsa.h +++ b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/ecdsa.h @@ -40,10 +40,10 @@ typedef enum { CSI_CURVES_SECP256K1 = 0U, /* SECG curve over a 256 bit prime field */ CSI_CURVES_SECP384R1, /* NIST/SECG curve over a 384 bit prime field */ CSI_CURVES_SECP521R1, /* NIST/SECG curve over a 521 bit prime field */ - CSI_CURVES_BRAINPOOL256R1, /* RFC 5639 curve over a 256 prime field */ - CSI_CURVES_BRAINPOOL256T1, /* RFC 5639 curve over a 256 prime field */ - CSI_CURVES_BRAINPOOL512R1, /* RFC 5639 curve over a 512 prime field */ - CSI_CURVES_BRAINPOOL512T1, /* RFC 5639 curve over a 512 prime field */ + CSI_CURVES_BRAINPOOL256R1, /* RFC 5639 curve over a 256 prime field */ + CSI_CURVES_BRAINPOOL256T1, /* RFC 5639 curve over a 256 prime field */ + CSI_CURVES_BRAINPOOL512R1, /* RFC 5639 curve over a 512 prime field */ + CSI_CURVES_BRAINPOOL512T1, /* RFC 5639 curve over a 512 prime field */ } csi_curve_type_t; /** @@ -88,7 +88,7 @@ csi_error_t csi_ecdsa_load_curve(csi_ecdsa_t *ecdsa, csi_curve_type_t type); \param[out] sig_len The signature length \return Error code \ref Csi_error_t */ -csi_error_t csi_ecdsa_sign(csi_ecdsa_t *ecdsa, const uint8_t *prikey, uint32_t prikey_len, +csi_error_t csi_ecdsa_sign(csi_ecdsa_t *ecdsa, const uint8_t *prikey, uint32_t prikey_len, const uint8_t *dgst, uint32_t dgst_len, uint8_t *sig, uint32_t *sig_len); /** @@ -102,7 +102,7 @@ csi_error_t csi_ecdsa_sign(csi_ecdsa_t *ecdsa, const uint8_t *prikey, uint32_t \param[in] sig_len The signature length \return Error code \ref Csi_error_t */ -csi_error_t csi_ecdsa_verify(csi_ecdsa_t *ecdsa, const uint8_t *pubkey, uint32_t pubkey_len, +csi_error_t csi_ecdsa_verify(csi_ecdsa_t *ecdsa, const uint8_t *pubkey, uint32_t pubkey_len, const uint8_t *dgst, uint32_t gst_len, const uint8_t *sig, uint32_t sig_len); #ifdef __cplusplus diff --git a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/gpio.h b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/gpio.h index e33545184b6..fb8aed65cca 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/gpio.h +++ b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/gpio.h @@ -189,7 +189,7 @@ csi_error_t csi_gpio_attach_callback(csi_gpio_t *gpio, void *callback, void *ar /** \brief Detach the interrupt callback to the port \param[in] gpio GPIO port handle - \return None + \return None */ void csi_gpio_detach_callback(csi_gpio_t *gpio); @@ -203,7 +203,7 @@ csi_error_t csi_gpio_enable_pm(csi_gpio_t *gpio); /** \brief Disable gpio power manage \param[in] gpio GPIO handle to operate - \return None + \return None */ void csi_gpio_disable_pm(csi_gpio_t *gpio); diff --git a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/hmac.h b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/hmac.h index b9298e19271..1033306e150 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/hmac.h +++ b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/hmac.h @@ -79,8 +79,8 @@ csi_error_t csi_hmac_set_key(csi_hmac_t *mac, uint8_t *key, uint32_t key_len); /** \brief MAC start operation function. \param[in] mac mac handle to operate. - \param[in] context mac context pointer. - \param[in] mode sc_sha_mode_t. + \param[in] context mac context pointer. + \param[in] mode sc_sha_mode_t. \return error code \ref csi_error_t */ csi_error_t csi_hmac_start(csi_hmac_t *mac, csi_hmac_context_t *context, csi_sha_mode_t mode); @@ -106,7 +106,7 @@ csi_error_t csi_hmac_finish(csi_hmac_t *mac, csi_hmac_context_t *context, uint8_ /** \brief MAC cacl operation function. \param[in] mac mac handle to operate. - \param[in] mode sc_sha_mode_t. + \param[in] mode sc_sha_mode_t. \param[in] msg Pointer to the mac input message. \param[in] msg_len Length of msg. \param[out] out mac buffer, malloc by caller. diff --git a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/irq.h b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/irq.h index 2e1a2bae899..47bf0e38ac1 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/irq.h +++ b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/irq.h @@ -72,7 +72,7 @@ void csi_irq_attach(uint32_t irq_num, void *irq_handler, csi_dev_t *dev); \param[in] irq_num Number of IRQ. \param[in] irq_handler2 IRQ Handler. \param[in] dev The dev to operate - \param[in] arg user data of irq_handler2 + \param[in] arg user data of irq_handler2 \return None. */ void csi_irq_attach2(uint32_t irq_num, void *irq_handler2, csi_dev_t *dev, void *arg); diff --git a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/pin.h b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/pin.h index 3bc07ba0639..4e7c89678f3 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/pin.h +++ b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/pin.h @@ -73,7 +73,7 @@ typedef enum{ PIN_I2S_SDI, PIN_I2S_SDO }csi_pin_i2s_t; - + typedef struct { pin_name_t pin_name; uint8_t idx; ///< ctrl idx. e.g: ADC0 channel 1, idx = 0, channel = 1 diff --git a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/rsa.h b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/rsa.h index 0229eb5785a..ea5b005daa8 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/rsa.h +++ b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/rsa.h @@ -35,28 +35,28 @@ extern "C" { /*----- RSA Control Codes: Mode Parameters: Key Bits -----*/ /****** RSA Key bits Type *****/ typedef enum { - RSA_KEY_BITS_192 = 0U, /* 192 Key bits */ - RSA_KEY_BITS_256, /* 256 Key bits */ - RSA_KEY_BITS_512, /* 512 Key bits */ - RSA_KEY_BITS_1024, /* 1024 Key bits */ - RSA_KEY_BITS_2048, /* 2048 Key bits */ - RSA_KEY_BITS_3072, /* 3072 Key bits */ - RSA_KEY_BITS_4096 /* 4096 Key bits */ + RSA_KEY_BITS_192 = 0U, /* 192 Key bits */ + RSA_KEY_BITS_256, /* 256 Key bits */ + RSA_KEY_BITS_512, /* 512 Key bits */ + RSA_KEY_BITS_1024, /* 1024 Key bits */ + RSA_KEY_BITS_2048, /* 2048 Key bits */ + RSA_KEY_BITS_3072, /* 3072 Key bits */ + RSA_KEY_BITS_4096 /* 4096 Key bits */ } csi_rsa_key_bits_t; /****** RSA Padding Type *****/ typedef enum { - RSA_PADDING_MODE_NO = 0, /* RSA NO Padding Mode */ - RSA_PADDING_MODE_PKCS1, /* RSA PKCS1 Padding Mode */ - RSA_PADDING_MODE_PKCS1_OAEP, /* RSA PKCS1 OAEP Padding Mode */ - RSA_PADDING_MODE_SSLV23, /* RSA SSLV23 Padding Mode */ - RSA_PADDING_MODE_X931, /* RSA X931 Padding Mode */ - RSA_PADDING_MODE_PSS /* RSA PSS Padding Mode */ + RSA_PADDING_MODE_NO = 0, /* RSA NO Padding Mode */ + RSA_PADDING_MODE_PKCS1, /* RSA PKCS1 Padding Mode */ + RSA_PADDING_MODE_PKCS1_OAEP, /* RSA PKCS1 OAEP Padding Mode */ + RSA_PADDING_MODE_SSLV23, /* RSA SSLV23 Padding Mode */ + RSA_PADDING_MODE_X931, /* RSA X931 Padding Mode */ + RSA_PADDING_MODE_PSS /* RSA PSS Padding Mode */ } csi_rsa_padding_type_t; /****** RSA Hash Type *****/ typedef enum { - RSA_HASH_TYPE_MD5 = 0, + RSA_HASH_TYPE_MD5 = 0, RSA_HASH_TYPE_SHA1, RSA_HASH_TYPE_SHA224, RSA_HASH_TYPE_SHA256, diff --git a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/sha.h b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/sha.h index bbc23598e60..668b9dcc9ab 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/sha.h +++ b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/sha.h @@ -36,14 +36,14 @@ extern "C" { /****** SHA mode ******/ typedef enum { - SHA_MODE_1 = 1U, /* SHA_1 mode */ - SHA_MODE_256, /* SHA_256 mode */ - SHA_MODE_224, /* SHA_224 mode */ - SHA_MODE_512, /* SHA_512 mode */ - SHA_MODE_384, /* SHA_384 mode */ - SHA_MODE_512_256, /* SHA_512_256 mode */ - SHA_MODE_512_224, /* SHA_512_224 mode */ - SHA_MODE_MD5 /* MD5 mode */ + SHA_MODE_1 = 1U, /* SHA_1 mode */ + SHA_MODE_256, /* SHA_256 mode */ + SHA_MODE_224, /* SHA_224 mode */ + SHA_MODE_512, /* SHA_512 mode */ + SHA_MODE_384, /* SHA_384 mode */ + SHA_MODE_512_256, /* SHA_512_256 mode */ + SHA_MODE_512_224, /* SHA_512_224 mode */ + SHA_MODE_MD5 /* MD5 mode */ } csi_sha_mode_t; /****** SHA State ******/ @@ -69,7 +69,7 @@ typedef enum { /****** SHA Ctrl ******/ typedef struct csi_sha csi_sha_t; struct csi_sha{ - csi_dev_t dev; + csi_dev_t dev; void (*callback)(csi_sha_t *sha, csi_sha_event_t event, void *arg); /* SHA event callback for user */ void *arg; /* SHA custom designed param passed to evt_cb */ csi_dma_ch_t *dma_in; /* SHA in dma handle param */ diff --git a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/spi.h b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/spi.h index a80bf10543d..80f7e4d37b5 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/spi.h +++ b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/spi.h @@ -124,7 +124,7 @@ csi_error_t csi_spi_init(csi_spi_t *spi, uint32_t idx); \brief De-initialize SPI Interface stops Operation and releases the software resources used by the spi instance \param[in] spi Handle - \return None + \return None */ void csi_spi_uninit(csi_spi_t *spi); diff --git a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/spinand.h b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/spinand.h index 17f6c6fb2eb..8a01198793b 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/spinand.h +++ b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/spinand.h @@ -45,7 +45,7 @@ typedef union { typedef struct { -uint32_t target; ///< target in chip +uint32_t target; ///< target in chip uint32_t lun; ///< lun in target uint32_t plane; ///< plane number in lun uint32_t block; ///< block index in lun @@ -76,7 +76,7 @@ typedef struct{ uint8_t nbytes; ///< dummy bytes uint8_t buswidth; ///< bus width }dummy; - + struct { uint8_t buswidth; ///< data buswidth @@ -87,12 +87,12 @@ typedef struct{ void* out; ///< write datat buf ptr }buf; }data; - + }spi_mem_op_t; typedef struct { - const uint8_t *id; ///< point to chip id array - const uint8_t len; ///< id length + const uint8_t *id; ///< point to chip id array + const uint8_t len; ///< id length }csi_spinand_id_t; typedef struct { @@ -102,63 +102,63 @@ typedef struct { typedef struct{ - uint16_t strength; ///< number of hw-ecc engine bits + uint16_t strength; ///< number of hw-ecc engine bits uint16_t step_size; ///< corect size by ecc per-step }csi_nand_ecc_req_t; typedef struct { - uint32_t bits_per_cell; ///< bit per-cell - uint32_t pagesize; ///< page size - uint32_t oobsize; ///< spare area size - uint32_t pages_per_eraseblock; ///< pages per block - uint32_t eraseblocks_per_lun; ///< blocks per lun(logic unit number== max block index ) - uint32_t max_bad_eraseblocks_per_lun; ///< max bad blocks per lun - uint32_t planes_per_lun; ///< planes per-lun - uint32_t luns_per_target; ///< luns per die + uint32_t bits_per_cell; ///< bit per-cell + uint32_t pagesize; ///< page size + uint32_t oobsize; ///< spare area size + uint32_t pages_per_eraseblock; ///< pages per block + uint32_t eraseblocks_per_lun; ///< blocks per lun(logic unit number== max block index ) + uint32_t max_bad_eraseblocks_per_lun; ///< max bad blocks per lun + uint32_t planes_per_lun; ///< planes per-lun + uint32_t luns_per_target; ///< luns per die uint32_t ntargets; ///< target index }csi_nand_mem_layout_t; typedef struct { - char *model; ///< chip name of vendor - uint32_t flags; ///< chip-specific feature bits group - csi_spinand_id_t devid; ///< devid of chip - csi_nand_mem_layout_t memorg; ///< mem layout of chip - csi_nand_ecc_req_t eccreq; ///< ecc capabilty of chip - csi_error_t (*select_target)(void *spinand, uint32_t target); ///< select target + char *model; ///< chip name of vendor + uint32_t flags; ///< chip-specific feature bits group + csi_spinand_id_t devid; ///< devid of chip + csi_nand_mem_layout_t memorg; ///< mem layout of chip + csi_nand_ecc_req_t eccreq; ///< ecc capabilty of chip + csi_error_t (*select_target)(void *spinand, uint32_t target); ///< select target csi_error_t (*check_ecc_status)(void *spinand,uint8_t status); ///< check vendor specific ecc status }csi_spinand_info_t; typedef struct { - csi_error_t (*init) (void *spinand); ///< vendor chip inition - void (*uninit) (void *spinand); ///< vendor chip uninition + csi_error_t (*init) (void *spinand); ///< vendor chip inition + void (*uninit) (void *spinand); ///< vendor chip uninition }csi_spinand_manufacturer_ops_t; typedef struct { - uint8_t id; ///< vendor id - char *name; ///< vendor name - const csi_spinand_info_t *chips; ///< vendor chip param - uint32_t nchips; ///< chips number supported - const csi_spinand_manufacturer_ops_t *ops; ///< vendor specific operations + uint8_t id; ///< vendor id + char *name; ///< vendor name + const csi_spinand_info_t *chips; ///< vendor chip param + uint32_t nchips; ///< chips number supported + const csi_spinand_manufacturer_ops_t *ops; ///< vendor specific operations }csi_spinand_manufacturer_t; typedef struct { - char *model_name; ///< name of nand-device module + char *model_name; ///< name of nand-device module uint16_t page_size; ///< page-size of nand-device uint16_t oob_size; ///< oob-size(spare size) of nand-device uint16_t pages_per_block; ///< pages-per-block - uint16_t max_bad_blocks; ///< max possible bad blocks of nand-device + uint16_t max_bad_blocks; ///< max possible bad blocks of nand-device uint32_t total_blocks; ///< total blocks of nand-device }csi_spinand_dev_params_t; -typedef struct +typedef struct { void *xfer_buf; ///< point to xfer data buf uint32_t xfer_buf_len; ///< length of xfer buf ,count in byte - uint16_t rxfer_copy_offset; ///< copy offset from word-aligned buf + uint16_t rxfer_copy_offset; ///< copy offset from word-aligned buf uint16_t rxfer_origin_len; ///< copy length from word-aligned buf }csi_xfer_data_buf_t; @@ -171,20 +171,20 @@ typedef struct { csi_nand_spi_qspi_t spi_qspi; ///< Spi/qspi handle uint8_t scractbuf[SPINAND_SCRAT_BUF_LEN]; ///< scracthbuf for read/write id or reg uint8_t cur_target; ///< current target - uint16_t max_tx_size; ///< max tx op size - uint16_t max_rx_size; ///< max rx op size + uint16_t max_tx_size; ///< max tx op size + uint16_t max_rx_size; ///< max rx op size csi_xfer_data_buf_t xfer; ///< xfer buf csi_spinand_info_t *chip_info; ///< Point to vendor private feature struct - csi_spinand_manufacturer_t *maf; ///< point to manufacture - void (*spi_cs_callback)(csi_gpio_pin_state_t value); ///< gpio chip select for spi or qspi + csi_spinand_manufacturer_t *maf; ///< point to manufacture + void (*spi_cs_callback)(csi_gpio_pin_state_t value); ///< gpio chip select for spi or qspi csi_error_t (*spi_mem)(void *spinand,spi_mem_op_t *op); ///< spi-mem op function void *priv; ///< User private param } csi_spinand_t; -typedef enum { - XFER_CPU_POLLING, ///< transfer by qspi with cpu polling mode - XFER_DMA, ///< transfer by qspi with external dma engine - XFER_INTR, ///< transfer by qspi with cpu-interrut +typedef enum { + XFER_CPU_POLLING, ///< transfer by qspi with cpu polling mode + XFER_DMA, ///< transfer by qspi with external dma engine + XFER_INTR, ///< transfer by qspi with cpu-interrut }csi_spinand_xfer_t; /** @@ -204,9 +204,9 @@ csi_error_t csi_spinand_qspi_init(csi_spinand_t *spinand, uint32_t qspi_idx,void void csi_spinand_qspi_uninit(csi_spinand_t *spinand); /** - \brief set xfer mode + \brief set xfer mode \param[in] spinand NANDFLASH handle to operate - \param[in] xfer_mode please ref csi_spinand_xfer_t + \param[in] xfer_mode please ref csi_spinand_xfer_t \return Error code */ csi_error_t csi_spinand_set_xfer_mode(csi_spinand_t *spinand,csi_spinand_xfer_t xfer_mode); @@ -234,9 +234,9 @@ int32_t csi_spinand_read(csi_spinand_t *spinand, uint64_t offset, void *data, ui /** - \brief Read spare data from specific page + \brief Read spare data from specific page \param[in] spinand NANDFLASH handle to operate - \param[in] page_addr page addr, address relative to zero, addr need page size aligned + \param[in] page_addr page addr, address relative to zero, addr need page size aligned \param[in] spare_offset offset address within the spare area of the page \param[out] data Pointer to a buffer storing the data read from Flash \param[in] size Number of data items to read @@ -257,7 +257,7 @@ int32_t csi_spinand_read_spare_data(csi_spinand_t *spinand,uint64_t page_addr,ui int32_t csi_spinand_write(csi_spinand_t *spinand, uint64_t offset, const void *data, uint64_t size); /** - \brief write spare data to specific page + \brief write spare data to specific page \param[in] spinand NANDFLASH handle to operate \param[in] page_addr page addr, address relative to zero, addr need page size aligned \param[in] spare_offset offset address within the spare area of the page @@ -282,7 +282,7 @@ csi_error_t csi_spinand_erase(csi_spinand_t *spinand, uint64_t offset, uint64_t /** \brief check whether the block is bad \param[in] spinand NANDFLASH handle to operate - \param[in] block_addr block addr (count in bytes) + \param[in] block_addr block addr (count in bytes) \return 1: bad 0: not bad <0 err code */ @@ -298,7 +298,7 @@ int32_t csi_spinand_block_is_bad(csi_spinand_t *spinand,uint64_t block_addr); csi_error_t csi_spinand_block_mark_bad(csi_spinand_t *spinand, uint64_t block_addr); /** - \brief reset spinand device + \brief reset spinand device \param[in] spinand NANDFLASH handle to operate \return Error code */ diff --git a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/syslog.h b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/syslog.h index b24586db4f2..063649c8aa6 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/syslog.h +++ b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/syslog.h @@ -15,7 +15,7 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + /****************************************************************************** * @file syslog.h * @brief Defines syslog APIs and usage diff --git a/bsp/xuantie/libraries/xuantie_libraries/pre_main/SConscript b/bsp/xuantie/libraries/xuantie_libraries/pre_main/SConscript index f530983e5c4..4e2f4ed392d 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/pre_main/SConscript +++ b/bsp/xuantie/libraries/xuantie_libraries/pre_main/SConscript @@ -4,7 +4,7 @@ import os cwd = GetCurrentDir() CPPPATH = [cwd] src = ['pre_main.c'] -src += ['sub_libcpu.S'] +src += ['libcpu.S'] group = DefineGroup('pre_main', src, depend = [''], CPPPATH = CPPPATH) diff --git a/bsp/xuantie/libraries/xuantie_libraries/pre_main/sub_libcpu.S b/bsp/xuantie/libraries/xuantie_libraries/pre_main/libcpu.S similarity index 100% rename from bsp/xuantie/libraries/xuantie_libraries/pre_main/sub_libcpu.S rename to bsp/xuantie/libraries/xuantie_libraries/pre_main/libcpu.S diff --git a/bsp/xuantie/libraries/xuantie_libraries/pre_main/pre_main.h b/bsp/xuantie/libraries/xuantie_libraries/pre_main/pre_main.h index c100d13d6d3..4e9563195ed 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/pre_main/pre_main.h +++ b/bsp/xuantie/libraries/xuantie_libraries/pre_main/pre_main.h @@ -5,7 +5,7 @@ #include void section_data_copy(void); -void section_ram_code_copy(void); +void section_ram_code_copy(void); void section_ram_code_copy(void); void section_bss_clear(void); diff --git a/bsp/xuantie/smartl/e906/rtconfig.py b/bsp/xuantie/smartl/e906/rtconfig.py index fd578de5240..c24bf39ff15 100644 --- a/bsp/xuantie/smartl/e906/rtconfig.py +++ b/bsp/xuantie/smartl/e906/rtconfig.py @@ -1,6 +1,6 @@ import os ARCH = 'risc-v' -CPU = 'e906fd' +CPU = 'e906' # toolchains options CROSS_TOOL = 'gcc' @@ -40,10 +40,10 @@ OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - MCPU = ' -mcpu=e906fd ' - DEVICE = MCPU + ' -Wno-main -mcmodel=medlow' + MCPU = ' -mcpu=e906fd ' # Modify here based on CPU architecture. + MCPU_DEFINE = ' -DCONFIG_CPU_XUANTIE_E906FD=1 ' # Modify here based on CPU architecture. + DEVICE = MCPU + MCPU_DEFINE + ' -Wno-main -mcmodel=medlow' - # 提取全局宏定义 GLOBAL_DEFINES = ( '-DCONFIG_KERNEL_RTTHREAD=1 ' '-D__RT_KERNEL_SOURCE__=1 ' @@ -54,7 +54,6 @@ '-DCONFIG_XIP=1 ' '-DCONFIG_ARCH_MAINSTACK=4096 ' '-DCONFIG_ARCH_INTERRUPTSTACK=4096 ' - '-DCONFIG_CPU_XUANTIE_E906FD=1 ' '-DCONFIG_BOARD_SMARTL_EVB=1 ' '-DCLI_CONFIG_STACK_SIZE=4096 ' ) From dcd17edf6aa08048982cfbf4463550b78e3dd649 Mon Sep 17 00:00:00 2001 From: Yaochenger <1516081466@qq.com> Date: Thu, 29 May 2025 14:57:43 +0800 Subject: [PATCH 2/8] =?UTF-8?q?[xuantie]=20=E6=B7=BB=E5=8A=A0E907=20BSP?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/xuantie/smartl/e907/.config | 1352 +++++++++++++++++ bsp/xuantie/smartl/e907/Kconfig | 18 + bsp/xuantie/smartl/e907/README.md | 98 ++ bsp/xuantie/smartl/e907/SConscript | 15 + bsp/xuantie/smartl/e907/SConstruct | 61 + .../smartl/e907/applications/SConscript | 10 + bsp/xuantie/smartl/e907/applications/main.c | 18 + bsp/xuantie/smartl/e907/board/Kconfig | 43 + bsp/xuantie/smartl/e907/board/SConscript | 15 + bsp/xuantie/smartl/e907/board/board.c | 41 + bsp/xuantie/smartl/e907/board/board.h | 442 ++++++ bsp/xuantie/smartl/e907/figures/1.env.png | Bin 0 -> 27810 bytes bsp/xuantie/smartl/e907/figures/2.scons.png | Bin 0 -> 50557 bytes bsp/xuantie/smartl/e907/figures/3.vscode.png | Bin 0 -> 168160 bytes bsp/xuantie/smartl/e907/objdump.bat | 8 + bsp/xuantie/smartl/e907/qemu.bat | 91 ++ bsp/xuantie/smartl/e907/rtconfig.h | 393 +++++ bsp/xuantie/smartl/e907/rtconfig.py | 91 ++ 18 files changed, 2696 insertions(+) create mode 100644 bsp/xuantie/smartl/e907/.config create mode 100644 bsp/xuantie/smartl/e907/Kconfig create mode 100644 bsp/xuantie/smartl/e907/README.md create mode 100644 bsp/xuantie/smartl/e907/SConscript create mode 100644 bsp/xuantie/smartl/e907/SConstruct create mode 100644 bsp/xuantie/smartl/e907/applications/SConscript create mode 100644 bsp/xuantie/smartl/e907/applications/main.c create mode 100644 bsp/xuantie/smartl/e907/board/Kconfig create mode 100644 bsp/xuantie/smartl/e907/board/SConscript create mode 100644 bsp/xuantie/smartl/e907/board/board.c create mode 100644 bsp/xuantie/smartl/e907/board/board.h create mode 100644 bsp/xuantie/smartl/e907/figures/1.env.png create mode 100644 bsp/xuantie/smartl/e907/figures/2.scons.png create mode 100644 bsp/xuantie/smartl/e907/figures/3.vscode.png create mode 100644 bsp/xuantie/smartl/e907/objdump.bat create mode 100644 bsp/xuantie/smartl/e907/qemu.bat create mode 100644 bsp/xuantie/smartl/e907/rtconfig.h create mode 100644 bsp/xuantie/smartl/e907/rtconfig.py diff --git a/bsp/xuantie/smartl/e907/.config b/bsp/xuantie/smartl/e907/.config new file mode 100644 index 00000000000..1393173d286 --- /dev/null +++ b/bsp/xuantie/smartl/e907/.config @@ -0,0 +1,1352 @@ +CONFIG_XUANTIAN_XIAOHUI_E907=y + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options + +# CONFIG_RT_UTEST_TC_USING_KLIBC is not set +# end of klibc options + +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50201 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV32=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +# +# Hardware Drivers Config +# +CONFIG_SOC_XUANTIE=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_ENABLE_FPU is not set +# end of On-chip Peripheral Drivers +# end of Hardware Drivers Config diff --git a/bsp/xuantie/smartl/e907/Kconfig b/bsp/xuantie/smartl/e907/Kconfig new file mode 100644 index 00000000000..fd316d0eb79 --- /dev/null +++ b/bsp/xuantie/smartl/e907/Kconfig @@ -0,0 +1,18 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../../.. + +PKGS_DIR := packages + +config XUANTIAN_XIAOHUI_E907 + bool + select ARCH_RISCV32 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/xuantie/smartl/e907/README.md b/bsp/xuantie/smartl/e907/README.md new file mode 100644 index 00000000000..4e60e1f0ddc --- /dev/null +++ b/bsp/xuantie/smartl/e907/README.md @@ -0,0 +1,98 @@ +# XuanTie - E907 Series + +## 一 简介 + +### 1. 内核 + +E907 是一款基于 RISC-V 指令集的高性能嵌入式微处理处理器，是玄铁 RISC-V MCU 产品线中的最高性能处理器。E907 主要面向语音、MPU、导航、WiFi 等应用领域。 + +### 2.特点 + +E907 处理器体系结构的主要特点如下： + +• 32 位 RISC 处理器； + +• 支持 RISC-V RV32IMA[F][D]C[P] 指令集； + +• 支持 RISC-V 32/16 位混编指令集； + +• 支持 RISC-V 机器模式和用户模式； + +• 32 个 32 位整型通用寄存器，32 个 32 位/64 位浮点通用寄存器； + +• 整型 5 级/浮点 7 级，单发射，顺序执行流水线； + +• 支持 AXI4.0 主设备接口以及 AHB5.0 外设接口； + +• 指令 Cache，两路组相连结构，2KB-32KB 可配置； + +• 数据 Cache，两路组相连结构，2KB-32KB 可配置； + +• 支持非对齐内存访问； + +• 双周期硬件乘法器，基 4 硬件除法器； + +• 可选配 BHT 和 BTB； + +• 支持玄铁扩展增强指令集； + +• 支持玄铁 MCU 特性扩展技术，包括中断处理加速技术、MCU 扩展特性； + +• 兼容 RISC-V CLIC 中断标准，支持中断嵌套，外部中断源数量最高可配置 240 个； + +• 兼容 RISC-V PMP 内存保护标准，0/4/8/12/16 区域可配置； + +• 支持可配的性能监测单元； + +• 支持 RISC-V Debug 协议标准； + +• 频率 >1.0GHz@T28 HPCPlus，9T SVT(worst case)，Coremark > 3.8 coremark/MHz，Dhrystone + +\> 2.0 DMIPS/MHz。 + +### 3.BSP支持情况 + +- 当前BSP支持下述内核： + + ```asciiarmor + e907 e907f e907fd e907p e907fp e907fdp + ``` + +- 当前BSP默认设置的内核是e907fd，该架构支持[F] [D]扩展，可以通过menuconfig工具使能[F]扩展或者[F] [D] 扩展。 + +- 当使用其他内核架构时需要修改，rtconfig.py文件中的`MCPU`字段。 + +### 4.运行QEMU + +- BSP根目录下存在`qemu.bat`脚本，生成可执行文件后可点击该脚本直接启动QEMU. + +## 二 工具 + +- 编译器： https://www.xrvm.cn/community/download?id=4433353576298909696 +- 模拟器： https://www.xrvm.cn/community/download?id=4397435198627713024 + +注：若上述链接中的编译器与模拟器不能使用，可以使用下述CDK中的编译器与模拟器 + +- SDK：https://www.xrvm.cn/community/download?id=4397799570420076544 + +## 三 调试方法 + +**下述调试方法以E906举例，本BSP操作方式一致**，搭建完成RT-Thread开发环境，在BSP根目录使用env工具在当前目录打开env。 + +![](figures/1.env.png) + +使用前执行一次**menuconfig**命令，更新rtconfig.h配置，然后在当前目录执行**scons -j12**命令编译生成可可执行文件。 + +env + +生成可执行文件，可以直接在命令行启动qemu或者配置vscode脚本借助vscode强大的插件进行图形化调试，qemu的相关命令可以查看玄铁qemu的[用户手册](https://www.xrvm.cn/community/download?id=4397435198627713024)，下述是启动qemu的命令，在powershell或命令行可直接执行下述命令，注意qemu需要导出至环境变量或者使用绝对路径。 + +```shell +qemu-system-riscv64 -machine smartl -nographic -kernel rtthread.elf -cpu e906 +``` + +下述是使用vscode调试的展示。 + +env + +一起为RISC-V加油！ \ No newline at end of file diff --git a/bsp/xuantie/smartl/e907/SConscript b/bsp/xuantie/smartl/e907/SConscript new file mode 100644 index 00000000000..20f7689c53c --- /dev/null +++ b/bsp/xuantie/smartl/e907/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/xuantie/smartl/e907/SConstruct b/bsp/xuantie/smartl/e907/SConstruct new file mode 100644 index 00000000000..b3b9d7050b0 --- /dev/null +++ b/bsp/xuantie/smartl/e907/SConstruct @@ -0,0 +1,61 @@ +import os +import sys +import rtconfig +from SCons.Script import * +from termcolor import colored + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] + +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +print(colored('RT-Thread root directory: %s' % RTT_ROOT, 'green')) +print(colored('Building path: %s' % os.path.abspath('.'), 'green')) +print(colored('Building target: %s' % TARGET, 'green')) + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') +print(colored('SDK_ROOT: %s' % SDK_ROOT, 'green')) + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '../libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/../libraries' + +print(colored('libraries_path_prefix: %s' % libraries_path_prefix, 'green')) +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +bsp_vdir = 'build' +library_vdir = 'build/libraries' + +# common include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'SConscript'), variant_dir=library_vdir, duplicate=0)) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/xuantie/smartl/e907/applications/SConscript b/bsp/xuantie/smartl/e907/applications/SConscript new file mode 100644 index 00000000000..f129b326245 --- /dev/null +++ b/bsp/xuantie/smartl/e907/applications/SConscript @@ -0,0 +1,10 @@ +from building import * +import os + +cwd = GetCurrentDir() +CPPPATH = [cwd] +src = ['main.c'] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/xuantie/smartl/e907/applications/main.c b/bsp/xuantie/smartl/e907/applications/main.c new file mode 100644 index 00000000000..d076c2064e9 --- /dev/null +++ b/bsp/xuantie/smartl/e907/applications/main.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-04-21 Wangshun first version + */ + +#include +#include +#include "pre_main.h" + +int main(void) +{ + rt_kprintf("Hello RT-Thread!\r\n"); +} diff --git a/bsp/xuantie/smartl/e907/board/Kconfig b/bsp/xuantie/smartl/e907/board/Kconfig new file mode 100644 index 00000000000..a6ab6a627af --- /dev/null +++ b/bsp/xuantie/smartl/e907/board/Kconfig @@ -0,0 +1,43 @@ +menu "Hardware Drivers Config" + +config SOC_XUANTIE + bool + select SOC_XUANTIE_SERIES_E906 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + + +menu "On-chip Peripheral Drivers" + + menuconfig BSP_USING_UART + bool "Enable UART" + select RT_USING_SERIAL + default n + + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0" + default n + endif + + menuconfig ENABLE_FPU + bool "Enable FPU" + select ARCH_RISCV_FPU + default n + + if ENABLE_FPU + choice + prompt "FPU Configuration" + default ARCH_RISCV_FPU_S + + config ARCH_RISCV_FPU_S + bool "Enable [F] Extension" + + config ARCH_RISCV_FPU_D + bool "Enable [F][D] Extension" + endchoice + endif +endmenu + +endmenu diff --git a/bsp/xuantie/smartl/e907/board/SConscript b/bsp/xuantie/smartl/e907/board/SConscript new file mode 100644 index 00000000000..d9603bd08e2 --- /dev/null +++ b/bsp/xuantie/smartl/e907/board/SConscript @@ -0,0 +1,15 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = ['board.c'] + +path = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) +Return('group') diff --git a/bsp/xuantie/smartl/e907/board/board.c b/bsp/xuantie/smartl/e907/board/board.c new file mode 100644 index 00000000000..48204fda4bb --- /dev/null +++ b/bsp/xuantie/smartl/e907/board/board.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-04-23 Wangshun first version + */ + +#include +#include +#include +#include + +extern unsigned long __heap_start; +extern unsigned long __heap_end; + +/** + * This function will initialize your board. + */ +void rt_hw_board_init() +{ + rt_hw_interrupt_init(); + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)&__heap_start, (void *)&__heap_end); +#endif + +#ifdef BSP_USING_UART + rt_hw_usart_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} diff --git a/bsp/xuantie/smartl/e907/board/board.h b/bsp/xuantie/smartl/e907/board/board.h new file mode 100644 index 00000000000..21d4e39007b --- /dev/null +++ b/bsp/xuantie/smartl/e907/board/board.h @@ -0,0 +1,442 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + This is an example board.h for Board Compment, New Board should flow the macro defines. +*/ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// Common Board Features Define + +/* + The Common BOARD_XXX Macro Defines Boards supported features which may reference by Solutions. + Common board macro include: + . BOARD_NAME + · UART + · GPIO + · PWM + · ADC + · BUTTON + · LED + · WIFI + · BT + · AUDIO + BOARD_XXX Macro descripted below should be defined if the board support. +*/ + +/****************************************************************************/ + +/* + This riscv dummy board include: + · UART x1 + · GPIO x2 + · PWM x2 + · ADC x1 + · BUTTON x2 + · LED x2 + · WIFI x0 + · BT x0 + · AUDIO x1 +*/ + +#ifndef CONFIG_BOARD_UART +#define CONFIG_BOARD_UART 1 +#endif + +#ifndef CONFIG_BOARD_GPIO +#define CONFIG_BOARD_GPIO 0 +#endif + +#ifndef CONFIG_BOARD_PWM +#define CONFIG_BOARD_PWM 0 +#endif + +#ifndef CONFIG_BOARD_ADC +#define CONFIG_BOARD_ADC 0 +#endif + +#ifndef CONFIG_BOARD_BUTTON +#define CONFIG_BOARD_BUTTON 0 +#endif + +#ifndef CONFIG_BOARD_LED +#define CONFIG_BOARD_LED 0 +#endif + +#ifndef CONFIG_BOARD_WIFI +#define CONFIG_BOARD_WIFI 0 +#endif + +#ifndef CONFIG_BOARD_BT +#define CONFIG_BOARD_BT 0 +#endif + +#ifndef CONFIG_BOARD_AUDIO +#define CONFIG_BOARD_AUDIO 0 +#endif + +#define BOARD_NAME "RISCV_DUMMY" + +/* the board pins, can be used as uart, gpio, pwd... */ +#define BOARD_PIN0 (0) +#define BOARD_PIN1 (1) +#define BOARD_PIN2 (2) +#define BOARD_PIN3 (3) +#define BOARD_PIN4 (4) +#define BOARD_PIN5 (5) +#define BOARD_PIN6 (6) +#define BOARD_PIN7 (7) +#define BOARD_PIN8 (8) +#define BOARD_PIN9 (9) +#define BOARD_PIN10 (10) +#define BOARD_PIN11 (11) +#define BOARD_PIN12 (12) +//... + +#if defined(CONFIG_BOARD_UART) && CONFIG_BOARD_UART +// UART + +/* + The total supported uart numbers on this board, 0 meas No uart support. + the BOARD_UART_XXX, x in rang of (0, BOARD_UART_NUM - 1) +*/ +#ifndef BOARD_UART_NUM +#define BOARD_UART_NUM (1) +#endif + +#if defined(BOARD_UART_NUM) && BOARD_UART_NUM > 0 +/* the board uart0 tx pin */ +#define BOARD_UART0_TX_PIN (BOARD_PIN0) +/* the borad uart0 rx pin */ +#define BOARD_UART0_RX_PIN (BOARD_PIN1) +/* The real UART port reference to board logic port 0 */ +#define BOARD_UART0_IDX (0) +/* The default baudrate for uart0 */ +#define BOARD_UART0_BAUD (115200) + +//#define BOARD_UART1_IDX (1) +//#define BOARD_UART1_BAUD (115200) +// ... +#endif // defined(BOARD_UART_NUM) && BOARD_UART_NUM > 0 + +#endif // defined(CONFIG_BOARD_UART) && CONFIG_BOARD_UART + +#if defined(CONFIG_BOARD_GPIO) && CONFIG_BOARD_GPIO +// GPIO +/* + The total supported GPIO Pin numbers on this board, 0 meas No uart support. + the BOARD_GPIO_PIN, x in rang of (0, BOARD_GPIO_PIN_NUM - 1) +*/ +#ifndef BOARD_GPIO_PIN_NUM +#define BOARD_GPIO_PIN_NUM (2) +#endif + +#if defined(BOARD_GPIO_PIN_NUM) && BOARD_GPIO_PIN_NUM > 0 +/* The real gpio reference to board logic gpio pin */ +#define BOARD_GPIO_PIN0 (BOARD_PIN2) +#define BOARD_GPIO_PIN1 (BOARD_PIN3) +//#define BOARD_GPIO_PIN2 (x) +//#define BOARD_GPIO_PIN3 (x) +#endif // defined(BOARD_GPIO_PIN_NUM) && BOARD_GPIO_PIN_NUM > 0 +#endif // defined(CONFIG_BOARD_GPIO) && CONFIG_BOARD_GPIO + +#if defined(CONFIG_BOARD_PWM) && CONFIG_BOARD_PWM +// PWM +/* the board supported pwm channels */ +#ifndef BOARD_PWM_NUM +#define BOARD_PWM_NUM (2) +#endif + +#if defined(BOARD_PWM_NUM) && BOARD_PWM_NUM > 0 +/* the board pwm pin */ +#define BOARD_PWM0_PIN (BOARD_PIN4) +/* The real pwm channel reference to board logic pwm channel */ +#define BOARD_PWM0_CH (0) + +#define BOARD_PWM1_PIN (BOARD_PIN5) +#define BOARD_PWM1_CH (1) +#endif // defined(BOARD_PWM_NUM) && BOARD_PWM_NUM > 0 +#endif // defined(CONFIG_BOARD_PWM) && CONFIG_BOARD_PWM + +#if defined(CONFIG_BOARD_ADC) && CONFIG_BOARD_ADC > 0 +// ADC +/* the board supported adc channels */ +#ifndef BOARD_ADC_NUM +#define BOARD_ADC_NUM (1) +#endif + +#if defined(BOARD_ADC_NUM) && BOARD_ADC_NUM > 0 +/* the board adc pin */ +#define BOARD_ADC0_PIN (BOARD_PIN6) +/* The real adc channel reference to board logic adc channel */ +#define BOARD_ADC0_CH (0) +#endif // defined(BOARD_ADC_NUM) && BOARD_ADC_NUM > 0 +#endif // defined(CONFIG_BOARD_ADC) && CONFIG_BOARD_ADC > 0 + +#if defined(CONFIG_BOARD_BUTTON) && CONFIG_BOARD_BUTTON > 0 +// BUTTON +#ifndef BOARD_BUTTON_NUM +/* + the board supported buttons, include gpio button and adc button, + BOARD_BUTTON_NUM = BOARD_BUTTON_GPIO_NUM + BOARD_BUTTON_ADC_NUM. + +*/ +#define BOARD_BUTTON_NUM (4) +#endif + +#if defined(BOARD_BUTTON_NUM) && BOARD_BUTTON_NUM > 0 + +#define BOARD_BUTTON0_PIN (BOARD_PIN7) +#define BOARD_BUTTON1_PIN (BOARD_PIN8) +#define BOARD_BUTTON2_PIN (BOARD_PIN9) +#define BOARD_BUTTON3_PIN (BOARD_PIN10) + +// GPIO BUTTON +/* the board supported GPIO Buttons */ +#ifndef BOARD_BUTTON_GPIO_NUM +#define BOARD_BUTTON_GPIO_NUM (2) +#endif + +#if defined(BOARD_BUTTON_GPIO_NUM) && BOARD_BUTTON_GPIO_NUM > 0 +/* the board logic button id, in range of (0, BOARD_BUTTON_GPIO_NUM - 1) */ +#define BOARD_BUTTON0 (0) +/* for gpio button, define the pin numner. if the gpio pin used as gpio button, it shoudn't reference as BOARD_GPIO_PINx + */ +#define BOARD_BUTTON0_GPIO_PIN (BOARD_BUTTON0_PIN) + +#define BOARD_BUTTON1 (1) +#define BOARD_BUTTON1_GPIO_PIN (BOARD_BUTTON1_PIN) +#endif // defined(BOARD_BUTTON_GPIO_NUM) && BOARD_BUTTON_GPIO_NUM > 0 + +// ADC BUTTON +/* the board supported adc Buttons */ +#ifndef BOARD_BUTTON_ADC_NUM +#define BOARD_BUTTON_ADC_NUM (2) +#endif + +#if defined(BOARD_BUTTON_ADC_NUM) && BOARD_BUTTON_ADC_NUM > 0 +/* the board logic adc button id, in range of (BOARD_BUTTON_GPIO_NUM, BOARD_BUTTON_NUM - 1), if not suuport GPIO Button, + * BOARD_BUTTON_GPIO_NUM should be 0 */ +#define BOARD_BUTTON2 (BOARD_BUTTON_GPIO_NUM + 0) +#define BOARD_BUTTON2_ADC_PIN (BOARD_BUTTON2_PIN) +/* the adc channel used for button2, if the adc channel used as adc button, it shoudn't reference as BOARD_ADCx_CH*/ +#define BOARD_BUTTON2_ADC_CH (1) +/* the adc device name */ +#define BOARD_BUTTON2_ADC_NAME "adc1" +/* adc voltage reference */ +#define BOARD_BUTTON2_ADC_REF (100) +/* adc voltage range */ +#define BOARD_BUTTON2_ADC_RANG (500) + +#define BOARD_BUTTON3 (BOARD_BUTTON_GPIO_NUM + 1) +#define BOARD_BUTTON3_ADC_PIN (BOARD_BUTTON3_PIN) +#define BOARD_BUTTON3_ADC_CH (1) +#define BOARD_BUTTON3_ADC_NAME "adc1" +#define BOARD_BUTTON3_ADC_REF (600) +#define BOARD_BUTTON3_ADC_RANG (500) + +//#define BOARD_ADC_BUTTON2 (2) +//#define BOARD_ADC_BUTTON2_CH (1) +//#define BOARD_ADC_BUTTON2_NAME "adc1" +//#define BOARD_ADC_BUTTON2_REF xxx +//#define BOARD_ADC_BUTTON2_RANG xxx +#endif // defined(BOARD_BUTTON_ADC_NUM) && BOARD_BUTTON_ADC_NUM > 0 + +#endif // defined(BOARD_BUTTON_NUM) && BOARD_BUTTON_NUM > 0 + +#endif // defined(BOARD_BUTTON_NUM) && BOARD_BUTTON_NUM > 0 + +#if defined(CONFIG_BOARD_LED) && CONFIG_BOARD_LED > 0 +// LED +/* the board supported leds */ +#ifndef BOARD_LED_NUM +#define BOARD_LED_NUM (2) +#endif + +#define BOARD_LED0_PIN BOARD_PIN11 +#define BOARD_LED1_PIN BOARD_PIN12 + +// PWM LED +/* the board supported pwm leds */ +#ifndef BOARD_LED_PWM_NUM +#define BOARD_LED_PWM_NUM (1) +#endif + +#if defined(BOARD_LED_PWM_NUM) && BOARD_LED_PWM_NUM > 0 +#define BOARD_LED0_PWM_PIN (BOARD_LED0_PIN) +/* the pwm channel used for led0, if the pwm channel used as led0, it shoudn't reference as BOARD_PWMx_CH */ +#define BOARD_LED0_PWM_CH (0) +#endif // defined(BOARD_LED_PWM_NUM) && BOARD_LED_PWM_NUM > 0 + +// GPIO LED +#ifndef BOARD_LED_GPIO_NUM +#define BOARD_LED_GPIO_NUM (1) +#endif + +#if defined(BOARD_LED_GPIO_NUM) && BOARD_LED_GPIO_NUM > 0 +/* the gpio pin used for led0, if the gpio pin used as led, it shoudn't reference as BOARD_GPIO_PINx */ +#define BOARD_LED1_GPIO_PIN (BOARD_LED1_PIN) +#endif // defined(BOARD_LED_GPIO_NUM) && BOARD_LED_GPIO_NUM > 0 +#endif // defined(CONFIG_BOARD_LED) && CONFIG_BOARD_LED > 0 + +#if defined(CONFIG_BOARD_BT) && CONFIG_BOARD_BT > 0 +// BT +/* the board support bluetooth */ +#ifndef BOARD_BT_SUPPORT +#define BOARD_BT_SUPPORT 1 +#endif +#endif // defined(CONFIG_BOARD_BT) && CONFIG_BOARD_BT > 0 + +#if defined(CONFIG_BOARD_WIFI) && CONFIG_BOARD_WIFI > 0 +// WIFI +/* the board support wifi */ +#ifndef BOARD_WIFI_SUPPORT +#define BOARD_WIFI_SUPPORT 1 +#endif +#endif // defined(CONFIG_BOARD_WIFI) && CONFIG_BOARD_WIFI > 0 + +#if defined(CONFIG_BOARD_AUDIO) && CONFIG_BOARD_AUDIO > 0 +// Audio +/* the board support audio */ +#ifndef BOARD_AUDIO_SUPPORT +#define BOARD_AUDIO_SUPPORT 1 +#endif +#endif // defined(CONFIG_BOARD_AUDIO) && CONFIG_BOARD_AUDIO > 0 + +/****************************************************************************/ +// Common solutions defines + +// Console config, Almost all solutions and demos use these. +#ifndef CONSOLE_UART_IDX +#define CONSOLE_UART_IDX (BOARD_UART0_IDX) +#endif + +#ifndef CONFIG_CLI_USART_BAUD +#define CONFIG_CLI_USART_BAUD (BOARD_UART0_BAUD) +#endif + +#ifndef CONFIG_CONSOLE_UART_BUFSIZE +#define CONFIG_CONSOLE_UART_BUFSIZE (128) +#endif + +/****************************************************************************/ +// Commom test demos defines + +// i2c +#define EXAMPLE_IIC_IDX 0 // 1 +#define EXAMPLE_PIN_IIC_SDA 0 // PC1 +#define EXAMPLE_PIN_IIC_SCL 0 // PC0 +#define EXAMPLE_PIN_IIC_SDA_FUNC 0 // PC1_I2C1_SDA +#define EXAMPLE_PIN_IIC_SCL_FUNC 0 // PC0_I2C1_SCL + +// adc +#define EXAMPLE_ADC_CH0 0 // PA8 +#define EXAMPLE_ADC_CH0_FUNC 0 // PA8_ADC_A0 +#define EXAMPLE_ADC_CH12 0 // PA26 +#define EXAMPLE_ADC_CH12_FUNC 0 // PA26_ADC_A12 + +/****************************************************************************/ +// Vendor board defines + +/* other board specific defines */ +//#define CUSTOM_BOARD_xxx + +/****************************************************************************/ +/** + * @brief init the board for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_init(void); + +/** + * @brief init the board gpio pin for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_gpio_pin_init(void); + +/** + * @brief init the board uart for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_uart_init(void); + +/** + * @brief init the board pwm for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_pwm_init(void); + +/** + * @brief init the board adc for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_adc_init(void); + +/** + * @brief init the board button for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_button_init(void); + +/** + * @brief init the board led for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_led_init(void); + +/** + * @brief init the board wifi for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_wifi_init(void); + +/** + * @brief init the board bt for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_bt_init(void); + +/** + * @brief init the board audio for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_audio_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ \ No newline at end of file diff --git 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