diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index 2718808caea..71ed62b145d 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -47,6 +47,7 @@ "at32/at32m416-start", "hc32/ev_hc32f4a0_lqfp176", "hc32/ev_hc32f4a8_lqfp176", + "hc32/ev_hc32f334_lqfp64", "hc32/ev_hc32f448_lqfp80", "hc32/ev_hc32f460_lqfp100_v2", "hc32/ev_hc32f472_lqfp100", diff --git a/MAINTAINERS b/MAINTAINERS index 0d3c84fc38f..9dd7d5647fa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -87,6 +87,10 @@ tag: bsp_gd32e503v-eval path: bsp/gd32/arm/gd32e503v-eval owners: 蒙蒙plus(meng-plus) +tag: bsp_hc32 +path: bsp/hc32 +owners: Levi Zhang(levizh) + tag: bsp_k230 path: bsp/k230 owners: Chen Wang(unicornx) diff --git a/bsp/hc32/ev_hc32f334_lqfp64/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f334_lqfp64/.ci/attachconfig/ci.attachconfig.yml new file mode 100644 index 00000000000..1ff7e77400f --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/.ci/attachconfig/ci.attachconfig.yml @@ -0,0 +1,7 @@ +devices.gpio: + kconfig: + - CONFIG_BSP_USING_GPIO=y +devices.uart: + kconfig: + - CONFIG_BSP_USING_UART=y + - CONFIG_BSP_USING_UART2=y diff --git a/bsp/hc32/ev_hc32f334_lqfp64/.config b/bsp/hc32/ev_hc32f334_lqfp64/.config new file mode 100644 index 00000000000..7f4bb1613c5 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/.config @@ -0,0 +1,1462 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options + +# CONFIG_RT_UTEST_TC_USING_KLIBC is not set +# end of klibc options + +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" +CONFIG_RT_VER_NUM=0x50201 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_SOFT_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER=y +CONFIG_PKG_HC32F3_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32-f3-cmsis" +CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER_LATEST_VERSION=y +CONFIG_PKG_HC32F3_CMSIS_DRIVER_VER="latest" +CONFIG_PKG_USING_HC32F3_SERIES_DRIVER=y +CONFIG_PKG_HC32F3_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32-f3-series" +CONFIG_PKG_USING_HC32F3_SERIES_DRIVER_LATEST_VERSION=y +CONFIG_PKG_HC32F3_SERIES_DRIVER_VER="latest" +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_FAMILY_HC32=y +CONFIG_SOC_SERIES_HC32F3=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_HC32F334KA=y + +# +# On-chip Drivers +# +CONFIG_BSP_USING_ON_CHIP_FLASH_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_ICODE_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_DCODE_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH=y +# end of On-chip Drivers + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_SPI_FLASH is not set +# end of Onboard Peripheral Drivers + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART1 is not set +CONFIG_BSP_USING_UART2=y +# CONFIG_BSP_UART2_RX_USING_DMA is not set +# CONFIG_BSP_UART2_TX_USING_DMA is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +CONFIG_BSP_USING_I2C=y +# CONFIG_BSP_USING_I2C1_SW is not set +CONFIG_BSP_USING_I2C_HW=y +CONFIG_BSP_USING_I2C1=y +# CONFIG_BSP_I2C1_TX_USING_DMA is not set +# CONFIG_BSP_I2C1_RX_USING_DMA is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_DAC is not set +# CONFIG_BSP_USING_MCAN is not set +# CONFIG_BSP_USING_WDT_TMR is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_PM is not set +# CONFIG_BSP_USING_HWCRYPTO is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_PULSE_ENCODER is not set +# CONFIG_BSP_USING_HWTIMER is not set +# CONFIG_BSP_USING_INPUT_CAPTURE is not set +# end of On-chip Peripheral Drivers + +# +# Board extended module Drivers +# +# end of Hardware Drivers Config diff --git a/bsp/hc32/ev_hc32f334_lqfp64/.cproject b/bsp/hc32/ev_hc32f334_lqfp64/.cproject new file mode 100644 index 00000000000..dd94ed91599 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/.cproject @@ -0,0 +1,220 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f334_lqfp64/.gitignore b/bsp/hc32/ev_hc32f334_lqfp64/.gitignore new file mode 100644 index 00000000000..7221bde019d --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/hc32/ev_hc32f334_lqfp64/.project b/bsp/hc32/ev_hc32f334_lqfp64/.project new file mode 100644 index 00000000000..cb1c6b03b3a --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/.project @@ -0,0 +1,78 @@ + + + project + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + rt-thread + 2 + virtual:/virtual + + + rt-thread/bsp + 2 + virtual:/virtual + + + rt-thread/components + 2 + $%7BPARENT-3-PROJECT_LOC%7D/components + + + rt-thread/include + 2 + $%7BPARENT-3-PROJECT_LOC%7D/include + + + rt-thread/libcpu + 2 + $%7BPARENT-3-PROJECT_LOC%7D/libcpu + + + rt-thread/src + 2 + $%7BPARENT-3-PROJECT_LOC%7D/src + + + rt-thread/bsp/hc32 + 2 + virtual:/virtual + + + rt-thread/bsp/hc32/libraries + 2 + $%7BPARENT-1-PROJECT_LOC%7D/libraries + + + rt-thread/bsp/hc32/platform + 2 + PARENT-1-PROJECT_LOC/platform + + + rt-thread/bsp/hc32/tests + 2 + PARENT-1-PROJECT_LOC/tests + + + diff --git a/bsp/hc32/ev_hc32f334_lqfp64/Kconfig b/bsp/hc32/ev_hc32f334_lqfp64/Kconfig new file mode 100644 index 00000000000..73238d3a13b --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/hc32/ev_hc32f334_lqfp64/README.md b/bsp/hc32/ev_hc32f334_lqfp64/README.md new file mode 100644 index 00000000000..81bd92ccaab --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/README.md @@ -0,0 +1,140 @@ +# XHSC EV_F334_LQ64_Rev1.0 开发板 BSP 说明 + +## 简介 + +本文档为小华半导体为 EV_F334_LQ64_Rev1.0 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +EV_F334_LQ64_Rev1.0 是 XHSC 官方推出的开发板，搭载 HC32F334MCTI 芯片，基于 ARM Cortex-M4 内核，最高主频 200 MHz，具有丰富的板载资源，可以充分发挥 HC32F334MCTI 的芯片性能。 + +开发板外观如下图所示： + + ![board](figures/board.png) + +EV_F334_LQ64_Rev1.0 开发板常用 **板载资源** 如下： + +- **MCU** + - HC32F334MCTI + - 主频200MHz + - 256KB FLASH + - 68KB RAM +- **外部Memory** + - BL24C256（EEPROM, 256Kbits） + - W25Q64（SPI NOR，64MB） + - IS62WV51216（SRAM， 1MB） +- **常用外设** + - LED: 4 个，User LED（LED0，LED1，LED2，LED3）。 + - 按键: 5 个，矩阵键盘（K1~K4）， WAKEUP（K5），RESET（K0） +- **常用接口** + - USB转串口 + - CAN DB9接口 * 2 + - TFT接口 + - SmartCard接口 + - I2C/USART/SPI接口 +- **调试接口** + - 板载DAP调试器 + - 标准JTAG/SWD/Trace + +开发板更多详细信息请参考小华半导体半导体[EV_F334_LQ64_Rev1.0](https://www.xhsc.com.cn) + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +|:-------- |:--------:|:--------:| +| USB 转串口 | 支持 | 使用 UART2 | +| LED | 支持 | LED1~4 | + +| **片上外设** | **支持情况** | **备注** | +|:------------- |:--------:|:------------------------------------------:| +| Crypto | 支持 | AES, CRC, HASH, RNG, UID | +| DAC | 支持 | | +| ADC | 支持 | ADC1: CH10, CH11,
ADC3: CH1 | +| CAN | 支持 | CAN1、CAN2 | +| GPIO | 支持 | PA0, PA1... PH2 ---> PIN: 0, 1...82 | +| I2C | 支持 | 软件模拟
硬件I2C1~2
I2C1支持EEPROM（BL24C256） | +| PM | 支持 | | +| Lptimer | 支持 | | +| Hwtimer | 支持 | Hwtimer1~5 | +| Pulse_encoder | 支持 | | +| PWM | 支持 | | +| RTC | 支持 | 闹钟精度为1分钟 | +| WDT | 支持 | | +| I2C | 支持 | 软件、硬件 I2C | +| QSPI | 支持 | | +| SPI | 支持 | SPI1~3
SPI1支持W25Q | +| UART | 支持 | UART1~6
UART2为console使用 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用Type-A to MircoUSB线连接开发板和PC供电。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用板载 DAP 下载程序，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED3会周期性闪烁。 + +USB虚拟COM端口默认连接串口2，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息: + +``` + \ | / +- RT - Thread Operating System + / | \ 5.0.1 build Feb 4 2024 16:44:26 + 2006 - 2022 Copyright by RT-Thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口 2 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 + +## 注意事项 + +| 板载外设 | 模式 | 注意事项 | +| ---- | ---- | ------------------------------------------------------------------------------------------------------ | +| USB | host | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 | + +## 联系人信息 + +维护人: + +- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱： \ No newline at end of file diff --git a/bsp/hc32/ev_hc32f334_lqfp64/SConscript b/bsp/hc32/ev_hc32f334_lqfp64/SConscript new file mode 100644 index 00000000000..20f7689c53c --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hc32/ev_hc32f334_lqfp64/SConstruct b/bsp/hc32/ev_hc32f334_lqfp64/SConstruct new file mode 100644 index 00000000000..fedff3fe63a --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/SConstruct @@ -0,0 +1,83 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "hc32-f3-cmsis-latest"), + os.path.join("packages", "hc32-f3-series-latest") + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +rtconfig.BSP_LIBRARY_TYPE = None + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript'))) + +# include platform +platform_path_prefix = os.path.dirname(SDK_ROOT) + '/platform' +objs.extend(SConscript(os.path.join(platform_path_prefix, 'SConscript'))) + +# include tests +test_path_prefix = os.path.dirname(SDK_ROOT) + '/tests' +objs.extend(SConscript(os.path.join(test_path_prefix, 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hc32/ev_hc32f334_lqfp64/applications/SConscript b/bsp/hc32/ev_hc32f334_lqfp64/applications/SConscript new file mode 100644 index 00000000000..9bb9abae897 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/applications/SConscript @@ -0,0 +1,15 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/hc32/ev_hc32f334_lqfp64/applications/main.c b/bsp/hc32/ev_hc32f334_lqfp64/applications/main.c new file mode 100644 index 00000000000..013a26633d4 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/applications/main.c @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-07-10 CDT first version + */ + +#include +#include +#include + +/* defined the LED_BLUE pin: PC13 */ +#define LED_BLUE_PIN GET_PIN(C, 13) + +int main(void) +{ + /* set LED_BLUE_PIN pin mode to output */ + rt_pin_mode(LED_BLUE_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED_BLUE_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_BLUE_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} + diff --git a/bsp/hc32/ev_hc32f334_lqfp64/applications/xtal32_fcm.c b/bsp/hc32/ev_hc32f334_lqfp64/applications/xtal32_fcm.c new file mode 100644 index 00000000000..4b24e3ae667 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/applications/xtal32_fcm.c @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +#include +#include +#include + +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + +#define XTAL32_FCM_THREAD_STACK_SIZE (1024) +#define XTAL32_FCM_UNIT (CM_FCM) + +/** + * @brief This thread is used to monitor whether XTAL32 is stable. + * This thread only runs once after the system starts. + * When stability is detected or 2s times out, the thread will end. + * (When a timeout occurs it will be prompted via rt_kprintf) + */ +void xtal32_fcm_thread_entry(void *parameter) +{ + stc_fcm_init_t stcFcmInit; + uint32_t u32TimeOut = 0UL; + uint32_t u32Time = 200UL; /* 200*10ms = 2s */ + + /* FCM config */ + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE); + (void)FCM_StructInit(&stcFcmInit); + stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; + stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ + stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; + stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; + stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1; + stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); + stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); + (void)FCM_Init(XTAL32_FCM_UNIT, &stcFcmInit); + /* Enable FCM, to ensure xtal32 stable */ + FCM_Cmd(XTAL32_FCM_UNIT, ENABLE); + + while (1) + { + if (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_END)) + { + FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_END); + if ((SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR)) || (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_OVF))) + { + FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR | FCM_FLAG_OVF); + } + else + { + (void)FCM_DeInit(XTAL32_FCM_UNIT); + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE); + /* XTAL32 stabled */ + break; + } + } + u32TimeOut++; + if (u32TimeOut > u32Time) + { + (void)FCM_DeInit(XTAL32_FCM_UNIT); + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE); + rt_kprintf("Error: XTAL32 still unstable, timeout.\n"); + break; + } + rt_thread_mdelay(10); + } +} + +int xtal32_fcm_thread_create(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL, + XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + rt_kprintf("create xtal32_fcm thread err!"); + } + return RT_EOK; +} +INIT_APP_EXPORT(xtal32_fcm_thread_create); + +#endif + + diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/Kconfig b/bsp/hc32/ev_hc32f334_lqfp64/board/Kconfig new file mode 100644 index 00000000000..6c6cdf0fd3d --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/Kconfig @@ -0,0 +1,619 @@ +menu "Hardware Drivers Config" + +config SOC_HC32F334KA + bool + select SOC_SERIES_HC32F3 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Drivers" + menuconfig BSP_USING_ON_CHIP_FLASH_CACHE + bool "Enable on-chip Flash Cache" + default y + if BSP_USING_ON_CHIP_FLASH_CACHE + config BSP_USING_ON_CHIP_FLASH_ICODE_CACHE + bool "Enable on-chip Flash ICODE Cache" + default y + config BSP_USING_ON_CHIP_FLASH_DCODE_CACHE + bool "Enable on-chip Flash DCODE Cache" + default y + config BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH + bool "Enable on-chip Flash ICODE Prefetch" + default y + endif +endmenu + +menu "Onboard Peripheral Drivers" + + config BSP_USING_SPI_FLASH + bool "Enable SPI FLASH (w25q64 spi1)" + select BSP_USING_SPI + select BSP_USING_SPI1 + select BSP_USING_ON_CHIP_FLASH + select RT_USING_SFUD + select RT_USING_DFS + select RT_USING_FAL + select RT_USING_MTD_NOR + default n + +endmenu + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default y + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART1_DMA_PING_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA + default 64 + endif + + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + + config BSP_UART2_DMA_PING_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA + default 64 + endif + + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART3_DMA_PING_BUFSIZE + int "Set UART3 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART3_RX_USING_DMA + default 64 + endif + + menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config BSP_UART4_RX_USING_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + + config BSP_UART4_TX_USING_DMA + bool "Enable UART4 TX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + + config BSP_UART4_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART4_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART4_DMA_PING_BUFSIZE + int "Set UART4 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART4_RX_USING_DMA + default 64 + endif + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C BUS" + default n + select RT_USING_I2C + + if BSP_USING_I2C + menuconfig BSP_USING_I2C1_SW + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1_SW + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 1 68 + default 22 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 1 68 + default 23 + endif + endif + + if BSP_USING_I2C + config BSP_I2C_USING_DMA + bool + default n + config BSP_USING_I2C_HW + bool + default n + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool + default n + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C1_USING_DMA + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C1_USING_DMA + endif + endif + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_SPI_USING_DMA + bool + default n + + menuconfig BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + if BSP_USING_SPI1 + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI1_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + if BSP_USING_SPI2 + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI2_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI3 + bool "Enable SPI3 BUS" + default n + if BSP_USING_SPI3 + config BSP_SPI3_TX_USING_DMA + bool "Enable SPI3 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI3_RX_USING_DMA + bool "Enable SPI3 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI3_TX_USING_DMA + default n + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC1 + bool "Enable ADC1" + default n + if BSP_USING_ADC1 + config BSP_ADC1_USING_DMA + bool "using adc1 dma" + default n + endif + menuconfig BSP_USING_ADC2 + bool "Enable ADC2" + default n + if BSP_USING_ADC2 + config BSP_ADC2_USING_DMA + bool "using adc2 dma" + default n + endif + menuconfig BSP_USING_ADC3 + bool "Enable ADC3" + default n + if BSP_USING_ADC3 + config BSP_ADC3_USING_DMA + bool "using adc3 dma" + default n + endif + endif + + menuconfig BSP_USING_DAC + bool "Enable DAC" + default n + select RT_USING_DAC + if BSP_USING_DAC + config BSP_USING_DAC1 + bool "using dac1" + default n + endif + + menuconfig BSP_USING_MCAN + bool "Enable MCAN" + default n + select RT_USING_CAN + select RT_CAN_USING_HDR + if BSP_USING_MCAN + config BSP_USING_MCAN1 + bool "using mcan1" + default n + config BSP_USING_MCAN2 + bool "using mcan2" + default n + endif + + menuconfig BSP_USING_WDT_TMR + bool "Enable Watchdog Timer" + default n + select RT_USING_WDT + if BSP_USING_WDT_TMR + choice + prompt "Select SWDT/WDT" + default BSP_USING_SWDT + + config BSP_USING_SWDT + bool "SWDT(3.72hour(max))" + config BSP_USING_WDT + bool "WDT(10.7s(max))" + endchoice + + config BSP_WDT_CONTINUE_COUNT + bool "Low Power Mode Keeps Counting" + default n + endif + + menuconfig BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + if BSP_USING_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_XTAL32 + + config BSP_RTC_USING_XTAL32 + bool "RTC Using XTAL32" + + config BSP_RTC_USING_LRC + bool "RTC Using LRC" + + config BSP_RTC_USING_XTAL_DIV + bool "RTC Using XTAL Division" + endchoice + endif + + menuconfig BSP_USING_PM + bool "Enable PM" + default n + select RT_USING_PM + if BSP_USING_PM + choice + prompt "Select WKTM Clock Src" + default BSP_USING_WKTM_LRC + + config BSP_USING_WKTM_XTAL32 + bool "Using Xtal32" + config BSP_USING_WKTM_LRC + bool "Using LRC" + if BSP_RTC_USING_XTAL32 + config BSP_USING_WKTM_64HZ + bool "Using 64HZ(Note:must use XTAL32 and run RTC)" + endif + endchoice + endif + + menuconfig BSP_USING_HWCRYPTO + bool "Using Hardware Crypto drivers" + default n + select RT_USING_HWCRYPTO + if BSP_USING_HWCRYPTO + config BSP_USING_UQID + bool "Enable UQID (unique id)" + default n + + config BSP_USING_RNG + bool "Using Hardware RNG" + default n + select RT_HWCRYPTO_USING_RNG + + config BSP_USING_CRC + bool "Using Hardware CRC" + default n + select RT_HWCRYPTO_USING_CRC + + config BSP_USING_AES + bool "Using Hardware AES" + default n + select RT_HWCRYPTO_USING_AES + if BSP_USING_AES + choice + prompt "Select AES Mode" + default BSP_USING_AES_ECB + + config BSP_USING_AES_ECB + bool "ECB mode" + select RT_HWCRYPTO_USING_AES_ECB + endchoice + endif + + config BSP_USING_HASH + bool "Using Hardware Hash" + default n + select RT_HWCRYPTO_USING_SHA2 + if BSP_USING_HASH + choice + prompt "Select Hash Mode" + default BSP_USING_SHA2_256 + + config BSP_USING_SHA2_256 + bool "SHA2_256 Mode" + select RT_HWCRYPTO_USING_SHA2_256 + endchoice + endif + + endif + + menuconfig BSP_USING_PWM + bool "Enable output PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM_TMRA + bool "Enable timerA output PWM" + default n + if BSP_USING_PWM_TMRA + menuconfig BSP_USING_PWM_TMRA_1 + bool "Enable timerA-1 output PWM" + default n + if BSP_USING_PWM_TMRA_1 + config BSP_USING_PWM_TMRA_1_CH1 + bool "Enable timerA-1 channel1" + default n + config BSP_USING_PWM_TMRA_1_CH2 + bool "Enable timerA-1 channel2" + default n + endif + menuconfig BSP_USING_PWM_TMRA_2 + bool "Enable timerA-2 output PWM" + default n + if BSP_USING_PWM_TMRA_2 + config BSP_USING_PWM_TMRA_2_CH1 + bool "Enable timerA-2 channel1" + default n + config BSP_USING_PWM_TMRA_2_CH2 + bool "Enable timerA-2 channel2" + default n + endif + endif + menuconfig BSP_USING_PWM_TMR4 + bool "Enable timer4 output PWM" + default n + if BSP_USING_PWM_TMR4 + menuconfig BSP_USING_PWM_TMR4_1 + bool "Enable timer4-1 output PWM" + default n + if BSP_USING_PWM_TMR4_1 + config BSP_USING_PWM_TMR4_1_OUH + bool "Enable TMR4_1_OUH channel0" + default n + config BSP_USING_PWM_TMR4_1_OUL + bool "Enable TMR4_1_OUL channel1" + default n + config BSP_USING_PWM_TMR4_1_OVH + bool "Enable TMR4_1_OVH channel2" + default n + config BSP_USING_PWM_TMR4_1_OVL + bool "Enable TMR4_1_OVL channel3" + default n + config BSP_USING_PWM_TMR4_1_OWH + bool "Enable TMR4_1_OWH channel4" + default n + config BSP_USING_PWM_TMR4_1_OWL + bool "Enable TMR4_1_OWL channel5" + default n + endif + endif + menuconfig BSP_USING_PWM_TMR6 + bool "Enable timer6 output PWM" + default n + if BSP_USING_PWM_TMR6 + menuconfig BSP_USING_PWM_TMR6_1 + bool "Enable timer6-1 output PWM" + default n + if BSP_USING_PWM_TMR6_1 + config BSP_USING_PWM_TMR6_1_A + bool "Enable TMR6_1_A channel0" + default n + config BSP_USING_PWM_TMR6_1_B + bool "Enable TMR6_1_B channel1" + default n + endif + endif + endif + + menuconfig BSP_USING_PULSE_ENCODER + bool "Enable Pulse Encoder" + default n + select RT_USING_PULSE_ENCODER + if BSP_USING_PULSE_ENCODER + menuconfig BSP_USING_TMRA_PULSE_ENCODER + bool "Use TIMERA As The Pulse Encoder" + default n + if BSP_USING_TMRA_PULSE_ENCODER + config BSP_USING_PULSE_ENCODER_TMRA_1 + bool "Use TIMERA_1 As The Pulse Encoder" + default n + endif + menuconfig BSP_USING_TMR6_PULSE_ENCODER + bool "Use TIMER6 As The Pulse Encoder" + default n + if BSP_USING_TMR6_PULSE_ENCODER + config BSP_USING_PULSE_ENCODER_TMR6_1 + bool "Use TIMER6_1 As The Pulse Encoder" + default n + endif + endif + + menuconfig BSP_USING_HWTIMER + bool "Enable Hw Timer" + default n + select RT_USING_HWTIMER + if BSP_USING_HWTIMER + config BSP_USING_TMRA_1 + bool "Use Timer_a1 As The Hw Timer" + default n + config BSP_USING_TMRA_2 + bool "Use Timer_a2 As The Hw Timer" + default n + config BSP_USING_TMRA_3 + bool "Use Timer_a3 As The Hw Timer" + default n + config BSP_USING_TMRA_4 + bool "Use Timer_a4 As The Hw Timer" + default n + config BSP_USING_TMRA_5 + bool "Use Timer_a5 As The Hw Timer" + default n + endif + + menuconfig BSP_USING_INPUT_CAPTURE + bool "Enable Input Capture" + default n + select RT_USING_INPUT_CAPTURE + if BSP_USING_INPUT_CAPTURE + menuconfig BSP_USING_INPUT_CAPTURE_TMR6 + bool "Use Timer6 As The Input Capture" + default n + if BSP_USING_INPUT_CAPTURE_TMR6 + config BSP_USING_INPUT_CAPTURE_TMR6_1 + bool "unit 1" + config BSP_USING_INPUT_CAPTURE_TMR6_2 + bool "unit 2" + config BSP_USING_INPUT_CAPTURE_TMR6_3 + bool "unit 3" + config BSP_USING_INPUT_CAPTURE_TMR6_4 + bool "unit 4" + config BSP_USING_INPUT_CAPTURE_TMR6_5 + bool "unit 5" + config BSP_USING_INPUT_CAPTURE_TMR6_6 + bool "unit 6" + config BSP_USING_INPUT_CAPTURE_TMR6_7 + bool "unit 7" + config BSP_USING_INPUT_CAPTURE_TMR6_8 + bool "unit 8" + endif + endif +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/SConscript b/bsp/hc32/ev_hc32f334_lqfp64/board/SConscript new file mode 100644 index 00000000000..8e03cfa0d49 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/SConscript @@ -0,0 +1,19 @@ +import os +from building import * + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +board_config.c +''') + +path = [cwd] +path += [cwd + '/ports'] +path += [cwd + '/config'] + +CPPDEFINES = ['HC32F334', '__DEBUG'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/board.c b/bsp/hc32/ev_hc32f334_lqfp64/board/board.c new file mode 100644 index 00000000000..35f7a1fbc63 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/board.c @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#include "board.h" +#include "board_config.h" + +/* unlock/lock peripheral */ +#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ + LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) +#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) + +/** System Base Configuration +*/ +void SystemBase_Config(void) +{ +#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_CACHE) + EFM_ICacheCmd(ENABLE); +#endif +#if defined(BSP_USING_ON_CHIP_FLASH_DCODE_CACHE) + EFM_DCacheCmd(ENABLE); +#endif +#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH) + EFM_PrefetchCmd(ENABLE); +#endif +} + +/** System Clock Configuration +*/ +void SystemClock_Config(void) +{ + stc_clock_xtal_init_t stcXtalInit; + stc_clock_pll_init_t stcPLLHInit; +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + stc_clock_xtal32_init_t stcXtal32Init; +#endif +#if defined(BSP_RTC_USING_XTAL_DIV) + stc_clock_xtaldiv_init_t stcXtaldivInit; +#endif + + /* PCLK0, HCLK Max 120MHz */ + /* PCLK1, PCLK2, PCLK3, PCLK4 Max 60MHz */ + CLK_SetClockDiv(CLK_BUS_CLK_ALL, + (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV2 | + CLK_PCLK3_DIV2 | CLK_PCLK4_DIV2 | CLK_HCLK_DIV1)); + + + GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE); + (void)CLK_XtalStructInit(&stcXtalInit); + /* Config Xtal and enable Xtal */ + stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; + stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; + stcXtalInit.u8State = CLK_XTAL_ON; + stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS; + (void)CLK_XtalInit(&stcXtalInit); + + (void)CLK_PLLStructInit(&stcPLLHInit); + /* VCO = (8/1)*60 = 480MHz*/ + stcPLLHInit.u8PLLState = CLK_PLL_ON; + stcPLLHInit.PLLCFGR = 0UL; + stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLN = 60UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL; + (void)CLK_PLLInit(&stcPLLHInit); + + /* 2 cycles for 100 ~ 120MHz */ + (void)EFM_SetWaitCycle(EFM_WAIT_CYCLE2); + /* 2 cycles for 100 ~ 120MHz */ + GPIO_SetReadWaitCycle(GPIO_RD_WAIT2); + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); + +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + /* Xtal32 config */ + GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE); + (void)CLK_Xtal32StructInit(&stcXtal32Init); + stcXtal32Init.u8State = CLK_XTAL32_ON; + stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; + stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD; + (void)CLK_Xtal32Init(&stcXtal32Init); +#endif + +#if defined(BSP_RTC_USING_XTAL_DIV) + /* Xtal Div config */ + (void)CLK_XtalDivStructInit(&stcXtaldivInit); + /* 8000000Hz / 32768Hz = 0x7A12 / 0x80 */ + stcXtaldivInit.u32Num = 0x7A12UL; + stcXtaldivInit.u32Den = 0x80UL; + stcXtaldivInit.u32State = CLK_XTALDIV_ON; + (void)CLK_XtalDivInit(&stcXtaldivInit); +#endif +} + +/** Peripheral Clock Configuration +*/ +void PeripheralClock_Config(void) +{ +#if defined(BSP_USING_MCAN1) + CLK_SetCANClockSrc(CLK_MCAN1, CLK_MCANCLK_SYSCLK_DIV3); +#endif +#if defined(BSP_USING_MCAN2) + CLK_SetCANClockSrc(CLK_MCAN2, CLK_MCANCLK_SYSCLK_DIV3); +#endif + +#if defined(RT_USING_ADC) + CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK); +#endif +} + +/** Peripheral Registers Unlock +*/ +void PeripheralRegister_Unlock(void) +{ + LL_PERIPH_WE(EXAMPLE_PERIPH_WE); +} + +/*@}*/ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/board.h b/bsp/hc32/ev_hc32f334_lqfp64/board/board.h new file mode 100644 index 00000000000..9976ff7bbd6 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/board.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "hc32_ll.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HC32_FLASH_ERASE_GRANULARITY (4 * 1024) +#define HC32_FLASH_WRITE_GRANULARITY (4) +#define HC32_FLASH_SIZE (128 * 1024) +#define HC32_FLASH_START_ADDRESS (0) +#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) + +#define HC32_SRAM_SIZE (32) +#define HC32_SRAM_END (0x1FFFC000 + HC32_SRAM_SIZE * 1024) + +#ifdef __ARMCC_VERSION +extern int Image$$RW_IRAM2$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END HC32_SRAM_END + +void PeripheralRegister_Unlock(void); +void PeripheralClock_Config(void); +void SystemBase_Config(void); +void SystemClock_Config(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.c b/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.c new file mode 100644 index 00000000000..0f30c3fd3df --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.c @@ -0,0 +1,388 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#include +#include "board_config.h" + +/** + * The below functions will initialize HC32 board. + */ + +#if defined RT_USING_SERIAL +rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)USARTx) + { +#if defined(BSP_USING_UART1) + case (rt_uint32_t)CM_USART1: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART1_RX_PORT, USART1_RX_PIN, USART1_RX_FUNC); + GPIO_SetFunc(USART1_TX_PORT, USART1_TX_PIN, USART1_TX_FUNC); + break; +#endif +#if defined(BSP_USING_UART2) + case (rt_uint32_t)CM_USART2: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART2_RX_PORT, USART2_RX_PIN, USART2_RX_FUNC); + GPIO_SetFunc(USART2_TX_PORT, USART2_TX_PIN, USART2_TX_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_I2C) +rt_err_t rt_hw_board_i2c_init(CM_I2C_TypeDef *I2Cx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + (void)GPIO_StructInit(&stcGpioInit); + + switch ((rt_uint32_t)I2Cx) + { +#if defined(BSP_USING_I2C1) + case (rt_uint32_t)CM_I2C: + /* Configure I2C1 SDA/SCL pin. */ + GPIO_SetFunc(I2C1_SDA_PORT, I2C1_SDA_PIN, I2C1_SDA_FUNC); + GPIO_SetFunc(I2C1_SCL_PORT, I2C1_SCL_PIN, I2C1_SCL_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + +#if defined(RT_USING_ADC) +rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG; + switch ((rt_uint32_t)ADCx) + { +#if defined(BSP_USING_ADC1) + case (rt_uint32_t)CM_ADC1: + (void)GPIO_Init(ADC1_CH_PORT, ADC1_CH_PIN, &stcGpioInit); + break; +#endif +#if defined(BSP_USING_ADC2) + case (rt_uint32_t)CM_ADC2: + (void)GPIO_Init(ADC2_CH_PORT, ADC2_CH_PIN, &stcGpioInit); + break; +#endif +#if defined(BSP_USING_ADC3) + case (rt_uint32_t)CM_ADC3: + (void)GPIO_Init(ADC3_CH_PORT, ADC3_CH_PIN, &stcGpioInit); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_DAC) +rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG; + switch ((rt_uint32_t)DACx) + { +#if defined(BSP_USING_DAC1) + case (rt_uint32_t)CM_DAC: + (void)GPIO_Init(DAC1_CH1_PORT, DAC1_CH1_PIN, &stcGpioInit); + (void)GPIO_Init(DAC1_CH2_PORT, DAC1_CH2_PIN, &stcGpioInit); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_CAN) +void CanPhyEnable(void) +{ +#if defined(BSP_USING_MCAN1) + TCA9539_WritePin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_PIN_RESET); + TCA9539_ConfigPin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_DIR_OUT); +#endif +#if defined(BSP_USING_MCAN2) + TCA9539_WritePin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_PIN_RESET); + TCA9539_ConfigPin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_DIR_OUT); +#endif +} +rt_err_t rt_hw_board_mcan_init(CM_MCAN_TypeDef *MCANx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)MCANx) + { +#if defined(BSP_USING_MCAN1) + case (rt_uint32_t)CM_MCAN1: + GPIO_SetFunc(MCAN1_TX_PORT, MCAN1_TX_PIN, MCAN1_TX_PIN_FUNC); + GPIO_SetFunc(MCAN1_RX_PORT, MCAN1_RX_PIN, MCAN1_RX_PIN_FUNC); + break; +#endif +#if defined(BSP_USING_MCAN2) + case (rt_uint32_t)CM_MCAN2: + GPIO_SetFunc(MCAN2_TX_PORT, MCAN2_TX_PIN, MCAN2_TX_PIN_FUNC); + GPIO_SetFunc(MCAN2_RX_PORT, MCAN2_RX_PIN, MCAN2_RX_PIN_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined (RT_USING_SPI) +rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) +{ + rt_err_t result = RT_EOK; +#if defined(BSP_USING_SPI1) + stc_gpio_init_t stcGpioInit; +#endif + + switch ((rt_uint32_t)CM_SPIx) + { +#if defined(BSP_USING_SPI1) + case (rt_uint32_t)CM_SPI1: + GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinState = PIN_STAT_SET; + stcGpioInit.u16PinDir = PIN_DIR_OUT; + GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit); + GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit); + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS; + (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit); + GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); + GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC); + GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_PWM) +#if defined(BSP_USING_PWM_TMRA) +rt_err_t rt_hw_board_pwm_tmra_init(CM_TMRA_TypeDef *TMRAx) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMRAx) + { +#if defined(BSP_USING_PWM_TMRA_1) + case (rt_uint32_t)CM_TMRA_1: +#ifdef BSP_USING_PWM_TMRA_1_CH1 + GPIO_SetFunc(PWM_TMRA_1_CH1_PORT, PWM_TMRA_1_CH1_PIN, PWM_TMRA_1_CH1_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH2 + GPIO_SetFunc(PWM_TMRA_1_CH2_PORT, PWM_TMRA_1_CH2_PIN, PWM_TMRA_1_CH2_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH3 + GPIO_SetFunc(PWM_TMRA_1_CH3_PORT, PWM_TMRA_1_CH3_PIN, PWM_TMRA_1_CH3_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH4 + GPIO_SetFunc(PWM_TMRA_1_CH4_PORT, PWM_TMRA_1_CH4_PIN, PWM_TMRA_1_CH4_PIN_FUNC); +#endif + break; +#endif +#if defined(BSP_USING_PWM_TMRA_2) + case (rt_uint32_t)CM_TMRA_2: +#ifdef BSP_USING_PWM_TMRA_2_CH1 + GPIO_SetFunc(PWM_TMRA_2_CH1_PORT, PWM_TMRA_2_CH1_PIN, PWM_TMRA_2_CH1_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_2_CH2 + GPIO_SetFunc(PWM_TMRA_2_CH2_PORT, PWM_TMRA_2_CH2_PIN, PWM_TMRA_2_CH2_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_2_CH3 + GPIO_SetFunc(PWM_TMRA_2_CH3_PORT, PWM_TMRA_2_CH3_PIN, PWM_TMRA_2_CH3_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_2_CH4 + GPIO_SetFunc(PWM_TMRA_2_CH4_PORT, PWM_TMRA_2_CH4_PIN, PWM_TMRA_2_CH4_PIN_FUNC); +#endif + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(BSP_USING_PWM_TMR4) +rt_err_t rt_hw_board_pwm_tmr4_init(CM_TMR4_TypeDef *TMR4x) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMR4x) + { +#if defined(BSP_USING_PWM_TMR4_1) + case (rt_uint32_t)CM_TMR4_1: +#ifdef BSP_USING_PWM_TMR4_1_OUH + GPIO_SetFunc(PWM_TMR4_1_OUH_PORT, PWM_TMR4_1_OUH_PIN, PWM_TMR4_1_OUH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OUL + GPIO_SetFunc(PWM_TMR4_1_OUL_PORT, PWM_TMR4_1_OUL_PIN, PWM_TMR4_1_OUL_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OVH + GPIO_SetFunc(PWM_TMR4_1_OVH_PORT, PWM_TMR4_1_OVH_PIN, PWM_TMR4_1_OVH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OVL + GPIO_SetFunc(PWM_TMR4_1_OVL_PORT, PWM_TMR4_1_OVL_PIN, PWM_TMR4_1_OVL_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OWH + GPIO_SetFunc(PWM_TMR4_1_OWH_PORT, PWM_TMR4_1_OWH_PIN, PWM_TMR4_1_OWH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OWL + GPIO_SetFunc(PWM_TMR4_1_OWL_PORT, PWM_TMR4_1_OWL_PIN, PWM_TMR4_1_OWL_PIN_FUNC); +#endif + break; +#endif + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + +#if defined(BSP_USING_PWM_TMR6) +rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMR6x) + { +#if defined(BSP_USING_PWM_TMR6_1) + case (rt_uint32_t)CM_TMR6_1: +#ifdef BSP_USING_PWM_TMR6_1_A + GPIO_SetFunc(PWM_TMR6_1_A_PORT, PWM_TMR6_1_A_PIN, PWM_TMR6_1_A_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR6_1_B + GPIO_SetFunc(PWM_TMR6_1_B_PORT, PWM_TMR6_1_B_PIN, PWM_TMR6_1_B_PIN_FUNC); +#endif + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif +#endif + +#if defined (BSP_USING_INPUT_CAPTURE) +rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)tmr_instance) + { +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) + case (rt_uint32_t)CM_TMR6_1: + GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, INPUT_CAPTURE_TMR6_FUNC); + break; +#endif +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) + case (rt_uint32_t)CM_TMR6_2: + GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, INPUT_CAPTURE_TMR6_FUNC); + break; +#endif +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3) + case (rt_uint32_t)CM_TMR6_3: + GPIO_SetFunc(INPUT_CAPTURE_TMR6_3_PORT, INPUT_CAPTURE_TMR6_3_PIN, INPUT_CAPTURE_TMR6_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + +#ifdef RT_USING_PM +void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode) +{ + switch (run_mode) + { + case PM_RUN_MODE_HIGH_SPEED: + case PM_RUN_MODE_NORMAL_SPEED: + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); + break; + + case PM_RUN_MODE_LOW_SPEED: + /* Ensure that system clock less than 8M */ + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_XTAL); + + default: + break; + } +} +#endif + +#if defined(BSP_USING_TMRA_PULSE_ENCODER) +rt_err_t rt_hw_board_pulse_encoder_tmra_init(void) +{ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) + GPIO_SetFunc(PULSE_ENCODER_TMRA_1_A_PORT, PULSE_ENCODER_TMRA_1_A_PIN, PULSE_ENCODER_TMRA_1_A_PIN_FUNC); + GPIO_SetFunc(PULSE_ENCODER_TMRA_1_B_PORT, PULSE_ENCODER_TMRA_1_B_PIN, PULSE_ENCODER_TMRA_1_B_PIN_FUNC); +#endif + return RT_EOK; +} +#endif + +#if defined(BSP_USING_TMR6_PULSE_ENCODER) +rt_err_t rt_hw_board_pulse_encoder_tmr6_init(void) +{ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) + GPIO_SetFunc(PULSE_ENCODER_TMR6_1_A_PORT, PULSE_ENCODER_TMR6_1_A_PIN, PULSE_ENCODER_TMR6_1_A_PIN_FUNC); + GPIO_SetFunc(PULSE_ENCODER_TMR6_1_B_PORT, PULSE_ENCODER_TMR6_1_B_PIN, PULSE_ENCODER_TMR6_1_B_PIN_FUNC); +#endif + return RT_EOK; +} +#endif diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.h new file mode 100644 index 00000000000..0a060ce4efd --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.h @@ -0,0 +1,276 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + + +#ifndef __BOARD_CONFIG_H__ +#define __BOARD_CONFIG_H__ + +#include +#include "hc32_ll.h" +#include "drv_config.h" + + +/************************* XTAL port **********************/ +#define XTAL_PORT (GPIO_PORT_F) +#define XTAL_IN_PIN (GPIO_PIN_00) +#define XTAL_OUT_PIN (GPIO_PIN_01) + +/************************ USART port **********************/ +#if defined(BSP_USING_UART1) + #define USART1_RX_PORT (GPIO_PORT_B) + #define USART1_RX_PIN (GPIO_PIN_06) + #define USART1_RX_FUNC (GPIO_FUNC_33) + + #define USART1_TX_PORT (GPIO_PORT_B) + #define USART1_TX_PIN (GPIO_PIN_07) + #define USART1_TX_FUNC (GPIO_FUNC_32) +#endif + +#if defined(BSP_USING_UART2) + #define USART2_RX_PORT (GPIO_PORT_C) + #define USART2_RX_PIN (GPIO_PIN_04) + #define USART2_RX_FUNC (GPIO_FUNC_37) + + #define USART2_TX_PORT (GPIO_PORT_C) + #define USART2_TX_PIN (GPIO_PIN_10) + #define USART2_TX_FUNC (GPIO_FUNC_36) +#endif + +/************************ I2C port **********************/ +#if defined(BSP_USING_I2C1) + #define I2C1_SDA_PORT (GPIO_PORT_B) + #define I2C1_SDA_PIN (GPIO_PIN_06) + #define I2C1_SDA_FUNC (GPIO_FUNC_52) + + #define I2C1_SCL_PORT (GPIO_PORT_B) + #define I2C1_SCL_PIN (GPIO_PIN_07) + #define I2C1_SCL_FUNC (GPIO_FUNC_53) +#endif + +/*********** ADC configure *********/ +#if defined(BSP_USING_ADC1) + #define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN10 */ + #define ADC1_CH_PIN (GPIO_PIN_00) +#endif + +#if defined(BSP_USING_ADC2) + #define ADC2_CH_PORT (GPIO_PORT_A) /* Default ADC12_IN4 */ + #define ADC2_CH_PIN (GPIO_PIN_04) +#endif + +#if defined(BSP_USING_ADC3) + #define ADC3_CH_PORT (GPIO_PORT_E) /* Default ADC3_IN1 */ + #define ADC3_CH_PIN (GPIO_PIN_03) +#endif + +/*********** DAC configure *********/ +#if defined(BSP_USING_DAC1) + #define DAC1_CH1_PORT (GPIO_PORT_A) + #define DAC1_CH1_PIN (GPIO_PIN_04) + #define DAC1_CH2_PORT (GPIO_PORT_A) + #define DAC1_CH2_PIN (GPIO_PIN_05) +#endif + +/*********** CAN configure *********/ +#if defined(BSP_USING_MCAN1) + #define MCAN1_TX_PORT (GPIO_PORT_C) + #define MCAN1_TX_PIN (GPIO_PIN_12) + #define MCAN1_TX_PIN_FUNC (GPIO_FUNC_56) + + #define MCAN1_RX_PORT (GPIO_PORT_D) + #define MCAN1_RX_PIN (GPIO_PIN_00) + #define MCAN1_RX_PIN_FUNC (GPIO_FUNC_57) +#endif + +#if defined(BSP_USING_MCAN2) + #define MCAN2_TX_PORT (GPIO_PORT_H) + #define MCAN2_TX_PIN (GPIO_PIN_02) + #define MCAN2_TX_PIN_FUNC (GPIO_FUNC_56) + + #define MCAN2_RX_PORT (GPIO_PORT_E) + #define MCAN2_RX_PIN (GPIO_PIN_04) + #define MCAN2_RX_PIN_FUNC (GPIO_FUNC_57) +#endif + +/************************* SPI port ***********************/ +#if defined(BSP_USING_SPI1) + #define SPI1_CS_PORT (GPIO_PORT_C) + #define SPI1_CS_PIN (GPIO_PIN_07) + + #define SPI1_SCK_PORT (GPIO_PORT_B) + #define SPI1_SCK_PIN (GPIO_PIN_14) + #define SPI1_SCK_FUNC (GPIO_FUNC_47) + + #define SPI1_MOSI_PORT (GPIO_PORT_B) + #define SPI1_MOSI_PIN (GPIO_PIN_13) + #define SPI1_MOSI_FUNC (GPIO_FUNC_44) + + #define SPI1_MISO_PORT (GPIO_PORT_D) + #define SPI1_MISO_PIN (GPIO_PIN_09) + #define SPI1_MISO_FUNC (GPIO_FUNC_45) + + #define SPI1_WP_PORT (GPIO_PORT_D) + #define SPI1_WP_PIN (GPIO_PIN_10) + + #define SPI1_HOLD_PORT (GPIO_PORT_D) + #define SPI1_HOLD_PIN (GPIO_PIN_11) +#endif + +/************************ RTC/PM *****************************/ +#if defined(BSP_USING_RTC) || defined(RT_USING_PM) + #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + #define XTAL32_PORT (GPIO_PORT_C) + #define XTAL32_IN_PIN (GPIO_PIN_14) + #define XTAL32_OUT_PIN (GPIO_PIN_15) + #endif +#endif + +#if defined(RT_USING_PWM) + /*********** PWM_TMRA configure *********/ + #if defined(BSP_USING_PWM_TMRA_1) + #if defined(BSP_USING_PWM_TMRA_1_CH1) + #define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) + #define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08) + #define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_1_CH2) + #define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) + #define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09) + #define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_1_CH3) + #define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) + #define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10) + #define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_1_CH4) + #define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) + #define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11) + #define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4) + #endif + #endif + + #if defined(BSP_USING_PWM_TMRA_2) + #if defined(BSP_USING_PWM_TMRA_2_CH1) + #define PWM_TMRA_2_CH1_PORT (GPIO_PORT_A) + #define PWM_TMRA_2_CH1_PIN (GPIO_PIN_00) + #define PWM_TMRA_2_CH1_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_2_CH2) + #define PWM_TMRA_2_CH2_PORT (GPIO_PORT_A) + #define PWM_TMRA_2_CH2_PIN (GPIO_PIN_01) + #define PWM_TMRA_2_CH2_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_2_CH3) + #define PWM_TMRA_2_CH3_PORT (GPIO_PORT_A) + #define PWM_TMRA_2_CH3_PIN (GPIO_PIN_02) + #define PWM_TMRA_2_CH3_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_2_CH4) + #define PWM_TMRA_2_CH4_PORT (GPIO_PORT_A) + #define PWM_TMRA_2_CH4_PIN (GPIO_PIN_03) + #define PWM_TMRA_2_CH4_PIN_FUNC (GPIO_FUNC_4) + #endif + #endif + + /*********** PWM_TMR4 configure *********/ + #if defined(BSP_USING_PWM_TMR4_1) + #if defined(BSP_USING_PWM_TMR4_1_OUH) + #define PWM_TMR4_1_OUH_PORT (GPIO_PORT_A) + #define PWM_TMR4_1_OUH_PIN (GPIO_PIN_08) + #define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OUL) + #define PWM_TMR4_1_OUL_PORT (GPIO_PORT_A) + #define PWM_TMR4_1_OUL_PIN (GPIO_PIN_07) + #define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OVH) + #define PWM_TMR4_1_OVH_PORT (GPIO_PORT_A) + #define PWM_TMR4_1_OVH_PIN (GPIO_PIN_09) + #define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OVL) + #define PWM_TMR4_1_OVL_PORT (GPIO_PORT_B) + #define PWM_TMR4_1_OVL_PIN (GPIO_PIN_00) + #define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OWH) + #define PWM_TMR4_1_OWH_PORT (GPIO_PORT_A) + #define PWM_TMR4_1_OWH_PIN (GPIO_PIN_10) + #define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OWL) + #define PWM_TMR4_1_OWL_PORT (GPIO_PORT_B) + #define PWM_TMR4_1_OWL_PIN (GPIO_PIN_01) + #define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2) + #endif + #endif + + /*********** PWM_TMR6 configure *********/ + #if defined(BSP_USING_PWM_TMR6_1) + #if defined(BSP_USING_PWM_TMR6_1_A) + #define PWM_TMR6_1_A_PORT (GPIO_PORT_A) + #define PWM_TMR6_1_A_PIN (GPIO_PIN_08) + #define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) + #endif + #if defined(BSP_USING_PWM_TMR6_1_B) + #define PWM_TMR6_1_B_PORT (GPIO_PORT_A) + #define PWM_TMR6_1_B_PIN (GPIO_PIN_07) + #define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) + #endif + #endif + +#endif + +#if defined(BSP_USING_INPUT_CAPTURE) + #define INPUT_CAPTURE_TMR6_FUNC (GPIO_FUNC_3) + #if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) + #define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_B) + #define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_09) + #endif + #if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) + #define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_E) + #define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_07) + #endif + #if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) + #define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_A) + #define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_00) + #endif +#endif + + +/*********** TMRA_PULSE_ENCODER configure *********/ +#if defined(RT_USING_PULSE_ENCODER) + #if defined(BSP_USING_TMRA_PULSE_ENCODER) + #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) + #define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) + #define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08) + #define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4) + #define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) + #define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09) + #define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4) + #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ + #endif /* BSP_USING_TMRA_PULSE_ENCODER */ + + #if defined(BSP_USING_TMR6_PULSE_ENCODER) + #if defined(BSP_USING_PULSE_ENCODER_TMR6_1) + #define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B) + #define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_05) + #define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) + #define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B) + #define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_13) + #define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) + #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ + #endif /* BSP_USING_TMR6_PULSE_ENCODER */ +#endif /* RT_USING_PULSE_ENCODER */ + +#endif + diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/adc_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/adc_config.h new file mode 100644 index 00000000000..be6d4c6de34 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/adc_config.h @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __ADC_CONFIG_H__ +#define __ADC_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_ADC1 +#ifndef ADC1_INIT_PARAMS +#define ADC1_INIT_PARAMS \ + { \ + .name = "adc1", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_EVT0, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC1_INIT_PARAMS */ + +#if defined (BSP_ADC1_USING_DMA) +#ifndef ADC1_EOCA_DMA_CONFIG +#define ADC1_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC1_EOCA_DMA_INSTANCE, \ + .channel = ADC1_EOCA_DMA_CHANNEL, \ + .clock = ADC1_EOCA_DMA_CLOCK, \ + .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC1_EOCA, \ + .flag = ADC1_EOCA_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = ADC1_EOCA_DMA_IRQn, \ + .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ + .int_src = ADC1_EOCA_DMA_INT_SRC, \ + }, \ + } +#endif /* ADC1_EOCA_DMA_CONFIG */ +#endif /* BSP_ADC1_USING_DMA */ +#endif /* BSP_USING_ADC1 */ + +#ifdef BSP_USING_ADC2 +#ifndef ADC2_INIT_PARAMS +#define ADC2_INIT_PARAMS \ + { \ + .name = "adc2", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_EVT0, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC2_INIT_PARAMS */ + +#if defined (BSP_ADC2_USING_DMA) +#ifndef ADC2_EOCA_DMA_CONFIG +#define ADC2_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC2_EOCA_DMA_INSTANCE, \ + .channel = ADC2_EOCA_DMA_CHANNEL, \ + .clock = ADC2_EOCA_DMA_CLOCK, \ + .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC2_EOCA, \ + .flag = ADC2_EOCA_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = ADC2_EOCA_DMA_IRQn, \ + .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ + .int_src = ADC2_EOCA_DMA_INT_SRC, \ + }, \ + } +#endif /* ADC2_EOCA_DMA_CONFIG */ +#endif /* BSP_ADC2_USING_DMA */ +#endif /* BSP_USING_ADC2 */ + +#ifdef BSP_USING_ADC3 +#ifndef ADC3_INIT_PARAMS +#define ADC3_INIT_PARAMS \ + { \ + .name = "adc3", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_EVT0, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC3_INIT_PARAMS */ + +#if defined (BSP_ADC3_USING_DMA) +#ifndef ADC3_EOCA_DMA_CONFIG +#define ADC3_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC3_EOCA_DMA_INSTANCE, \ + .channel = ADC3_EOCA_DMA_CHANNEL, \ + .clock = ADC3_EOCA_DMA_CLOCK, \ + .trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC3_EOCA, \ + .flag = ADC3_EOCA_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = ADC3_EOCA_DMA_IRQn, \ + .irq_prio = ADC3_EOCA_DMA_INT_PRIO, \ + .int_src = ADC3_EOCA_DMA_INT_SRC, \ + }, \ + } +#endif /* ADC3_EOCA_DMA_CONFIG */ +#endif /* BSP_ADC3_USING_DMA */ +#endif /* BSP_USING_ADC3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/dac_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/dac_config.h new file mode 100644 index 00000000000..610e3f5b2e5 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/dac_config.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __DAC_CONFIG_H__ +#define __DAC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_DAC1 +#ifndef DAC1_INIT_PARAMS +#define DAC1_INIT_PARAMS \ + { \ + .name = "dac1", \ + .vref = 3300, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_data_src = DAC_DATA_SRC_DATAREG, \ + .ch2_data_src = DAC_DATA_SRC_DATAREG, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ + } +#endif /* DAC1_INIT_PARAMS */ +#endif /* BSP_USING_DAC1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/dma_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/dma_config.h new file mode 100644 index 00000000000..64bda151cc6 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/dma_config.h @@ -0,0 +1,191 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __DMA_CONFIG_H__ +#define __DMA_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* DMA1 ch0 */ +#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) +#define UART1_TX_DMA_INSTANCE CM_DMA +#define UART1_TX_DMA_CHANNEL DMA_CH0 +#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define UART1_TX_DMA_TRIG_SELECT AOS_DMA_0 +#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define UART1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define UART1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define UART1_TX_DMA_INT_SRC INT_SRC_DMA_TC0 + +#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#define SPI1_TX_DMA_INSTANCE CM_DMA +#define SPI1_TX_DMA_CHANNEL DMA_CH0 +#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA_0 +#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SPI1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA_TC0 +#endif + +/* DMA1 ch1 */ +#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) +#define UART1_RX_DMA_INSTANCE CM_DMA +#define UART1_RX_DMA_CHANNEL DMA_CH1 +#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define UART1_RX_DMA_TRIG_SELECT AOS_DMA_1 +#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define UART1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define UART1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define UART1_RX_DMA_INT_SRC INT_SRC_DMA_TC1 + +#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_RX_DMA_INSTANCE CM_DMA +#define SPI1_RX_DMA_CHANNEL DMA_CH1 +#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA_1 +#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SPI1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA_TC1 +#endif + +/* DMA1 ch2 */ +#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) +#define UART2_TX_DMA_INSTANCE CM_DMA +#define UART2_TX_DMA_CHANNEL DMA_CH2 +#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define UART2_TX_DMA_TRIG_SELECT AOS_DMA_2 +#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define UART2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define UART2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define UART2_TX_DMA_INT_SRC INT_SRC_DMA_TC2 + +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) +#define I2C1_TX_DMA_INSTANCE CM_DMA +#define I2C1_TX_DMA_CHANNEL DMA_CH2 +#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA_2 +#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define I2C1_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA_TC2 +#endif + +/* DMA1 ch3 */ +#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) +#define UART2_RX_DMA_INSTANCE CM_DMA +#define UART2_RX_DMA_CHANNEL DMA_CH3 +#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define UART2_RX_DMA_TRIG_SELECT AOS_DMA_3 +#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define UART2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define UART2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define UART2_RX_DMA_INT_SRC INT_SRC_DMA_TC3 + +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) +#define I2C1_RX_DMA_INSTANCE CM_DMA +#define I2C1_RX_DMA_CHANNEL DMA_CH3 +#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA_3 +#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define I2C1_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA_TC3 +#endif + +/* DMA1 ch4 */ +#if defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE) +#define UART3_TX_DMA_INSTANCE CM_DMA +#define UART3_TX_DMA_CHANNEL DMA_CH4 +#define UART3_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define UART3_TX_DMA_TRIG_SELECT AOS_DMA_4 +#define UART3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define UART3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define UART3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define UART3_TX_DMA_INT_SRC INT_SRC_DMA_TC4 + +#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE) +#define ADC1_EOCA_DMA_INSTANCE CM_DMA +#define ADC1_EOCA_DMA_CHANNEL DMA_CH4 +#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA_4 +#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA_TC4 +#endif + +/* DMA1 ch5 */ +#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) +#define UART3_RX_DMA_INSTANCE CM_DMA +#define UART3_RX_DMA_CHANNEL DMA_CH5 +#define UART3_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define UART3_RX_DMA_TRIG_SELECT AOS_DMA_5 +#define UART3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define UART3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define UART3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define UART3_RX_DMA_INT_SRC INT_SRC_DMA_TC5 + +#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE) +#define ADC2_EOCA_DMA_INSTANCE CM_DMA +#define ADC2_EOCA_DMA_CHANNEL DMA_CH5 +#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA_5 +#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA_TC5 +#endif + +/* DMA1 ch6 */ +#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE) +#define UART4_TX_DMA_INSTANCE CM_DMA +#define UART4_TX_DMA_CHANNEL DMA_CH6 +#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define UART4_TX_DMA_TRIG_SELECT AOS_DMA_6 +#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define UART4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM +#define UART4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO +#define UART4_TX_DMA_INT_SRC INT_SRC_DMA_TC6 + +#elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE) +#define ADC3_EOCA_DMA_INSTANCE CM_DMA +#define ADC3_EOCA_DMA_CHANNEL DMA_CH6 +#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA_6 +#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM +#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO +#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA_TC6 +#endif + +/* DMA1 ch7 */ +#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) +#define UART4_RX_DMA_INSTANCE CM_DMA +#define UART4_RX_DMA_CHANNEL DMA_CH7 +#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define UART4_RX_DMA_TRIG_SELECT AOS_DMA_7 +#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define UART4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM +#define UART4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO +#define UART4_RX_DMA_INT_SRC INT_SRC_DMA_TC7 +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DMA_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/gpio_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/gpio_config.h new file mode 100644 index 00000000000..a1238ffe9a6 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/gpio_config.h @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __GPIO_CONFIG_H__ +#define __GPIO_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(RT_USING_PIN) + +#ifndef EXTINT0_IRQ_CONFIG +#define EXTINT0_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT0_IRQ_NUM, \ + .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ0, \ + } +#endif /* EXTINT1_IRQ_CONFIG */ + +#ifndef EXTINT1_IRQ_CONFIG +#define EXTINT1_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT1_IRQ_NUM, \ + .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ1, \ + } +#endif /* EXTINT1_IRQ_CONFIG */ + +#ifndef EXTINT2_IRQ_CONFIG +#define EXTINT2_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT2_IRQ_NUM, \ + .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ2, \ + } +#endif /* EXTINT2_IRQ_CONFIG */ + +#ifndef EXTINT3_IRQ_CONFIG +#define EXTINT3_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT3_IRQ_NUM, \ + .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ3, \ + } +#endif /* EXTINT3_IRQ_CONFIG */ + +#ifndef EXTINT4_IRQ_CONFIG +#define EXTINT4_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT4_IRQ_NUM, \ + .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ4, \ + } +#endif /* EXTINT4_IRQ_CONFIG */ + +#ifndef EXTINT5_IRQ_CONFIG +#define EXTINT5_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT5_IRQ_NUM, \ + .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ5, \ + } +#endif /* EXTINT5_IRQ_CONFIG */ + +#ifndef EXTINT6_IRQ_CONFIG +#define EXTINT6_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT6_IRQ_NUM, \ + .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ6, \ + } +#endif /* EXTINT6_IRQ_CONFIG */ + +#ifndef EXTINT7_IRQ_CONFIG +#define EXTINT7_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT7_IRQ_NUM, \ + .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ7, \ + } +#endif /* EXTINT7_IRQ_CONFIG */ + +#ifndef EXTINT8_IRQ_CONFIG +#define EXTINT8_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT8_IRQ_NUM, \ + .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ8, \ + } +#endif /* EXTINT8_IRQ_CONFIG */ + +#ifndef EXTINT9_IRQ_CONFIG +#define EXTINT9_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT9_IRQ_NUM, \ + .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ9, \ + } +#endif /* EXTINT9_IRQ_CONFIG */ + +#ifndef EXTINT10_IRQ_CONFIG +#define EXTINT10_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT10_IRQ_NUM, \ + .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ10, \ + } +#endif /* EXTINT10_IRQ_CONFIG */ + +#ifndef EXTINT11_IRQ_CONFIG +#define EXTINT11_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT11_IRQ_NUM, \ + .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ11, \ + } +#endif /* EXTINT11_IRQ_CONFIG */ + +#ifndef EXTINT12_IRQ_CONFIG +#define EXTINT12_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT12_IRQ_NUM, \ + .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ12, \ + } +#endif /* EXTINT12_IRQ_CONFIG */ + +#ifndef EXTINT13_IRQ_CONFIG +#define EXTINT13_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT13_IRQ_NUM, \ + .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ13, \ + } +#endif /* EXTINT13_IRQ_CONFIG */ + +#ifndef EXTINT14_IRQ_CONFIG +#define EXTINT14_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT14_IRQ_NUM, \ + .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ14, \ + } +#endif /* EXTINT14_IRQ_CONFIG */ + +#ifndef EXTINT15_IRQ_CONFIG +#define EXTINT15_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT15_IRQ_NUM, \ + .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ15, \ + } +#endif /* EXTINT15_IRQ_CONFIG */ + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIO_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/i2c_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/i2c_config.h new file mode 100644 index 00000000000..de883143386 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/i2c_config.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_USING_I2C1) +#ifndef I2C1_CONFIG +#define I2C1_CONFIG \ + { \ + .name = "i2c1", \ + .Instance = CM_I2C, \ + .clock = FCG1_PERIPH_I2C, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C1_CONFIG */ +#endif + +#if defined(BSP_I2C1_USING_DMA) +#ifndef I2C1_TX_DMA_CONFIG +#define I2C1_TX_DMA_CONFIG \ + { \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .channel = I2C1_TX_DMA_CHANNEL, \ + .clock = I2C1_TX_DMA_CLOCK, \ + .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C_TEI, \ + .flag = I2C1_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C1_TX_DMA_IRQn, \ + .irq_prio = I2C1_TX_DMA_INT_PRIO, \ + .int_src = I2C1_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C1_TX_DMA_CONFIG */ + +#ifndef I2C1_RX_DMA_CONFIG +#define I2C1_RX_DMA_CONFIG \ + { \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + .clock = I2C1_RX_DMA_CLOCK, \ + .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C_RXI, \ + .flag = I2C1_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C1_RX_DMA_IRQn, \ + .irq_prio = I2C1_RX_DMA_INT_PRIO, \ + .int_src = I2C1_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/irq_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/irq_config.h new file mode 100644 index 00000000000..d9cf2d80ff6 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/irq_config.h @@ -0,0 +1,236 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __IRQ_CONFIG_H__ +#define __IRQ_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_EXTINT0_IRQ_NUM EXTINT_PORT_EIRQ0_IRQn +#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT1_IRQ_NUM EXTINT_PORT_EIRQ1_IRQn +#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT2_IRQ_NUM EXTINT_PORT_EIRQ2_IRQn +#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT3_IRQ_NUM EXTINT_PORT_EIRQ3_IRQn +#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT4_IRQ_NUM EXTINT_PORT_EIRQ4_IRQn +#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT5_IRQ_NUM EXTINT_PORT_EIRQ5_IRQn +#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT6_IRQ_NUM EXTINT_PORT_EIRQ6_IRQn +#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT7_IRQ_NUM EXTINT_PORT_EIRQ7_IRQn +#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT8_IRQ_NUM EXTINT_PORT_EIRQ8_IRQn +#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT9_IRQ_NUM EXTINT_PORT_EIRQ9_IRQn +#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT10_IRQ_NUM EXTINT_PORT_EIRQ10_IRQn +#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT11_IRQ_NUM EXTINT_PORT_EIRQ11_IRQn +#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT12_IRQ_NUM EXTINT_PORT_EIRQ12_IRQn +#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT13_IRQ_NUM EXTINT_PORT_EIRQ13_IRQn +#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT14_IRQ_NUM EXTINT_PORT_EIRQ14_IRQn +#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT15_IRQ_NUM EXTINT_PORT_EIRQ15_IRQn +#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* DMA1 ch0 */ +#define BSP_DMA1_CH0_IRQ_NUM INT000_IRQn +#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch1 */ +#define BSP_DMA1_CH1_IRQ_NUM INT001_IRQn +#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch2 */ +#define BSP_DMA1_CH2_IRQ_NUM INT002_IRQn +#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch3 */ +#define BSP_DMA1_CH3_IRQ_NUM INT003_IRQn +#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch4 */ +#define BSP_DMA1_CH4_IRQ_NUM INT004_IRQn +#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch5 */ +#define BSP_DMA1_CH5_IRQ_NUM INT005_IRQn +#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch6 */ +#define BSP_DMA1_CH6_IRQ_NUM INT006_IRQn +#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch7 */ +#define BSP_DMA1_CH7_IRQ_NUM INT007_IRQn +#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_USING_UART1) +#define BSP_UART1_IRQ_NUM USART1_IRQn +#define BSP_UART1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)) || \ + defined(RT_USING_SERIAL_V2) +#define BSP_UART1_TX_CPLT_IRQ_NUM USART1_TCI_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#define BSP_UART2_IRQ_NUM USART2_IRQn +#define BSP_UART2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)) || \ + defined(RT_USING_SERIAL_V2) +#define BSP_UART2_TX_CPLT_IRQ_NUM USART2_TCI_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#define BSP_UART3_IRQ_NUM USART3_IRQn +#define BSP_UART3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA)) || \ + defined(RT_USING_SERIAL_V2) +#define BSP_UART3_TX_CPLT_IRQ_NUM USART3_TCI_IRQn +#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#define BSP_UART4_IRQ_NUM USART4_IRQn +#define BSP_UART4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)) || \ + defined(RT_USING_SERIAL_V2) +#define BSP_UART4_TX_CPLT_IRQ_NUM USART4_TCI_IRQn +#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_SPI1) +#define BSP_SPI1_ERR_IRQ_NUM SPI1_IRQn +#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_SPI2) +#define BSP_SPI2_ERR_IRQ_NUM SPI2_IRQn +#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_SPI3) +#define BSP_SPI3_ERR_IRQ_NUM SPI3_IRQn +#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined (BSP_USING_QSPI) +#define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn +#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_QSPI */ + +#if defined(BSP_USING_TMRA_1) +#define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn +#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_1 */ + +#if defined(BSP_USING_TMRA_2) +#define BSP_USING_TMRA_2_IRQ_NUM TMRA_2_OVF_UDF_IRQn +#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_2 */ + +#if defined(BSP_USING_TMRA_3) +#define BSP_USING_TMRA_3_IRQ_NUM TMRA_3_OVF_UDF_IRQn +#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_3 */ + +#if defined(BSP_USING_TMRA_4) +#define BSP_USING_TMRA_4_IRQ_NUM TMRA_4_OVF_UDF_IRQn +#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_4 */ + +#if defined(BSP_USING_TMRA_5) +#define BSP_USING_TMRA_5_IRQ_NUM TMRA_5_OVF_UDF_IRQn +#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_5 */ + +#if defined(BSP_USING_MCAN1) +#define BSP_MCAN1_INT0_IRQ_NUM MCAN1_INT0_IRQn +#define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define BSP_MCAN1_INT1_IRQ_NUM MCAN1_INT1_IRQn +#define BSP_MCAN1_INT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_MCAN1 */ + +#if defined(BSP_USING_MCAN2) +#define BSP_MCAN2_INT0_IRQ_NUM MCAN2_INT0_IRQn +#define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#define BSP_MCAN2_INT1_IRQ_NUM MCAN2_INT1_IRQn +#define BSP_MCAN2_INT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_MCAN2 */ + +#if defined(RT_USING_ALARM) +#define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn +#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* RT_USING_ALARM */ + +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM TMRA_1_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM TMRA_1_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_2) +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM TMRA_2_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM TMRA_2_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_3) +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM TMRA_3_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM TMRA_3_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_4) +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM TMRA_4_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM TMRA_4_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_5) +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM TMRA_5_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM TMRA_5_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */ + +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM TMR6_1_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM TMR6_1_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_2) +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM TMR6_2_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM TMR6_2_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __IRQ_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/mcan_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/mcan_config.h new file mode 100644 index 00000000000..febd731d1d0 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/mcan_config.h @@ -0,0 +1,363 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __MCAN_CONFIG_H__ +#define __MCAN_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***********************************************************************************************/ +/***********************************************************************************************/ +/* The default configuration for MCANs. Users can modify the configurations based on the application. + For the message RAM: + 1. MCAN1 and MCAN2 share 2048 bytes message RAM + 2. User can modify the definitions of filter number, Rx FIFO number, Tx FIFO number. + 3. MCAN has two configurable Receive FIFOs, Rx FIFO0 and Rx FIFO1. There use Rx FIFO0 only by default. + If only one FIFO is needed, use Rx FIFO0. If Rx FIFO1 is needed, define it's macro between 1 and 64, + and pay attention the total size of meesage RAM that to be allocated. +*/ + +#ifdef RT_CAN_USING_CANFD +#define MCAN_FD_SEL MCAN_FD_ISO_FD_BRS +#define MCAN_TOTAL_FILTER_NUM (26U) +#define MCAN_STD_FILTER_NUM (13U) /* Each standard filter element size is 4 bytes */ +#define MCAN_EXT_FILTER_NUM (13U) /* Each extended filter element size is 8 bytes */ +#define MCAN_TX_FIFO_NUM (6U) +#define MCAN_RX_FIFO_NUM (6U) +#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_64BYTE) /* Each FIFO element size is 64+8 bytes */ +#else +#define MCAN_FD_SEL MCAN_FD_CLASSICAL +#define MCAN_TOTAL_FILTER_NUM (32U) +#define MCAN_STD_FILTER_NUM (16U) /* Each standard filter element size is 4 bytes */ +#define MCAN_EXT_FILTER_NUM (16U) /* Each extended filter element size is 8 bytes */ +#define MCAN_TX_FIFO_NUM (26U) +#define MCAN_RX_FIFO_NUM (26U) +#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_8BYTE) /* Each FIFO element size is 8+8 bytes */ +#endif + +#ifdef BSP_USING_MCAN1 +#define MCAN1_NAME ("mcan1") +#define MCAN1_WORK_MODE (RT_CAN_MODE_NORMAL) +#define MCAN1_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */ + +#define MCAN1_FD_SEL MCAN_FD_SEL + +#define MCAN1_STD_FILTER_NUM MCAN_STD_FILTER_NUM +#define MCAN1_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM + +#define MCAN1_RX_FIFO0_NUM MCAN_RX_FIFO_NUM +#define MCAN1_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE + +#define MCAN1_TX_FIFO_NUM MCAN_TX_FIFO_NUM +#define MCAN1_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE +#define MCAN1_TX_NOTIFICATION_BUF ((1UL << MCAN1_TX_FIFO_NUM) - 1U) +#endif /* BSP_USING_MCAN1 */ + +#ifdef BSP_USING_MCAN2 +#define MCAN2_NAME ("mcan2") +#define MCAN2_WORK_MODE (RT_CAN_MODE_NORMAL) +#define MCAN2_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */ + +#define MCAN2_FD_SEL MCAN_FD_SEL +#define MCAN2_STD_FILTER_NUM MCAN_STD_FILTER_NUM +#define MCAN2_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM + +#define MCAN2_RX_FIFO0_NUM MCAN_RX_FIFO_NUM +#define MCAN2_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE + +#define MCAN2_TX_FIFO_NUM MCAN_TX_FIFO_NUM +#define MCAN2_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE +#define MCAN2_TX_NOTIFICATION_BUF ((1UL << MCAN2_TX_FIFO_NUM) - 1U) +#endif /* BSP_USING_MCAN2 */ + +/***********************************************************************************************/ +/***********************************************************************************************/ + +/* + Bit rate configuration examples for CAN FD. + Nominal bit rate for CAN FD arbitration phase and data bit rate for CAN FD data phase. + BitRate(bps) = MCANClock(Hz) / (Prescaler * (TimeSeg1 + TimeSeg2)) + SamplePoint(%) = TimeSeg1 / (TimeSeg1 + TimeSeg2) + eg. + BitRate(bps) = 40000000(Hz) / (2 * (16 + 4)) = 1000000 = 1M(bps) + SamplePoint(%) = 16 / (16 + 4) = 80% + The following bit rate configurations are based on the max MCAN Clock(40MHz). + NOTE: + 1. It is better to limit u32NominalPrescaler and u32DataPrescaler between 1 and 2. + 1. The unit of u32SspOffset is MCANClock. + 2. For the corresponding function of u32TdcFilter, please refer to the reference manual for details(TDCR.TDCF). + The u32TdcFilter can be get from PSR.TDCV. +*/ +#define MCAN_FD_CFG_500K_1M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 64, \ + .u32NominalTimeSeg2 = 16, \ + .u32NominalSyncJumpWidth = 16, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 32, \ + .u32DataTimeSeg2 = 8, \ + .u32DataSyncJumpWidth = 8, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 32, \ + .u32TdcFilter = 32 + 1, \ + } + +#define MCAN_FD_CFG_500K_2M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 64, \ + .u32NominalTimeSeg2 = 16, \ + .u32NominalSyncJumpWidth = 16, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 16, \ + .u32DataTimeSeg2 = 4, \ + .u32DataSyncJumpWidth = 4, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 16, \ + .u32TdcFilter = 16 + 1, \ + } + +#define MCAN_FD_CFG_500K_4M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 64, \ + .u32NominalTimeSeg2 = 16, \ + .u32NominalSyncJumpWidth = 16, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 8, \ + .u32DataTimeSeg2 = 2, \ + .u32DataSyncJumpWidth = 2, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 8, \ + .u32TdcFilter = 8 + 1, \ + } + +#define MCAN_FD_CFG_500K_5M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 64, \ + .u32NominalTimeSeg2 = 16, \ + .u32NominalSyncJumpWidth = 16, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 6, \ + .u32DataTimeSeg2 = 2, \ + .u32DataSyncJumpWidth = 2, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 6, \ + .u32TdcFilter = 6 + 1, \ + } + +#define MCAN_FD_CFG_500K_8M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 64, \ + .u32NominalTimeSeg2 = 16, \ + .u32NominalSyncJumpWidth = 16, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 4, \ + .u32DataTimeSeg2 = 1, \ + .u32DataSyncJumpWidth = 1, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 4, \ + .u32TdcFilter = 4 + 1, \ + } + +#define MCAN_FD_CFG_1M_1M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 32, \ + .u32DataTimeSeg2 = 8, \ + .u32DataSyncJumpWidth = 8, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 2*32, \ + .u32TdcFilter = 2*32 + 1, \ + } + +#define MCAN_FD_CFG_1M_2M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 16, \ + .u32DataTimeSeg2 = 4, \ + .u32DataSyncJumpWidth = 4, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 16, \ + .u32TdcFilter = 16 + 1, \ + } + +#define MCAN_FD_CFG_1M_4M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 8, \ + .u32DataTimeSeg2 = 2, \ + .u32DataSyncJumpWidth = 2, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 8, \ + .u32TdcFilter = 8 + 1, \ + } + +#define MCAN_FD_CFG_1M_5M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 6, \ + .u32DataTimeSeg2 = 2, \ + .u32DataSyncJumpWidth = 2, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 6, \ + .u32TdcFilter = 6 + 1, \ + } + +#define MCAN_FD_CFG_1M_8M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 4, \ + .u32DataTimeSeg2 = 1, \ + .u32DataSyncJumpWidth = 1, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 4, \ + .u32TdcFilter = 4 + 1, \ + } + +/* + Bit rate configuration examples for classical CAN. + BitRate(bps) = MCANClock(Hz) / (u32NominalPrescaler * (u32NominalTimeSeg1 + u32NominalTimeSeg2)) + SamplePoint(%) = u32NominalTimeSeg1 / (u32NominalTimeSeg1 + u32NominalTimeSeg2) + eg. + BitRate(bps) = 40000000(Hz) / (2 * (16 + 4)) = 1000000 = 1M(bps) + SamplePoint(%) = 16 / (16 + 4) = 80% + The following bit rate configurations are based on the max MCAN Clock(40MHz). +*/ +#define MCAN_CC_CFG_1M \ + { \ + .u32NominalPrescaler = 2, \ + .u32NominalTimeSeg1 = 16, \ + .u32NominalTimeSeg2 = 4, \ + .u32NominalSyncJumpWidth = 4, \ + } + +#define MCAN_CC_CFG_800K \ + { \ + .u32NominalPrescaler = 2, \ + .u32NominalTimeSeg1 = 20, \ + .u32NominalTimeSeg2 = 5, \ + .u32NominalSyncJumpWidth = 5, \ + } + +#define MCAN_CC_CFG_500K \ + { \ + .u32NominalPrescaler = 4, \ + .u32NominalTimeSeg1 = 16, \ + .u32NominalTimeSeg2 = 4, \ + .u32NominalSyncJumpWidth = 4, \ + } + +#define MCAN_CC_CFG_250K \ + { \ + .u32NominalPrescaler = 4, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + } + +#define MCAN_CC_CFG_125K \ + { \ + .u32NominalPrescaler = 8, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + } + +#define MCAN_CC_CFG_100K \ + { \ + .u32NominalPrescaler = 10, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + } + +#define MCAN_CC_CFG_50K \ + { \ + .u32NominalPrescaler = 20, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + } + +#define MCAN_CC_CFG_20K \ + { \ + .u32NominalPrescaler = 50, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + } + +#define MCAN_CC_CFG_10K \ + { \ + .u32NominalPrescaler = 100, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + } + +#ifdef RT_CAN_USING_CANFD +#define MCAN1_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M +#define MCAN1_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M +#define MCAN1_DATA_BAUD_RATE CANFD_DATA_BAUD_4M + +#define MCAN2_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M +#define MCAN2_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M +#define MCAN2_DATA_BAUD_RATE CANFD_DATA_BAUD_4M + +#else +#define MCAN1_BAUD_RATE_CFG MCAN_CC_CFG_1M +#define MCAN1_NOMINAL_BAUD_RATE CAN1MBaud +#define MCAN1_DATA_BAUD_RATE 0 + +#define MCAN2_BAUD_RATE_CFG MCAN_CC_CFG_1M +#define MCAN2_NOMINAL_BAUD_RATE CAN1MBaud +#define MCAN2_DATA_BAUD_RATE 0 + +#endif /* #ifdef RT_CAN_USING_CANFD */ + +/***********************************************************************************************/ +/***********************************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* __MCAN_CONFIG_H__ */ + + diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/pm_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/pm_config.h new file mode 100644 index 00000000000..4d86a2aaee2 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/pm_config.h @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __PM_CONFIG_H__ +#define __PM_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PM +extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); + +#ifndef PM_TICKLESS_TIMER_ENABLE_MASK +#define PM_TICKLESS_TIMER_ENABLE_MASK \ +( (1UL << PM_SLEEP_MODE_IDLE) | \ + (1UL << PM_SLEEP_MODE_DEEP)) +#endif + +/** + * @brief run mode config @ref pm_run_mode_config structure + */ +#ifndef PM_RUN_MODE_CFG +#define PM_RUN_MODE_CFG \ + { \ + .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ + } +#endif /* PM_RUN_MODE_CFG */ + +/** + * @brief sleep idle config @ref pm_sleep_mode_idle_config structure + */ +#ifndef PM_SLEEP_IDLE_CFG +#define PM_SLEEP_IDLE_CFG \ +{ \ + .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ +} +#endif /*PM_SLEEP_IDLE_CFG*/ + +/** + * @brief sleep deep config @ref pm_sleep_mode_deep_config structure + */ +#ifndef PM_SLEEP_DEEP_CFG +#define PM_SLEEP_DEEP_CFG \ +{ \ + { \ + .u16Clock = PWC_STOP_CLK_KEEP, \ + .u8StopDrv = PWC_STOP_DRV_HIGH, \ + .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \ + .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ + }, \ + .pwc_stop_type = PWC_STOP_WFE_INT, \ +} +#endif /*PM_SLEEP_DEEP_CFG*/ + +/** + * @brief sleep standby config @ref pm_sleep_mode_standby_config structure + */ +#ifndef PM_SLEEP_STANDBY_CFG +#define PM_SLEEP_STANDBY_CFG \ +{ \ + { \ + .u8Mode = PWC_PD_MD1, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ +} +#endif /*PM_SLEEP_STANDBY_CFG*/ + +/** + * @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure + */ +#ifndef PM_SLEEP_SHUTDOWN_CFG +#define PM_SLEEP_SHUTDOWN_CFG \ +{ \ + { \ + .u8Mode = PWC_PD_MD3, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ +} +#endif /*PM_SLEEP_SHUTDOWN_CFG*/ + +#endif /* BSP_USING_PM */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PM_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/pulse_encoder_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/pulse_encoder_config.h new file mode 100644 index 00000000000..5fa7584534e --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/pulse_encoder_config.h @@ -0,0 +1,206 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __PULSE_ENCODER_CONFIG_H__ +#define __PULSE_ENCODER_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(RT_USING_PULSE_ENCODER) + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_1 +#ifndef PULSE_ENCODER_TMRA_1_CONFIG +#define PULSE_ENCODER_TMRA_1_CONFIG \ + { \ + .tmr_handler = CM_TMRA_1, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_1, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a1" \ + } +#endif /* PULSE_ENCODER_TMRA_1_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_2 +#ifndef PULSE_ENCODER_TMRA_2_CONFIG +#define PULSE_ENCODER_TMRA_2_CONFIG \ + { \ + .tmr_handler = CM_TMRA_2, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_2, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a2" \ + } +#endif /* PULSE_ENCODER_TMRA_2_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_3 +#ifndef PULSE_ENCODER_TMRA_3_CONFIG +#define PULSE_ENCODER_TMRA_3_CONFIG \ + { \ + .tmr_handler = CM_TMRA_3, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_3, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a3" \ + } +#endif /* PULSE_ENCODER_TMRA_3_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_4 +#ifndef PULSE_ENCODER_TMRA_4_CONFIG +#define PULSE_ENCODER_TMRA_4_CONFIG \ + { \ + .tmr_handler = CM_TMRA_4, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_4, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a4" \ + } +#endif /* PULSE_ENCODER_TMRA_4_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_5 +#ifndef PULSE_ENCODER_TMRA_5_CONFIG +#define PULSE_ENCODER_TMRA_5_CONFIG \ + { \ + .tmr_handler = CM_TMRA_5, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_5, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a5" \ + } +#endif /* PULSE_ENCODER_TMRA_5_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_1 +#ifndef PULSE_ENCODER_TMR6_1_CONFIG +#define PULSE_ENCODER_TMR6_1_CONFIG \ + { \ + .tmr_handler = CM_TMR6_1, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_1, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_61" \ + } +#endif /* PULSE_ENCODER_TMR6_1_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_2 +#ifndef PULSE_ENCODER_TMR6_2_CONFIG +#define PULSE_ENCODER_TMR6_2_CONFIG \ + { \ + .tmr_handler = CM_TMR6_2, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_2, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_62" \ + } +#endif /* PULSE_ENCODER_TMR6_2_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */ + +#endif /* RT_USING_PULSE_ENCODER */ + +#endif /* __PULSE_ENCODER_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/pwm_tmr_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/pwm_tmr_config.h new file mode 100644 index 00000000000..e432b5a83d0 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/pwm_tmr_config.h @@ -0,0 +1,663 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __PWM_TMR_CONFIG_H__ +#define __PWM_TMR_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PWM_TMRA + +#ifdef BSP_USING_PWM_TMRA_1 +#ifndef PWM_TMRA_1_CONFIG +#define PWM_TMRA_1_CONFIG \ + { \ + .name = "pwm_a1", \ + .instance = CM_TMRA_1, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_1_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_1 */ + +#ifdef BSP_USING_PWM_TMRA_2 +#ifndef PWM_TMRA_2_CONFIG +#define PWM_TMRA_2_CONFIG \ + { \ + .name = "pwm_a2", \ + .instance = CM_TMRA_2, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_2_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_2 */ + +#ifdef BSP_USING_PWM_TMRA_3 +#ifndef PWM_TMRA_3_CONFIG +#define PWM_TMRA_3_CONFIG \ + { \ + .name = "pwm_a3", \ + .instance = CM_TMRA_3, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_3_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_3 */ + +#ifdef BSP_USING_PWM_TMRA_4 +#ifndef PWM_TMRA_4_CONFIG +#define PWM_TMRA_4_CONFIG \ + { \ + .name = "pwm_a4", \ + .instance = CM_TMRA_4, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_4_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_4 */ + +#ifdef BSP_USING_PWM_TMRA_5 +#ifndef PWM_TMRA_5_CONFIG +#define PWM_TMRA_5_CONFIG \ + { \ + .name = "pwm_a5", \ + .instance = CM_TMRA_5, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_5_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_5 */ +#endif /* BSP_USING_PWM_TMRA */ + +#ifdef BSP_USING_PWM_TMR4 + +#ifdef BSP_USING_PWM_TMR4_1 +#ifndef PWM_TMR4_1_CONFIG +#define PWM_TMR4_1_CONFIG \ + { \ + .name = "pwm_t41", \ + .instance = CM_TMR4_1, \ + .channel = 0, \ + .stcTmr4Init = \ + { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ + }, \ + .stcTmr4OcInit = \ + { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = \ + { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ + }, \ + } +#endif /* PWM_TMR4_1_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_1 */ + +#ifdef BSP_USING_PWM_TMR4_2 +#ifndef PWM_TMR4_2_CONFIG +#define PWM_TMR4_2_CONFIG \ + { \ + .name = "pwm_t42", \ + .instance = CM_TMR4_2, \ + .channel = 0, \ + .stcTmr4Init = \ + { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ + }, \ + .stcTmr4OcInit = \ + { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = \ + { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ + }, \ + } +#endif /* PWM_TMR4_2_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_2 */ + +#ifdef BSP_USING_PWM_TMR4_3 +#ifndef PWM_TMR4_3_CONFIG +#define PWM_TMR4_3_CONFIG \ + { \ + .name = "pwm_t43", \ + .instance = CM_TMR4_3, \ + .channel = 0, \ + .stcTmr4Init = \ + { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ + }, \ + .stcTmr4OcInit = \ + { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = \ + { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ + }, \ + } +#endif /* PWM_TMR4_3_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_3 */ + +#endif /* BSP_USING_PWM_TMR4 */ + +#ifdef BSP_USING_PWM_TMR6 + +#ifdef BSP_USING_PWM_TMR6_1 +#ifndef PWM_TMR6_1_CONFIG +#define PWM_TMR6_1_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_1, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } \ + }, \ + } +#endif /* PWM_TMR6_1_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_1 */ +#ifdef BSP_USING_PWM_TMR6_2 +#ifndef PWM_TMR6_2_CONFIG +#define PWM_TMR6_2_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_2, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } \ + }, \ + } +#endif /* PWM_TMR6_2_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_2 */ +#ifdef BSP_USING_PWM_TMR6_3 +#ifndef PWM_TMR6_3_CONFIG +#define PWM_TMR6_3_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_3, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } \ + }, \ + } +#endif /* PWM_TMR6_3_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_3 */ +#ifdef BSP_USING_PWM_TMR6_4 +#ifndef PWM_TMR6_4_CONFIG +#define PWM_TMR6_4_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_4, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } \ + }, \ + } +#endif /* PWM_TMR6_4_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_4 */ +#ifdef BSP_USING_PWM_TMR6_5 +#ifndef PWM_TMR6_5_CONFIG +#define PWM_TMR6_5_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_5, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } \ + }, \ + } +#endif /* PWM_TMR6_5_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_5 */ +#ifdef BSP_USING_PWM_TMR6_6 +#ifndef PWM_TMR6_6_CONFIG +#define PWM_TMR6_6_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_6, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } \ + }, \ + } +#endif /* PWM_TMR6_6_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_6 */ +#ifdef BSP_USING_PWM_TMR6_7 +#ifndef PWM_TMR6_7_CONFIG +#define PWM_TMR6_7_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_7, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } \ + }, \ + } +#endif /* PWM_TMR6_7_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_7 */ +#ifdef BSP_USING_PWM_TMR6_8 +#ifndef PWM_TMR6_8_CONFIG +#define PWM_TMR6_8_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_8, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } \ + }, \ + } +#endif /* PWM_TMR6_8_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_8 */ + +#endif /* BSP_USING_PWM_TMR6 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PWM_TMRA_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/spi_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/spi_config.h new file mode 100644 index 00000000000..9789abe9dfb --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/spi_config.h @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __SPI_CONFIG_H__ +#define __SPI_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef BSP_USING_SPI1 +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = CM_SPI, \ + .bus_name = "spi1", \ + .clock = FCG1_PERIPH_SPI, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI_SPEI, \ + }, \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .clock = SPI1_TX_DMA_CLOCK, \ + .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI_SPTI, \ + .flag = SPI1_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI1_TX_DMA_IRQn, \ + .irq_prio = SPI1_TX_DMA_INT_PRIO, \ + .int_src = SPI1_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ + +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .clock = SPI1_RX_DMA_CLOCK, \ + .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI_SPRI, \ + .flag = SPI1_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI1_RX_DMA_IRQn, \ + .irq_prio = SPI1_RX_DMA_INT_PRIO, \ + .int_src = SPI1_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SPI_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/timer_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/timer_config.h new file mode 100644 index 00000000000..44d3362b803 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/timer_config.h @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __TMR_CONFIG_H__ +#define __TMR_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_TMRA_1 +#ifndef TMRA_1_CONFIG +#define TMRA_1_CONFIG \ + { \ + .tmr_handle = CM_TMRA_1, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_1, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_1_OVF, \ + .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ + }, \ + .name = "tmra_1" \ + } +#endif /* TMRA_1_CONFIG */ +#endif /* BSP_USING_TMRA_1 */ + +#ifdef BSP_USING_TMRA_2 +#ifndef TMRA_2_CONFIG +#define TMRA_2_CONFIG \ + { \ + .tmr_handle = CM_TMRA_2, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_2, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_2_OVF, \ + .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ + }, \ + .name = "tmra_2" \ + } +#endif /* TMRA_2_CONFIG */ +#endif /* BSP_USING_TMRA_2 */ + +#ifdef BSP_USING_TMRA_3 +#ifndef TMRA_3_CONFIG +#define TMRA_3_CONFIG \ + { \ + .tmr_handle = CM_TMRA_3, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_3, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_3_OVF, \ + .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ + }, \ + .name = "tmra_3" \ + } +#endif /* TMRA_3_CONFIG */ +#endif /* BSP_USING_TMRA_3 */ + +#ifdef BSP_USING_TMRA_4 +#ifndef TMRA_4_CONFIG +#define TMRA_4_CONFIG \ + { \ + .tmr_handle = CM_TMRA_4, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_4, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_4_OVF, \ + .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ + }, \ + .name = "tmra_4" \ + } +#endif /* TMRA_4_CONFIG */ +#endif /* BSP_USING_TMRA_4 */ + +#ifdef BSP_USING_TMRA_5 +#ifndef TMRA_5_CONFIG +#define TMRA_5_CONFIG \ + { \ + .tmr_handle = CM_TMRA_5, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_5, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_5_OVF, \ + .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ + }, \ + .name = "tmra_5" \ + } +#endif /* TMRA_5_CONFIG */ +#endif /* BSP_USING_TMRA_5 */ +#endif /* __TMR_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/tmr_capture_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/tmr_capture_config.h new file mode 100644 index 00000000000..65d4d8eed54 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/tmr_capture_config.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-01-10 CDT first version + */ + +#ifndef __IC_CONFIG_H__ +#define __IC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) +#define IC1_NAME "ic1" +#define INPUT_CAPTURE_CFG_TMR6_1 \ +{ \ + .name = IC1_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \ +} +#endif + +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) +#define IC2_NAME "ic2" +#define INPUT_CAPTURE_CFG_TMR6_2 \ +{ \ + .name = IC2_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_TRIGB_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \ +} +#endif + +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3) +#define IC3_NAME "ic3" +#define INPUT_CAPTURE_CFG_TMR6_3 \ +{ \ + .name = IC3_NAME, \ + .ch = TMR6_CH_B, \ + .clk_div = TMR6_CLK_DIV16, \ + .first_edge = TMR6_CAPT_COND_TRIGC_FALLING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \ +} +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __IC_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/uart_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/uart_config.h new file mode 100644 index 00000000000..13b166e9431 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/uart_config.h @@ -0,0 +1,390 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = CM_USART1, \ + .clock = FCG3_PERIPH_USART1, \ + .irq_num = BSP_UART1_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART1_EI, \ + .rx_int_src = INT_SRC_USART1_RI, \ + .tx_int_src = INT_SRC_USART1_TI, \ + } +#endif /* UART1_CONFIG */ + +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_RX_CONFIG +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .clock = UART1_RX_DMA_CLOCK, \ + .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_RI, \ + .flag = UART1_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART1_RX_DMA_IRQn, \ + .irq_prio = UART1_RX_DMA_INT_PRIO, \ + .int_src = UART1_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART1_DMA_RX_CONFIG */ + +#ifndef UART1_RXTO_CONFIG +#define UART1_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + } +#endif /* UART1_RXTO_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_CPLT_CONFIG +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART1_TX_CPLT_CONFIG +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ + } +#endif +#endif /* UART1_TX_CPLT_CONFIG */ + +#if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_DMA_TX_CONFIG +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .channel = UART1_TX_DMA_CHANNEL, \ + .clock = UART1_TX_DMA_CLOCK, \ + .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART1_TX_DMA_IRQn, \ + .irq_prio = UART1_TX_DMA_INT_PRIO, \ + .int_src = UART1_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART1_DMA_TX_CONFIG */ +#endif /* BSP_UART1_TX_USING_DMA */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = CM_USART2, \ + .clock = FCG3_PERIPH_USART2, \ + .irq_num = BSP_UART2_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART2_EI, \ + .rx_int_src = INT_SRC_USART2_RI, \ + .tx_int_src = INT_SRC_USART2_TI, \ + } +#endif /* UART2_CONFIG */ + +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_RX_CONFIG +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .channel = UART2_RX_DMA_CHANNEL, \ + .clock = UART2_RX_DMA_CLOCK, \ + .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_RI, \ + .flag = UART2_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART2_RX_DMA_IRQn, \ + .irq_prio = UART2_RX_DMA_INT_PRIO, \ + .int_src = UART2_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART2_DMA_RX_CONFIG */ + +#ifndef UART2_RXTO_CONFIG +#define UART2_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + } +#endif /* UART2_RXTO_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_CPLT_CONFIG +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART2_TX_CPLT_CONFIG +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ + } +#endif +#endif /* UART2_TX_CPLT_CONFIG */ + +#if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_DMA_TX_CONFIG +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .channel = UART2_TX_DMA_CHANNEL, \ + .clock = UART2_TX_DMA_CLOCK, \ + .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_TI, \ + .flag = UART2_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART2_TX_DMA_IRQn, \ + .irq_prio = UART2_TX_DMA_INT_PRIO, \ + .int_src = UART2_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART2_DMA_TX_CONFIG */ +#endif /* BSP_UART2_TX_USING_DMA */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = CM_USART3, \ + .clock = FCG3_PERIPH_USART3, \ + .irq_num = BSP_UART3_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART3_EI, \ + .rx_int_src = INT_SRC_USART3_RI, \ + .tx_int_src = INT_SRC_USART3_TI, \ + } +#endif /* UART3_CONFIG */ + +#if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_DMA_RX_CONFIG +#define UART3_DMA_RX_CONFIG \ + { \ + .Instance = UART3_RX_DMA_INSTANCE, \ + .channel = UART3_RX_DMA_CHANNEL, \ + .clock = UART3_RX_DMA_CLOCK, \ + .trigger_select = UART3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART3_RI, \ + .flag = UART3_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART3_RX_DMA_IRQn, \ + .irq_prio = UART3_RX_DMA_INT_PRIO, \ + .int_src = UART3_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART3_DMA_RX_CONFIG */ + +#ifndef UART3_RXTO_CONFIG +#define UART3_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + } +#endif /* UART3_RXTO_CONFIG */ +#endif /* BSP_UART3_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA) +#ifndef UART3_TX_CPLT_CONFIG +#define UART3_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART3_TX_CPLT_CONFIG +#define UART3_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TCI, \ + }, \ + } +#endif +#endif /* UART3_TX_CPLT_CONFIG */ + +#if defined(BSP_UART3_TX_USING_DMA) +#ifndef UART3_DMA_TX_CONFIG +#define UART3_DMA_TX_CONFIG \ + { \ + .Instance = UART3_TX_DMA_INSTANCE, \ + .channel = UART3_TX_DMA_CHANNEL, \ + .clock = UART3_TX_DMA_CLOCK, \ + .trigger_select = UART3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART3_TI, \ + .flag = UART3_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART3_TX_DMA_IRQn, \ + .irq_prio = UART3_TX_DMA_INT_PRIO, \ + .int_src = UART3_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART3_DMA_TX_CONFIG */ +#endif /* BSP_UART3_TX_USING_DMA */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = CM_USART4, \ + .clock = FCG3_PERIPH_USART4, \ + .irq_num = BSP_UART4_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART4_EI, \ + .rx_int_src = INT_SRC_USART4_RI, \ + .tx_int_src = INT_SRC_USART4_TI, \ + } +#endif /* UART4_CONFIG */ + +#if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_DMA_RX_CONFIG +#define UART4_DMA_RX_CONFIG \ + { \ + .Instance = UART4_RX_DMA_INSTANCE, \ + .channel = UART4_RX_DMA_CHANNEL, \ + .clock = UART4_RX_DMA_CLOCK, \ + .trigger_select = UART4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART4_RI, \ + .flag = UART4_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART4_RX_DMA_IRQn, \ + .irq_prio = UART4_RX_DMA_INT_PRIO, \ + .int_src = UART4_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART4_DMA_RX_CONFIG */ + +#ifndef UART4_RXTO_CONFIG +#define UART4_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + } +#endif /* UART4_RXTO_CONFIG */ +#endif /* BSP_UART4_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA) +#ifndef UART4_TX_CPLT_CONFIG +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART4_TX_CPLT_CONFIG +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ + } +#endif +#endif /* UART4_TX_CPLT_CONFIG */ + +#if defined(BSP_UART4_TX_USING_DMA) +#ifndef UART4_DMA_TX_CONFIG +#define UART4_DMA_TX_CONFIG \ + { \ + .Instance = UART4_TX_DMA_INSTANCE, \ + .channel = UART4_TX_DMA_CHANNEL, \ + .clock = UART4_TX_DMA_CLOCK, \ + .trigger_select = UART4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART4_TI, \ + .flag = UART4_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART4_TX_DMA_IRQn, \ + .irq_prio = UART4_TX_DMA_INT_PRIO, \ + .int_src = UART4_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART4_DMA_TX_CONFIG */ +#endif /* BSP_UART4_TX_USING_DMA */ +#endif /* BSP_USING_UART4 */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/drv_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/drv_config.h new file mode 100644 index 00000000000..c9161d4b3ab --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/drv_config.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __DRV_CONFIG_H__ +#define __DRV_CONFIG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dma_config.h" +#include "uart_config.h" +#include "spi_config.h" +#include "adc_config.h" +#include "dac_config.h" +#include "gpio_config.h" +#include "mcan_config.h" +#include "pm_config.h" +#include "i2c_config.h" +#include "pulse_encoder_config.h" +#include "timer_config.h" +#include "tmr_capture_config.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/hc32f3xx_conf.h b/bsp/hc32/ev_hc32f334_lqfp64/board/hc32f3xx_conf.h new file mode 100644 index 00000000000..c6927993ad7 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/hc32f3xx_conf.h @@ -0,0 +1,127 @@ +/** + ******************************************************************************* + * @file template/source/hc32f3xx_conf.h + * @brief This file contains HC32 Series Device Driver Library usage management. + @verbatim + Change Logs: + Date Author Notes + 2024-01-15 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F3XX_CONF_H__ +#define __HC32F3XX_CONF_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @brief This is the list of modules to be used in the Device Driver Library. + * Select the modules you need to use to DDL_ON. + * @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works + * properly. + * @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver + * Library. + * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. + */ +#define LL_ICG_ENABLE (DDL_ON) +#define LL_UTILITY_ENABLE (DDL_ON) +#define LL_PRINT_ENABLE (DDL_OFF) + +#define LL_ADC_ENABLE (DDL_ON) +#define LL_AOS_ENABLE (DDL_ON) +#define LL_CLK_ENABLE (DDL_ON) +#define LL_CMP_ENABLE (DDL_ON) +#define LL_CRC_ENABLE (DDL_ON) +#define LL_CTC_ENABLE (DDL_ON) +#define LL_DAC_ENABLE (DDL_ON) +#define LL_DBGC_ENABLE (DDL_OFF) +#define LL_DMA_ENABLE (DDL_ON) +#define LL_EFM_ENABLE (DDL_ON) +#define LL_EMB_ENABLE (DDL_ON) +#define LL_EVENT_PORT_ENABLE (DDL_OFF) +#define LL_FCG_ENABLE (DDL_ON) +#define LL_FCM_ENABLE (DDL_ON) +#define LL_HRPWM_ENABLE (DDL_ON) +#define LL_GPIO_ENABLE (DDL_ON) +#define LL_I2C_ENABLE (DDL_ON) +#define LL_INTERRUPTS_ENABLE (DDL_ON) +#define LL_MCAN_ENABLE (DDL_ON) +#define LL_MPU_ENABLE (DDL_ON) +#define LL_PLA_ENABLE (DDL_ON) +#define LL_PWC_ENABLE (DDL_ON) +#define LL_RMU_ENABLE (DDL_ON) +#define LL_RTC_ENABLE (DDL_ON) +#define LL_SPI_ENABLE (DDL_ON) +#define LL_SRAM_ENABLE (DDL_ON) +#define LL_SWDT_ENABLE (DDL_ON) +#define LL_TMR0_ENABLE (DDL_ON) +#define LL_TMR4_ENABLE (DDL_ON) +#define LL_TMR6_ENABLE (DDL_ON) +#define LL_TMRA_ENABLE (DDL_ON) +#define LL_USART_ENABLE (DDL_ON) +#define LL_WDT_ENABLE (DDL_ON) + +/** + * @brief The following is a list of currently supported BSP boards. + */ +#define BSP_EV_HC32F334_LQFP64 (1U) + +/** + * @brief The macro BSP_EV_HC32F3XX is used to specify the BSP board currently + * in use. + * The value should be set to one of the list of currently supported BSP boards. + * @note If there is no supported BSP board or the BSP function is not used, + * the value needs to be set to 0U. + */ +#define BSP_EV_HC32F3XX (0U) + +/** + * @brief This is the list of BSP components to be used. + * Select the components you need to use to DDL_ON. + */ +#define BSP_24CXX_ENABLE (DDL_OFF) +#define BSP_W25QXX_ENABLE (DDL_OFF) +#define BSP_INT_KEY_ENABLE (DDL_OFF) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F3XX_CONF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/linker_scripts/link.icf b/bsp/hc32/ev_hc32f334_lqfp64/board/linker_scripts/link.icf new file mode 100644 index 00000000000..6279dc54ae1 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/linker_scripts/link.icf @@ -0,0 +1,111 @@ +/***************************************************************************//** + * \file HC32F334.icf + * \version 1.0 + * + * \brief Linker file for the IAR compiler. + * +******************************************************************************** +* \copyright + * Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause +*******************************************************************************/ +/*###ICF### Section handled by ICF editor, don't touch! *****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ + +// Check that necessary symbols have been passed to linker via command line interface +if((!isdefinedsymbol(_LINK_RAM_)) && (!isdefinedsymbol(_LINK_FLASH_))) { + error "Link location not defined or not supported!"; +} +if((!isdefinedsymbol(_HC32F334_128K_)) && (!isdefinedsymbol(_HC32F334_64K_))) { + error "Mcu type or size not defined or not supported!"; +} + +/******************************************************************************* + * Memory address and size definitions + ******************************************************************************/ +define symbol ram1_base_address = 0x1FFFC000; +define symbol ram1_end_address = 0x20003FFF; + +if(isdefinedsymbol(_LINK_RAM_)) { + define symbol ram_start_reserve = 0x4000; + define symbol rom1_base_address = ram1_base_address; + define symbol rom1_end_address = rom1_base_address + ram_start_reserve - 0x01; + define symbol rom2_base_address = 0x0; + define symbol rom2_end_address = 0x0; + define symbol rom3_base_address = 0x0; + define symbol rom3_end_address = 0x0; +} else { + define symbol ram_start_reserve = 0x0; + define symbol rom1_base_address = 0x0; + define symbol rom3_base_address = 0x03000C00; + define symbol rom3_end_address = 0x03000FFF; + if(isdefinedsymbol(_HC32F334_128K_)) { + define symbol rom1_end_address = 0x0001FFFF; + define symbol rom2_base_address = 0x0; + define symbol rom2_end_address = 0x0; + } else if (isdefinedsymbol(_HC32F334_64K_)) { + define symbol rom1_end_address = 0x0000FFFF; + define symbol rom2_base_address = 0x0; + define symbol rom2_end_address = 0x0; + } +} + +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = rom1_base_address; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = rom1_base_address; +define symbol __ICFEDIT_region_IROM1_end__ = rom1_end_address; +define symbol __ICFEDIT_region_IROM2_start__ = rom2_base_address; +define symbol __ICFEDIT_region_IROM2_end__ = rom2_end_address; +define symbol __ICFEDIT_region_IROM3_start__ = rom3_base_address; +define symbol __ICFEDIT_region_IROM3_end__ = rom3_end_address; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = ram1_base_address + ram_start_reserve; +define symbol __ICFEDIT_region_IRAM1_end__ = ram1_end_address; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x1000; +/**** End of ICF editor section. ###ICF###*/ + +/******************************************************************************* + * Memory definitions + ******************************************************************************/ +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region OTP_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in OTP_region { readonly section .otp_data }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/linker_scripts/link.ld b/bsp/hc32/ev_hc32f334_lqfp64/board/linker_scripts/link.ld new file mode 100644 index 00000000000..de56096145b --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/linker_scripts/link.ld @@ -0,0 +1,288 @@ +/****************************************************************************** + * Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + */ +/*****************************************************************************/ +/* File HC32F334xA.ld */ +/* Abstract Linker script for HC32F334 Device with */ +/* 128KByte FLASH, 68KByte RAM */ +/* Version V1.0 */ +/* Date 2024-01-15 */ +/*****************************************************************************/ +/* OTP section(not flash multiplexed region) implementation. + You need to pay attention to the size of the specified OTP block. + Take two OTP blocks for example. */ +__OTP_DATA_BASE = 0x03000C00; +__OTP_LOCK_BASE = 0x03000A80; +/* OTP block 1 */ +__OTP_DATA_B1_START = 0x03000C00; +__OTP_LOCK_B1_START = 0x03000AC0; +__OTP_DATA_B1_OFFSET = __OTP_DATA_B1_START - __OTP_DATA_BASE; +__OTP_LOCK_B1_OFFSET = __OTP_LOCK_B1_START - __OTP_LOCK_BASE; +/* OTP block 2 */ +__OTP_DATA_B2_START = 0x03000C40; +__OTP_LOCK_B2_START = 0x03000AC4; +__OTP_DATA_B2_OFFSET = __OTP_DATA_B2_START - __OTP_DATA_BASE; +__OTP_LOCK_B2_OFFSET = __OTP_LOCK_B2_START - __OTP_LOCK_BASE; + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 128K + OTP_DATA (rx): ORIGIN = 0x03000C00, LENGTH = 1K + OTP_LOCK (rx): ORIGIN = 0x03000A80, LENGTH = 68 + RAM (rwx): ORIGIN = 0x1FFFC000, LENGTH = 32K + RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_data : + { + . = ALIGN(4); + . = ORIGIN(OTP_DATA) + __OTP_DATA_B1_OFFSET; + KEEP(*(.otp_b1_data*)) + . = ORIGIN(OTP_DATA) + __OTP_DATA_B2_OFFSET; + KEEP(*(.otp_b2_data*)) + . = ALIGN(4); + } >OTP_DATA + + .otp_lock : + { + . = ALIGN(4); + . = ORIGIN(OTP_LOCK) + __OTP_LOCK_B1_OFFSET; + KEEP(*(.otp_b1_lock*)) + . = ORIGIN(OTP_LOCK) + __OTP_LOCK_B2_OFFSET; + KEEP(*(.otp_b2_lock*)) + . = ALIGN(4); + } >OTP_LOCK + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + *(.gnu.linkonce.d*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4); + .ramb_data : AT (__etext_ramb) + { + . = ALIGN(4); + __data_start_ramb__ = .; + *(.ramb_data) + *(.ramb_data*) + . = ALIGN(4); + __data_end_ramb__ = .; + } >RAMB + + __bss_start = .; + .bss __StackTop (NOLOAD): + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + . = ALIGN(4); + *(.noinit*) + . = ALIGN(4); + } >RAM + __bss_end = .; + + .ramb_bss : + { + . = ALIGN(4); + __bss_start_ramb__ = .; + *(.ramb_bss) + *(.ramb_bss*) + . = ALIGN(4); + __bss_end_ramb__ = .; + } >RAMB + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/linker_scripts/link.sct b/bsp/hc32/ev_hc32f334_lqfp64/board/linker_scripts/link.sct new file mode 100644 index 00000000000..f49a077b4a1 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/linker_scripts/link.sct @@ -0,0 +1,22 @@ +; **************************************************************** +; Scatter-Loading Description File +; **************************************************************** +LR_IROM1 0x00000000 0x0001FFFF { ; load region size_region + ER_IROM1 0x00000000 0x0001FFFF { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x1FFFC000 UNINIT 0x00000008 { ; RW data + *(.bss.noinit) + } + RW_IRAM2 0x1FFFC008 0x00007FF8 { ; RW data + .ANY (+RW +ZI) + .ANY (RAMCODE) + } + RW_IRAMB 0x200F0000 0x00001000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/ports/fal_cfg.h b/bsp/hc32/ev_hc32f334_lqfp64/board/ports/fal_cfg.h new file mode 100644 index 00000000000..e0071375474 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/ports/fal_cfg.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +/* enable hc32f3 onchip flash driver sample */ +#define FAL_FLASH_PORT_DRIVER_HC32F3 +/* enable SFUD flash driver sample */ +#define FAL_FLASH_PORT_DRIVER_SFUD + +extern const struct fal_flash_dev hc32_onchip_flash; +extern struct fal_flash_dev ext_nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &hc32_onchip_flash, \ + &ext_nor_flash0, \ +} + +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 128 * 1024, 0}, \ + {FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/figures/board.png b/bsp/hc32/ev_hc32f334_lqfp64/figures/board.png new file mode 100644 index 00000000000..f1c984dbd15 Binary files /dev/null and b/bsp/hc32/ev_hc32f334_lqfp64/figures/board.png differ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/jlink/ev_hc32f334_lqfp64 Debug.launch b/bsp/hc32/ev_hc32f334_lqfp64/jlink/ev_hc32f334_lqfp64 Debug.launch new file mode 100644 index 00000000000..01af1be1a46 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/jlink/ev_hc32f334_lqfp64 Debug.launch @@ -0,0 +1,84 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f334_lqfp64/project.ewd b/bsp/hc32/ev_hc32f334_lqfp64/project.ewd new file mode 100644 index 00000000000..5bbf370b92b --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/project.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 0 + + C-SPY + 2 + + 32 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 32 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFFC000 -FC4000 -FN2 -FF0HC32F334_128K -FS00 -FL020000 -FP0($$Device:HC32F334KATI$FlashARM\HC32F334_128K.FLM) -FF1HC32F334_otp -FS13000000 -FL11800 -FP1($$Device:HC32F334KATI$FlashARM\HC32F334_otp.FLM) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32/ev_hc32f334_lqfp64/project.uvprojx b/bsp/hc32/ev_hc32f334_lqfp64/project.uvprojx new file mode 100644 index 00000000000..5e7b085e349 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/project.uvprojx @@ -0,0 +1,1368 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
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..\libraries\hc32_drivers\drv_soft_i2c.c + + + + + drv_usart.c + 1 + ..\libraries\hc32_drivers\drv_usart.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + msh_parse.c + 1 + ..\..\..\components\finsh\msh_parse.c + + + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + HC32F334-LL + + + hc32_ll_efm.c + 1 + packages\hc32-f3-series-latest\hc32f334\src\hc32_ll_efm.c + + + + + hc32_ll_interrupts.c + 1 + packages\hc32-f3-series-latest\hc32f334\src\hc32_ll_interrupts.c + + + + + hc32_ll_gpio.c + 1 + packages\hc32-f3-series-latest\hc32f334\src\hc32_ll_gpio.c + + + + + hc32_ll_aos.c + 1 + packages\hc32-f3-series-latest\hc32f334\src\hc32_ll_aos.c + + + + + hc32_ll_fcg.c + 1 + packages\hc32-f3-series-latest\hc32f334\src\hc32_ll_fcg.c + + + + + hc32_ll_sram.c + 1 + packages\hc32-f3-series-latest\hc32f334\src\hc32_ll_sram.c + + + + + hc32_ll_tmr0.c + 1 + packages\hc32-f3-series-latest\hc32f334\src\hc32_ll_tmr0.c + + + + + hc32_ll.c + 1 + packages\hc32-f3-series-latest\hc32f334\src\hc32_ll.c + + + + + hc32_ll_utility.c + 1 + packages\hc32-f3-series-latest\hc32f334\src\hc32_ll_utility.c + + + + + hc32_ll_dma.c + 1 + packages\hc32-f3-series-latest\hc32f334\src\hc32_ll_dma.c + + + + + hc32_ll_i2c.c + 1 + packages\hc32-f3-series-latest\hc32f334\src\hc32_ll_i2c.c + + + + + hc32_ll_clk.c + 1 + packages\hc32-f3-series-latest\hc32f334\src\hc32_ll_clk.c + + + + + hc32_ll_rmu.c + 1 + packages\hc32-f3-series-latest\hc32f334\src\hc32_ll_rmu.c + + + + + hc32_ll_usart.c + 1 + packages\hc32-f3-series-latest\hc32f334\src\hc32_ll_usart.c + + + + + hc32_ll_icg.c + 1 + packages\hc32-f3-series-latest\hc32f334\src\hc32_ll_icg.c + + + + + hc32_ll_pwc.c + 1 + packages\hc32-f3-series-latest\hc32f334\src\hc32_ll_pwc.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + cpu_up.c + 1 + ..\..\..\src\cpu_up.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + defunct.c + 1 + ..\..\..\src\defunct.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + scheduler_comm.c + 1 + ..\..\..\src\scheduler_comm.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + scheduler_up.c + 1 + ..\..\..\src\scheduler_up.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + klibc + + + kstring.c + 1 + ..\..\..\src\klibc\kstring.c + + + + + kstdio.c + 1 + ..\..\..\src\klibc\kstdio.c + + + + + kerrno.c + 1 + ..\..\..\src\klibc\kerrno.c + + + + + rt_vsnprintf_tiny.c + 1 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + + + rt_vsscanf.c + 1 + ..\..\..\src\klibc\rt_vsscanf.c + + + + + libcpu + + + atomic_arm.c + 1 + ..\..\..\libcpu\arm\common\atomic_arm.c + + + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + Libraries + + + system_hc32f334.c + 1 + packages\hc32-f3-cmsis-latest\Device\HDSC\hc32f334\Source\system_hc32f334.c + + + + + startup_hc32f334.s + 2 + packages\hc32-f3-cmsis-latest\Device\HDSC\hc32f334\Source\ARM\startup_hc32f334.s + + + + + Tests + + + test_soft_i2c.c + 1 + ..\tests\test_soft_i2c.c + + + + + test_gpio.c + 1 + ..\tests\test_gpio.c + + + + + test_i2c.c + 1 + ..\tests\test_i2c.c + + + + + test_uart_v1.c + 1 + ..\tests\test_uart_v1.c + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f334_lqfp64/rtconfig.h b/bsp/hc32/ev_hc32f334_lqfp64/rtconfig.h new file mode 100644 index 00000000000..c05e35788f1 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/rtconfig.h @@ -0,0 +1,438 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart2" +#define RT_VER_NUM 0x50201 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +#define PKG_USING_HC32F3_CMSIS_DRIVER +#define PKG_USING_HC32F3_CMSIS_DRIVER_LATEST_VERSION +#define PKG_USING_HC32F3_SERIES_DRIVER +#define PKG_USING_HC32F3_SERIES_DRIVER_LATEST_VERSION +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_FAMILY_HC32 +#define SOC_SERIES_HC32F3 + +/* Hardware Drivers Config */ + +#define SOC_HC32F334KA + +/* On-chip Drivers */ + +#define BSP_USING_ON_CHIP_FLASH_CACHE +#define BSP_USING_ON_CHIP_FLASH_ICODE_CACHE +#define BSP_USING_ON_CHIP_FLASH_DCODE_CACHE +#define BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH +/* end of On-chip Drivers */ + +/* Onboard Peripheral Drivers */ + +/* end of Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART2 +#define BSP_USING_I2C +#define BSP_USING_I2C_HW +#define BSP_USING_I2C1 +/* end of On-chip Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/hc32/ev_hc32f334_lqfp64/rtconfig.py b/bsp/hc32/ev_hc32f334_lqfp64/rtconfig.py new file mode 100644 index 00000000000..568d50f2a65 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + else: + EXEC_PATH = r'C:/Users/XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4' + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/hc32/ev_hc32f334_lqfp64/template.ewp b/bsp/hc32/ev_hc32f334_lqfp64/template.ewp new file mode 100644 index 00000000000..8c9d3b79f0d --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/template.ewp @@ -0,0 +1,1927 @@ + + + + 2 + + Debug + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/hc32/ev_hc32f334_lqfp64/template.eww b/bsp/hc32/ev_hc32f334_lqfp64/template.eww new file mode 100644 index 00000000000..bd036bb4c98 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/hc32/ev_hc32f334_lqfp64/template.uvoptx b/bsp/hc32/ev_hc32f334_lqfp64/template.uvoptx new file mode 100644 index 00000000000..1f4a2590f79 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/template.uvoptx @@ -0,0 +1,179 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFFC000 -FC4000 -FN2 -FF0HC32F334_128K -FS00 -FL020000 -FP0($$Device:HC32F334KATI$FlashARM\HC32F334_128K.FLM) -FF1HC32F334_otp -FS13000000 -FL11800 -FP1($$Device:HC32F334KATI$FlashARM\HC32F334_otp.FLM) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32/ev_hc32f334_lqfp64/template.uvprojx b/bsp/hc32/ev_hc32f334_lqfp64/template.uvprojx new file mode 100644 index 00000000000..847334da616 --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/template.uvprojx @@ -0,0 +1,390 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060020::V5.06 (build 20)::ARMCC + 0 + + + HC32F334KATI + HDSC + HDSC.HC32F334.1.0.0 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IROM1(0x00000000,0x20000) IROM2(0x03000000,0x1800) IRAM1(0x1FFFC000,0x8000) IRAM2(0x200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(8000000) ESEL ELITTLE + + + CMSIS_AGDI(-S0 -C0 -P00 -FO15 -FD1FFFC000 -FC4000 -FN2 -FF0HC32F334_128K -FS00 -FL0020000 -FP0($$Device:HC32F334PETB$FlashARM\HC32F334_128K.FLM) -FF1HC32F334_otp -FS13000000 -FL11800 -FP1($$Device:HC32F334KATI$FlashARM\HC32F334_otp.FLM)) + 0 + $$Device:HC32F334KATI$Device\Include\HC32F334KATI.h + + + + + + + + + + ./packages/hc32-f3-cmsis-latest/Device/HDSC/hc32f334/Source/ARM/sfr/HC32F334.SFR + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 1 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 1 + 1 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1FFFC000 + 0x8000 + + + 1 + 0x0 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x20000 + + + 1 + 0x03000000 + 0x1800 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1FFFC000 + 0x8000 + + + 0 + 0x200F0000 + 0x1000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x0 + 0x1FFFC000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f448_lqfp80/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f448_lqfp80/.ci/attachconfig/ci.attachconfig.yml new file mode 100644 index 00000000000..92d777ca640 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/.ci/attachconfig/ci.attachconfig.yml @@ -0,0 +1,12 @@ +devices.gpio: + kconfig: + - CONFIG_BSP_USING_GPIO=y + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_I2C_HW=y + - CONFIG_BSP_USING_I2C1=y + - CONFIG_BSP_USING_TCA9539=y + - CONFIG_BSP_USING_EXT_IO=y +devices.uart: + kconfig: + - CONFIG_BSP_USING_UART=y + - CONFIG_BSP_USING_UART2=y diff --git a/bsp/hc32/ev_hc32f448_lqfp80/.config b/bsp/hc32/ev_hc32f448_lqfp80/.config index cf2b4c23a7a..2a2db836e31 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/.config +++ b/bsp/hc32/ev_hc32f448_lqfp80/.config @@ -389,6 +389,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set # CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set # # Wi-Fi @@ -633,6 +634,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ZDEBUG is not set # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set # end of tools packages # diff --git a/bsp/hc32/ev_hc32f448_lqfp80/.cproject b/bsp/hc32/ev_hc32f448_lqfp80/.cproject index f24a2c2e431..6bb292ae3b5 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/.cproject +++ b/bsp/hc32/ev_hc32f448_lqfp80/.cproject @@ -67,10 +67,10 @@ + + + - - - @@ -166,10 +166,10 @@ + + + - - - @@ -194,7 +194,7 @@ - + diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h index 119d3da9a77..610e3f5b2e5 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h @@ -21,7 +21,16 @@ extern "C" { #ifndef DAC1_INIT_PARAMS #define DAC1_INIT_PARAMS \ { \ - .name = "dac1", \ + .name = "dac1", \ + .vref = 3300, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_data_src = DAC_DATA_SRC_DATAREG, \ + .ch2_data_src = DAC_DATA_SRC_DATAREG, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ } #endif /* DAC1_INIT_PARAMS */ #endif /* BSP_USING_DAC1 */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/jlink/ev_hc32f448_lqfp80 Debug.launch b/bsp/hc32/ev_hc32f448_lqfp80/jlink/ev_hc32f448_lqfp80 Debug.launch index d55ce7cf5b8..1f6743ceb03 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/jlink/ev_hc32f448_lqfp80 Debug.launch +++ b/bsp/hc32/ev_hc32f448_lqfp80/jlink/ev_hc32f448_lqfp80 Debug.launch @@ -1,6 +1,6 @@ - + @@ -41,7 +41,7 @@ - + diff --git a/bsp/hc32/ev_hc32f448_lqfp80/project.ewd b/bsp/hc32/ev_hc32f448_lqfp80/project.ewd index 7380d22af8c..cae51a801fc 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/project.ewd +++ b/bsp/hc32/ev_hc32f448_lqfp80/project.ewd @@ -44,7 +44,7 @@ @@ -321,34 +319,31 @@ @@ -1321,34 +1314,31 @@ @@ -321,34 +319,31 @@ @@ -1321,34 +1314,31 @@ @@ -321,35 +319,32 @@ @@ -1322,35 +1315,32 @@ @@ -321,35 +319,32 @@ @@ -1322,35 +1315,32 @@ @@ -321,35 +319,32 @@ @@ -1322,35 +1315,32 @@