diff --git a/bsp/hc32/README.md b/bsp/hc32/README.md index 57f03240a53..523387d7e16 100644 --- a/bsp/hc32/README.md +++ b/bsp/hc32/README.md @@ -3,15 +3,18 @@ HC32 系列 BSP 目前支持情况如下表所示： -| **BSP 文件夹名称** | **开发板名称** | -|:------------------------- |:------------------------- | +| **BSP 文件夹名称** | **开发板名称** | +|:------------------------- |:----------------------------- | | **F1 系列** | | +| **F3 系列** | | +| [ev_hc32f334_lqfp64](ev_hc32f334_lqfp64) | 小华 官方 EV_F334_LQ64 开发板 | | **F4 系列** | | -| [ev_hc32f460_lqfp100_v2](ev_hc32f460_lqfp100_v2) | 小华 官方 EV_F460_LQ100_V2 开发板 | -| [ev_hc32f4a0_lqfp176](ev_hc32f4a0_lqfp176) | 小华 官方 EV_F4A0_LQ176 开发板 | -| [ev_hc32f448_lqfp80](ev_hc32f448_lqfp80) | 小华 官方 EV_F448_LQ80 开发板 | -| [ev_hc32f472_lqfp100](ev_hc32f472_lqfp100) | 小华 官方 EV_F472_LQ100 开发板 | -| [lckfb-hc32f4a0-lqfp100](lckfb-hc32f4a0-lqfp100) | 立创开发板 天空星-HC32F4A0PITB | +| [ev_hc32f448_lqfp80](ev_hc32f448_lqfp80) | 小华 官方 EV_F448_LQ80 开发板 | +| [ev_hc32f460_lqfp100_v2](ev_hc32f460_lqfp100_v2) | 小华 官方 EV_F460_LQ100_V2 开发板 | +| [ev_hc32f472_lqfp100](ev_hc32f472_lqfp100) | 小华 官方 EV_F472_LQ100 开发板 | +| [ev_hc32f4a0_lqfp176](ev_hc32f4a0_lqfp176) | 小华 官方 EV_F4A0_LQ176 开发板 | +| [lckfb-hc32f4a0-lqfp100](lckfb-hc32f4a0-lqfp100) | 立创开发板 天空星-HC32F4A0PITB | +| [ev_hc32f4a8_lqfp176](ev_hc32f4a8_lqfp176) | 小华 官方 EV_F4A8_LQ176 开发板 | | **M1 系列** | | | **M4 系列** | | @@ -23,4 +26,3 @@ HC32 系列 BSP 目前支持情况如下表所示： | [外设驱动介绍](docs/HC32系列驱动介绍.md) | 讲解 HC32 系列 BSP 驱动的支持情况，以及如何利用驱动框架开发应用程序 | | **BSP 制作与提交** | **简介** | | [BSP 制作教程](docs/HC32系列BSP制作教程.md) | 讲解 HC32 系列 BSP 的制作方法 | - diff --git a/bsp/hc32/ev_hc32f334_lqfp64/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f334_lqfp64/.ci/attachconfig/ci.attachconfig.yml index 1ff7e77400f..84e83f68114 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/hc32/ev_hc32f334_lqfp64/.ci/attachconfig/ci.attachconfig.yml @@ -1,7 +1,137 @@ +# ------ device CI ------ +devices.adc: + kconfig: + - CONFIG_BSP_USING_ADC=y + - CONFIG_BSP_USING_ADC1=y + - CONFIG_BSP_USING_ADC2=y + - CONFIG_BSP_USING_ADC3=y + - CONFIG_BSP_ADC1_USING_DMA=y + - CONFIG_BSP_ADC2_USING_DMA=y + - CONFIG_BSP_ADC3_USING_DMA=y +devices.crypto: + kconfig: + - CONFIG_BSP_USING_HWCRYPTO=y + - CONFIG_BSP_USING_UQID=y + - CONFIG_BSP_USING_CRC=y +devices.dac: + kconfig: + - CONFIG_BSP_USING_DAC=y + - CONFIG_BSP_USING_DAC1=y + - CONFIG_BSP_USING_DAC2=y +devices.flash: + kconfig: + - CONFIG_BSP_USING_ON_CHIP_FLASH=y devices.gpio: - kconfig: + kconfig: - CONFIG_BSP_USING_GPIO=y -devices.uart: +devices.hwtimer: + kconfig: + - CONFIG_BSP_USING_HWTIMER=y + - CONFIG_BSP_USING_TMRA_1=y +devices.i2c: + kconfig: + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_I2C1=y + - CONFIG_BSP_I2C1_TX_USING_DMA=y + - CONFIG_BSP_I2C1_RX_USING_DMA=y +devices.input_capture: + kconfig: + - CONFIG_BSP_USING_INPUT_CAPTURE=y + - CONFIG_BSP_USING_INPUT_CAPTURE_TMR6=y + - CONFIG_BSP_USING_INPUT_CAPTURE_TMR6_1=y +devices.mcan: + kconfig: + - CONFIG_BSP_USING_MCAN=y + - CONFIG_BSP_USING_MCAN1=y + - CONFIG_BSP_USING_MCAN2=y + - CONFIG_RT_CAN_USING_CANFD=y + - CONFIG_RT_CAN_USING_HDR=y +devices.pm: + kconfig: + - CONFIG_BSP_USING_PM=y + - CONFIG_IDLE_THREAD_STACK_SIZE=512 +devices.pulse_encoder_tmr6: + kconfig: + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_TMR6_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER_TMR6_1=y +devices.pulse_encoder_tmra: + kconfig: + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_TMRA_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER_TMRA_1=y +devices.pwm_tmr4: kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMR4=y + - CONFIG_BSP_USING_PWM_TMR4_1=y + - CONFIG_BSP_USING_PWM_TMR4_1_OUH=y + - CONFIG_BSP_USING_PWM_TMR4_1_OUL=y + - CONFIG_BSP_USING_PWM_TMR4_1_OVH=y + - CONFIG_BSP_USING_PWM_TMR4_1_OVL=y + - CONFIG_BSP_USING_PWM_TMR4_1_OWH=y + - CONFIG_BSP_USING_PWM_TMR4_1_OWL=y + - CONFIG_BSP_USING_PWM_TMR4_1_OXH=y + - CONFIG_BSP_USING_PWM_TMR4_1_OXL=y +devices.pwm_tmr6: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMR6=y + - CONFIG_BSP_USING_PWM_TMR6_1=y + - CONFIG_BSP_USING_PWM_TMR6_1_A=y + - CONFIG_BSP_USING_PWM_TMR6_1_B=y +devices.pwm_tmra: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMRA=y + - CONFIG_BSP_USING_PWM_TMRA_1=y + - CONFIG_BSP_USING_PWM_TMRA_1_CH1=y + - CONFIG_BSP_USING_PWM_TMRA_1_CH2=y + - CONFIG_BSP_USING_PWM_TMRA_1_CH3=y + - CONFIG_BSP_USING_PWM_TMRA_1_CH4=y +devices.rtc: + kconfig: + - CONFIG_BSP_USING_RTC=y + - CONFIG_RT_USING_ALARM=y +devices.soft_i2c: + kconfig: + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_I2C1_SW=y +devices.spi: + kconfig: + - CONFIG_BSP_USING_SPI=y + - CONFIG_BSP_USING_SPI1=y + - CONFIG_BSP_SPI1_TX_USING_DMA=y + - CONFIG_BSP_SPI1_RX_USING_DMA=y + - CONFIG_BSP_SPI_USING_DMA=y +devices.uart_v1: + kconfig: + - CONFIG_RT_USING_SERIAL_V1=y - CONFIG_BSP_USING_UART=y - - CONFIG_BSP_USING_UART2=y + - CONFIG_BSP_USING_UART1=y + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_UART1_RX_USING_DMA=y + - CONFIG_BSP_UART1_TX_USING_DMA=y +devices.uart_v2: + kconfig: + - CONFIG_RT_USING_SERIAL_V2=y + - CONFIG_BSP_USING_UART=y + - CONFIG_BSP_USING_UART1=y + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_UART1_RX_USING_DMA=y + - CONFIG_BSP_UART1_TX_USING_DMA=y +devices.watchdog_swdt: + kconfig: + - CONFIG_BSP_USING_WDT_TMR=y + - CONFIG_BSP_USING_SWDT=y +devices.watchdog_wdt: + kconfig: + - CONFIG_BSP_USING_WDT_TMR=y + - CONFIG_BSP_USING_WDT=y + +# ------ peripheral CI ------ +peripheral.spi_flash: + kconfig: + - CONFIG_BSP_USING_SPI_FLASH=y + - CONFIG_BSP_USING_SPI=y + - CONFIG_BSP_USING_SPI1=y diff --git a/bsp/hc32/ev_hc32f334_lqfp64/README.md b/bsp/hc32/ev_hc32f334_lqfp64/README.md index 81bd92ccaab..a7e2ff21424 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/README.md +++ b/bsp/hc32/ev_hc32f334_lqfp64/README.md @@ -1,8 +1,8 @@ -# XHSC EV_F334_LQ64_Rev1.0 开发板 BSP 说明 +# XHSC EV_F334_LQ64 开发板 BSP 说明 ## 简介 -本文档为小华半导体为 EV_F334_LQ64_Rev1.0 开发板提供的 BSP (板级支持包) 说明。 +本文档为小华半导体为 EV_F334_LQ64 开发板提供的 BSP (板级支持包) 说明。 主要内容如下： @@ -14,79 +14,63 @@ ## 开发板介绍 -EV_F334_LQ64_Rev1.0 是 XHSC 官方推出的开发板，搭载 HC32F334MCTI 芯片，基于 ARM Cortex-M4 内核，最高主频 200 MHz，具有丰富的板载资源，可以充分发挥 HC32F334MCTI 的芯片性能。 +EV_F334_LQ64 是 XHSC 官方推出的开发板，搭载 HC32F334KATI 芯片，基于 ARM Cortex-M4 内核，最高主频 120 MHz，具有丰富的板载资源，可以充分发挥 HC32F334KATI 的芯片性能。 开发板外观如下图所示： ![board](figures/board.png) -EV_F334_LQ64_Rev1.0 开发板常用 **板载资源** 如下： - -- **MCU** - - HC32F334MCTI - - 主频200MHz - - 256KB FLASH - - 68KB RAM -- **外部Memory** - - BL24C256（EEPROM, 256Kbits） - - W25Q64（SPI NOR，64MB） - - IS62WV51216（SRAM， 1MB） -- **常用外设** - - LED: 4 个，User LED（LED0，LED1，LED2，LED3）。 - - 按键: 5 个，矩阵键盘（K1~K4）， WAKEUP（K5），RESET（K0） -- **常用接口** - - USB转串口 - - CAN DB9接口 * 2 - - TFT接口 - - SmartCard接口 - - I2C/USART/SPI接口 -- **调试接口** - - 板载DAP调试器 - - 标准JTAG/SWD/Trace - -开发板更多详细信息请参考小华半导体半导体[EV_F334_LQ64_Rev1.0](https://www.xhsc.com.cn) +EV_F334_LQ64 开发板常用 **板载资源** 如下： + +- MCU：HC32F334KATI，主频120MHz，128KB FLASH，36KB RAM +- 常用外设 + - LED：2 个，User LED(LED0、LED1)。 + - 按键：4个，K1、K2、WAKEUP(K3)、RESET(K0)。 +- 常用接口：CAN接口、LIN接口、RS485接口。 +- 调试接口：板载DAP调试器（含USB转串口）、标准JTAG/SWD。 + +开发板更多详细信息请参考小华半导体半导体[EV_F334_LQ64](https://www.xhsc.com.cn) ## 外设支持 本 BSP 目前对外设的支持情况如下： -| **板载外设** | **支持情况** | **备注** | -|:-------- |:--------:|:--------:| -| USB 转串口 | 支持 | 使用 UART2 | -| LED | 支持 | LED1~4 | - -| **片上外设** | **支持情况** | **备注** | -|:------------- |:--------:|:------------------------------------------:| -| Crypto | 支持 | AES, CRC, HASH, RNG, UID | -| DAC | 支持 | | -| ADC | 支持 | ADC1: CH10, CH11,
ADC3: CH1 | -| CAN | 支持 | CAN1、CAN2 | -| GPIO | 支持 | PA0, PA1... PH2 ---> PIN: 0, 1...82 | -| I2C | 支持 | 软件模拟
硬件I2C1~2
I2C1支持EEPROM（BL24C256） | -| PM | 支持 | | -| Lptimer | 支持 | | -| Hwtimer | 支持 | Hwtimer1~5 | -| Pulse_encoder | 支持 | | -| PWM | 支持 | | -| RTC | 支持 | 闹钟精度为1分钟 | -| WDT | 支持 | | -| I2C | 支持 | 软件、硬件 I2C | -| QSPI | 支持 | | -| SPI | 支持 | SPI1~3
SPI1支持W25Q | -| UART | 支持 | UART1~6
UART2为console使用 | +| **板载外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| USB 转串口 | 支持 | 使用 UART2 | + +| **片上外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| ADC | 支持 | | +| Crypto | 支持 | CRC | +| DAC | 支持 | | +| FLASH | 支持 | | +| GPIO | 支持 | PA0，PA1...PF3 ---> PIN：0，1...68 | +| HwTimer | 支持 | | +| I2C | 支持 | 软件、硬件 I2C | +| InputCapture | 支持 | | +| MCAN | 支持 | | +| PM | 支持 | | +| PulseEncoder | 支持 | | +| PWM | 支持 | | +| RTC | 支持 | 闹钟精度为1分钟 | +| SPI | 支持 | | +| UART V1 & V2 | 支持 | | +| WDT | 支持 | | ## 使用说明 使用说明分为如下两个章节： - 快速上手 - + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 - 进阶使用 - + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + ### 快速上手 本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 @@ -103,14 +87,14 @@ EV_F334_LQ64_Rev1.0 开发板常用 **板载资源** 如下： #### 运行结果 -下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED3会周期性闪烁。 +下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED1会周期性闪烁。 USB虚拟COM端口默认连接串口2，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息: ``` \ | / - RT - Thread Operating System - / | \ 5.0.1 build Feb 4 2024 16:44:26 + / | \ 4.1.0 build Apr 24 2022 13:32:39 2006 - 2022 Copyright by RT-Thread team msh > ``` @@ -127,12 +111,6 @@ msh > 4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 -## 注意事项 - -| 板载外设 | 模式 | 注意事项 | -| ---- | ---- | ------------------------------------------------------------------------------------------------------ | -| USB | host | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 | - ## 联系人信息 维护人: diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/Kconfig b/bsp/hc32/ev_hc32f334_lqfp64/board/Kconfig index 6c6cdf0fd3d..a2bf2035bfb 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/Kconfig +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/Kconfig @@ -30,11 +30,6 @@ menu "Onboard Peripheral Drivers" bool "Enable SPI FLASH (w25q64 spi1)" select BSP_USING_SPI select BSP_USING_SPI1 - select BSP_USING_ON_CHIP_FLASH - select RT_USING_SFUD - select RT_USING_DFS - select RT_USING_FAL - select RT_USING_MTD_NOR default n endmenu @@ -198,11 +193,11 @@ menu "On-chip Peripheral Drivers" config BSP_I2C1_SCL_PIN int "i2c1 scl pin number" range 1 68 - default 22 + default 22 # PB6 config BSP_I2C1_SDA_PIN int "I2C1 sda pin number" range 1 68 - default 23 + default 23 # PB7 endif endif @@ -262,36 +257,6 @@ menu "On-chip Peripheral Drivers" select BSP_SPI1_TX_USING_DMA default n endif - - menuconfig BSP_USING_SPI2 - bool "Enable SPI2 BUS" - default n - if BSP_USING_SPI2 - config BSP_SPI2_TX_USING_DMA - bool "Enable SPI2 TX DMA" - select BSP_SPI_USING_DMA - default n - config BSP_SPI2_RX_USING_DMA - bool "Enable SPI2 RX DMA" - select BSP_SPI_USING_DMA - select BSP_SPI2_TX_USING_DMA - default n - endif - - menuconfig BSP_USING_SPI3 - bool "Enable SPI3 BUS" - default n - if BSP_USING_SPI3 - config BSP_SPI3_TX_USING_DMA - bool "Enable SPI3 TX DMA" - select BSP_SPI_USING_DMA - default n - config BSP_SPI3_RX_USING_DMA - bool "Enable SPI3 RX DMA" - select BSP_SPI_USING_DMA - select BSP_SPI3_TX_USING_DMA - default n - endif endif menuconfig BSP_USING_ADC @@ -333,6 +298,9 @@ menu "On-chip Peripheral Drivers" config BSP_USING_DAC1 bool "using dac1" default n + config BSP_USING_DAC2 + bool "using dac2" + default n endif menuconfig BSP_USING_MCAN @@ -361,7 +329,7 @@ menu "On-chip Peripheral Drivers" config BSP_USING_SWDT bool "SWDT(3.72hour(max))" config BSP_USING_WDT - bool "WDT(10.7s(max))" + bool "WDT(8.9s(max))" endchoice config BSP_WDT_CONTINUE_COUNT @@ -383,9 +351,6 @@ menu "On-chip Peripheral Drivers" config BSP_RTC_USING_LRC bool "RTC Using LRC" - - config BSP_RTC_USING_XTAL_DIV - bool "RTC Using XTAL Division" endchoice endif @@ -479,16 +444,11 @@ menu "On-chip Peripheral Drivers" config BSP_USING_PWM_TMRA_1_CH2 bool "Enable timerA-1 channel2" default n - endif - menuconfig BSP_USING_PWM_TMRA_2 - bool "Enable timerA-2 output PWM" - default n - if BSP_USING_PWM_TMRA_2 - config BSP_USING_PWM_TMRA_2_CH1 - bool "Enable timerA-2 channel1" + config BSP_USING_PWM_TMRA_1_CH3 + bool "Enable timerA-1 channel3" default n - config BSP_USING_PWM_TMRA_2_CH2 - bool "Enable timerA-2 channel2" + config BSP_USING_PWM_TMRA_1_CH4 + bool "Enable timerA-1 channel4" default n endif endif @@ -518,6 +478,12 @@ menu "On-chip Peripheral Drivers" config BSP_USING_PWM_TMR4_1_OWL bool "Enable TMR4_1_OWL channel5" default n + config BSP_USING_PWM_TMR4_1_OXH + bool "Enable TMR4_1_OXH channel6" + default n + config BSP_USING_PWM_TMR4_1_OXL + bool "Enable TMR4_1_OXL channel7" + default n endif endif menuconfig BSP_USING_PWM_TMR6 @@ -600,14 +566,6 @@ menu "On-chip Peripheral Drivers" bool "unit 3" config BSP_USING_INPUT_CAPTURE_TMR6_4 bool "unit 4" - config BSP_USING_INPUT_CAPTURE_TMR6_5 - bool "unit 5" - config BSP_USING_INPUT_CAPTURE_TMR6_6 - bool "unit 6" - config BSP_USING_INPUT_CAPTURE_TMR6_7 - bool "unit 7" - config BSP_USING_INPUT_CAPTURE_TMR6_8 - bool "unit 8" endif endif endmenu diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/board.c b/bsp/hc32/ev_hc32f334_lqfp64/board/board.c index 35f7a1fbc63..f5791403f24 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/board.c +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/board.c @@ -80,7 +80,7 @@ void SystemClock_Config(void) #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) /* Xtal32 config */ - GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE); + GPIO_AnalogCmd(XTAL32_PORT, XTAL32_PIN, ENABLE); (void)CLK_Xtal32StructInit(&stcXtal32Init); stcXtal32Init.u8State = CLK_XTAL32_ON; stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.c b/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.c index 0f30c3fd3df..46dc6f4c45f 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.c +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.c @@ -114,10 +114,15 @@ rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx) switch ((rt_uint32_t)DACx) { #if defined(BSP_USING_DAC1) - case (rt_uint32_t)CM_DAC: + case (rt_uint32_t)CM_DAC1: (void)GPIO_Init(DAC1_CH1_PORT, DAC1_CH1_PIN, &stcGpioInit); (void)GPIO_Init(DAC1_CH2_PORT, DAC1_CH2_PIN, &stcGpioInit); break; +#endif +#if defined(BSP_USING_DAC2) + case (rt_uint32_t)CM_DAC2: + (void)GPIO_Init(DAC2_CH1_PORT, DAC2_CH1_PIN, &stcGpioInit); + break; #endif default: result = -RT_ERROR; @@ -131,15 +136,22 @@ rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx) #if defined(RT_USING_CAN) void CanPhyEnable(void) { + stc_gpio_init_t stcGpioInit; + #if defined(BSP_USING_MCAN1) - TCA9539_WritePin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_PIN_RESET); - TCA9539_ConfigPin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_DIR_OUT); + GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinState = PIN_STAT_RST; + stcGpioInit.u16PinDir = PIN_DIR_OUT; + GPIO_Init(MCAN1_PHY_STBY_PORT, MCAN1_PHY_STBY_PIN, &stcGpioInit); #endif #if defined(BSP_USING_MCAN2) - TCA9539_WritePin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_PIN_RESET); - TCA9539_ConfigPin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_DIR_OUT); + GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinState = PIN_STAT_RST; + stcGpioInit.u16PinDir = PIN_DIR_OUT; + GPIO_Init(MCAN2_PHY_STBY_PORT, MCAN2_PHY_STBY_PIN, &stcGpioInit); #endif } + rt_err_t rt_hw_board_mcan_init(CM_MCAN_TypeDef *MCANx) { rt_err_t result = RT_EOK; @@ -178,13 +190,7 @@ rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) switch ((rt_uint32_t)CM_SPIx) { #if defined(BSP_USING_SPI1) - case (rt_uint32_t)CM_SPI1: - GPIO_StructInit(&stcGpioInit); - stcGpioInit.u16PinState = PIN_STAT_SET; - stcGpioInit.u16PinDir = PIN_DIR_OUT; - GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit); - GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit); - + case (rt_uint32_t)CM_SPI: (void)GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinDrv = PIN_HIGH_DRV; stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS; @@ -227,22 +233,6 @@ rt_err_t rt_hw_board_pwm_tmra_init(CM_TMRA_TypeDef *TMRAx) GPIO_SetFunc(PWM_TMRA_1_CH4_PORT, PWM_TMRA_1_CH4_PIN, PWM_TMRA_1_CH4_PIN_FUNC); #endif break; -#endif -#if defined(BSP_USING_PWM_TMRA_2) - case (rt_uint32_t)CM_TMRA_2: -#ifdef BSP_USING_PWM_TMRA_2_CH1 - GPIO_SetFunc(PWM_TMRA_2_CH1_PORT, PWM_TMRA_2_CH1_PIN, PWM_TMRA_2_CH1_PIN_FUNC); -#endif -#ifdef BSP_USING_PWM_TMRA_2_CH2 - GPIO_SetFunc(PWM_TMRA_2_CH2_PORT, PWM_TMRA_2_CH2_PIN, PWM_TMRA_2_CH2_PIN_FUNC); -#endif -#ifdef BSP_USING_PWM_TMRA_2_CH3 - GPIO_SetFunc(PWM_TMRA_2_CH3_PORT, PWM_TMRA_2_CH3_PIN, PWM_TMRA_2_CH3_PIN_FUNC); -#endif -#ifdef BSP_USING_PWM_TMRA_2_CH4 - GPIO_SetFunc(PWM_TMRA_2_CH4_PORT, PWM_TMRA_2_CH4_PIN, PWM_TMRA_2_CH4_PIN_FUNC); -#endif - break; #endif default: result = -RT_ERROR; @@ -260,7 +250,7 @@ rt_err_t rt_hw_board_pwm_tmr4_init(CM_TMR4_TypeDef *TMR4x) switch ((rt_uint32_t)TMR4x) { #if defined(BSP_USING_PWM_TMR4_1) - case (rt_uint32_t)CM_TMR4_1: + case (rt_uint32_t)CM_TMR4: #ifdef BSP_USING_PWM_TMR4_1_OUH GPIO_SetFunc(PWM_TMR4_1_OUH_PORT, PWM_TMR4_1_OUH_PIN, PWM_TMR4_1_OUH_PIN_FUNC); #endif @@ -278,6 +268,12 @@ rt_err_t rt_hw_board_pwm_tmr4_init(CM_TMR4_TypeDef *TMR4x) #endif #ifdef BSP_USING_PWM_TMR4_1_OWL GPIO_SetFunc(PWM_TMR4_1_OWL_PORT, PWM_TMR4_1_OWL_PIN, PWM_TMR4_1_OWL_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OXH + GPIO_SetFunc(PWM_TMR4_1_OXH_PORT, PWM_TMR4_1_OXH_PIN, PWM_TMR4_1_OXH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OXL + GPIO_SetFunc(PWM_TMR4_1_OXL_PORT, PWM_TMR4_1_OXL_PIN, PWM_TMR4_1_OXL_PIN_FUNC); #endif break; #endif diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.h index 0a060ce4efd..4fa4759a5df 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.h @@ -66,8 +66,8 @@ #endif #if defined(BSP_USING_ADC3) - #define ADC3_CH_PORT (GPIO_PORT_E) /* Default ADC3_IN1 */ - #define ADC3_CH_PIN (GPIO_PIN_03) + #define ADC3_CH_PORT (GPIO_PORT_B) /* Default ADC3_IN1 */ + #define ADC3_CH_PIN (GPIO_PIN_13) #endif /*********** DAC configure *********/ @@ -77,58 +77,61 @@ #define DAC1_CH2_PORT (GPIO_PORT_A) #define DAC1_CH2_PIN (GPIO_PIN_05) #endif +#if defined(BSP_USING_DAC2) + #define DAC2_CH1_PORT (GPIO_PORT_A) + #define DAC2_CH1_PIN (GPIO_PIN_06) +#endif /*********** CAN configure *********/ #if defined(BSP_USING_MCAN1) - #define MCAN1_TX_PORT (GPIO_PORT_C) - #define MCAN1_TX_PIN (GPIO_PIN_12) - #define MCAN1_TX_PIN_FUNC (GPIO_FUNC_56) + #define MCAN1_TX_PORT (GPIO_PORT_A) + #define MCAN1_TX_PIN (GPIO_PIN_02) + #define MCAN1_TX_PIN_FUNC (GPIO_FUNC_54) + + #define MCAN1_RX_PORT (GPIO_PORT_C) + #define MCAN1_RX_PIN (GPIO_PIN_05) + #define MCAN1_RX_PIN_FUNC (GPIO_FUNC_55) - #define MCAN1_RX_PORT (GPIO_PORT_D) - #define MCAN1_RX_PIN (GPIO_PIN_00) - #define MCAN1_RX_PIN_FUNC (GPIO_FUNC_57) + #define MCAN1_PHY_STBY_PORT (GPIO_PORT_B) + #define MCAN1_PHY_STBY_PIN (GPIO_PIN_01) #endif #if defined(BSP_USING_MCAN2) - #define MCAN2_TX_PORT (GPIO_PORT_H) - #define MCAN2_TX_PIN (GPIO_PIN_02) + #define MCAN2_TX_PORT (GPIO_PORT_B) + #define MCAN2_TX_PIN (GPIO_PIN_11) #define MCAN2_TX_PIN_FUNC (GPIO_FUNC_56) - #define MCAN2_RX_PORT (GPIO_PORT_E) - #define MCAN2_RX_PIN (GPIO_PIN_04) + #define MCAN2_RX_PORT (GPIO_PORT_B) + #define MCAN2_RX_PIN (GPIO_PIN_10) #define MCAN2_RX_PIN_FUNC (GPIO_FUNC_57) + + #define MCAN2_PHY_STBY_PORT (GPIO_PORT_B) + #define MCAN2_PHY_STBY_PIN (GPIO_PIN_02) #endif /************************* SPI port ***********************/ #if defined(BSP_USING_SPI1) #define SPI1_CS_PORT (GPIO_PORT_C) - #define SPI1_CS_PIN (GPIO_PIN_07) + #define SPI1_CS_PIN (GPIO_PIN_01) #define SPI1_SCK_PORT (GPIO_PORT_B) - #define SPI1_SCK_PIN (GPIO_PIN_14) - #define SPI1_SCK_FUNC (GPIO_FUNC_47) - - #define SPI1_MOSI_PORT (GPIO_PORT_B) - #define SPI1_MOSI_PIN (GPIO_PIN_13) - #define SPI1_MOSI_FUNC (GPIO_FUNC_44) + #define SPI1_SCK_PIN (GPIO_PIN_05) + #define SPI1_SCK_FUNC (GPIO_FUNC_49) - #define SPI1_MISO_PORT (GPIO_PORT_D) - #define SPI1_MISO_PIN (GPIO_PIN_09) - #define SPI1_MISO_FUNC (GPIO_FUNC_45) + #define SPI1_MOSI_PORT (GPIO_PORT_A) + #define SPI1_MOSI_PIN (GPIO_PIN_00) + #define SPI1_MOSI_FUNC (GPIO_FUNC_50) - #define SPI1_WP_PORT (GPIO_PORT_D) - #define SPI1_WP_PIN (GPIO_PIN_10) - - #define SPI1_HOLD_PORT (GPIO_PORT_D) - #define SPI1_HOLD_PIN (GPIO_PIN_11) + #define SPI1_MISO_PORT (GPIO_PORT_A) + #define SPI1_MISO_PIN (GPIO_PIN_01) + #define SPI1_MISO_FUNC (GPIO_FUNC_51) #endif /************************ RTC/PM *****************************/ #if defined(BSP_USING_RTC) || defined(RT_USING_PM) #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) #define XTAL32_PORT (GPIO_PORT_C) - #define XTAL32_IN_PIN (GPIO_PIN_14) - #define XTAL32_OUT_PIN (GPIO_PIN_15) + #define XTAL32_PIN (GPIO_PIN_14 | GPIO_PIN_15) #endif #endif @@ -137,46 +140,23 @@ #if defined(BSP_USING_PWM_TMRA_1) #if defined(BSP_USING_PWM_TMRA_1_CH1) #define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08) - #define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4) + #define PWM_TMRA_1_CH1_PIN (GPIO_PIN_00) + #define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_15) #endif #if defined(BSP_USING_PWM_TMRA_1_CH2) #define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09) - #define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4) + #define PWM_TMRA_1_CH2_PIN (GPIO_PIN_01) + #define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_15) #endif #if defined(BSP_USING_PWM_TMRA_1_CH3) #define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10) - #define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4) + #define PWM_TMRA_1_CH3_PIN (GPIO_PIN_02) + #define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_15) #endif #if defined(BSP_USING_PWM_TMRA_1_CH4) #define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11) - #define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4) - #endif - #endif - - #if defined(BSP_USING_PWM_TMRA_2) - #if defined(BSP_USING_PWM_TMRA_2_CH1) - #define PWM_TMRA_2_CH1_PORT (GPIO_PORT_A) - #define PWM_TMRA_2_CH1_PIN (GPIO_PIN_00) - #define PWM_TMRA_2_CH1_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_2_CH2) - #define PWM_TMRA_2_CH2_PORT (GPIO_PORT_A) - #define PWM_TMRA_2_CH2_PIN (GPIO_PIN_01) - #define PWM_TMRA_2_CH2_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_2_CH3) - #define PWM_TMRA_2_CH3_PORT (GPIO_PORT_A) - #define PWM_TMRA_2_CH3_PIN (GPIO_PIN_02) - #define PWM_TMRA_2_CH3_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_2_CH4) - #define PWM_TMRA_2_CH4_PORT (GPIO_PORT_A) - #define PWM_TMRA_2_CH4_PIN (GPIO_PIN_03) - #define PWM_TMRA_2_CH4_PIN_FUNC (GPIO_FUNC_4) + #define PWM_TMRA_1_CH4_PIN (GPIO_PIN_03) + #define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_15) #endif #endif @@ -184,65 +164,75 @@ #if defined(BSP_USING_PWM_TMR4_1) #if defined(BSP_USING_PWM_TMR4_1_OUH) #define PWM_TMR4_1_OUH_PORT (GPIO_PORT_A) - #define PWM_TMR4_1_OUH_PIN (GPIO_PIN_08) - #define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2) + #define PWM_TMR4_1_OUH_PIN (GPIO_PIN_02) + #define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_20) #endif #if defined(BSP_USING_PWM_TMR4_1_OUL) #define PWM_TMR4_1_OUL_PORT (GPIO_PORT_A) - #define PWM_TMR4_1_OUL_PIN (GPIO_PIN_07) - #define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2) + #define PWM_TMR4_1_OUL_PIN (GPIO_PIN_01) + #define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_20) #endif #if defined(BSP_USING_PWM_TMR4_1_OVH) #define PWM_TMR4_1_OVH_PORT (GPIO_PORT_A) - #define PWM_TMR4_1_OVH_PIN (GPIO_PIN_09) - #define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2) + #define PWM_TMR4_1_OVH_PIN (GPIO_PIN_06) + #define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_20) #endif #if defined(BSP_USING_PWM_TMR4_1_OVL) - #define PWM_TMR4_1_OVL_PORT (GPIO_PORT_B) - #define PWM_TMR4_1_OVL_PIN (GPIO_PIN_00) - #define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2) + #define PWM_TMR4_1_OVL_PORT (GPIO_PORT_A) + #define PWM_TMR4_1_OVL_PIN (GPIO_PIN_04) + #define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_20) #endif #if defined(BSP_USING_PWM_TMR4_1_OWH) #define PWM_TMR4_1_OWH_PORT (GPIO_PORT_A) - #define PWM_TMR4_1_OWH_PIN (GPIO_PIN_10) - #define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2) + #define PWM_TMR4_1_OWH_PIN (GPIO_PIN_07) + #define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_20) #endif #if defined(BSP_USING_PWM_TMR4_1_OWL) #define PWM_TMR4_1_OWL_PORT (GPIO_PORT_B) - #define PWM_TMR4_1_OWL_PIN (GPIO_PIN_01) - #define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2) + #define PWM_TMR4_1_OWL_PIN (GPIO_PIN_02) + #define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_20) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OXH) + #define PWM_TMR4_1_OXH_PORT (GPIO_PORT_A) + #define PWM_TMR4_1_OXH_PIN (GPIO_PIN_01) + #define PWM_TMR4_1_OXH_PIN_FUNC (GPIO_FUNC_23) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OXL) + #define PWM_TMR4_1_OXL_PORT (GPIO_PORT_A) + #define PWM_TMR4_1_OXL_PIN (GPIO_PIN_00) + #define PWM_TMR4_1_OXL_PIN_FUNC (GPIO_FUNC_23) #endif #endif /*********** PWM_TMR6 configure *********/ #if defined(BSP_USING_PWM_TMR6_1) #if defined(BSP_USING_PWM_TMR6_1_A) - #define PWM_TMR6_1_A_PORT (GPIO_PORT_A) - #define PWM_TMR6_1_A_PIN (GPIO_PIN_08) - #define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) + #define PWM_TMR6_1_A_PORT (GPIO_PORT_C) + #define PWM_TMR6_1_A_PIN (GPIO_PIN_00) + #define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_12) #endif #if defined(BSP_USING_PWM_TMR6_1_B) #define PWM_TMR6_1_B_PORT (GPIO_PORT_A) - #define PWM_TMR6_1_B_PIN (GPIO_PIN_07) - #define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) + #define PWM_TMR6_1_B_PIN (GPIO_PIN_00) + #define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_12) #endif #endif #endif #if defined(BSP_USING_INPUT_CAPTURE) - #define INPUT_CAPTURE_TMR6_FUNC (GPIO_FUNC_3) + #define INPUT_CAPTURE_TMR6_FUNC (GPIO_FUNC_14) #if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) - #define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_B) - #define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_09) + #define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_C) + #define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_06) #endif #if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) - #define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_E) + #define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_C) #define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_07) #endif #if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) - #define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_A) - #define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_00) + #define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_B) + #define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_02) #endif #endif diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/adc_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/adc_config.h index be6d4c6de34..13bb213c9ad 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/config/adc_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/adc_config.h @@ -34,7 +34,7 @@ extern "C" { .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ .internal_trig1_comtrg0_enable = RT_FALSE, \ .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_MAX, \ + .internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \ .continue_conv_mode_enable = RT_FALSE, \ .data_reg_auto_clear = RT_TRUE, \ } @@ -77,7 +77,7 @@ extern "C" { .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ .internal_trig1_comtrg0_enable = RT_FALSE, \ .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_MAX, \ + .internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \ .continue_conv_mode_enable = RT_FALSE, \ .data_reg_auto_clear = RT_TRUE, \ } @@ -120,7 +120,7 @@ extern "C" { .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ .internal_trig1_comtrg0_enable = RT_FALSE, \ .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_MAX, \ + .internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \ .continue_conv_mode_enable = RT_FALSE, \ .data_reg_auto_clear = RT_TRUE, \ } diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/dac_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/dac_config.h index 610e3f5b2e5..e7bb3e89632 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/config/dac_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/dac_config.h @@ -27,14 +27,26 @@ extern "C" { .dac_adp_sel = DAC_ADP_SEL_ALL, \ .ch1_output_enable = RT_TRUE, \ .ch2_output_enable = RT_TRUE, \ - .ch1_data_src = DAC_DATA_SRC_DATAREG, \ - .ch2_data_src = DAC_DATA_SRC_DATAREG, \ .ch1_amp_enable = RT_TRUE, \ .ch2_amp_enable = RT_TRUE, \ } #endif /* DAC1_INIT_PARAMS */ #endif /* BSP_USING_DAC1 */ +#ifdef BSP_USING_DAC2 +#ifndef DAC2_INIT_PARAMS +#define DAC2_INIT_PARAMS \ + { \ + .name = "dac2", \ + .vref = 3300, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch1_amp_enable = RT_TRUE, \ + } +#endif /* DAC2_INIT_PARAMS */ +#endif /* BSP_USING_DAC2 */ + #ifdef __cplusplus } #endif diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/irq_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/irq_config.h index d9cf2d80ff6..e968e9043fd 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/config/irq_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/irq_config.h @@ -120,20 +120,10 @@ extern "C" { #endif /* BSP_USING_UART4 */ #if defined(BSP_USING_SPI1) -#define BSP_SPI1_ERR_IRQ_NUM SPI1_IRQn +#define BSP_SPI1_ERR_IRQ_NUM SPI_IRQn #define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif -#if defined(BSP_USING_SPI2) -#define BSP_SPI2_ERR_IRQ_NUM SPI2_IRQn -#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#endif - -#if defined(BSP_USING_SPI3) -#define BSP_SPI3_ERR_IRQ_NUM SPI3_IRQn -#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#endif - #if defined (BSP_USING_QSPI) #define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn #define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT @@ -167,17 +157,11 @@ extern "C" { #if defined(BSP_USING_MCAN1) #define BSP_MCAN1_INT0_IRQ_NUM MCAN1_INT0_IRQn #define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT - -#define BSP_MCAN1_INT1_IRQ_NUM MCAN1_INT1_IRQn -#define BSP_MCAN1_INT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_MCAN1 */ #if defined(BSP_USING_MCAN2) #define BSP_MCAN2_INT0_IRQ_NUM MCAN2_INT0_IRQn #define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT - -#define BSP_MCAN2_INT1_IRQ_NUM MCAN2_INT1_IRQn -#define BSP_MCAN2_INT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_MCAN2 */ #if defined(RT_USING_ALARM) @@ -229,6 +213,28 @@ extern "C" { #define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */ +#if defined(BSP_USING_INPUT_CAPTURE) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT008_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT009_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT010_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT011_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM (INT012_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM (INT013_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_NUM (INT014_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_NUM (INT015_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#endif/* BSP_USING_INPUT_CAPTURE */ + #ifdef __cplusplus } #endif diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/pm_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/pm_config.h index 4d86a2aaee2..9804d7df223 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/config/pm_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/pm_config.h @@ -54,8 +54,6 @@ extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); { \ { \ .u16Clock = PWC_STOP_CLK_KEEP, \ - .u8StopDrv = PWC_STOP_DRV_HIGH, \ - .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \ .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ }, \ .pwc_stop_type = PWC_STOP_WFE_INT, \ @@ -71,7 +69,6 @@ extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); { \ .u8Mode = PWC_PD_MD1, \ .u8IOState = PWC_PD_IO_KEEP1, \ - .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ }, \ } #endif /*PM_SLEEP_STANDBY_CFG*/ @@ -85,7 +82,6 @@ extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); { \ .u8Mode = PWC_PD_MD3, \ .u8IOState = PWC_PD_IO_KEEP1, \ - .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ }, \ } #endif /*PM_SLEEP_SHUTDOWN_CFG*/ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/pwm_tmr_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/pwm_tmr_config.h index e432b5a83d0..651bbc22baa 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/config/pwm_tmr_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/pwm_tmr_config.h @@ -182,7 +182,7 @@ extern "C" { #define PWM_TMR4_1_CONFIG \ { \ .name = "pwm_t41", \ - .instance = CM_TMR4_1, \ + .instance = CM_TMR4, \ .channel = 0, \ .stcTmr4Init = \ { \ @@ -209,70 +209,6 @@ extern "C" { #endif /* PWM_TMR4_1_CONFIG */ #endif /* BSP_USING_PWM_TMR4_1 */ -#ifdef BSP_USING_PWM_TMR4_2 -#ifndef PWM_TMR4_2_CONFIG -#define PWM_TMR4_2_CONFIG \ - { \ - .name = "pwm_t42", \ - .instance = CM_TMR4_2, \ - .channel = 0, \ - .stcTmr4Init = \ - { \ - .u16ClockDiv = TMR4_CLK_DIV1, \ - .u16PeriodValue = 0xFFFFU, \ - .u16CountMode = TMR4_MD_SAWTOOTH, \ - .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ - }, \ - .stcTmr4OcInit = \ - { \ - .u16CompareValue = 0x0000, \ - .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ - .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ - .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ - .u16BufLinkTransObject = 0U, \ - }, \ - .stcTmr4PwmInit = \ - { \ - .u16Mode = TMR4_PWM_MD_THROUGH, \ - .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ - .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ - }, \ - } -#endif /* PWM_TMR4_2_CONFIG */ -#endif /* BSP_USING_PWM_TMR4_2 */ - -#ifdef BSP_USING_PWM_TMR4_3 -#ifndef PWM_TMR4_3_CONFIG -#define PWM_TMR4_3_CONFIG \ - { \ - .name = "pwm_t43", \ - .instance = CM_TMR4_3, \ - .channel = 0, \ - .stcTmr4Init = \ - { \ - .u16ClockDiv = TMR4_CLK_DIV1, \ - .u16PeriodValue = 0xFFFFU, \ - .u16CountMode = TMR4_MD_SAWTOOTH, \ - .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ - }, \ - .stcTmr4OcInit = \ - { \ - .u16CompareValue = 0x0000, \ - .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ - .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ - .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ - .u16BufLinkTransObject = 0U, \ - }, \ - .stcTmr4PwmInit = \ - { \ - .u16Mode = TMR4_PWM_MD_THROUGH, \ - .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ - .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ - }, \ - } -#endif /* PWM_TMR4_3_CONFIG */ -#endif /* BSP_USING_PWM_TMR4_3 */ - #endif /* BSP_USING_PWM_TMR4 */ #ifdef BSP_USING_PWM_TMR6 @@ -328,7 +264,7 @@ extern "C" { #ifndef PWM_TMR6_2_CONFIG #define PWM_TMR6_2_CONFIG \ { \ - .name = "pwm_t61", \ + .name = "pwm_t62", \ .instance = CM_TMR6_2, \ .channel = 0, \ .stcTmr6Init = \ @@ -375,7 +311,7 @@ extern "C" { #ifndef PWM_TMR6_3_CONFIG #define PWM_TMR6_3_CONFIG \ { \ - .name = "pwm_t61", \ + .name = "pwm_t63", \ .instance = CM_TMR6_3, \ .channel = 0, \ .stcTmr6Init = \ @@ -422,7 +358,7 @@ extern "C" { #ifndef PWM_TMR6_4_CONFIG #define PWM_TMR6_4_CONFIG \ { \ - .name = "pwm_t61", \ + .name = "pwm_t64", \ .instance = CM_TMR6_4, \ .channel = 0, \ .stcTmr6Init = \ @@ -465,194 +401,6 @@ extern "C" { } #endif /* PWM_TMR6_4_CONFIG */ #endif /* BSP_USING_PWM_TMR6_4 */ -#ifdef BSP_USING_PWM_TMR6_5 -#ifndef PWM_TMR6_5_CONFIG -#define PWM_TMR6_5_CONFIG \ - { \ - .name = "pwm_t61", \ - .instance = CM_TMR6_5, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ - } -#endif /* PWM_TMR6_5_CONFIG */ -#endif /* BSP_USING_PWM_TMR6_5 */ -#ifdef BSP_USING_PWM_TMR6_6 -#ifndef PWM_TMR6_6_CONFIG -#define PWM_TMR6_6_CONFIG \ - { \ - .name = "pwm_t61", \ - .instance = CM_TMR6_6, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ - } -#endif /* PWM_TMR6_6_CONFIG */ -#endif /* BSP_USING_PWM_TMR6_6 */ -#ifdef BSP_USING_PWM_TMR6_7 -#ifndef PWM_TMR6_7_CONFIG -#define PWM_TMR6_7_CONFIG \ - { \ - .name = "pwm_t61", \ - .instance = CM_TMR6_7, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ - } -#endif /* PWM_TMR6_7_CONFIG */ -#endif /* BSP_USING_PWM_TMR6_7 */ -#ifdef BSP_USING_PWM_TMR6_8 -#ifndef PWM_TMR6_8_CONFIG -#define PWM_TMR6_8_CONFIG \ - { \ - .name = "pwm_t61", \ - .instance = CM_TMR6_8, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ - } -#endif /* PWM_TMR6_8_CONFIG */ -#endif /* BSP_USING_PWM_TMR6_8 */ #endif /* BSP_USING_PWM_TMR6 */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/tmr_capture_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/tmr_capture_config.h index 65d4d8eed54..d147ec7d084 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/config/tmr_capture_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/tmr_capture_config.h @@ -39,7 +39,7 @@ extern "C" { .name = IC2_NAME, \ .ch = TMR6_CH_A, \ .clk_div = TMR6_CLK_DIV32, \ - .first_edge = TMR6_CAPT_COND_TRIGB_RISING, \ + .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ @@ -54,7 +54,7 @@ extern "C" { .name = IC3_NAME, \ .ch = TMR6_CH_B, \ .clk_div = TMR6_CLK_DIV16, \ - .first_edge = TMR6_CAPT_COND_TRIGC_FALLING, \ + .first_edge = TMR6_CAPT_COND_TRIGD_RISING, \ .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \ .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \ .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \ @@ -62,6 +62,21 @@ extern "C" { } #endif +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_4) +#define IC4_NAME "ic4" +#define INPUT_CAPTURE_CFG_TMR6_4 \ +{ \ + .name = IC4_NAME, \ + .ch = TMR6_CH_B, \ + .clk_div = TMR6_CLK_DIV16, \ + .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_PRIO, \ +} +#endif + #ifdef __cplusplus } #endif diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/linker_scripts/link.icf b/bsp/hc32/ev_hc32f334_lqfp64/board/linker_scripts/link.icf index 6279dc54ae1..27176e7c87c 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/linker_scripts/link.icf +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/linker_scripts/link.icf @@ -82,9 +82,9 @@ define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; /*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_cstack__ = 0x800; define symbol __ICFEDIT_size_proc_stack__ = 0x0; -define symbol __ICFEDIT_size_heap__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x0; /**** End of ICF editor section. ###ICF###*/ /******************************************************************************* diff --git a/bsp/hc32/ev_hc32f334_lqfp64/bsp_compile_ci.bat b/bsp/hc32/ev_hc32f334_lqfp64/bsp_compile_ci.bat new file mode 100644 index 00000000000..f35553ed5ab --- /dev/null +++ b/bsp/hc32/ev_hc32f334_lqfp64/bsp_compile_ci.bat @@ -0,0 +1,91 @@ +scons --attach=devices.adc +scons -j4 +scons --attach=default + +scons --attach=devices.crypto +scons -j4 +scons --attach=default + +scons --attach=devices.dac +scons -j4 +scons --attach=default + +scons --attach=devices.flash +scons -j4 +scons --attach=default + +scons --attach=devices.gpio +scons -j4 +scons --attach=default + +scons --attach=devices.hwtimer +scons -j4 +scons --attach=default + +scons --attach=devices.i2c +scons -j4 +scons --attach=default + +scons --attach=devices.input_capture +scons -j4 +scons --attach=default + +scons --attach=devices.mcan +scons -j4 +scons --attach=default + +scons --attach=devices.pm +scons -j4 +scons --attach=default + +scons --attach=devices.pulse_encoder_tmr6 +scons -j4 +scons --attach=default + +scons --attach=devices.pulse_encoder_tmra +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmr4 +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmr6 +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmra +scons -j4 +scons --attach=default + +scons --attach=devices.rtc +scons -j4 +scons --attach=default + +scons --attach=devices.soft_i2c +scons -j4 +scons --attach=default + +scons --attach=devices.spi +scons -j4 +scons --attach=default + +scons --attach=devices.uart_v1 +scons -j4 +scons --attach=default + +scons --attach=devices.uart_v2 +scons -j4 +scons --attach=default + +scons --attach=devices.watchdog_swdt +scons -j4 +scons --attach=default + +scons --attach=devices.watchdog_wdt +scons -j4 +scons --attach=default + +scons --attach=peripheral.spi_flash +scons -j4 +scons --attach=default diff --git a/bsp/hc32/ev_hc32f334_lqfp64/figures/board.png b/bsp/hc32/ev_hc32f334_lqfp64/figures/board.png index f1c984dbd15..3b38373a82c 100644 Binary files a/bsp/hc32/ev_hc32f334_lqfp64/figures/board.png and b/bsp/hc32/ev_hc32f334_lqfp64/figures/board.png differ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/project.uvprojx b/bsp/hc32/ev_hc32f334_lqfp64/project.uvprojx index 5e7b085e349..4052ca9128b 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/project.uvprojx +++ b/bsp/hc32/ev_hc32f334_lqfp64/project.uvprojx @@ -322,7 +322,7 @@ 0 0 1 - 0 + 1 0 0 0 diff --git a/bsp/hc32/ev_hc32f334_lqfp64/template.uvprojx b/bsp/hc32/ev_hc32f334_lqfp64/template.uvprojx index 847334da616..d8205236be3 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/template.uvprojx +++ b/bsp/hc32/ev_hc32f334_lqfp64/template.uvprojx @@ -325,7 +325,7 @@ 0 0 1 - 0 + 1 0 0 0 diff --git a/bsp/hc32/ev_hc32f448_lqfp80/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f448_lqfp80/.ci/attachconfig/ci.attachconfig.yml index 92d777ca640..7eb2f098c02 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/hc32/ev_hc32f448_lqfp80/.ci/attachconfig/ci.attachconfig.yml @@ -1,12 +1,133 @@ +# ------ device CI ------ +devices.adc: + kconfig: + - CONFIG_BSP_USING_ADC=y + - CONFIG_BSP_USING_ADC1=y + - CONFIG_BSP_ADC1_USING_DMA=y +devices.crypto: + kconfig: + - CONFIG_BSP_USING_HWCRYPTO=y + - CONFIG_BSP_USING_UQID=y + - CONFIG_BSP_USING_RNG=y + - CONFIG_BSP_USING_CRC=y + - CONFIG_BSP_USING_HASH=y +devices.dac: + kconfig: + - CONFIG_BSP_USING_DAC=y + - CONFIG_BSP_USING_DAC1=y +devices.flash: + kconfig: + - CONFIG_BSP_USING_ON_CHIP_FLASH=y + - CONFIG_RT_USING_FAL=y + - CONFIG_RT_USING_SPI=y + - CONFIG_RT_USING_SFUD=y devices.gpio: kconfig: - CONFIG_BSP_USING_GPIO=y +devices.hwtimer: + kconfig: + - CONFIG_BSP_USING_HWTIMER=y + - CONFIG_BSP_USING_TMRA_1=y +devices.i2c: + kconfig: - CONFIG_BSP_USING_I2C=y - - CONFIG_BSP_USING_I2C_HW=y - CONFIG_BSP_USING_I2C1=y - - CONFIG_BSP_USING_TCA9539=y - - CONFIG_BSP_USING_EXT_IO=y -devices.uart: + - CONFIG_BSP_I2C1_TX_USING_DMA=y + - CONFIG_BSP_I2C1_RX_USING_DMA=y +devices.input_capture: + kconfig: + - CONFIG_BSP_USING_INPUT_CAPTURE=y + - CONFIG_BSP_USING_INPUT_CAPTURE_TMR6=y + - CONFIG_BSP_USING_INPUT_CAPTURE_TMR6_1=y +devices.mcan: + kconfig: + - CONFIG_BSP_USING_MCAN=y + - CONFIG_BSP_USING_MCAN1=y + - CONFIG_RT_CAN_USING_CANFD=y + - CONFIG_RT_CAN_USING_HDR=y +devices.pm: + kconfig: + - CONFIG_BSP_USING_PM=y + - CONFIG_IDLE_THREAD_STACK_SIZE=512 +devices.pulse_encoder_tmr6: + kconfig: + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_TMR6_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER_TMR6_1=y +devices.pulse_encoder_tmra: + kconfig: + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_TMRA_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER_TMRA_1=y +devices.pwm_tmr4: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMR4=y + - CONFIG_BSP_USING_PWM_TMR4_1=y + - CONFIG_BSP_USING_PWM_TMR4_1_OUH=y + - CONFIG_BSP_USING_PWM_TMR4_1_OUL=y +devices.pwm_tmr6: kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMR6=y + - CONFIG_BSP_USING_PWM_TMR6_1=y + - CONFIG_BSP_USING_PWM_TMR6_1_A=y + - CONFIG_BSP_USING_PWM_TMR6_1_B=y +devices.pwm_tmra: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMRA=y + - CONFIG_BSP_USING_PWM_TMRA_1=y + - CONFIG_BSP_USING_PWM_TMRA_1_CH1=y + - CONFIG_BSP_USING_PWM_TMRA_1_CH2=y +devices.qspi: + kconfig: + - CONFIG_BSP_USING_QSPI=y + - CONFIG_BSP_QSPI_USING_DMA=y + - CONFIG_BSP_QSPI_USING_SOFT_CS=y +devices.rtc: + kconfig: + - CONFIG_BSP_USING_RTC=y + - CONFIG_RT_USING_ALARM=y +devices.soft_i2c: + kconfig: + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_I2C1_SW=y +devices.spi: + kconfig: + - CONFIG_BSP_USING_SPI=y + - CONFIG_BSP_USING_SPI1=y + - CONFIG_BSP_SPI1_TX_USING_DMA=y + - CONFIG_BSP_SPI1_RX_USING_DMA=y + - CONFIG_BSP_SPI_USING_DMA=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.uart_v1: + kconfig: + - CONFIG_RT_USING_SERIAL_V1=y + - CONFIG_BSP_USING_UART=y + - CONFIG_BSP_USING_UART1=y + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_UART1_RX_USING_DMA=y + - CONFIG_BSP_UART1_TX_USING_DMA=y +devices.uart_v2: + kconfig: + - CONFIG_RT_USING_SERIAL_V2=y - CONFIG_BSP_USING_UART=y - - CONFIG_BSP_USING_UART2=y + - CONFIG_BSP_USING_UART1=y + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_UART1_RX_USING_DMA=y + - CONFIG_BSP_UART1_TX_USING_DMA=y +devices.watchdog_swdt: + kconfig: + - CONFIG_BSP_USING_WDT_TMR=y + - CONFIG_BSP_USING_SWDT=y +devices.watchdog_wdt: + kconfig: + - CONFIG_BSP_USING_WDT_TMR=y + - CONFIG_BSP_USING_WDT=y + +# ------ peripheral CI ------ +peripheral.spi_flash: + kconfig: + - CONFIG_BSP_USING_SPI_FLASH=y diff --git a/bsp/hc32/ev_hc32f448_lqfp80/README.md b/bsp/hc32/ev_hc32f448_lqfp80/README.md index aedac9baecb..e614500cca8 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/README.md +++ b/bsp/hc32/ev_hc32f448_lqfp80/README.md @@ -1,8 +1,8 @@ -# XHSC EV_F448_LQ80_Rev1.0 开发板 BSP 说明 +# XHSC EV_F448_LQ80 开发板 BSP 说明 ## 简介 -本文档为小华半导体为 EV_F448_LQ80_Rev1.0 开发板提供的 BSP (板级支持包) 说明。 +本文档为小华半导体为 EV_F448_LQ80 开发板提供的 BSP (板级支持包) 说明。 主要内容如下： @@ -14,79 +14,65 @@ ## 开发板介绍 -EV_F448_LQ80_Rev1.0 是 XHSC 官方推出的开发板，搭载 HC32F448MCTI 芯片，基于 ARM Cortex-M4 内核，最高主频 200 MHz，具有丰富的板载资源，可以充分发挥 HC32F448MCTI 的芯片性能。 +EV_F448_LQ80 是 XHSC 官方推出的开发板，搭载 HC32F448MCTI 芯片，基于 ARM Cortex-M4 内核，最高主频 200 MHz，具有丰富的板载资源，可以充分发挥 HC32F448MCTI 的芯片性能。 开发板外观如下图所示： ![board](figures/board.png) -EV_F448_LQ80_Rev1.0 开发板常用 **板载资源** 如下： - -- **MCU** - - HC32F448MCTI - - 主频200MHz - - 256KB FLASH - - 68KB RAM -- **外部Memory** - - BL24C256（EEPROM, 256Kbits） - - W25Q64（SPI NOR，64MB） - - IS62WV51216（SRAM， 1MB） -- **常用外设** - - LED: 4 个，User LED（LED0，LED1，LED2，LED3）。 - - 按键: 5 个，矩阵键盘（K1~K4）， WAKEUP（K5），RESET（K0） -- **常用接口** - - USB转串口 - - CAN DB9接口 * 2 - - TFT接口 - - SmartCard接口 - - I2C/USART/SPI接口 -- **调试接口** - - 板载DAP调试器 - - 标准JTAG/SWD/Trace - -开发板更多详细信息请参考小华半导体半导体[EV_F448_LQ80_Rev1.0](https://www.xhsc.com.cn) +EV_F448_LQ80 开发板常用 **板载资源** 如下： + +- MCU：HC32F448MCTI，主频200MHz，256KB FLASH，68KB RAM +- 外部RAM：IS61LV6416（SRAM， 128KB） +- 常用外设 + - LED：3 个，User LED(LED0、LED1、LED2) + - 按键：6个，矩阵键盘（K1~K4）， WAKEUP（K5），RESET（K0） +- 常用接口：LCD接口、CAN接口、LIN接口。 +- 调试接口：板载DAP调试器（含USB转串口）、标准JTAG/SWD。 + +开发板更多详细信息请参考小华半导体半导体[EV_F448_LQ80](https://www.xhsc.com.cn) ## 外设支持 本 BSP 目前对外设的支持情况如下： -| **板载外设** | **支持情况** | **备注** | -|:-------- |:--------:|:--------:| -| USB 转串口 | 支持 | 使用 UART2 | -| LED | 支持 | LED1~4 | - -| **片上外设** | **支持情况** | **备注** | -|:------------- |:--------:|:------------------------------------------:| -| Crypto | 支持 | AES, CRC, HASH, RNG, UID | -| DAC | 支持 | | -| ADC | 支持 | ADC1: CH10, CH11,
ADC3: CH1 | -| CAN | 支持 | CAN1、CAN2 | -| GPIO | 支持 | PA0, PA1... PH2 ---> PIN: 0, 1...82 | -| I2C | 支持 | 软件模拟
硬件I2C1~2
I2C1支持EEPROM（BL24C256） | -| PM | 支持 | | -| Lptimer | 支持 | | -| Hwtimer | 支持 | Hwtimer1~5 | -| Pulse_encoder | 支持 | | -| PWM | 支持 | | -| RTC | 支持 | 闹钟精度为1分钟 | -| WDT | 支持 | | -| I2C | 支持 | 软件、硬件 I2C | -| QSPI | 支持 | | -| SPI | 支持 | SPI1~3
SPI1支持W25Q | -| UART | 支持 | UART1~6
UART2为console使用 | +| **板载外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| USB 转串口 | 支持 | 使用 UART2 | + +| **片上外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| ADC | 支持 | | +| Crypto | 支持 | CRC，HASH，RNG | +| DAC | 支持 | | +| FLASH | 支持 | | +| GPIO | 支持 | PA0，PA1...PH2 ---> PIN：0，1...82 | +| HwTimer | 支持 | | +| I2C | 支持 | 软件、硬件 I2C | +| InputCapture | 支持 | | +| MCAN | 支持 | | +| PM | 支持 | | +| PulseEncoder | 支持 | | +| PWM | 支持 | | +| QSPI | 支持 | | +| RTC | 支持 | 闹钟精度为1分钟 | +| SPI | 支持 | | +| UART V1 & V2 | 支持 | | +| WDT | 支持 | | ## 使用说明 使用说明分为如下两个章节： - 快速上手 - + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 - 进阶使用 - + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + ### 快速上手 本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 @@ -110,7 +96,7 @@ USB虚拟COM端口默认连接串口2，在终端工具里打开相应的串口 ``` \ | / - RT - Thread Operating System - / | \ 5.0.1 build Feb 4 2024 16:44:26 + / | \ 4.1.0 build Apr 24 2022 13:32:39 2006 - 2022 Copyright by RT-Thread team msh > ``` @@ -127,12 +113,6 @@ msh > 4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 -## 注意事项 - -| 板载外设 | 模式 | 注意事项 | -| ---- | ---- | ------------------------------------------------------------------------------------------------------ | -| USB | host | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 | - ## 联系人信息 维护人: diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig b/bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig index 6a543d53b8d..5859ec06f4d 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig @@ -662,6 +662,22 @@ menu "On-chip Peripheral Drivers" default n endif + menuconfig BSP_USING_INPUT_CAPTURE + bool "Enable Input Capture" + default n + select RT_USING_INPUT_CAPTURE + if BSP_USING_INPUT_CAPTURE + menuconfig BSP_USING_INPUT_CAPTURE_TMR6 + bool "Use Timer6 As The Input Capture" + default n + if BSP_USING_INPUT_CAPTURE_TMR6 + config BSP_USING_INPUT_CAPTURE_TMR6_1 + bool "unit 1" + config BSP_USING_INPUT_CAPTURE_TMR6_2 + bool "unit 2" + endif + endif + menuconfig BSP_USING_SENSOR bool "Enable SENSOR" default n diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.c b/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.c index 63ae63320e0..2df8c3583a1 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.c +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.c @@ -332,6 +332,31 @@ rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x) #endif #endif +#if defined (BSP_USING_INPUT_CAPTURE) +rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)tmr_instance) + { +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) + case (rt_uint32_t)CM_TMR6_1: + GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, INPUT_CAPTURE_TMR6_1_FUNC); + break; +#endif +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) + case (rt_uint32_t)CM_TMR6_2: + GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, INPUT_CAPTURE_TMR6_2_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + #ifdef RT_USING_PM #define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode) diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.h index 487e4f2f88e..b67c66df7cf 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.h @@ -252,6 +252,19 @@ #endif +#if defined(BSP_USING_INPUT_CAPTURE) + #if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) + #define INPUT_CAPTURE_TMR6_1_FUNC (GPIO_FUNC_3) + #define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_A) + #define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_08) + #endif + #if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) + #define INPUT_CAPTURE_TMR6_2_FUNC (GPIO_FUNC_3) + #define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_B) + #define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_02) + #endif +#endif + #if defined(BSP_USING_QSPI) #ifndef BSP_QSPI_USING_SOFT_CS /* QSSN */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/irq_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/irq_config.h index e1d962ab910..2e0cce799f4 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/config/irq_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/irq_config.h @@ -191,17 +191,11 @@ extern "C" { #if defined(BSP_USING_MCAN1) #define BSP_MCAN1_INT0_IRQ_NUM MCAN1_INT0_IRQn #define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT - -#define BSP_MCAN1_INT1_IRQ_NUM MCAN1_INT1_IRQn -#define BSP_MCAN1_INT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_MCAN1 */ #if defined(BSP_USING_MCAN2) #define BSP_MCAN2_INT0_IRQ_NUM MCAN2_INT0_IRQn #define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT - -#define BSP_MCAN2_INT1_IRQ_NUM MCAN2_INT1_IRQn -#define BSP_MCAN2_INT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_MCAN2 */ #if defined(RT_USING_ALARM) @@ -253,6 +247,18 @@ extern "C" { #define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */ +#if defined(BSP_USING_INPUT_CAPTURE) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#endif + #ifdef __cplusplus } #endif diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/tmr_capture_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/tmr_capture_config.h new file mode 100644 index 00000000000..d5aa901a6cc --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/tmr_capture_config.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-14 CDT first version + */ + +#ifndef __IC_CONFIG_H__ +#define __IC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) +#define IC1_NAME "ic1" +#define INPUT_CAPTURE_CFG_TMR6_1 \ +{ \ + .name = IC1_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \ +} +#endif + +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) +#define IC2_NAME "ic2" +#define INPUT_CAPTURE_CFG_TMR6_2 \ +{ \ + .name = IC2_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_TRIGB_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \ +} +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __IC_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/drv_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/drv_config.h index 13e84fa275f..6f0f5e4d826 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/drv_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/drv_config.h @@ -30,6 +30,7 @@ extern "C" { #include "qspi_config.h" #include "pulse_encoder_config.h" #include "timer_config.h" +#include "tmr_capture_config.h" #ifdef __cplusplus } diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.icf b/bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.icf index f9aef6bc410..c0b90175c16 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.icf +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.icf @@ -75,9 +75,9 @@ define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; /*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0xC00; +define symbol __ICFEDIT_size_cstack__ = 0x800; define symbol __ICFEDIT_size_proc_stack__ = 0x0; -define symbol __ICFEDIT_size_heap__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x0; /**** End of ICF editor section. ###ICF###*/ /******************************************************************************* diff --git a/bsp/hc32/ev_hc32f448_lqfp80/bsp_compile_ci.bat b/bsp/hc32/ev_hc32f448_lqfp80/bsp_compile_ci.bat new file mode 100644 index 00000000000..12d5baf2780 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/bsp_compile_ci.bat @@ -0,0 +1,96 @@ +scons --attach=devices.adc +scons -j4 +scons --attach=default + +scons --attach=devices.crypto +scons -j4 +scons --attach=default + +scons --attach=devices.dac +scons -j4 +scons --attach=default + +scons --attach=devices.flash +scons -j4 +scons --attach=default + +scons --attach=devices.gpio +scons -j4 +scons --attach=default + +scons --attach=devices.hwtimer +scons -j4 +scons --attach=default + +scons --attach=devices.i2c +scons -j4 +scons --attach=default + +scons --attach=devices.input_capture +scons -j4 +scons --attach=default + +scons --attach=devices.mcan +scons -j4 +scons --attach=default + +scons --attach=devices.pm +scons -j4 +scons --attach=default + +scons --attach=devices.pulse_encoder_tmr6 +scons -j4 +scons --attach=default + +scons --attach=devices.pulse_encoder_tmra +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmr4 +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmr6 +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmra +scons -j4 +scons --attach=default + +scons --attach=devices.qspi +scons -j4 +scons --attach=default + +scons --attach=devices.rtc +scons -j4 +scons --attach=default + +scons --attach=devices.soft_i2c +scons -j4 +scons --attach=default + +scons --attach=devices.spi +scons -j4 +scons --attach=default + +scons --attach=devices.uart_v1 +scons -j4 +scons --attach=default + +scons --attach=devices.uart_v2 +scons -j4 +scons --attach=default + +scons --attach=devices.watchdog_swdt +scons -j4 +scons --attach=default + +scons --attach=devices.watchdog_wdt +scons -j4 +scons --attach=default + + +scons --attach=peripheral.spi_flash +scons -j4 +scons --attach=default diff --git a/bsp/hc32/ev_hc32f448_lqfp80/project.uvprojx b/bsp/hc32/ev_hc32f448_lqfp80/project.uvprojx index 89d9b64fe61..aaf9e7b389b 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/project.uvprojx +++ b/bsp/hc32/ev_hc32f448_lqfp80/project.uvprojx @@ -323,7 +323,7 @@ 0 0 1 - 0 + 1 0 0 0 diff --git a/bsp/hc32/ev_hc32f448_lqfp80/template.uvprojx b/bsp/hc32/ev_hc32f448_lqfp80/template.uvprojx index ac0502478ba..c79587809b5 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/template.uvprojx +++ b/bsp/hc32/ev_hc32f448_lqfp80/template.uvprojx @@ -326,7 +326,7 @@ 0 0 1 - 0 + 1 0 0 0 diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f460_lqfp100_v2/.ci/attachconfig/ci.attachconfig.yml index d3686da6699..047a4483ef7 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/.ci/attachconfig/ci.attachconfig.yml @@ -1,7 +1,166 @@ +# ------ device CI ------ +devices.adc: + kconfig: + - CONFIG_BSP_USING_ADC=y + - CONFIG_BSP_USING_ADC1=y + - CONFIG_BSP_ADC1_USING_DMA=y +devices.can: + kconfig: + - CONFIG_BSP_USING_CAN=y + - CONFIG_BSP_USING_CAN1=y + - CONFIG_RT_CAN_USING_HDR=y +devices.crypto: + kconfig: + - CONFIG_BSP_USING_HWCRYPTO=y + - CONFIG_BSP_USING_UQID=y + - CONFIG_BSP_USING_RNG=y + - CONFIG_BSP_USING_CRC=y + - CONFIG_BSP_USING_HASH=y +devices.flash: + kconfig: + - CONFIG_BSP_USING_ON_CHIP_FLASH=y + - CONFIG_RT_USING_FAL=y + - CONFIG_RT_USING_SPI=y + - CONFIG_RT_USING_SFUD=y devices.gpio: kconfig: - CONFIG_BSP_USING_GPIO=y -devices.uart: +devices.hwtimer: + kconfig: + - CONFIG_BSP_USING_HWTIMER=y + - CONFIG_BSP_USING_TMRA_1=y +devices.i2c: + kconfig: + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_I2C1=y + - CONFIG_BSP_I2C1_TX_USING_DMA=y + - CONFIG_BSP_I2C1_RX_USING_DMA=y +devices.input_capture: + kconfig: + - CONFIG_BSP_USING_INPUT_CAPTURE=y + - CONFIG_BSP_USING_INPUT_CAPTURE_TMR6=y + - CONFIG_BSP_USING_INPUT_CAPTURE_TMR6_1=y +devices.pm: + kconfig: + - CONFIG_BSP_USING_PM=y + - CONFIG_IDLE_THREAD_STACK_SIZE=512 +devices.pulse_encoder_tmr6: + kconfig: + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_TMR6_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER_TMR6_1=y +devices.pulse_encoder_tmra: + kconfig: + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_TMRA_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER_TMRA_1=y +devices.pwm_tmr4: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMR4=y + - CONFIG_BSP_USING_PWM_TMR4_1=y + - CONFIG_BSP_USING_PWM_TMR4_1_OUH=y + - CONFIG_BSP_USING_PWM_TMR4_1_OUL=y +devices.pwm_tmr6: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMR6=y + - CONFIG_BSP_USING_PWM_TMR6_1=y + - CONFIG_BSP_USING_PWM_TMR6_1_A=y + - CONFIG_BSP_USING_PWM_TMR6_1_B=y +devices.pwm_tmra: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMRA=y + - CONFIG_BSP_USING_PWM_TMRA_1=y + - CONFIG_BSP_USING_PWM_TMRA_1_CH1=y + - CONFIG_BSP_USING_PWM_TMRA_1_CH2=y +devices.qspi: + kconfig: + - CONFIG_BSP_USING_QSPI=y + - CONFIG_BSP_QSPI_USING_DMA=y + - CONFIG_BSP_QSPI_USING_SOFT_CS=y +devices.rtc: kconfig: + - CONFIG_BSP_USING_RTC=y + - CONFIG_RT_USING_ALARM=y +devices.sdio: + kconfig: + - CONFIG_BSP_USING_SDIO=y + - CONFIG_BSP_USING_SDIO1=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.soft_i2c: + kconfig: + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_I2C1_SW=y +devices.spi: + kconfig: + - CONFIG_BSP_USING_SPI=y + - CONFIG_BSP_USING_SPI1=y + - CONFIG_BSP_SPI1_TX_USING_DMA=y + - CONFIG_BSP_SPI1_RX_USING_DMA=y + - CONFIG_BSP_SPI_USING_DMA=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.uart_v1: + kconfig: + - CONFIG_RT_USING_SERIAL_V1=y - CONFIG_BSP_USING_UART=y - - CONFIG_BSP_USING_UART4=y + - CONFIG_BSP_USING_UART1=y + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_UART1_RX_USING_DMA=y + - CONFIG_BSP_UART1_TX_USING_DMA=y +devices.uart_v2: + kconfig: + - CONFIG_RT_USING_SERIAL_V2=y + - CONFIG_BSP_USING_UART=y + - CONFIG_BSP_USING_UART1=y + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_UART1_RX_USING_DMA=y + - CONFIG_BSP_UART1_TX_USING_DMA=y +devices.usb_hs_device: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBD=y + - CONFIG_BSP_USING_USBHS=y + - CONFIG_BSP_USING_USBD_HS=y + - CONFIG_RT_USB_DEVICE_MSTORAGE=y +devices.usb_hs_host: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBH=y + - CONFIG_BSP_USING_USBHS=y + - CONFIG_BSP_USING_USBH_HS=y + - CONFIG_RT_USBH_MSTORAGE=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.usb_fs_device: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBD=y + - CONFIG_BSP_USING_USBFS=y + - CONFIG_BSP_USING_USBD_FS=y + - CONFIG_RT_USB_DEVICE_MSTORAGE=y +devices.usb_fs_host: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBH=y + - CONFIG_BSP_USING_USBFS=y + - CONFIG_BSP_USING_USBH_FS=y + - CONFIG_RT_USBH_MSTORAGE=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.watchdog_swdt: + kconfig: + - CONFIG_BSP_USING_WDT_TMR=y + - CONFIG_BSP_USING_SWDT=y +devices.watchdog_wdt: + kconfig: + - CONFIG_BSP_USING_WDT_TMR=y + - CONFIG_BSP_USING_WDT=y + +# ------ peripheral CI ------ +peripheral.spi_flash: + kconfig: + - CONFIG_BSP_USING_SPI_FLASH=y diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/README.md b/bsp/hc32/ev_hc32f460_lqfp100_v2/README.md index 1b9e1d1db07..7c6a879aef8 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/README.md +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/README.md @@ -22,12 +22,12 @@ EV_F460_LQ100_V2 是 XHSC 官方推出的开发板，搭载 HC32F460PETB 芯片 EV_F460_LQ100_V2 开发板常用 **板载资源** 如下： -- MCU: HC32F460PETB，主频200MHz，512KB FLASH，192KB RAM +- MCU：HC32F460PETB，主频200MHz，512KB FLASH，192KB RAM - 常用外设 - - LED: 4 个，User LED(LED0，LED1，LED2，LED3)。 - - 按键: 11 个，矩阵键盘(K1~K9), WAKEUP(K10), RESET(K11) -- 常用接口: USB转串口、SD卡接口、USB FS、3.5mm耳机接口、Line in接口、喇叭接口 -- 调试接口: 板载DAP调试器、标准JTAG/SWD + - LED：4 个，User LED(LED0、LED1、LED2、LED3)。 + - 按键：11 个，矩阵键盘(K1~K9)、WAKEUP(K10)、RESET(K11) +- 常用接口：SD卡接口、USB FS接口、3.5mm耳机接口、Line in接口、CAN接口。 +- 调试接口：板载DAP调试器（含USB转串口）、标准JTAG/SWD。 开发板更多详细信息请参考小华半导体半导体[EV_F460_LQ100_V2](https://www.xhsc.com.cn) @@ -35,31 +35,44 @@ EV_F460_LQ100_V2 开发板常用 **板载资源** 如下： 本 BSP 目前对外设的支持情况如下： -| **板载外设** | **支持情况** | **备注** | -|:-------- |:--------:|:--------:| -| USB 转串口 | 支持 | 使用 UART4 | -| LED | 支持 | LED | - -| **片上外设** | **支持情况** | **备注** | -|:-------- |:--------:|:-----------------------------------:| -| ADC | 支持 | ADC1~2 | -| CAN | 支持 | CAN1 | -| GPIO | 支持 | PA0, PA1... PH2 ---> PIN: 0, 1...82 | -| I2C | 支持 | 软件 | -| UART | 支持 | UART1~4 | +| **板载外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| USB 转串口 | 支持 | 使用 UART4 | + +| **片上外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| ADC | 支持 | | +| CAN | 支持 | | +| Crypto | 支持 | CRC，HASH，RNG | +| FLASH | 支持 | | +| GPIO | 支持 | PA0，PA1... PH2 ---> PIN：0，1...82 | +| HwTimer | 支持 | | +| I2C | 支持 | 软件、硬件 I2C | +| InputCapture | 支持 | | +| PM | 支持 | | +| PulseEncoder | 支持 | | +| PWM | 支持 | | +| QSPI | 支持 | | +| RTC | 支持 | 闹钟精度为1分钟 | +| SDIO | 支持 | | +| SPI | 支持 | | +| UART V1 & V2 | 支持 | | +| USB | 支持 | USBFS Core， device/host模式 | +| WDT | 支持 | | ## 使用说明 使用说明分为如下两个章节： - 快速上手 - + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 - 进阶使用 - + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + ### 快速上手 本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 @@ -83,7 +96,7 @@ USB虚拟COM端口默认连接串口4，在终端工具里打开相应的串口 ``` \ | / - RT - Thread Operating System - / | \ 4.1.1 build May 25 2022 08:55:55 + / | \ 4.1.0 build Apr 24 2022 13:32:39 2006 - 2022 Copyright by RT-Thread team msh > ``` @@ -102,11 +115,14 @@ msh > ## 注意事项 -| 板载外设 | 模式 | 注意事项 | -| -------- | ------ | ------------------------------------------------------------ | -| USB | device | 由于RTT抽象层的设计，当配置为CDC设备时，打开USB虚拟串口，需使能流控的DTR信号。（如使用SSCOM串口助手打开USB虚拟串口时，勾选DTR选框） | -| USB | host | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 | -| USB | host | 目前仅实现并测试了对U盘的支持。 | +| 板载外设 | 模式 | 协议栈 | 注意事项 | +| -------- | ------ | :------------: | ------------------------------------------------------------ | +| USB | device | ALL | 由于协议栈的设计，当配置为CDC设备时，打开USB虚拟串口，需使能流控的DTR信号。（如使用SSCOM串口助手打开USB虚拟串口时，勾选DTR选框） | +| USB | host | RTT legacy USB | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 | +| USB | host | RTT legacy USB | 目前仅实现并测试了对U盘的支持。 | +| USB | ALL | ALL | CherryUSB 与 RTT legacy USB 组件不可同时使用;
CherryUSB与 ”On-Chip Peripheral Driver---> []Enable USB“ 不可同时使能及配置。 | +| USB | ALL | RTT legacy USB | 通过“board/config/usb_config/usb_app_conf.h” 进行应用个性化配置（主要为FIFO分配） | +| USB | ALL | CherryUSB | 通过“board/ports/usb_config.h”进行应用个性化配置（如FIFO分配、是否使用DMA[Device]等） | ## 联系人信息 diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig index 7a431c98b7d..23155b14f4b 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig @@ -68,7 +68,7 @@ menu "On-chip Peripheral Drivers" int "Set UART1 RX DMA ping-pong buffer size" range 32 65535 depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA - default 64 + default 64 endif menuconfig BSP_USING_UART2 @@ -101,7 +101,7 @@ menu "On-chip Peripheral Drivers" int "Set UART2 RX DMA ping-pong buffer size" range 32 65535 depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA - default 64 + default 64 endif menuconfig BSP_USING_UART3 @@ -134,7 +134,7 @@ menu "On-chip Peripheral Drivers" int "Set UART3 RX DMA ping-pong buffer size" range 32 65535 depends on RT_USING_SERIAL_V2 && BSP_UART3_RX_USING_DMA - default 64 + default 64 endif menuconfig BSP_USING_UART4 @@ -167,7 +167,7 @@ menu "On-chip Peripheral Drivers" int "Set UART4 RX DMA ping-pong buffer size" range 32 65535 depends on RT_USING_SERIAL_V2 && BSP_UART4_RX_USING_DMA - default 64 + default 64 endif endif @@ -377,7 +377,7 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT if BSP_USING_WDT_TMR config BSP_USING_WDT - bool + bool default y config BSP_WDT_CONTINUE_COUNT @@ -562,6 +562,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_USB bool "Enable USB" default n + depends on !RT_USING_CHERRYUSB select RT_USING_USB_DEVICE if BSP_USING_USBD select RT_USING_USB_HOST if BSP_USING_USBH if BSP_USING_USB diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.c b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.c index 1e03c37f5ee..ba3672a90a6 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.c +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.c @@ -32,7 +32,7 @@ void SystemClock_Config(void) { stc_clock_xtal_init_t stcXtalInit; stc_clock_pll_init_t stcMpllInit; -#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) stc_clock_pllx_init_t stcUpllInit; #endif #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) @@ -80,7 +80,7 @@ void SystemClock_Config(void) /* Switch system clock source to MPLL. */ CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); -#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) /* PLLX for USB */ (void)CLK_PLLxStructInit(&stcUpllInit); /* VCO = (8/2)*120 = 480MHz*/ @@ -113,7 +113,7 @@ void PeripheralClock_Config(void) CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK); #endif -#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) CLK_SetUSBClockSrc(CLK_USBCLK_PLLXP); #endif } diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.c b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.c index 43898a37a42..abeef5591bb 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.c +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.c @@ -366,6 +366,27 @@ rt_err_t rt_hw_usbfs_board_init(void) } #endif +#if defined(RT_USING_CHERRYUSB) +rt_err_t rt_hw_usbfs_board_init(uint8_t devmode) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBF_DM_PORT, USBF_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBF_DP_PORT, USBF_DP_PIN, &stcGpioCfg); + if (0U != devmode) + { + GPIO_SetFunc(USBF_VBUS_PORT, USBF_VBUS_PIN, USBF_VBUS_FUNC); /* VBUS */ + } + else + { + GPIO_SetFunc(USBF_DRVVBUS_PORT, USBF_DRVVBUS_PIN, USBF_DRVVBUS_FUNC); /* DRV VBUS */ + } + return RT_EOK; +} +#endif + #if defined(BSP_USING_QSPI) rt_err_t rt_hw_qspi_board_init(void) { diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.h index d247e6e2a44..48a4d29a19c 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.h @@ -15,7 +15,9 @@ #include #include "hc32_ll.h" #include "drv_config.h" - +#if defined(RT_USING_CHERRYUSB) + #include "usb_config.h" +#endif /************************* XTAL port **********************/ #define XTAL_PORT (GPIO_PORT_H) @@ -242,8 +244,15 @@ #endif #endif -#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) - #if defined(BSP_USING_USBFS) +#if defined(RT_USING_CHERRYUSB) + #if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || \ + defined(BSP_USING_USBFS) || defined(RT_USING_USB) + #error "When using CherryUSB, Please donot Enable 'On-Chip Peripheral Driver---> []Enable USB' or using USB legacy version!" + #endif +#endif + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) + #if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) /* USBFS Core*/ #define USBF_DP_PORT (GPIO_PORT_A) #define USBF_DP_PIN (GPIO_PIN_12) diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/irq_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/irq_config.h index 62122c63948..6290ce25438 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/irq_config.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/irq_config.h @@ -204,7 +204,7 @@ extern "C" { #define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* RT_USING_ALARM */ -#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) #define BSP_USBFS_GLB_IRQ_NUM INT003_IRQn #define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_USBD */ diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.icf b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.icf index a85e876d63e..54ab4f758ba 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.icf +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.icf @@ -73,9 +73,9 @@ define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; /*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_cstack__ = 0x800; define symbol __ICFEDIT_size_proc_stack__ = 0x0; -define symbol __ICFEDIT_size_heap__ = 0x2000; +define symbol __ICFEDIT_size_heap__ = 0x0; /**** End of ICF editor section. ###ICF###*/ /******************************************************************************* diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.ld b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.ld index 707126ba630..82e7fe0a8ec 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.ld +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.ld @@ -88,6 +88,12 @@ SECTIONS __rt_init_end = .; . = ALIGN(4); + /* section for CherryUSB. */ + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(4); _etext = .; } >FLASH diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/usb_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/usb_config.h new file mode 100644 index 00000000000..723f0b19040 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/usb_config.h @@ -0,0 +1,307 @@ +/* + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-08 CDT first version + */ + +#ifndef CHERRYUSB_CONFIG_H +#define CHERRYUSB_CONFIG_H + +/* ================ USB common Configuration ================ */ + +#ifdef __RTTHREAD__ + #include + + #define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) +#else + #define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) +#endif + +#ifndef CONFIG_USB_DBG_LEVEL + #define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#endif + +/* Enable print with color */ +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +// #define CONFIG_USB_DCACHE_ENABLE + +/* data align size when use dma or use dcache */ +#ifdef CONFIG_USB_DCACHE_ENABLE + #define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64 +#else + #define CONFIG_USB_ALIGN_SIZE 4 +#endif + +/* attribute data into no cache ram */ +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) + +/* use usb_memcpy default for high performance but cost more flash memory. + * And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4. +*/ +// #define CONFIG_USB_MEMCPY_DISABLE + +/* ================= USB Device Stack Configuration ================ */ + +/* Ep0 in and out transfer buffer */ +#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN + #define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#endif + +/* Send ep0 in data from user buffer instead of copying into ep0 reqdata + * Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE +*/ +// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY + +/* Check if the input descriptor is correct */ +// #define CONFIG_USBDEV_DESC_CHECK + +/* Enable test mode */ +// #define CONFIG_USBDEV_TEST_MODE + +/* enable advance desc register api */ +#define CONFIG_USBDEV_ADVANCE_DESC + +/* move ep0 setup handler from isr to thread */ +// #define CONFIG_USBDEV_EP0_THREAD + +#ifndef CONFIG_USBDEV_EP0_PRIO + #define CONFIG_USBDEV_EP0_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_EP0_STACKSIZE + #define CONFIG_USBDEV_EP0_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_LUN + #define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE + #define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#endif + +#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING + #define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING + #define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_VERSION_STRING + #define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +/* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */ +// #define CONFIG_USBDEV_MSC_POLLING + +/* move msc read & write from isr to thread */ +// #define CONFIG_USBDEV_MSC_THREAD + +#ifndef CONFIG_USBDEV_MSC_PRIO + #define CONFIG_USBDEV_MSC_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MSC_STACKSIZE + #define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE + #define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS + #define CONFIG_USBDEV_MTP_MAX_OBJECTS 256 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME + #define CONFIG_USBDEV_MTP_MAX_PATHNAME 256 +#endif + +#define CONFIG_USBDEV_MTP_THREAD + +#ifndef CONFIG_USBDEV_MTP_PRIO + #define CONFIG_USBDEV_MTP_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MTP_STACKSIZE + #define CONFIG_USBDEV_MTP_STACKSIZE 4096 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE + #define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ +#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE + #define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID + #define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC + #define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#endif + +#define CONFIG_USBDEV_RNDIS_USING_LWIP +#define CONFIG_USBDEV_CDC_ECM_USING_LWIP + +/* ================ USB HOST Stack Configuration ================== */ + +#define CONFIG_USBHOST_MAX_RHPORTS 1 +#define CONFIG_USBHOST_MAX_EXTHUBS 1 +#define CONFIG_USBHOST_MAX_EHPORTS 4 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 4 + +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO + #define CONFIG_USBHOST_PSC_PRIO 0 +#endif +#ifndef CONFIG_USBHOST_PSC_STACKSIZE + #define CONFIG_USBHOST_PSC_STACKSIZE 2048 +#endif + +//#define CONFIG_USBHOST_GET_STRING_DESC + +// #define CONFIG_USBHOST_MSOS_ENABLE +#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE + #define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#endif + +/* Ep0 max transfer buffer */ +#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN + #define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#endif + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT + #define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT + #define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#endif + +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#endif + +#define CONFIG_USBHOST_BLUETOOTH_HCI_H4 +// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG + +#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE + #define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#endif +#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE + #define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#endif + +/* ================ USB Device Port Configuration ================*/ + +#ifndef CONFIG_USBDEV_MAX_BUS + #define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip +#endif + +#ifndef CONFIG_USBDEV_EP_NUM + #define CONFIG_USBDEV_EP_NUM 8 +#endif + +// #define CONFIG_USBDEV_SOF_ENABLE + +/* ---------------- DWC2 Configuration ---------------- */ +/* enable dwc2 buffer dma mode for device +*/ +// #define CONFIG_USB_DWC2_DMA_ENABLE + +/* Defined FS Core device FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE (32) + +/* Defined FS Core host FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE (64) + +/* Defined FS Core total FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE (320) + +/* ================ USB Host Port Configuration ==================*/ +#ifndef CONFIG_USBHOST_MAX_BUS + #define CONFIG_USBHOST_MAX_BUS 1 +#endif + +#ifndef CONFIG_USBHOST_PIPE_NUM + #define CONFIG_USBHOST_PIPE_NUM 10 +#endif + + +#ifndef usb_phyaddr2ramaddr + #define usb_phyaddr2ramaddr(addr) (addr) +#endif + +#ifndef usb_ramaddr2phyaddr + #define usb_ramaddr2phyaddr(addr) (addr) +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/bsp_compile_ci.bat b/bsp/hc32/ev_hc32f460_lqfp100_v2/bsp_compile_ci.bat new file mode 100644 index 00000000000..5ae6c2aa698 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/bsp_compile_ci.bat @@ -0,0 +1,112 @@ +scons --attach=devices.adc +scons -j4 +scons --attach=default + +scons --attach=devices.can +scons -j4 +scons --attach=default + +scons --attach=devices.crypto +scons -j4 +scons --attach=default + +scons --attach=devices.flash +scons -j4 +scons --attach=default + +scons --attach=devices.gpio +scons -j4 +scons --attach=default + +scons --attach=devices.hwtimer +scons -j4 +scons --attach=default + +scons --attach=devices.i2c +scons -j4 +scons --attach=default + +scons --attach=devices.input_capture +scons -j4 +scons --attach=default + +scons --attach=devices.pm +scons -j4 +scons --attach=default + +scons --attach=devices.pulse_encoder_tmr6 +scons -j4 +scons --attach=default + +scons --attach=devices.pulse_encoder_tmra +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmr4 +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmr6 +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmra +scons -j4 +scons --attach=default + +scons --attach=devices.qspi +scons -j4 +scons --attach=default + +scons --attach=devices.rtc +scons -j4 +scons --attach=default + +scons --attach=devices.sdio +scons -j4 +scons --attach=default + +scons --attach=devices.soft_i2c +scons -j4 +scons --attach=default + +scons --attach=devices.spi +scons -j4 +scons --attach=default + +scons --attach=devices.uart_v1 +scons -j4 +scons --attach=default + +scons --attach=devices.uart_v2 +scons -j4 +scons --attach=default + +scons --attach=devices.usb_hs_device +scons -j4 +scons --attach=default + +scons --attach=devices.usb_hs_host +scons -j4 +scons --attach=default + +scons --attach=devices.usb_fs_device +scons -j4 +scons --attach=default + +scons --attach=devices.usb_fs_host +scons -j4 +scons --attach=default + +scons --attach=devices.watchdog_swdt +scons -j4 +scons --attach=default + +scons --attach=devices.watchdog_wdt +scons -j4 +scons --attach=default + + +scons --attach=peripheral.spi_flash +scons -j4 +scons --attach=default diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvprojx b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvprojx index 376544be85a..429c5c2857c 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvprojx +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvprojx @@ -323,7 +323,7 @@ 0 0 1 - 0 + 1 0 0 0 diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/template.uvprojx b/bsp/hc32/ev_hc32f460_lqfp100_v2/template.uvprojx index f01be29aedc..9285f6c20dd 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/template.uvprojx +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/template.uvprojx @@ -326,7 +326,7 @@ 0 0 1 - 0 + 1 0 0 0 diff --git a/bsp/hc32/ev_hc32f472_lqfp100/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f472_lqfp100/.ci/attachconfig/ci.attachconfig.yml index 92d777ca640..7ec37e6f4a7 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/hc32/ev_hc32f472_lqfp100/.ci/attachconfig/ci.attachconfig.yml @@ -1,12 +1,166 @@ +# ------ device CI ------ +devices.adc: + kconfig: + - CONFIG_BSP_USING_ADC=y + - CONFIG_BSP_USING_ADC1=y + - CONFIG_BSP_ADC1_USING_DMA=y +devices.can: + kconfig: + - CONFIG_BSP_USING_CAN=y + - CONFIG_BSP_USING_CAN1=y + - CONFIG_RT_CAN_USING_CANFD=y + - CONFIG_RT_CAN_USING_HDR=y +devices.crypto: + kconfig: + - CONFIG_BSP_USING_HWCRYPTO=y + - CONFIG_BSP_USING_UQID=y + - CONFIG_BSP_USING_RNG=y + - CONFIG_BSP_USING_CRC=y + - CONFIG_BSP_USING_AES=y + - CONFIG_BSP_USING_HASH=y +devices.dac: + kconfig: + - CONFIG_BSP_USING_DAC=y + - CONFIG_BSP_USING_DAC1=y +devices.flash: + kconfig: + - CONFIG_BSP_USING_ON_CHIP_FLASH=y + - CONFIG_RT_USING_FAL=y + - CONFIG_RT_USING_SPI=y + - CONFIG_RT_USING_SFUD=y devices.gpio: kconfig: - CONFIG_BSP_USING_GPIO=y +devices.hwtimer: + kconfig: + - CONFIG_BSP_USING_HWTIMER=y + - CONFIG_BSP_USING_TMRA_1=y +devices.i2c: + kconfig: - CONFIG_BSP_USING_I2C=y - - CONFIG_BSP_USING_I2C_HW=y - CONFIG_BSP_USING_I2C1=y - - CONFIG_BSP_USING_TCA9539=y - - CONFIG_BSP_USING_EXT_IO=y -devices.uart: + - CONFIG_BSP_I2C1_TX_USING_DMA=y + - CONFIG_BSP_I2C1_RX_USING_DMA=y +devices.input_capture: + kconfig: + - CONFIG_BSP_USING_INPUT_CAPTURE=y + - CONFIG_BSP_USING_INPUT_CAPTURE_TMR6=y + - CONFIG_BSP_USING_INPUT_CAPTURE_TMR6_1=y +devices.pm: + kconfig: + - CONFIG_BSP_USING_PM=y + - CONFIG_IDLE_THREAD_STACK_SIZE=512 +devices.pulse_encoder_tmr6: + kconfig: + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_TMR6_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER_TMR6_1=y +devices.pulse_encoder_tmra: + kconfig: + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_TMRA_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER_TMRA_1=y +devices.pwm_tmr4: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMR4=y + - CONFIG_BSP_USING_PWM_TMR4_1=y + - CONFIG_BSP_USING_PWM_TMR4_1_OUH=y + - CONFIG_BSP_USING_PWM_TMR4_1_OUL=y +devices.pwm_tmr6: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMR6=y + - CONFIG_BSP_USING_PWM_TMR6_1=y + - CONFIG_BSP_USING_PWM_TMR6_1_A=y + - CONFIG_BSP_USING_PWM_TMR6_1_B=y +devices.pwm_tmra: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMRA=y + - CONFIG_BSP_USING_PWM_TMRA_1=y + - CONFIG_BSP_USING_PWM_TMRA_1_CH1=y + - CONFIG_BSP_USING_PWM_TMRA_1_CH2=y +devices.qspi: kconfig: + - CONFIG_BSP_USING_QSPI=y + - CONFIG_BSP_QSPI_USING_DMA=y + - CONFIG_BSP_QSPI_USING_SOFT_CS=y +devices.rtc: + kconfig: + - CONFIG_BSP_USING_RTC=y + - CONFIG_RT_USING_ALARM=y +devices.soft_i2c: + kconfig: + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_I2C1_SW=y +devices.spi: + kconfig: + - CONFIG_BSP_USING_SPI=y + - CONFIG_BSP_USING_SPI1=y + - CONFIG_BSP_SPI1_TX_USING_DMA=y + - CONFIG_BSP_SPI1_RX_USING_DMA=y + - CONFIG_BSP_SPI_USING_DMA=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.uart_v1: + kconfig: + - CONFIG_RT_USING_SERIAL_V1=y + - CONFIG_BSP_USING_UART=y + - CONFIG_BSP_USING_UART1=y + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_UART1_RX_USING_DMA=y + - CONFIG_BSP_UART1_TX_USING_DMA=y +devices.uart_v2: + kconfig: + - CONFIG_RT_USING_SERIAL_V2=y - CONFIG_BSP_USING_UART=y - - CONFIG_BSP_USING_UART2=y + - CONFIG_BSP_USING_UART1=y + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_UART1_RX_USING_DMA=y + - CONFIG_BSP_UART1_TX_USING_DMA=y +devices.usb_hs_device: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBD=y + - CONFIG_BSP_USING_USBHS=y + - CONFIG_BSP_USING_USBD_HS=y + - CONFIG_RT_USB_DEVICE_MSTORAGE=y +devices.usb_hs_host: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBH=y + - CONFIG_BSP_USING_USBHS=y + - CONFIG_BSP_USING_USBH_HS=y + - CONFIG_RT_USBH_MSTORAGE=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.usb_fs_device: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBD=y + - CONFIG_BSP_USING_USBFS=y + - CONFIG_BSP_USING_USBD_FS=y + - CONFIG_RT_USB_DEVICE_MSTORAGE=y +devices.usb_fs_host: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBH=y + - CONFIG_BSP_USING_USBFS=y + - CONFIG_BSP_USING_USBH_FS=y + - CONFIG_RT_USBH_MSTORAGE=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.watchdog_swdt: + kconfig: + - CONFIG_BSP_USING_WDT_TMR=y + - CONFIG_BSP_USING_SWDT=y +devices.watchdog_wdt: + kconfig: + - CONFIG_BSP_USING_WDT_TMR=y + - CONFIG_BSP_USING_WDT=y + +# ------ peripheral CI ------ +peripheral.spi_flash: + kconfig: + - CONFIG_BSP_USING_SPI_FLASH=y diff --git a/bsp/hc32/ev_hc32f472_lqfp100/README.md b/bsp/hc32/ev_hc32f472_lqfp100/README.md index 63ef09d84d2..a348e2a89e6 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/README.md +++ b/bsp/hc32/ev_hc32f472_lqfp100/README.md @@ -1,8 +1,8 @@ -# XHSC EV_F472_LQ80_Rev1.0 开发板 BSP 说明 +# XHSC EV_F472_LQ100 开发板 BSP 说明 ## 简介 -本文档为小华半导体为 EV_F472_LQ80_Rev1.0 开发板提供的 BSP (板级支持包) 说明。 +本文档为小华半导体为 EV_F472_LQ100 开发板提供的 BSP (板级支持包) 说明。 主要内容如下： @@ -14,69 +14,66 @@ ## 开发板介绍 -EV_F472_LQ80_Rev1.0 是 XHSC 官方推出的开发板，搭载 HC32F472PETI 芯片，基于 ARM Cortex-M4 内核，最高主频 200 MHz，具有丰富的板载资源，可以充分发挥 HC32F472PETI 的芯片性能。 +EV_F472_LQ100 是 XHSC 官方推出的开发板，搭载 HC32F472PETI 芯片，基于 ARM Cortex-M4 内核，最高主频 120 MHz，具有丰富的板载资源，可以充分发挥 HC32F472PETI 的芯片性能。 开发板外观如下图所示： ![board](figures/board.png) -EV_F472_LQ80_Rev1.0 开发板常用 **板载资源** 如下： - -- **MCU** - - HC32F472PETI - - 主频200MHz - - 256KB FLASH - - 68KB RAM -- **外部Memory** - - BL24C256（EEPROM, 256Kbits） - - W25Q64（SPI NOR，64MB） - - IS62WV51216（SRAM， 1MB） -- **常用外设** - - LED: 4 个，User LED（LED0，LED1，LED2，LED3）。 - - 按键: 5 个，矩阵键盘（K1~K4）， WAKEUP（K5），RESET（K0） -- **常用接口** - - USB转串口 - - CAN DB9接口 * 2 - - TFT接口 - - SmartCard接口 - - I2C/USART/SPI接口 -- **调试接口** - - 板载DAP调试器 - - 标准JTAG/SWD/Trace - -开发板更多详细信息请参考小华半导体半导体[EV_F472_LQ80_Rev1.0](https://www.xhsc.com.cn) +EV_F472_LQ100 开发板常用 **板载资源** 如下： + +- MCU：HC32F472PETI，主频120MHz，512KB FLASH，68KB RAM +- 外部RAM：IS62WV51216(SRAM，1MB) +- 常用外设 + - LED：3 个，User LED(LED0、LED1、LED2)。 + - 按键：11 个，矩阵键盘(K1~K9)、WAKEUP(K10)、RESET(K0)。 +- 常用接口：LCD接口、USB FS接口、CAN接口、LIN接口。 +- 调试接口：板载DAP调试器（含USB转串口）、标准JTAG/SWD。 + +开发板更多详细信息请参考小华半导体半导体[EV_F472_LQ100](https://www.xhsc.com.cn) ## 外设支持 本 BSP 目前对外设的支持情况如下： -| **板载外设** | **支持情况** | **备注** | -|:-------- |:--------:|:--------:| -| USB 转串口 | 支持 | 使用 UART2 | -| LED | 支持 | LED1~4 | - -| **片上外设** | **支持情况** | **备注** | -|:-------- |:--------:|:------------------------------------------:| -| ADC | 支持 | ADC1: CH10, CH11,
ADC3: CH1 | -| CAN | 支持 | CAN1、CAN2 | -| GPIO | 支持 | PA0, PA1... PH2 ---> PIN: 0, 1...82 | -| I2C | 支持 | 软件模拟
硬件I2C1~2
I2C1支持EEPROM（BL24C256） | -| Hwtimer | 支持 | Hwtimer1~5 | -| SPI | 支持 | SPI1~3
SPI1支持W25Q | -| UART | 支持 | UART1~6
UART2为console使用 | +| **板载外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| USB 转串口 | 支持 | 使用 UART2 | + +| **片上外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| ADC | 支持 | | +| CAN | 支持 | | +| Crypto | 支持 | AES，CRC，HASH，RNG | +| DAC | 支持 | | +| FLASH | 支持 | | +| GPIO | 支持 | PA0，PA1... PF8 ---> PIN：0，1...89 | +| HwTimer | 支持 | | +| I2C | 支持 | 软件、硬件 I2C | +| InputCapture | 支持 | | +| PM | 支持 | | +| PulseEncoder | 支持 | | +| PWM | 支持 | | +| QSPI | 支持 | | +| RTC | 支持 | 闹钟精度为1分钟 | +| SPI | 支持 | | +| UART V1 & V2 | 支持 | | +| USB | 支持 | USBFS Core， device/host模式 | +| WDT | 支持 | | ## 使用说明 使用说明分为如下两个章节： - 快速上手 - + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 - 进阶使用 - + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + ### 快速上手 本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 @@ -93,14 +90,14 @@ EV_F472_LQ80_Rev1.0 开发板常用 **板载资源** 如下： #### 运行结果 -下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED3会周期性闪烁。 +下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED5会周期性闪烁。 USB虚拟COM端口默认连接串口2，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息: ``` \ | / - RT - Thread Operating System - / | \ 5.0.1 build Feb 4 2024 16:44:26 + / | \ 4.1.0 build Apr 24 2022 13:32:39 2006 - 2022 Copyright by RT-Thread team msh > ``` @@ -119,13 +116,16 @@ msh > ## 注意事项 -| 板载外设 | 模式 | 注意事项 | -| -------- | ------ | ------------------------------------------------------------ | -| USB | device | 由于RTT抽象层的设计，当配置为CDC设备时，打开USB虚拟串口，需使能流控的DTR信号。（如使用SSCOM串口助手打开USB虚拟串口时，勾选DTR选框） | -| USB | host | 由于main()函数中的LED闪烁示例，使用的是USBFS主机口的供电控制管脚，因而当配置为使用USBFS 的主机模式时，需要将main()函数中的LED示例代码手动屏蔽。 | -| USB | host | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 | -| USB | host | 为确保USB主机对外供电充足，建议通过J7外接5V电源供电，并短接J8的VIN跳帽。 | -| USB | host | 目前仅实现并测试了对U盘的支持。 | +| 板载外设 | 模式 | 协议栈 | 注意事项 | +| -------- | ------ | :------------: | ------------------------------------------------------------ | +| USB | device | ALL | 由于协议栈的设计，当配置为CDC设备时，打开USB虚拟串口，需使能流控的DTR信号。（如使用SSCOM串口助手打开USB虚拟串口时，勾选DTR选框） | +| USB | ALL | ALL | 由于main()函数中的LED闪烁示例，使用的是USBFS主机的供电控制管脚，因而当使用USBFS时，需要将main()函数中的LED示例代码手动屏蔽。 | +| USB | host | RTT legacy USB | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 | +| USB | host | ALL | 为确保USB主机对外供电充足，建议通过J7外接5V电源供电，并短接J8的VIN跳帽。 | +| USB | host | RTT legacy USB | 目前仅实现并测试了对U盘的支持。 | +| USB | ALL | ALL | CherryUSB 与 RTT legacy USB 组件不可同时使用;
CherryUSB与 ”On-Chip Peripheral Driver---> []Enable USB“ 不可同时使能及配置。 | +| USB | ALL | RTT legacy USB | 通过“board/config/usb_config/usb_app_conf.h” 进行应用个性化配置（主要为FIFO分配） | +| USB | ALL | CherryUSB | 通过“board/ports/usb_config.h”进行应用个性化配置（如FIFO分配、是否使用DMA[Device]等） | ## 联系人信息 diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/Kconfig b/bsp/hc32/ev_hc32f472_lqfp100/board/Kconfig index 3b0159ec43d..0867ee69290 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/Kconfig +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/Kconfig @@ -90,7 +90,7 @@ menu "On-chip Peripheral Drivers" int "Set UART1 RX DMA ping-pong buffer size" range 32 65535 depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA - default 64 + default 64 endif menuconfig BSP_USING_UART2 @@ -123,7 +123,7 @@ menu "On-chip Peripheral Drivers" int "Set UART2 RX DMA ping-pong buffer size" range 32 65535 depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA - default 64 + default 64 endif menuconfig BSP_USING_UART3 @@ -173,7 +173,7 @@ menu "On-chip Peripheral Drivers" int "Set UART4 RX DMA ping-pong buffer size" range 32 65535 depends on RT_USING_SERIAL_V2 && BSP_UART4_RX_USING_DMA - default 64 + default 64 endif menuconfig BSP_USING_UART5 @@ -206,7 +206,7 @@ menu "On-chip Peripheral Drivers" int "Set UART5 RX DMA ping-pong buffer size" range 32 65535 depends on RT_USING_SERIAL_V2 && BSP_UART5_RX_USING_DMA - default 64 + default 64 endif menuconfig BSP_USING_UART6 @@ -634,6 +634,38 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_INPUT_CAPTURE + bool "Enable Input Capture" + default n + select RT_USING_INPUT_CAPTURE + if BSP_USING_INPUT_CAPTURE + menuconfig BSP_USING_INPUT_CAPTURE_TMR6 + bool "Use Timer6 As The Input Capture" + default n + if BSP_USING_INPUT_CAPTURE_TMR6 + config BSP_USING_INPUT_CAPTURE_TMR6_1 + bool "unit 1" + config BSP_USING_INPUT_CAPTURE_TMR6_2 + bool "unit 2" + config BSP_USING_INPUT_CAPTURE_TMR6_3 + bool "unit 3" + config BSP_USING_INPUT_CAPTURE_TMR6_4 + bool "unit 4" + config BSP_USING_INPUT_CAPTURE_TMR6_5 + bool "unit 5" + config BSP_USING_INPUT_CAPTURE_TMR6_6 + bool "unit 6" + config BSP_USING_INPUT_CAPTURE_TMR6_7 + bool "unit 7" + config BSP_USING_INPUT_CAPTURE_TMR6_8 + bool "unit 8" + config BSP_USING_INPUT_CAPTURE_TMR6_9 + bool "unit 9" + config BSP_USING_INPUT_CAPTURE_TMR6_10 + bool "unit 10" + endif + endif + menuconfig BSP_USING_QSPI bool "Enable QSPI BUS" select RT_USING_QSPI @@ -710,6 +742,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_USB bool "Enable USB" default n + depends on !RT_USING_CHERRYUSB select RT_USING_USB_DEVICE if BSP_USING_USBD select RT_USING_USB_HOST if BSP_USING_USBH if BSP_USING_USB diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/board.c b/bsp/hc32/ev_hc32f472_lqfp100/board/board.c index bb1fde8dbff..2a65b3ac58c 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/board.c +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/board.c @@ -118,7 +118,7 @@ void PeripheralClock_Config(void) #if defined(RT_USING_ADC) CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK); #endif -#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) CLK_SetUSBClockSrc(CLK_USBCLK_PLLQ); #endif } diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.c b/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.c index c2104338305..8527affb4d4 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.c +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.c @@ -342,6 +342,36 @@ rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x) #endif #endif +#if defined (BSP_USING_INPUT_CAPTURE) +rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)tmr_instance) + { +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) + case (rt_uint32_t)CM_TMR6_1: + GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, INPUT_CAPTURE_TMR6_1_FUNC); + break; +#endif +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) + case (rt_uint32_t)CM_TMR6_2: + GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, INPUT_CAPTURE_TMR6_2_FUNC); + break; +#endif +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_10) + case (rt_uint32_t)CM_TMR6_10: + GPIO_SetFunc(INPUT_CAPTURE_TMR6_10_PORT, INPUT_CAPTURE_TMR6_10_PIN, INPUT_CAPTURE_TMR6_10_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + #ifdef RT_USING_PM #define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) @@ -424,3 +454,26 @@ rt_err_t rt_hw_usbfs_board_init(void) return RT_EOK; } #endif + +#if defined(RT_USING_CHERRYUSB) +rt_err_t rt_hw_usbfs_board_init(uint8_t devmode) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBF_DM_PORT, USBF_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBF_DP_PORT, USBF_DP_PIN, &stcGpioCfg); + if (0U != devmode) + { + /* reserved */ + } + else + { + GPIO_OutputCmd(USBF_DRVVBUS_PORT, USBF_DRVVBUS_PIN, ENABLE); + GPIO_SetPins(USBF_DRVVBUS_PORT, USBF_DRVVBUS_PIN); /* DRV VBUS with GPIO funciton */ + } + return RT_EOK; +} + +#endif diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.h index f942e7ef72c..996a262f19e 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.h @@ -16,7 +16,9 @@ #include #include "hc32_ll.h" #include "drv_config.h" - +#if defined(RT_USING_CHERRYUSB) + #include "usb_config.h" +#endif /************************* XTAL port **********************/ #define XTAL_PORT (GPIO_PORT_F) @@ -292,6 +294,24 @@ #endif +#if defined(BSP_USING_INPUT_CAPTURE) + #if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) + #define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_A) + #define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_00) + #define INPUT_CAPTURE_TMR6_1_FUNC (GPIO_FUNC_11) + #endif + #if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) + #define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_B) + #define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_02) + #define INPUT_CAPTURE_TMR6_2_FUNC (GPIO_FUNC_12) + #endif + #if defined(BSP_USING_INPUT_CAPTURE_TMR6_10) + #define INPUT_CAPTURE_TMR6_10_PORT (GPIO_PORT_A) + #define INPUT_CAPTURE_TMR6_10_PIN (GPIO_PIN_12) + #define INPUT_CAPTURE_TMR6_10_FUNC (GPIO_FUNC_11) + #endif +#endif + #if defined(BSP_USING_QSPI) #ifndef BSP_QSPI_USING_SOFT_CS /* QSSN */ @@ -346,8 +366,15 @@ #endif /* BSP_USING_TMR6_PULSE_ENCODER */ #endif /* RT_USING_PULSE_ENCODER */ -#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) - #if defined(BSP_USING_USBFS) +#if defined(RT_USING_CHERRYUSB) + #if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || \ + defined(BSP_USING_USBFS) || defined(RT_USING_USB) + #error "When using CherryUSB, Please donot Enable 'On-Chip Peripheral Driver---> []Enable USB' or using USB legacy version!" + #endif +#endif + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) + #if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) /* USBFS Core*/ #define USBF_DP_PORT (GPIO_PORT_A) #define USBF_DP_PIN (GPIO_PIN_12) diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/irq_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/irq_config.h index a9ec788bda1..48e1c60796f 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/config/irq_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/irq_config.h @@ -316,11 +316,28 @@ extern "C" { #define BSP_PULSE_ENCODER_TMR6_10_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_10 */ -#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) #define BSP_USBFS_GLB_IRQ_NUM USBFS_GLB_IRQn #define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif +#if defined(BSP_USING_INPUT_CAPTURE) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_10_OVF_IRQ_NUM (INT010_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_10_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_10_CAP_IRQ_NUM (INT011_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_10_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#endif/* BSP_USING_INPUT_CAPTURE */ + #ifdef __cplusplus } #endif diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/pm_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/pm_config.h index e77cc0f20e4..df1ee98de31 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/config/pm_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/pm_config.h @@ -55,7 +55,6 @@ extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); { \ { \ .u16Clock = PWC_STOP_CLK_KEEP, \ - .u8StopDrv = PWC_STOP_DRV_HIGH, \ .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \ .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ }, \ @@ -72,7 +71,6 @@ extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); { \ .u8Mode = PWC_PD_MD1, \ .u8IOState = PWC_PD_IO_KEEP1, \ - .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ }, \ } #endif /*PM_SLEEP_STANDBY_CFG*/ @@ -86,7 +84,6 @@ extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); { \ .u8Mode = PWC_PD_MD3, \ .u8IOState = PWC_PD_IO_KEEP1, \ - .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ }, \ } #endif /*PM_SLEEP_SHUTDOWN_CFG*/ diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/tmr_capture_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/tmr_capture_config.h new file mode 100644 index 00000000000..089d106ae87 --- /dev/null +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/tmr_capture_config.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-14 CDT first version + */ + +#ifndef __IC_CONFIG_H__ +#define __IC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) +#define IC1_NAME "ic1" +#define INPUT_CAPTURE_CFG_TMR6_1 \ +{ \ + .name = IC1_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \ +} +#endif + +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) +#define IC2_NAME "ic2" +#define INPUT_CAPTURE_CFG_TMR6_2 \ +{ \ + .name = IC2_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_TRIGB_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \ +} +#endif + +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_10) +#define IC10_NAME "ic10" +#define INPUT_CAPTURE_CFG_TMR6_10 \ +{ \ + .name = IC10_NAME, \ + .ch = TMR6_CH_B, \ + .clk_div = TMR6_CLK_DIV16, \ + .first_edge = TMR6_CAPT_COND_TRIGC_FALLING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_10_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_10_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_10_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_10_OVF_IRQ_PRIO, \ +} +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __IC_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/drv_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/drv_config.h index d250b654a47..35f5a1fd434 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/drv_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/drv_config.h @@ -30,6 +30,7 @@ extern "C" { #include "qspi_config.h" #include "pulse_encoder_config.h" #include "timer_config.h" +#include "tmr_capture_config.h" #ifdef __cplusplus } diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.icf b/bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.icf index 1e01b623b0c..394bd6e847d 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.icf +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.icf @@ -87,9 +87,9 @@ define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; /*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0xC00; +define symbol __ICFEDIT_size_cstack__ = 0x800; define symbol __ICFEDIT_size_proc_stack__ = 0x0; -define symbol __ICFEDIT_size_heap__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x0; /**** End of ICF editor section. ###ICF###*/ /******************************************************************************* diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.ld b/bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.ld index 031047e2080..e135b56b8b1 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.ld +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.ld @@ -88,6 +88,12 @@ SECTIONS __rt_init_end = .; . = ALIGN(4); + /* section for CherryUSB. */ + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(4); _etext = .; } >FLASH diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/ports/usb_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/ports/usb_config.h new file mode 100644 index 00000000000..723f0b19040 --- /dev/null +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/ports/usb_config.h @@ -0,0 +1,307 @@ +/* + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-08 CDT first version + */ + +#ifndef CHERRYUSB_CONFIG_H +#define CHERRYUSB_CONFIG_H + +/* ================ USB common Configuration ================ */ + +#ifdef __RTTHREAD__ + #include + + #define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) +#else + #define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) +#endif + +#ifndef CONFIG_USB_DBG_LEVEL + #define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#endif + +/* Enable print with color */ +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +// #define CONFIG_USB_DCACHE_ENABLE + +/* data align size when use dma or use dcache */ +#ifdef CONFIG_USB_DCACHE_ENABLE + #define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64 +#else + #define CONFIG_USB_ALIGN_SIZE 4 +#endif + +/* attribute data into no cache ram */ +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) + +/* use usb_memcpy default for high performance but cost more flash memory. + * And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4. +*/ +// #define CONFIG_USB_MEMCPY_DISABLE + +/* ================= USB Device Stack Configuration ================ */ + +/* Ep0 in and out transfer buffer */ +#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN + #define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#endif + +/* Send ep0 in data from user buffer instead of copying into ep0 reqdata + * Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE +*/ +// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY + +/* Check if the input descriptor is correct */ +// #define CONFIG_USBDEV_DESC_CHECK + +/* Enable test mode */ +// #define CONFIG_USBDEV_TEST_MODE + +/* enable advance desc register api */ +#define CONFIG_USBDEV_ADVANCE_DESC + +/* move ep0 setup handler from isr to thread */ +// #define CONFIG_USBDEV_EP0_THREAD + +#ifndef CONFIG_USBDEV_EP0_PRIO + #define CONFIG_USBDEV_EP0_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_EP0_STACKSIZE + #define CONFIG_USBDEV_EP0_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_LUN + #define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE + #define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#endif + +#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING + #define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING + #define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_VERSION_STRING + #define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +/* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */ +// #define CONFIG_USBDEV_MSC_POLLING + +/* move msc read & write from isr to thread */ +// #define CONFIG_USBDEV_MSC_THREAD + +#ifndef CONFIG_USBDEV_MSC_PRIO + #define CONFIG_USBDEV_MSC_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MSC_STACKSIZE + #define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE + #define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS + #define CONFIG_USBDEV_MTP_MAX_OBJECTS 256 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME + #define CONFIG_USBDEV_MTP_MAX_PATHNAME 256 +#endif + +#define CONFIG_USBDEV_MTP_THREAD + +#ifndef CONFIG_USBDEV_MTP_PRIO + #define CONFIG_USBDEV_MTP_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MTP_STACKSIZE + #define CONFIG_USBDEV_MTP_STACKSIZE 4096 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE + #define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ +#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE + #define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID + #define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC + #define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#endif + +#define CONFIG_USBDEV_RNDIS_USING_LWIP +#define CONFIG_USBDEV_CDC_ECM_USING_LWIP + +/* ================ USB HOST Stack Configuration ================== */ + +#define CONFIG_USBHOST_MAX_RHPORTS 1 +#define CONFIG_USBHOST_MAX_EXTHUBS 1 +#define CONFIG_USBHOST_MAX_EHPORTS 4 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 4 + +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO + #define CONFIG_USBHOST_PSC_PRIO 0 +#endif +#ifndef CONFIG_USBHOST_PSC_STACKSIZE + #define CONFIG_USBHOST_PSC_STACKSIZE 2048 +#endif + +//#define CONFIG_USBHOST_GET_STRING_DESC + +// #define CONFIG_USBHOST_MSOS_ENABLE +#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE + #define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#endif + +/* Ep0 max transfer buffer */ +#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN + #define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#endif + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT + #define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT + #define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#endif + +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#endif + +#define CONFIG_USBHOST_BLUETOOTH_HCI_H4 +// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG + +#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE + #define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#endif +#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE + #define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#endif + +/* ================ USB Device Port Configuration ================*/ + +#ifndef CONFIG_USBDEV_MAX_BUS + #define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip +#endif + +#ifndef CONFIG_USBDEV_EP_NUM + #define CONFIG_USBDEV_EP_NUM 8 +#endif + +// #define CONFIG_USBDEV_SOF_ENABLE + +/* ---------------- DWC2 Configuration ---------------- */ +/* enable dwc2 buffer dma mode for device +*/ +// #define CONFIG_USB_DWC2_DMA_ENABLE + +/* Defined FS Core device FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE (32) + +/* Defined FS Core host FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE (64) + +/* Defined FS Core total FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE (320) + +/* ================ USB Host Port Configuration ==================*/ +#ifndef CONFIG_USBHOST_MAX_BUS + #define CONFIG_USBHOST_MAX_BUS 1 +#endif + +#ifndef CONFIG_USBHOST_PIPE_NUM + #define CONFIG_USBHOST_PIPE_NUM 10 +#endif + + +#ifndef usb_phyaddr2ramaddr + #define usb_phyaddr2ramaddr(addr) (addr) +#endif + +#ifndef usb_ramaddr2phyaddr + #define usb_ramaddr2phyaddr(addr) (addr) +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f472_lqfp100/bsp_compile_ci.bat b/bsp/hc32/ev_hc32f472_lqfp100/bsp_compile_ci.bat new file mode 100644 index 00000000000..be8ad075384 --- /dev/null +++ b/bsp/hc32/ev_hc32f472_lqfp100/bsp_compile_ci.bat @@ -0,0 +1,112 @@ +scons --attach=devices.adc +scons -j4 +scons --attach=default + +scons --attach=devices.can +scons -j4 +scons --attach=default + +scons --attach=devices.crypto +scons -j4 +scons --attach=default + +scons --attach=devices.dac +scons -j4 +scons --attach=default + +scons --attach=devices.flash +scons -j4 +scons --attach=default + +scons --attach=devices.gpio +scons -j4 +scons --attach=default + +scons --attach=devices.hwtimer +scons -j4 +scons --attach=default + +scons --attach=devices.i2c +scons -j4 +scons --attach=default + +scons --attach=devices.input_capture +scons -j4 +scons --attach=default + +scons --attach=devices.pm +scons -j4 +scons --attach=default + +scons --attach=devices.pulse_encoder_tmr6 +scons -j4 +scons --attach=default + +scons --attach=devices.pulse_encoder_tmra +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmr4 +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmr6 +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmra +scons -j4 +scons --attach=default + +scons --attach=devices.qspi +scons -j4 +scons --attach=default + +scons --attach=devices.rtc +scons -j4 +scons --attach=default + +scons --attach=devices.soft_i2c +scons -j4 +scons --attach=default + +scons --attach=devices.spi +scons -j4 +scons --attach=default + +scons --attach=devices.uart_v1 +scons -j4 +scons --attach=default + +scons --attach=devices.uart_v2 +scons -j4 +scons --attach=default + +scons --attach=devices.usb_hs_device +scons -j4 +scons --attach=default + +scons --attach=devices.usb_hs_host +scons -j4 +scons --attach=default + +scons --attach=devices.usb_fs_device +scons -j4 +scons --attach=default + +scons --attach=devices.usb_fs_host +scons -j4 +scons --attach=default + +scons --attach=devices.watchdog_swdt +scons -j4 +scons --attach=default + +scons --attach=devices.watchdog_wdt +scons -j4 +scons --attach=default + + +scons --attach=peripheral.spi_flash +scons -j4 +scons --attach=default diff --git a/bsp/hc32/ev_hc32f472_lqfp100/project.uvprojx b/bsp/hc32/ev_hc32f472_lqfp100/project.uvprojx index 271141cf701..20cdef17275 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/project.uvprojx +++ b/bsp/hc32/ev_hc32f472_lqfp100/project.uvprojx @@ -323,7 +323,7 @@ 0 0 1 - 0 + 1 0 0 0 diff --git a/bsp/hc32/ev_hc32f472_lqfp100/template.uvprojx b/bsp/hc32/ev_hc32f472_lqfp100/template.uvprojx index 48a8d19c05b..45ab5234303 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/template.uvprojx +++ b/bsp/hc32/ev_hc32f472_lqfp100/template.uvprojx @@ -326,7 +326,7 @@ 0 0 1 - 0 + 1 0 0 0 diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f4a0_lqfp176/.ci/attachconfig/ci.attachconfig.yml index 1966b8266d2..d4a7b92a9dc 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/.ci/attachconfig/ci.attachconfig.yml @@ -1,18 +1,36 @@ +# ------ device CI ------ devices.adc: kconfig: - CONFIG_BSP_USING_ADC=y - CONFIG_BSP_USING_ADC1=y + - CONFIG_BSP_ADC1_USING_DMA=y +devices.can: + kconfig: + - CONFIG_BSP_USING_CAN=y + - CONFIG_BSP_USING_CAN1=y + - CONFIG_RT_CAN_USING_CANFD=y + - CONFIG_RT_CAN_USING_HDR=y +devices.crypto: + kconfig: + - CONFIG_BSP_USING_HWCRYPTO=y + - CONFIG_BSP_USING_UQID=y + - CONFIG_BSP_USING_RNG=y + - CONFIG_BSP_USING_CRC=y + - CONFIG_BSP_USING_AES=y + - CONFIG_BSP_USING_HASH=y +devices.dac: + kconfig: + - CONFIG_BSP_USING_DAC=y + - CONFIG_BSP_USING_DAC1=y devices.flash: kconfig: - CONFIG_BSP_USING_ON_CHIP_FLASH=y + - CONFIG_RT_USING_FAL=y + - CONFIG_RT_USING_SPI=y + - CONFIG_RT_USING_SFUD=y devices.gpio: kconfig: - CONFIG_BSP_USING_GPIO=y - - CONFIG_BSP_USING_I2C=y - - CONFIG_BSP_USING_I2C_HW=y - - CONFIG_BSP_USING_I2C1=y - - CONFIG_BSP_USING_TCA9539=y - - CONFIG_BSP_USING_EXT_IO=y devices.hwtimer: kconfig: - CONFIG_BSP_USING_HWTIMER=y @@ -20,31 +38,158 @@ devices.hwtimer: devices.i2c: kconfig: - CONFIG_BSP_USING_I2C=y -devices.pwm: + - CONFIG_BSP_USING_I2C1=y + - CONFIG_BSP_I2C1_TX_USING_DMA=y + - CONFIG_BSP_I2C1_RX_USING_DMA=y +devices.input_capture: + kconfig: + - CONFIG_BSP_USING_INPUT_CAPTURE=y + - CONFIG_BSP_USING_INPUT_CAPTURE_TMR6=y + - CONFIG_BSP_USING_INPUT_CAPTURE_TMR6_1=y +devices.pm: + kconfig: + - CONFIG_BSP_USING_PM=y + - CONFIG_IDLE_THREAD_STACK_SIZE=512 +devices.pulse_encoder_tmr6: + kconfig: + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_TMR6_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER_TMR6_1=y +devices.pulse_encoder_tmra: + kconfig: + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_TMRA_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER_TMRA_1=y +devices.pwm_tmr4: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMR4=y + - CONFIG_BSP_USING_PWM_TMR4_1=y + - CONFIG_BSP_USING_PWM_TMR4_1_OUH=y + - CONFIG_BSP_USING_PWM_TMR4_1_OUL=y +devices.pwm_tmr6: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMR6=y + - CONFIG_BSP_USING_PWM_TMR6_1=y + - CONFIG_BSP_USING_PWM_TMR6_1_A=y + - CONFIG_BSP_USING_PWM_TMR6_1_B=y +devices.pwm_tmra: kconfig: - CONFIG_BSP_USING_PWM=y - CONFIG_BSP_USING_PWM_TMRA=y - CONFIG_BSP_USING_PWM_TMRA_1=y - CONFIG_BSP_USING_PWM_TMRA_1_CH1=y - CONFIG_BSP_USING_PWM_TMRA_1_CH2=y +devices.qspi: + kconfig: + - CONFIG_BSP_USING_QSPI=y + - CONFIG_BSP_QSPI_USING_DMA=y + - CONFIG_BSP_QSPI_USING_SOFT_CS=y devices.rtc: kconfig: - CONFIG_BSP_USING_RTC=y - - CONFIG_BSP_RTC_USING_XTAL32=y + - CONFIG_RT_USING_ALARM=y +devices.sdio: + kconfig: + - CONFIG_BSP_USING_SDIO=y + - CONFIG_BSP_USING_SDIO1=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.soft_i2c: + kconfig: + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_I2C1_SW=y devices.spi: kconfig: - CONFIG_BSP_USING_SPI=y - CONFIG_BSP_USING_SPI1=y -devices.uart: + - CONFIG_BSP_SPI1_TX_USING_DMA=y + - CONFIG_BSP_SPI1_RX_USING_DMA=y + - CONFIG_BSP_SPI_USING_DMA=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.uart_v1: + kconfig: + - CONFIG_RT_USING_SERIAL_V1=y + - CONFIG_BSP_USING_UART=y + - CONFIG_BSP_USING_UART1=y + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_UART1_RX_USING_DMA=y + - CONFIG_BSP_UART1_TX_USING_DMA=y +devices.uart_v2: kconfig: + - CONFIG_RT_USING_SERIAL_V2=y - CONFIG_BSP_USING_UART=y - CONFIG_BSP_USING_UART1=y -devices.watchdog: + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_UART1_RX_USING_DMA=y + - CONFIG_BSP_UART1_TX_USING_DMA=y +devices.usb_hs_device: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBD=y + - CONFIG_BSP_USING_USBHS=y + - CONFIG_BSP_USING_USBD_HS=y + - CONFIG_RT_USB_DEVICE_MSTORAGE=y +devices.usb_hs_host: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBH=y + - CONFIG_BSP_USING_USBHS=y + - CONFIG_BSP_USING_USBH_HS=y + - CONFIG_RT_USBH_MSTORAGE=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.usb_fs_device: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBD=y + - CONFIG_BSP_USING_USBFS=y + - CONFIG_BSP_USING_USBD_FS=y + - CONFIG_RT_USB_DEVICE_MSTORAGE=y +devices.usb_fs_host: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBH=y + - CONFIG_BSP_USING_USBFS=y + - CONFIG_BSP_USING_USBH_FS=y + - CONFIG_RT_USBH_MSTORAGE=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.watchdog_swdt: kconfig: - CONFIG_BSP_USING_WDT_TMR=y - CONFIG_BSP_USING_SWDT=y -# ------ SEGGER CI ------ -segger: +devices.watchdog_wdt: + kconfig: + - CONFIG_BSP_USING_WDT_TMR=y + - CONFIG_BSP_USING_WDT=y + +# ------ peripheral CI ------ +peripheral.eth_mii: + kconfig: + - CONFIG_BSP_USING_ETH=y + - CONFIG_ETH_INTERFACE_USING_MII=y + - CONFIG_RT_USING_LWIP212=y + - CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +peripheral.eth_rmii: + kconfig: + - CONFIG_BSP_USING_ETH=y + - CONFIG_ETH_INTERFACE_USING_RMII=y + - CONFIG_ETH_PHY_USING_INTERRUPT_MODE=y + - CONFIG_RT_USING_LWIP212=y + - CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +peripheral.exmc_nand: + kconfig: + - CONFIG_BSP_USING_EXMC=y + - CONFIG_BSP_USING_NAND=y + - CONFIG_FINSH_USING_MSH=y +peripheral.exmc_sdram: + kconfig: + - CONFIG_BSP_USING_EXMC=y + - CONFIG_BSP_USING_SDRAM=y + - CONFIG_FINSH_USING_MSH=y +peripheral.spi_flash: kconfig: - - CONFIG_PKG_USING_SEGGER_RTT=y - - CONFIG_RT_USING_SERIAL_V1=y \ No newline at end of file + - CONFIG_BSP_USING_SPI_FLASH=y diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/README.md b/bsp/hc32/ev_hc32f4a0_lqfp176/README.md index c822f632ec1..bbe6eb75b4a 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/README.md +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/README.md @@ -23,13 +23,13 @@ EV_F4A0_LQ176 是 XHSC 官方推出的开发板，搭载 HC32F4A0SITB 芯片， EV_F4A0_LQ176 开发板常用 **板载资源** 如下： - MCU：HC32F4A0SITB，主频240MHz，2048KB FLASH，512KB RAM -- 外部RAM：IS62WV51216(SRAM, 1MB) IS42S16400J(SDRAM, 8MB) -- 外部FLASH: MT29F2G08AB(Nand, 256MB) W25Q64(SPI NOR, 64MB) +- 外部RAM：IS62WV51216(SRAM，1MB) IS42S16400J(SDRAM，8MB) +- 外部FLASH: MT29F2G08AB(Nand，256MB) W25Q64(SPI NOR，8MB) - 常用外设 - - LED：3 个， user LED(LED0,LED1,LED2)。 + - LED：3 个，User LED(LED0、LED1、LED2)。 - 按键：11 个，矩阵键盘(K1~K9)、WAKEUP(K10)、RESET(K11)。 -- 常用接口：USB转串口、SD卡接口、以太网接口、LCD接口、USB HS、USB FS、USB 3300、DVP接口、3.5mm耳机接口、Line in接口、喇叭接口 -- 调试接口：板载DAP调试器、标准JTAG/SWD。 +- 常用接口：SD卡接口、以太网接口、LCD接口、USB FS/HS接口、DVP接口、3.5mm耳机接口、Line in接口、CAN接口、LIN接口。 +- 调试接口：板载DAP调试器（含USB转串口）、标准JTAG/SWD。 开发板更多详细信息请参考小华半导体半导体[EV_F4A0_LQ176](https://www.xhsc.com.cn) @@ -37,34 +37,34 @@ EV_F4A0_LQ176 开发板常用 **板载资源** 如下： 本 BSP 目前对外设的支持情况如下： -| **板载外设** | **支持情况** | **备注** | +| **板载外设** | **支持情况** | **备注** | | :------------ | :-----------: | :-----------------------------------: | -| USB 转串口 | 支持 | 使用 UART1 | -| ETH | 支持 | | -| LED | 支持 | LED | -| Nand | 支持 | MT29F2G08AB | -| SDRAM | 支持 | IS42S16400J | +| ETH | 支持 | RTL8201F | +| Nand | 支持 | MT29F2G08AB | +| SDRAM | 支持 | IS42S16400J | +| USB 转串口 | 支持 | 使用 UART1 | -| **片上外设** | **支持情况** | **备注** | +| **片上外设** | **支持情况** | **备注** | | :------------ | :-----------: | :-----------------------------------: | -| Crypto | 支持 | AES, CRC, HASH, RNG, UID | -| DAC | 支持 | | -| ADC | 支持 | | -| CAN | 支持 | | -| GPIO | 支持 | PA0, PA1... PI13 ---> PIN: 0, 1...141 | -| PM | 支持 | | -| Lptimer | 支持 | | -| Hwtimer | 支持 | | -| Pulse_encoder | 支持 | | -| PWM | 支持 | | -| RTC | 支持 | 闹钟精度为1分钟 | -| WDT | 支持 | | -| I2C | 支持 | 软件、硬件 I2C | -| QSPI | 支持 | | -| SPI | 支持 | SPI1~6 | -| SDIO | 支持 | | -| UART V1 & V2 | 支持 | UART1~10 | -| USB | 支持 | USBFS/HS Core， device/host模式 | +| ADC | 支持 | | +| CAN | 支持 | | +| Crypto | 支持 | AES，CRC，HASH，RNG | +| DAC | 支持 | | +| FLASH | 支持 | | +| GPIO | 支持 | PA0，PA1...PI13 ---> PIN：0，1...141 | +| HwTimer | 支持 | | +| I2C | 支持 | 软件、硬件 I2C | +| InputCapture | 支持 | | +| PM | 支持 | | +| PulseEncoder | 支持 | | +| PWM | 支持 | | +| QSPI | 支持 | | +| RTC | 支持 | 闹钟精度为1分钟 | +| SDIO | 支持 | | +| SPI | 支持 | | +| UART V1 & V2 | 支持 | | +| USB | 支持 | USBFS/HS Core， device/host模式 | +| WDT | 支持 | | ## 使用说明 @@ -121,19 +121,22 @@ msh > ## 注意事项 -| 板载外设 | 模式 | 注意事项 | -| :------: | :----: | :----------------------------------------------------------- | -| USB | device | 由于RTT抽象层的设计，当配置为CDC设备时，打开USB虚拟串口，需使能流控的DTR信号。（如使用SSCOM串口助手打开USB虚拟串口时，勾选DTR选框） | -| USB | device | 由于外部PHY管脚复用的原因，当配置使用USBHS Core并且使用外部PHY时，需先通过J14连接到主机（如PC），再复位MCU运行程序；或者将J24跳帽先短接，再复位MCU运行程序。 | -| USB | host | 由于main()函数中的LED闪烁示例，使用的是USBFS主机口的供电控制管脚，因而当配置为使用USBFS Core的主机模式时，需要将main()函数中的LED示例代码手动屏蔽。 | -| USB | host | 为确保USB主机对外供电充足，建议通过J35外接5V电源供电，并短接J32的EXT跳帽。 | -| USB | host | 由于外部PHY管脚复用的原因，当配置使用USBHS Core并且使用外部PHY时，需通过J14先连接好OTG线，再复位MCU运行程序；或者将J24跳帽先短接，再复位MCU运行程序。 | -| USB | host | 目前仅实现并测试了对U盘的支持。 | -| USB | host | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 | -| USB | ALL | 由于管脚复用的原因，当配置使用USBHS Core时，无法同时使用板载SPI FLASH。 | +| 板载外设 | 模式 | 协议栈 | 注意事项 | +| :------: | :----: | :------------: | :----------------------------------------------------------- | +| USB | device | ALL | 由于协议栈的设计，当配置为CDC设备时，打开USB虚拟串口，需使能流控的DTR信号。（如使用SSCOM串口助手打开USB虚拟串口时，勾选DTR选框） | +| USB | device | ALL | 由于外部PHY管脚复用的原因，当配置使用USBHS Core并且使用外部PHY时，需先通过J14连接到主机（如PC），再复位MCU运行程序；或者将J24跳帽先短接，再复位MCU运行程序。 | +| USB | ALL | ALL | 由于main()函数中的LED闪烁示例，使用的是USBFS主机的供电控制管脚，因而当配置为使用USBFS Core时，需要将main()函数中的LED示例代码手动屏蔽。 | +| USB | host | ALL | 为确保USB主机对外供电充足，建议通过J35外接5V电源供电，并短接J32的EXT跳帽。 | +| USB | host | ALL | 由于外部PHY管脚复用的原因，当配置使用USBHS Core并且使用外部PHY时，需通过J14先连接好OTG线，再复位MCU运行程序；或者将J24跳帽先短接，再复位MCU运行程序。 | +| USB | host | RTT legacy USB | 目前仅实现并测试了对U盘的支持。 | +| USB | host | RTT legacy USB | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 | +| USB | ALL | ALL | 由于管脚复用的原因，当配置使用USBHS Core时，无法同时使用板载SPI FLASH。 | +| USB | ALL | ALL | CherryUSB 与 RTT legacy USB 组件不可同时使用;
CherryUSB与 ”On-Chip Peripheral Driver---> []Enable USB“ 不可同时使能及配置。 | +| USB | ALL | RTT legacy USB | 通过“board/config/usb_config/usb_app_conf.h” 进行应用个性化配置（主要为FIFO分配） | +| USB | ALL | CherryUSB | 通过“board/ports/usb_config.h”进行应用个性化配置（如FIFO分配、是否使用DMA[Device]、是否使用高速PHY等） | ## 联系人信息 维护人: -- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱： \ No newline at end of file +- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱： \ No newline at end of file diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig b/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig index afeee7e418c..dd6cf3734e3 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig @@ -146,7 +146,7 @@ menu "On-chip Peripheral Drivers" int "Set UART1 RX DMA ping-pong buffer size" range 32 65535 depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA - default 64 + default 64 endif menuconfig BSP_USING_UART2 @@ -179,7 +179,7 @@ menu "On-chip Peripheral Drivers" int "Set UART2 RX DMA ping-pong buffer size" range 32 65535 depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA - default 64 + default 64 endif menuconfig BSP_USING_UART3 @@ -263,7 +263,7 @@ menu "On-chip Peripheral Drivers" int "Set UART6 RX DMA ping-pong buffer size" range 32 65535 depends on RT_USING_SERIAL_V2 && BSP_UART6_RX_USING_DMA - default 64 + default 64 endif menuconfig BSP_USING_UART7 @@ -296,7 +296,7 @@ menu "On-chip Peripheral Drivers" int "Set UART7 RX DMA ping-pong buffer size" range 32 65535 depends on RT_USING_SERIAL_V2 && BSP_UART7_RX_USING_DMA - default 64 + default 64 endif @@ -834,6 +834,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_USB bool "Enable USB" default n + depends on !RT_USING_CHERRYUSB if BSP_USING_USB config BSP_USING_USBD bool diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c index d18b1402c57..18a1d51da3b 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c @@ -40,7 +40,7 @@ void SystemClock_Config(void) { stc_clock_xtal_init_t stcXtalInit; stc_clock_pll_init_t stcPLLHInit; -#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) stc_clock_pllx_init_t stcPLLAInit; #endif #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) @@ -87,7 +87,7 @@ void SystemClock_Config(void) GPIO_SetReadWaitCycle(GPIO_RD_WAIT4); CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); -#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) /* PLLX for USB */ (void)CLK_PLLxStructInit(&stcPLLAInit); /* VCO = (8/2)*120 = 480MHz*/ @@ -127,7 +127,7 @@ void PeripheralClock_Config(void) CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK); #endif -#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) CLK_SetUSBClockSrc(CLK_USBCLK_PLLXP); #endif } diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c index 5e05d061786..34e3d86602e 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c @@ -630,6 +630,84 @@ rt_err_t rt_hw_usbhs_board_init(void) } #endif +#if defined(RT_USING_CHERRYUSB) +rt_err_t rt_hw_usbfs_board_init(uint8_t devmode) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBF_DM_PORT, USBF_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBF_DP_PORT, USBF_DP_PIN, &stcGpioCfg); + if (0U != devmode) + { + GPIO_SetFunc(USBF_VBUS_PORT, USBF_VBUS_PIN, USBF_VBUS_FUNC); /* VBUS */ + } + else + { + GPIO_SetFunc(USBF_DRVVBUS_PORT, USBF_DRVVBUS_PIN, USBF_DRVVBUS_FUNC); /* DRV VBUS */ + } + return RT_EOK; +} + +rt_err_t rt_hw_usbhs_board_init(uint8_t devmode) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + +#if !defined(CONFIG_USB_HS) + /* USBHS work in embedded PHY */ + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBH_DM_PORT, USBH_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_DP_PORT, USBH_DP_PIN, &stcGpioCfg); + if (0U != devmode) + { + GPIO_SetFunc(USBH_VBUS_PORT, USBH_VBUS_PIN, USBH_VBUS_FUNC); + } + else + { + GPIO_OutputCmd(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN, ENABLE); + GPIO_SetPins(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN); /* DRV VBUS with GPIO funciton */ + } +#else + /* Reset 3300 */ + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_SET); + TCA9539_ConfigPin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_DIR_OUT); + + (void)GPIO_StructInit(&stcGpioCfg); + /* High drive capability */ + stcGpioCfg.u16PinDrv = PIN_HIGH_DRV; + (void)GPIO_Init(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, &stcGpioCfg); + + GPIO_SetFunc(USBH_ULPI_CLK_PORT, USBH_ULPI_CLK_PIN, USBH_ULPI_CLK_FUNC); + GPIO_SetFunc(USBH_ULPI_DIR_PORT, USBH_ULPI_DIR_PIN, USBH_ULPI_DIR_FUNC); + GPIO_SetFunc(USBH_ULPI_NXT_PORT, USBH_ULPI_NXT_PIN, USBH_ULPI_NXT_FUNC); + GPIO_SetFunc(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, USBH_ULPI_STP_FUNC); + GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); + GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); + GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); + GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); + GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); + GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); + GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); + GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); + + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_RESET); +#endif + + return RT_EOK; +} +#endif + + #if defined(BSP_USING_QSPI) rt_err_t rt_hw_qspi_board_init(void) { diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h index 78eae162a53..31d26ab2354 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h @@ -15,7 +15,9 @@ #include #include "hc32_ll.h" #include "drv_config.h" - +#if defined(RT_USING_CHERRYUSB) + #include "usb_config.h" +#endif /************************* XTAL port **********************/ #define XTAL_PORT (GPIO_PORT_H) @@ -561,8 +563,17 @@ #endif #endif -#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) - #if defined(BSP_USING_USBFS) +#if defined(RT_USING_CHERRYUSB) + #if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || \ + defined(BSP_USING_USBFS) || defined(BSP_USING_USBHS) || \ + defined(BSP_USING_USBHS_PHY_EMBED) || defined(BSP_USING_USBHS_PHY_EXTERN) || \ + defined(RT_USING_USB) + #error "When using CherryUSB, Please donot Enable 'On-Chip Peripheral Driver---> []Enable USB' or using USB legacy version!" + #endif +#endif + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) + #if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) /* USBFS Core*/ #define USBF_DP_PORT (GPIO_PORT_A) #define USBF_DP_PIN (GPIO_PIN_12) @@ -575,9 +586,9 @@ #define USBF_DRVVBUS_PIN (GPIO_PIN_09) #define USBF_DRVVBUS_FUNC (GPIO_FUNC_10) #endif - #if defined(BSP_USING_USBHS) + #if defined(BSP_USING_USBHS) || defined(RT_USING_CHERRYUSB) /* USBHS Core*/ - #if defined(BSP_USING_USBHS_PHY_EMBED) + #if defined(BSP_USING_USBHS_PHY_EMBED) || (defined(RT_USING_CHERRYUSB) && !defined(CONFIG_USB_HS)) #define USBH_DP_PORT (GPIO_PORT_B) #define USBH_DP_PIN (GPIO_PIN_15) #define USBH_DP_FUNC (GPIO_FUNC_10) diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/irq_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/irq_config.h index eebe5cbcda2..9ceb83944b1 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/irq_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/irq_config.h @@ -308,12 +308,12 @@ extern "C" { #endif/* RT_USING_ALARM */ -#if defined(BSP_USING_USBFS) +#if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) #define BSP_USBFS_GLB_IRQ_NUM INT003_IRQn #define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_USBFS */ -#if defined(BSP_USING_USBHS) +#if defined(BSP_USING_USBHS) || defined(RT_USING_CHERRYUSB) #define BSP_USBHS_GLB_IRQ_NUM INT000_IRQn #define BSP_USBHS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_USBHS */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h index eaa2c4bd874..d762176f47b 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h @@ -144,44 +144,14 @@ extern "C" #define ETH_MAC_ADDR4 (0x00U) #define ETH_MAC_ADDR5 (0x00U) -/* Common PHY Registers */ -#define PHY_BCR (0x00U) /*!< Basic Control Register */ -#define PHY_BSR (0x01U) /*!< Basic Status Register */ - -#define PHY_SOFT_RESET (0x8000U) /*!< PHY Soft Reset */ -#define PHY_LOOPBACK (0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M (0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M (0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M (0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M (0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION (0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_POWERDOWN (0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE (0x0400U) /*!< Isolate PHY from MII */ -#define PHY_RESTART_AUTONEGOTIATION (0x0200U) /*!< Restart auto-negotiation function */ - -#define PHY_100BASE_TX_FD (0x4000U) /*!< 100Base-TX full duplex support */ -#define PHY_100BASE_TX_HD (0x2000U) /*!< 100Base-TX half duplex support */ -#define PHY_10BASE_T_FD (0x1000U) /*!< 10Base-T full duplex support */ -#define PHY_10BASE_T_HD (0x0800U) /*!< 10Base-T half duplex support */ -#define PHY_AUTONEGO_COMPLETE (0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINK_STATUS (0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION (0x0002U) /*!< Jabber condition detected */ - #if defined (ETH_PHY_USING_RTL8201F) /* PHY(RTL8201F) Address*/ -#define ETH_PHY_ADDR (0x00U) - -/* PHY Configuration delay(ms) */ -#define ETH_PHY_RST_DELAY (0x0080UL) -#define ETH_PHY_CONFIG_DELAY (0x0800UL) -#define ETH_PHY_RD_TIMEOUT (0x0005UL) -#define ETH_PHY_WR_TIMEOUT (0x0005UL) +#define ETH_PHY_ADDR (0x01U) /* PHY Status Register */ -#define PHY_SR (PHY_BCR) /*!< PHY status register */ - -#define PHY_DUPLEX_STATUS (PHY_FULLDUPLEX_10M) /*!< PHY Duplex mask */ -#define PHY_SPEED_STATUS (PHY_HALFDUPLEX_100M) /*!< PHY Speed mask */ +#define PHY_SR (0x00U) /*!< PHY status register */ +#define PHY_DUPLEX_STATUS (0x0100U) /*!< PHY Duplex mask */ +#define PHY_SPEED_STATUS (0x2000U) /*!< PHY Speed mask */ #endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.icf b/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.icf index b19e19460ad..6e3bb10d40c 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.icf +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.icf @@ -86,9 +86,9 @@ define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; /*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_cstack__ = 0x800; define symbol __ICFEDIT_size_proc_stack__ = 0x0; -define symbol __ICFEDIT_size_heap__ = 0x2000; +define symbol __ICFEDIT_size_heap__ = 0x0; /**** End of ICF editor section. ###ICF###*/ /******************************************************************************* diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.ld b/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.ld index 9eba9a320d7..a1e0bc0573f 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.ld +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.ld @@ -88,6 +88,12 @@ SECTIONS __rt_init_end = .; . = ALIGN(4); + /* section for CherryUSB. */ + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(4); _etext = .; } >FLASH diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/usb_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/usb_config.h new file mode 100644 index 00000000000..dd239502be3 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/usb_config.h @@ -0,0 +1,351 @@ +/* + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-08 CDT first version + */ + +#ifndef CHERRYUSB_CONFIG_H +#define CHERRYUSB_CONFIG_H + +/* ================ USB common Configuration ================ */ + +#ifdef __RTTHREAD__ + #include + + #define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) +#else + #define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) +#endif + +#ifndef CONFIG_USB_DBG_LEVEL + #define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#endif + +/* Enable print with color */ +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +// #define CONFIG_USB_DCACHE_ENABLE + +/* data align size when use dma or use dcache */ +#ifdef CONFIG_USB_DCACHE_ENABLE + #define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64 +#else + #define CONFIG_USB_ALIGN_SIZE 4 +#endif + +/* attribute data into no cache ram */ +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) + +/* use usb_memcpy default for high performance but cost more flash memory. + * And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4. +*/ +// #define CONFIG_USB_MEMCPY_DISABLE + +/* ================= USB Device Stack Configuration ================ */ + +/* Ep0 in and out transfer buffer */ +#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN + #define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#endif + +/* Send ep0 in data from user buffer instead of copying into ep0 reqdata + * Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE +*/ +// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY + +/* Check if the input descriptor is correct */ +// #define CONFIG_USBDEV_DESC_CHECK + +/* Enable test mode */ +// #define CONFIG_USBDEV_TEST_MODE + +/* enable advance desc register api */ +#define CONFIG_USBDEV_ADVANCE_DESC + +/* move ep0 setup handler from isr to thread */ +// #define CONFIG_USBDEV_EP0_THREAD + +#ifndef CONFIG_USBDEV_EP0_PRIO + #define CONFIG_USBDEV_EP0_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_EP0_STACKSIZE + #define CONFIG_USBDEV_EP0_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_LUN + #define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE + #define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#endif + +#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING + #define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING + #define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_VERSION_STRING + #define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +/* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */ +// #define CONFIG_USBDEV_MSC_POLLING + +/* move msc read & write from isr to thread */ +// #define CONFIG_USBDEV_MSC_THREAD + +#ifndef CONFIG_USBDEV_MSC_PRIO + #define CONFIG_USBDEV_MSC_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MSC_STACKSIZE + #define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE + #define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS + #define CONFIG_USBDEV_MTP_MAX_OBJECTS 256 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME + #define CONFIG_USBDEV_MTP_MAX_PATHNAME 256 +#endif + +#define CONFIG_USBDEV_MTP_THREAD + +#ifndef CONFIG_USBDEV_MTP_PRIO + #define CONFIG_USBDEV_MTP_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MTP_STACKSIZE + #define CONFIG_USBDEV_MTP_STACKSIZE 4096 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE + #define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ +#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE + #define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID + #define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC + #define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#endif + +#define CONFIG_USBDEV_RNDIS_USING_LWIP +#define CONFIG_USBDEV_CDC_ECM_USING_LWIP + +/* ================ USB HOST Stack Configuration ================== */ + +#define CONFIG_USBHOST_MAX_RHPORTS 1 +#define CONFIG_USBHOST_MAX_EXTHUBS 1 +#define CONFIG_USBHOST_MAX_EHPORTS 4 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 4 + +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO + #define CONFIG_USBHOST_PSC_PRIO 0 +#endif +#ifndef CONFIG_USBHOST_PSC_STACKSIZE + #define CONFIG_USBHOST_PSC_STACKSIZE 2048 +#endif + +//#define CONFIG_USBHOST_GET_STRING_DESC + +// #define CONFIG_USBHOST_MSOS_ENABLE +#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE + #define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#endif + +/* Ep0 max transfer buffer */ +#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN + #define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#endif + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT + #define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT + #define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#endif + +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#endif + +#define CONFIG_USBHOST_BLUETOOTH_HCI_H4 +// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG + +#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE + #define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#endif +#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE + #define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#endif + +/* ================ USB Device Port Configuration ================*/ + +#ifndef CONFIG_USBDEV_MAX_BUS + #define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip +#endif + +#ifndef CONFIG_USBDEV_EP_NUM + #define CONFIG_USBDEV_EP_NUM 8 +#endif + +// #define CONFIG_USBDEV_SOF_ENABLE + +/* When your chip hardware supports high-speed and wants to initialize it in high-speed mode, + * the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS. + * +*/ +//#define CONFIG_USB_HS + +/* ---------------- DWC2 Configuration ---------------- */ +/* enable dwc2 buffer dma mode for device +*/ +// #define CONFIG_USB_DWC2_DMA_ENABLE + +/* Defined FS Core device FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX6_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX7_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX8_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX9_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX10_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX11_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX12_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX13_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX14_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX15_FIFO_SIZE (32) + +/* Defined FS Core host FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE (64) + +/* Defined FS Core total FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE (640) + +/* Defined HS Core Device FIFO Size in words 32-bits */ +#define CONFIG_USB_HS_CORE_DEVICE_RX_FIFO_SIZE (1024) +#define CONFIG_USB_HS_CORE_DEVICE_TX0_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX1_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX2_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX3_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX4_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX5_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX6_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX7_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX8_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX9_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX10_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX11_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX12_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX13_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX14_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX15_FIFO_SIZE (0) + +/* Defined HS Core host FIFO Size in words 32-bits */ +#define CONFIG_USB_HS_CORE_HOST_RX_FIFO_SIZE (512) +#define CONFIG_USB_HS_CORE_HOST_NP_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_HOST_PE_FIFO_SIZE (256) + +/* Defined HS Core total FIFO Size in words 32-bits */ +#define CONFIG_USB_HS_CORE_TOTAL_FIFO_SIZE (2048) + + +/* ================ USB Host Port Configuration ==================*/ +#ifndef CONFIG_USBHOST_MAX_BUS + #define CONFIG_USBHOST_MAX_BUS 1 +#endif + +#ifndef CONFIG_USBHOST_PIPE_NUM + #define CONFIG_USBHOST_PIPE_NUM 10 +#endif + + +#ifndef usb_phyaddr2ramaddr + #define usb_phyaddr2ramaddr(addr) (addr) +#endif + +#ifndef usb_ramaddr2phyaddr + #define usb_ramaddr2phyaddr(addr) (addr) +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/bsp_compile_ci.bat b/bsp/hc32/ev_hc32f4a0_lqfp176/bsp_compile_ci.bat new file mode 100644 index 00000000000..7a3904105df --- /dev/null +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/bsp_compile_ci.bat @@ -0,0 +1,132 @@ +scons --attach=devices.adc +scons -j4 +scons --attach=default + +scons --attach=devices.can +scons -j4 +scons --attach=default + +scons --attach=devices.crypto +scons -j4 +scons --attach=default + +scons --attach=devices.dac +scons -j4 +scons --attach=default + +scons --attach=devices.flash +scons -j4 +scons --attach=default + +scons --attach=devices.gpio +scons -j4 +scons --attach=default + +scons --attach=devices.hwtimer +scons -j4 +scons --attach=default + +scons --attach=devices.i2c +scons -j4 +scons --attach=default + +scons --attach=devices.input_capture +scons -j4 +scons --attach=default + +scons --attach=devices.pm +scons -j4 +scons --attach=default + +scons --attach=devices.pulse_encoder_tmr6 +scons -j4 +scons --attach=default + +scons --attach=devices.pulse_encoder_tmra +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmr4 +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmr6 +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmra +scons -j4 +scons --attach=default + +scons --attach=devices.qspi +scons -j4 +scons --attach=default + +scons --attach=devices.rtc +scons -j4 +scons --attach=default + +scons --attach=devices.sdio +scons -j4 +scons --attach=default + +scons --attach=devices.soft_i2c +scons -j4 +scons --attach=default + +scons --attach=devices.spi +scons -j4 +scons --attach=default + +scons --attach=devices.uart_v1 +scons -j4 +scons --attach=default + +scons --attach=devices.uart_v2 +scons -j4 +scons --attach=default + +scons --attach=devices.usb_hs_device +scons -j4 +scons --attach=default + +scons --attach=devices.usb_hs_host +scons -j4 +scons --attach=default + +scons --attach=devices.usb_fs_device +scons -j4 +scons --attach=default + +scons --attach=devices.usb_fs_host +scons -j4 +scons --attach=default + +scons --attach=devices.watchdog_swdt +scons -j4 +scons --attach=default + +scons --attach=devices.watchdog_wdt +scons -j4 +scons --attach=default + + +scons --attach=peripheral.eth_mii +scons -j4 +scons --attach=default + +scons --attach=peripheral.eth_rmii +scons -j4 +scons --attach=default + +scons --attach=peripheral.exmc_nand +scons -j4 +scons --attach=default + +scons --attach=peripheral.exmc_sdram +scons -j4 +scons --attach=default + +scons --attach=peripheral.spi_flash +scons -j4 +scons --attach=default diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/template.uvprojx b/bsp/hc32/ev_hc32f4a0_lqfp176/template.uvprojx index f4ae04a9877..cf934ed2a47 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/template.uvprojx +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/template.uvprojx @@ -325,7 +325,7 @@ 0 0 1 - 0 + 1 0 0 0 diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f4a8_lqfp176/.ci/attachconfig/ci.attachconfig.yml index 4be9a3f29aa..e5798b47293 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/.ci/attachconfig/ci.attachconfig.yml @@ -1,12 +1,202 @@ +# ------ device CI ------ +devices.adc: + kconfig: + - CONFIG_BSP_USING_ADC=y + - CONFIG_BSP_USING_ADC1=y + - CONFIG_BSP_ADC1_USING_DMA=y +devices.can: + kconfig: + - CONFIG_RT_USING_CAN_MCAN=y + - CONFIG_BSP_USING_CAN=y + - CONFIG_BSP_USING_CAN1=y + - CONFIG_RT_CAN_USING_CANFD=y + - CONFIG_RT_CAN_USING_HDR=y +devices.crypto: + kconfig: + - CONFIG_BSP_USING_HWCRYPTO=y + - CONFIG_BSP_USING_UQID=y + - CONFIG_BSP_USING_RNG=y + - CONFIG_BSP_USING_CRC=y + - CONFIG_BSP_USING_HASH=y +devices.dac: + kconfig: + - CONFIG_BSP_USING_DAC=y + - CONFIG_BSP_USING_DAC1=y +devices.flash: + kconfig: + - CONFIG_BSP_USING_ON_CHIP_FLASH=y + - CONFIG_RT_USING_FAL=y + - CONFIG_RT_USING_SPI=y + - CONFIG_RT_USING_SFUD=y devices.gpio: kconfig: - CONFIG_BSP_USING_GPIO=y +devices.hwtimer: + kconfig: + - CONFIG_BSP_USING_HWTIMER=y + - CONFIG_BSP_USING_TMRA_1=y +devices.i2c: + kconfig: - CONFIG_BSP_USING_I2C=y - - CONFIG_BSP_USING_I2C_HW=y - CONFIG_BSP_USING_I2C1=y - - CONFIG_BSP_USING_TCA9539=y - - CONFIG_BSP_USING_EXT_IO=y -devices.uart: + - CONFIG_BSP_I2C1_TX_USING_DMA=y + - CONFIG_BSP_I2C1_RX_USING_DMA=y +devices.input_capture: + kconfig: + - CONFIG_BSP_USING_INPUT_CAPTURE=y + - CONFIG_BSP_USING_INPUT_CAPTURE_TMR6=y + - CONFIG_BSP_USING_INPUT_CAPTURE_TMR6_1=y +devices.mcan: + kconfig: + - CONFIG_RT_USING_CAN_MCAN=y + - CONFIG_BSP_USING_MCAN=y + - CONFIG_BSP_USING_MCAN1=y + - CONFIG_RT_CAN_USING_CANFD=y + - CONFIG_RT_CAN_USING_HDR=y +devices.pm: + kconfig: + - CONFIG_BSP_USING_PM=y + - CONFIG_IDLE_THREAD_STACK_SIZE=512 +devices.pulse_encoder_tmr6: + kconfig: + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_TMR6_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER_TMR6_1=y +devices.pulse_encoder_tmra: + kconfig: + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_TMRA_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER_TMRA_1=y +devices.pwm_tmr4: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMR4=y + - CONFIG_BSP_USING_PWM_TMR4_1=y + - CONFIG_BSP_USING_PWM_TMR4_1_OUH=y + - CONFIG_BSP_USING_PWM_TMR4_1_OUL=y +devices.pwm_tmr6: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMR6=y + - CONFIG_BSP_USING_PWM_TMR6_1=y + - CONFIG_BSP_USING_PWM_TMR6_1_A=y + - CONFIG_BSP_USING_PWM_TMR6_1_B=y +devices.pwm_tmra: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMRA=y + - CONFIG_BSP_USING_PWM_TMRA_1=y + - CONFIG_BSP_USING_PWM_TMRA_1_CH1=y + - CONFIG_BSP_USING_PWM_TMRA_1_CH2=y +devices.qspi: + kconfig: + - CONFIG_BSP_USING_QSPI=y + - CONFIG_BSP_QSPI_USING_DMA=y + - CONFIG_BSP_QSPI_USING_SOFT_CS=y +devices.rtc: + kconfig: + - CONFIG_BSP_USING_RTC=y + - CONFIG_RT_USING_ALARM=y +devices.sdio: + kconfig: + - CONFIG_BSP_USING_SDIO=y + - CONFIG_BSP_USING_SDIO1=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.soft_i2c: kconfig: + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_I2C1_SW=y +devices.spi: + kconfig: + - CONFIG_BSP_USING_SPI=y + - CONFIG_BSP_USING_SPI1=y + - CONFIG_BSP_SPI1_TX_USING_DMA=y + - CONFIG_BSP_SPI1_RX_USING_DMA=y + - CONFIG_BSP_SPI_USING_DMA=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.uart_v1: + kconfig: + - CONFIG_RT_USING_SERIAL_V1=y - CONFIG_BSP_USING_UART=y - CONFIG_BSP_USING_UART1=y + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_UART1_RX_USING_DMA=y + - CONFIG_BSP_UART1_TX_USING_DMA=y +devices.uart_v2: + kconfig: + - CONFIG_RT_USING_SERIAL_V2=y + - CONFIG_BSP_USING_UART=y + - CONFIG_BSP_USING_UART1=y + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_UART1_RX_USING_DMA=y + - CONFIG_BSP_UART1_TX_USING_DMA=y +devices.usb_hs_device: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBD=y + - CONFIG_BSP_USING_USBHS=y + - CONFIG_BSP_USING_USBD_HS=y + - CONFIG_RT_USB_DEVICE_MSTORAGE=y +devices.usb_hs_host: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBH=y + - CONFIG_BSP_USING_USBHS=y + - CONFIG_BSP_USING_USBH_HS=y + - CONFIG_RT_USBH_MSTORAGE=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.usb_fs_device: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBD=y + - CONFIG_BSP_USING_USBFS=y + - CONFIG_BSP_USING_USBD_FS=y + - CONFIG_RT_USB_DEVICE_MSTORAGE=y +devices.usb_fs_host: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBH=y + - CONFIG_BSP_USING_USBFS=y + - CONFIG_BSP_USING_USBH_FS=y + - CONFIG_RT_USBH_MSTORAGE=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.watchdog_swdt: + kconfig: + - CONFIG_BSP_USING_WDT_TMR=y + - CONFIG_BSP_USING_SWDT=y +devices.watchdog_wdt: + kconfig: + - CONFIG_BSP_USING_WDT_TMR=y + - CONFIG_BSP_USING_WDT=y + +# ------ peripheral CI ------ +peripheral.eth_mii: + kconfig: + - CONFIG_BSP_USING_ETH=y + - CONFIG_ETH_INTERFACE_USING_MII=y + - CONFIG_RT_USING_LWIP212=y + - CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +peripheral.eth_rmii: + kconfig: + - CONFIG_BSP_USING_ETH=y + - CONFIG_ETH_INTERFACE_USING_RMII=y + - CONFIG_ETH_PHY_USING_INTERRUPT_MODE=y + - CONFIG_RT_USING_LWIP212=y + - CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +peripheral.exmc_nand: + kconfig: + - CONFIG_BSP_USING_EXMC=y + - CONFIG_BSP_USING_NAND=y + - CONFIG_FINSH_USING_MSH=y +peripheral.exmc_sdram: + kconfig: + - CONFIG_BSP_USING_EXMC=y + - CONFIG_BSP_USING_SDRAM=y + - CONFIG_FINSH_USING_MSH=y +peripheral.spi_flash: + kconfig: + - CONFIG_BSP_USING_SPI_FLASH=y diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/README.md b/bsp/hc32/ev_hc32f4a8_lqfp176/README.md index 258c8e3fe45..65d551688a7 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/README.md +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/README.md @@ -23,13 +23,13 @@ EV_F4A8_LQ176 是 XHSC 官方推出的开发板，搭载 HC32F4A8SITB 芯片， EV_F4A8_LQ176 开发板常用 **板载资源** 如下： - MCU：HC32F4A8SITB，主频240MHz，2048KB FLASH，512KB RAM -- 外部RAM：IS62WV51216(SRAM, 1MB) W9825G6KH(SDRAM, 8MB) -- 外部FLASH: MT29F2G08AB(Nand, 256MB) W25Q64(SPI NOR, 8MB) +- 外部RAM：IS62WV51216(SRAM，1MB) W9825G6KH(SDRAM，8MB) +- 外部FLASH: MT29F2G08AB(Nand，256MB) W25Q64(SPI NOR，8MB) - 常用外设 - - LED：3 个， user LED(LED0,LED1,LED2)。 + - LED：3 个，User LED(LED0、LED1、LED2)。 - 按键：6个，矩阵键盘(K1~K4)、WAKEUP(K5)、RESET(K0)。 -- 常用接口：USB转串口、SD卡接口、以太网接口、LCD接口、USB HS、USB FS、USB 3300、DVP接口、3.5mm耳机接口、Line in接口、喇叭接口 -- 调试接口：板载DAP调试器、标准JTAG/SWD。 +- 常用接口：SD卡接口、以太网接口、LCD接口、USB FS/HS接口、DVP接口、3.5mm耳机接口、Line in接口、CAN/MCAN接口、LIN接口、RS485接口。 +- 调试接口：板载DAP调试器（含USB转串口）、标准JTAG/SWD。 开发板更多详细信息请参考小华半导体半导体[EV_F4A8_LQ176](https://www.xhsc.com.cn) @@ -37,20 +37,35 @@ EV_F4A8_LQ176 开发板常用 **板载资源** 如下： 本 BSP 目前对外设的支持情况如下： -| **板载外设** | **支持情况** | **备注** | +| **板载外设** | **支持情况** | **备注** | | :------------ | :-----------: | :-----------------------------------: | -| USB 转串口 | 支持 | 使用 UART1 | -| LED | 支持 | LED | -| SDRAM | 支持 | IS42S16400J | +| ETH | 支持 | RTL8201F | +| Nand | 支持 | MT29F2G08AB | +| SDRAM | 支持 | W9825G6KH | +| USB 转串口 | 支持 | 使用 UART1 | -| **片上外设** | **支持情况** | **备注** | +| **片上外设** | **支持情况** | **备注** | | :------------ | :-----------: | :-----------------------------------: | -| CAN | 支持 | | -| GPIO | 支持 | PA0, PA1... PI13 ---> PIN: 0, 1...141 | -| WDT | 支持 | | -| SPI | 支持 | SPI1~6 | -| SDIO | 支持 | | -| UART V1 & V2 | 支持 | UART1~10 | +| ADC | 支持 | | +| CAN | 支持 | | +| Crypto | 支持 | AES，CRC，HASH，RNG | +| DAC | 支持 | | +| FLASH | 支持 | | +| GPIO | 支持 | PA0，PA1...PI13 ---> PIN：0，1...141 | +| HwTimer | 支持 | | +| I2C | 支持 | 软件、硬件 I2C | +| InputCapture | 支持 | | +| MCAN | 支持 | | +| PM | 支持 | | +| PulseEncoder | 支持 | | +| PWM | 支持 | | +| QSPI | 支持 | | +| RTC | 支持 | 闹钟精度为1分钟 | +| SDIO | 支持 | | +| SPI | 支持 | | +| UART V1 & V2 | 支持 | | +| USB | 支持 | USBFS/HS Core， device/host模式 | +| WDT | 支持 | | ## 使用说明 @@ -105,9 +120,24 @@ msh > 4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 +## 注意事项 + +| 板载外设 | 模式 | 协议栈 | 注意事项 | +| -------- | ------ | :------------: | ------------------------------------------------------------ | +| USB | device | ALL | 由于协议栈的设计，当配置为CDC设备时，打开USB虚拟串口，需使能流控的DTR信号。（如使用SSCOM串口助手打开USB虚拟串口时，勾选DTR选框） | +| USB | device | ALL | 由于外部PHY管脚复用的原因，当配置使用USBHS Core并且使用外部PHY时，需先通过J14连接到主机（如PC），再复位MCU运行程序；或者将J24跳帽先短接，再复位MCU运行程序。 | +| USB | ALL | ALL | 由于main()函数中的LED闪烁示例，使用的是USBFS主机的供电控制管脚，因而当配置为使用USBFS Core时，需要将main()函数中的LED示例代码手动屏蔽。 | +| USB | host | ALL | 为确保USB主机对外供电充足，建议通过J35外接5V电源供电，并短接J32对应跳帽。 | +| USB | host | ALL | 由于外部PHY管脚复用的原因，当配置使用USBHS Core并且使用外部PHY时，需通过J14先连接好OTG线，再复位MCU运行程序；或者将J24跳帽先短接，再复位MCU运行程序。 | +| USB | host | RTT legacy USB | 目前仅实现并测试了对U盘的支持。 | +| USB | host | RTT legacy USB | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 | +| USB | ALL | ALL | 由于管脚复用的原因，当配置使用USBHS Core时，无法同时使用板载SPI FLASH。 | +| USB | ALL | ALL | CherryUSB 与 RTT legacy USB 组件不可同时使用;
CherryUSB与 ”On-Chip Peripheral Driver---> []Enable USB“ 不可同时使能及配置。 | +| USB | ALL | RTT legacy USB | 通过“board/config/usb_config/usb_app_conf.h” 进行应用个性化配置（主要为FIFO分配） | +| USB | ALL | CherryUSB | 通过“board/ports/usb_config.h”进行应用个性化配置（如FIFO分配、是否使用DMA[Device]、是否使用高速PHY等） | ## 联系人信息 维护人: -- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱： \ No newline at end of file +- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱： \ No newline at end of file diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/Kconfig b/bsp/hc32/ev_hc32f4a8_lqfp176/board/Kconfig index a542cd175e1..cae9576d068 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/Kconfig +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/Kconfig @@ -738,16 +738,6 @@ menu "On-chip Peripheral Drivers" bool "Using Hardware AES" default n select RT_HWCRYPTO_USING_AES - if BSP_USING_AES - choice - prompt "Select AES Mode" - default BSP_USING_AES_ECB - - config BSP_USING_AES_ECB - bool "ECB mode" - select RT_HWCRYPTO_USING_AES_ECB - endchoice - endif config BSP_USING_HASH bool "Using Hardware Hash" @@ -842,6 +832,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_USB bool "Enable USB" default n + depends on !RT_USING_CHERRYUSB if BSP_USING_USB config BSP_USING_USBD bool diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/board.c b/bsp/hc32/ev_hc32f4a8_lqfp176/board/board.c index 1510d82e215..4a2e0ccce65 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/board.c +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/board.c @@ -40,7 +40,7 @@ void SystemClock_Config(void) { stc_clock_xtal_init_t stcXtalInit; stc_clock_pll_init_t stcPLLHInit; -#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) stc_clock_pllx_init_t stcPLLAInit; #endif #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) @@ -87,7 +87,7 @@ void SystemClock_Config(void) GPIO_SetReadWaitCycle(GPIO_RD_WAIT4); CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); -#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) /* PLLX for USB */ (void)CLK_PLLxStructInit(&stcPLLAInit); /* VCO = (8/2)*120 = 480MHz*/ @@ -134,7 +134,7 @@ void PeripheralClock_Config(void) CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK); #endif -#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) CLK_SetUSBClockSrc(CLK_USBCLK_PLLXP); #endif } diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.c b/bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.c index 85514577772..9aa7eb65d2a 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.c +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.c @@ -669,6 +669,83 @@ rt_err_t rt_hw_usbhs_board_init(void) } #endif +#if defined(RT_USING_CHERRYUSB) +rt_err_t rt_hw_usbfs_board_init(uint8_t devmode) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBF_DM_PORT, USBF_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBF_DP_PORT, USBF_DP_PIN, &stcGpioCfg); + if (0U != devmode) + { + GPIO_SetFunc(USBF_VBUS_PORT, USBF_VBUS_PIN, USBF_VBUS_FUNC); /* VBUS */ + } + else + { + GPIO_SetFunc(USBF_DRVVBUS_PORT, USBF_DRVVBUS_PIN, USBF_DRVVBUS_FUNC); /* DRV VBUS */ + } + return RT_EOK; +} + +rt_err_t rt_hw_usbhs_board_init(uint8_t devmode) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + +#if !defined(CONFIG_USB_HS) + /* USBHS work in embedded PHY */ + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBH_DM_PORT, USBH_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_DP_PORT, USBH_DP_PIN, &stcGpioCfg); + if (0U != devmode) + { + GPIO_SetFunc(USBH_VBUS_PORT, USBH_VBUS_PIN, USBH_VBUS_FUNC); + } + else + { + GPIO_OutputCmd(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN, ENABLE); + GPIO_SetPins(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN); /* DRV VBUS with GPIO funciton */ + } +#else + /* Reset 3300 */ + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_SET); + TCA9539_ConfigPin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_DIR_OUT); + + (void)GPIO_StructInit(&stcGpioCfg); + /* High drive capability */ + stcGpioCfg.u16PinDrv = PIN_HIGH_DRV; + (void)GPIO_Init(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, &stcGpioCfg); + + GPIO_SetFunc(USBH_ULPI_CLK_PORT, USBH_ULPI_CLK_PIN, USBH_ULPI_CLK_FUNC); + GPIO_SetFunc(USBH_ULPI_DIR_PORT, USBH_ULPI_DIR_PIN, USBH_ULPI_DIR_FUNC); + GPIO_SetFunc(USBH_ULPI_NXT_PORT, USBH_ULPI_NXT_PIN, USBH_ULPI_NXT_FUNC); + GPIO_SetFunc(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, USBH_ULPI_STP_FUNC); + GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); + GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); + GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); + GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); + GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); + GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); + GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); + GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); + + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_RESET); +#endif + + return RT_EOK; +} +#endif + #if defined(BSP_USING_QSPI) rt_err_t rt_hw_qspi_board_init(void) { diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.h index 4543a1c5a44..4997929780e 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.h @@ -15,7 +15,9 @@ #include #include "hc32_ll.h" #include "drv_config.h" - +#if defined(RT_USING_CHERRYUSB) + #include "usb_config.h" +#endif /************************* XTAL port **********************/ #define XTAL_PORT (GPIO_PORT_H) @@ -585,8 +587,17 @@ #endif #endif -#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) - #if defined(BSP_USING_USBFS) +#if defined(RT_USING_CHERRYUSB) + #if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || \ + defined(BSP_USING_USBFS) || defined(BSP_USING_USBHS) || \ + defined(BSP_USING_USBHS_PHY_EMBED) || defined(BSP_USING_USBHS_PHY_EXTERN) || \ + defined(RT_USING_USB) + #error "When using CherryUSB, Please donot Enable 'On-Chip Peripheral Driver---> []Enable USB' or using USB legacy version!" + #endif +#endif + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) + #if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) /* USBFS Core*/ #define USBF_DP_PORT (GPIO_PORT_A) #define USBF_DP_PIN (GPIO_PIN_12) @@ -599,9 +610,9 @@ #define USBF_DRVVBUS_PIN (GPIO_PIN_09) #define USBF_DRVVBUS_FUNC (GPIO_FUNC_10) #endif - #if defined(BSP_USING_USBHS) + #if defined(BSP_USING_USBHS) || defined(RT_USING_CHERRYUSB) /* USBHS Core*/ - #if defined(BSP_USING_USBHS_PHY_EMBED) + #if defined(BSP_USING_USBHS_PHY_EMBED) || (defined(RT_USING_CHERRYUSB) && !defined(CONFIG_USB_HS)) #define USBH_DP_PORT (GPIO_PORT_B) #define USBH_DP_PIN (GPIO_PIN_15) #define USBH_DP_FUNC (GPIO_FUNC_10) diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/irq_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/irq_config.h index 01d2dda2af4..85ea6124400 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/irq_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/irq_config.h @@ -369,17 +369,11 @@ extern "C" { #if defined(BSP_USING_MCAN1) #define BSP_MCAN1_INT0_IRQ_NUM INT124_IRQn #define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT - -#define BSP_MCAN1_INT1_IRQ_NUM INT125_IRQn -#define BSP_MCAN1_INT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_MCAN1 */ #if defined(BSP_USING_MCAN2) #define BSP_MCAN2_INT0_IRQ_NUM INT126_IRQn #define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT - -#define BSP_MCAN2_INT1_IRQ_NUM INT127_IRQn -#define BSP_MCAN2_INT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_MCAN2 */ #if defined(BSP_USING_SDIO1) @@ -398,12 +392,12 @@ extern "C" { #endif/* RT_USING_ALARM */ -#if defined(BSP_USING_USBFS) +#if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) #define BSP_USBFS_GLB_IRQ_NUM INT003_IRQn #define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_USBFS */ -#if defined(BSP_USING_USBHS) +#if defined(BSP_USING_USBHS) || defined(RT_USING_CHERRYUSB) #define BSP_USBHS_GLB_IRQ_NUM INT000_IRQn #define BSP_USBHS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_USBHS */ diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/linker_scripts/link.icf b/bsp/hc32/ev_hc32f4a8_lqfp176/board/linker_scripts/link.icf index d001ffd3bb0..2262402986a 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/linker_scripts/link.icf +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/linker_scripts/link.icf @@ -73,9 +73,9 @@ define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; /*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_cstack__ = 0x800; define symbol __ICFEDIT_size_proc_stack__ = 0x0; -define symbol __ICFEDIT_size_heap__ = 0x2000; +define symbol __ICFEDIT_size_heap__ = 0x0; /**** End of ICF editor section. ###ICF###*/ /******************************************************************************* diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/linker_scripts/link.ld b/bsp/hc32/ev_hc32f4a8_lqfp176/board/linker_scripts/link.ld index c620bc8170b..d97be4a677b 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/linker_scripts/link.ld +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/linker_scripts/link.ld @@ -88,6 +88,12 @@ SECTIONS __rt_init_end = .; . = ALIGN(4); + /* section for CherryUSB. */ + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(4); _etext = .; } >FLASH diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/usb_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/usb_config.h new file mode 100644 index 00000000000..dd239502be3 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/usb_config.h @@ -0,0 +1,351 @@ +/* + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-08 CDT first version + */ + +#ifndef CHERRYUSB_CONFIG_H +#define CHERRYUSB_CONFIG_H + +/* ================ USB common Configuration ================ */ + +#ifdef __RTTHREAD__ + #include + + #define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) +#else + #define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) +#endif + +#ifndef CONFIG_USB_DBG_LEVEL + #define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#endif + +/* Enable print with color */ +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +// #define CONFIG_USB_DCACHE_ENABLE + +/* data align size when use dma or use dcache */ +#ifdef CONFIG_USB_DCACHE_ENABLE + #define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64 +#else + #define CONFIG_USB_ALIGN_SIZE 4 +#endif + +/* attribute data into no cache ram */ +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) + +/* use usb_memcpy default for high performance but cost more flash memory. + * And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4. +*/ +// #define CONFIG_USB_MEMCPY_DISABLE + +/* ================= USB Device Stack Configuration ================ */ + +/* Ep0 in and out transfer buffer */ +#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN + #define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#endif + +/* Send ep0 in data from user buffer instead of copying into ep0 reqdata + * Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE +*/ +// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY + +/* Check if the input descriptor is correct */ +// #define CONFIG_USBDEV_DESC_CHECK + +/* Enable test mode */ +// #define CONFIG_USBDEV_TEST_MODE + +/* enable advance desc register api */ +#define CONFIG_USBDEV_ADVANCE_DESC + +/* move ep0 setup handler from isr to thread */ +// #define CONFIG_USBDEV_EP0_THREAD + +#ifndef CONFIG_USBDEV_EP0_PRIO + #define CONFIG_USBDEV_EP0_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_EP0_STACKSIZE + #define CONFIG_USBDEV_EP0_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_LUN + #define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE + #define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#endif + +#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING + #define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING + #define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_VERSION_STRING + #define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +/* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */ +// #define CONFIG_USBDEV_MSC_POLLING + +/* move msc read & write from isr to thread */ +// #define CONFIG_USBDEV_MSC_THREAD + +#ifndef CONFIG_USBDEV_MSC_PRIO + #define CONFIG_USBDEV_MSC_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MSC_STACKSIZE + #define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE + #define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS + #define CONFIG_USBDEV_MTP_MAX_OBJECTS 256 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME + #define CONFIG_USBDEV_MTP_MAX_PATHNAME 256 +#endif + +#define CONFIG_USBDEV_MTP_THREAD + +#ifndef CONFIG_USBDEV_MTP_PRIO + #define CONFIG_USBDEV_MTP_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MTP_STACKSIZE + #define CONFIG_USBDEV_MTP_STACKSIZE 4096 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE + #define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ +#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE + #define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID + #define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC + #define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#endif + +#define CONFIG_USBDEV_RNDIS_USING_LWIP +#define CONFIG_USBDEV_CDC_ECM_USING_LWIP + +/* ================ USB HOST Stack Configuration ================== */ + +#define CONFIG_USBHOST_MAX_RHPORTS 1 +#define CONFIG_USBHOST_MAX_EXTHUBS 1 +#define CONFIG_USBHOST_MAX_EHPORTS 4 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 4 + +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO + #define CONFIG_USBHOST_PSC_PRIO 0 +#endif +#ifndef CONFIG_USBHOST_PSC_STACKSIZE + #define CONFIG_USBHOST_PSC_STACKSIZE 2048 +#endif + +//#define CONFIG_USBHOST_GET_STRING_DESC + +// #define CONFIG_USBHOST_MSOS_ENABLE +#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE + #define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#endif + +/* Ep0 max transfer buffer */ +#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN + #define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#endif + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT + #define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT + #define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#endif + +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE + #define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE + #define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#endif + +#define CONFIG_USBHOST_BLUETOOTH_HCI_H4 +// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG + +#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE + #define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#endif +#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE + #define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#endif + +/* ================ USB Device Port Configuration ================*/ + +#ifndef CONFIG_USBDEV_MAX_BUS + #define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip +#endif + +#ifndef CONFIG_USBDEV_EP_NUM + #define CONFIG_USBDEV_EP_NUM 8 +#endif + +// #define CONFIG_USBDEV_SOF_ENABLE + +/* When your chip hardware supports high-speed and wants to initialize it in high-speed mode, + * the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS. + * +*/ +//#define CONFIG_USB_HS + +/* ---------------- DWC2 Configuration ---------------- */ +/* enable dwc2 buffer dma mode for device +*/ +// #define CONFIG_USB_DWC2_DMA_ENABLE + +/* Defined FS Core device FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX6_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX7_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX8_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX9_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX10_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX11_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX12_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX13_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX14_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX15_FIFO_SIZE (32) + +/* Defined FS Core host FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE (64) + +/* Defined FS Core total FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE (640) + +/* Defined HS Core Device FIFO Size in words 32-bits */ +#define CONFIG_USB_HS_CORE_DEVICE_RX_FIFO_SIZE (1024) +#define CONFIG_USB_HS_CORE_DEVICE_TX0_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX1_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX2_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX3_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX4_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX5_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX6_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX7_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX8_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX9_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX10_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX11_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX12_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX13_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX14_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX15_FIFO_SIZE (0) + +/* Defined HS Core host FIFO Size in words 32-bits */ +#define CONFIG_USB_HS_CORE_HOST_RX_FIFO_SIZE (512) +#define CONFIG_USB_HS_CORE_HOST_NP_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_HOST_PE_FIFO_SIZE (256) + +/* Defined HS Core total FIFO Size in words 32-bits */ +#define CONFIG_USB_HS_CORE_TOTAL_FIFO_SIZE (2048) + + +/* ================ USB Host Port Configuration ==================*/ +#ifndef CONFIG_USBHOST_MAX_BUS + #define CONFIG_USBHOST_MAX_BUS 1 +#endif + +#ifndef CONFIG_USBHOST_PIPE_NUM + #define CONFIG_USBHOST_PIPE_NUM 10 +#endif + + +#ifndef usb_phyaddr2ramaddr + #define usb_phyaddr2ramaddr(addr) (addr) +#endif + +#ifndef usb_ramaddr2phyaddr + #define usb_ramaddr2phyaddr(addr) (addr) +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/bsp_compile_ci.bat b/bsp/hc32/ev_hc32f4a8_lqfp176/bsp_compile_ci.bat new file mode 100644 index 00000000000..b5b3bbe7468 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/bsp_compile_ci.bat @@ -0,0 +1,136 @@ +scons --attach=devices.adc +scons -j4 +scons --attach=default + +scons --attach=devices.can +scons -j4 +scons --attach=default + +scons --attach=devices.crypto +scons -j4 +scons --attach=default + +scons --attach=devices.dac +scons -j4 +scons --attach=default + +scons --attach=devices.flash +scons -j4 +scons --attach=default + +scons --attach=devices.gpio +scons -j4 +scons --attach=default + +scons --attach=devices.hwtimer +scons -j4 +scons --attach=default + +scons --attach=devices.i2c +scons -j4 +scons --attach=default + +scons --attach=devices.input_capture +scons -j4 +scons --attach=default + +scons --attach=devices.mcan +scons -j4 +scons --attach=default + +scons --attach=devices.pm +scons -j4 +scons --attach=default + +scons --attach=devices.pulse_encoder_tmr6 +scons -j4 +scons --attach=default + +scons --attach=devices.pulse_encoder_tmra +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmr4 +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmr6 +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmra +scons -j4 +scons --attach=default + +scons --attach=devices.qspi +scons -j4 +scons --attach=default + +scons --attach=devices.rtc +scons -j4 +scons --attach=default + +scons --attach=devices.sdio +scons -j4 +scons --attach=default + +scons --attach=devices.soft_i2c +scons -j4 +scons --attach=default + +scons --attach=devices.spi +scons -j4 +scons --attach=default + +scons --attach=devices.uart_v1 +scons -j4 +scons --attach=default + +scons --attach=devices.uart_v2 +scons -j4 +scons --attach=default + +scons --attach=devices.usb_hs_device +scons -j4 +scons --attach=default + +scons --attach=devices.usb_hs_host +scons -j4 +scons --attach=default + +scons --attach=devices.usb_fs_device +scons -j4 +scons --attach=default + +scons --attach=devices.usb_fs_host +scons -j4 +scons --attach=default + +scons --attach=devices.watchdog_swdt +scons -j4 +scons --attach=default + +scons --attach=devices.watchdog_wdt +scons -j4 +scons --attach=default + + +scons --attach=peripheral.eth_mii +scons -j4 +scons --attach=default + +scons --attach=peripheral.eth_rmii +scons -j4 +scons --attach=default + +scons --attach=peripheral.exmc_nand +scons -j4 +scons --attach=default + +scons --attach=peripheral.exmc_sdram +scons -j4 +scons --attach=default + +scons --attach=peripheral.spi_flash +scons -j4 +scons --attach=default diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.icf b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.icf index 863d995ff94..581b4dd2848 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.icf +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.icf @@ -86,9 +86,9 @@ define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; /*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_cstack__ = 0x800; define symbol __ICFEDIT_size_proc_stack__ = 0x0; -define symbol __ICFEDIT_size_heap__ = 0x2000; +define symbol __ICFEDIT_size_heap__ = 0x0; /**** End of ICF editor section. ###ICF###*/ /******************************************************************************* diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/project.uvprojx b/bsp/hc32/lckfb-hc32f4a0-lqfp100/project.uvprojx index 626117540b1..629b5d18d32 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/project.uvprojx +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/project.uvprojx @@ -324,7 +324,7 @@ 0 0 1 - 0 + 1 0 0 0 diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/template.uvprojx b/bsp/hc32/lckfb-hc32f4a0-lqfp100/template.uvprojx index 591f3cb5cc4..95d7e9e8e41 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/template.uvprojx +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/template.uvprojx @@ -327,7 +327,7 @@ 0 0 1 - 0 + 1 0 0 0 diff --git a/bsp/hc32/libraries/hc32_drivers/drv_adc.c b/bsp/hc32/libraries/hc32_drivers/drv_adc.c index 581872a1e72..e4de8623d9e 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_adc.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_adc.c @@ -87,7 +87,7 @@ static void _adc_internal_trigger0_set(adc_device *p_adc_dev) case (rt_uint32_t)CM_ADC2: u32TriggerSel = AOS_ADC2_0; break; -#if defined (HC32F472) || defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) +#if defined (HC32F472) || defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) case (rt_uint32_t)CM_ADC3: u32TriggerSel = AOS_ADC3_0; break; @@ -118,7 +118,7 @@ static void _adc_internal_trigger1_set(adc_device *p_adc_dev) case (rt_uint32_t)CM_ADC2: u32TriggerSel = AOS_ADC2_1; break; -#if defined (HC32F472) || defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) +#if defined (HC32F472) || defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) case (rt_uint32_t)CM_ADC3: u32TriggerSel = AOS_ADC3_1; break; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_crypto.c b/bsp/hc32/libraries/hc32_drivers/drv_crypto.c index f1989f69443..720ddd25728 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_crypto.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_crypto.c @@ -7,6 +7,7 @@ * Date Author Notes * 2023-02-10 CDT first version * 2024-06-11 CDT Fix compiler warning + * 2025-07-29 CDT Support HC32F334 */ #include "board.h" @@ -92,9 +93,12 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r LOG_E("crc width only support 16/32."); goto _exit; } - +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || \ + defined(HC32F334) stcCrcInit.u32InitValue = ctx->crc_cfg.last_val; - +#elif defined(HC32F4A8) + stcCrcInit.u64InitValue = ctx->crc_cfg.last_val; +#endif if (CRC_Init(&stcCrcInit) != LL_OK) { LOG_E("crc init error."); @@ -103,6 +107,16 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r LOG_D("CRC_Init."); rt_memcpy(&crc_cfgbk, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg)); } +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A8) + if (16U == ctx->crc_cfg.width) + { + (void)CRC_CRC16_AccumulateData(CRC_DATA_WIDTH_8BIT, in, length, (uint16_t *)&result); + } + else /* CRC32 */ + { + (void)CRC_CRC32_AccumulateData(CRC_DATA_WIDTH_8BIT, in, length, &result); + } +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F334) if (16U == ctx->crc_cfg.width) { result = CRC_CRC16_AccumulateData(CRC_DATA_WIDTH_8BIT, in, length); @@ -111,7 +125,7 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r { result = CRC_CRC32_AccumulateData(CRC_DATA_WIDTH_8BIT, in, length); } - +#endif _exit: rt_mutex_release(&hc32_hw_dev->mutex); @@ -225,25 +239,118 @@ static const struct hwcrypto_hash_ops hash_ops = #endif /* BSP_USING_HASH */ #if defined(BSP_USING_AES) +#if defined (HC32F4A8) +#define AES_KEY_SIZE_16BYTE (16U) +#define AES_KEY_SIZE_24BYTE (24U) +#define AES_KEY_SIZE_32BYTE (32U) +static stc_ske_init_t stcSkeInit = {0}; +static int32_t AES_Encrypt(const uint8_t *pu8Plaintext, uint32_t u32PlaintextSize, \ + const uint8_t *pu8Key, uint8_t u8KeySize, uint8_t *pu8Ciphertext) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + stc_ske_crypto_t stcCrypto; + + if ((pu8Plaintext != NULL) && (u32PlaintextSize > 0UL) && (pu8Key != NULL) && (pu8Ciphertext != NULL)) + { + if (u8KeySize == AES_KEY_SIZE_16BYTE) + { + stcSkeInit.u32Alg = SKE_ALG_AES_128; + } + else if (u8KeySize == AES_KEY_SIZE_24BYTE) + { + stcSkeInit.u32Alg = SKE_ALG_AES_192; + } + else + { + stcSkeInit.u32Alg = SKE_ALG_AES_256; + } + stcSkeInit.u32Crypto = SKE_CRYPTO_ENCRYPT; + stcSkeInit.pu8Key = pu8Key; + /* Initialize SKE */ + i32Ret = SKE_Init(&stcSkeInit); + + stcCrypto.u32Alg = stcSkeInit.u32Alg; + stcCrypto.u32Mode = stcSkeInit.u32Mode; + stcCrypto.u32CryptoSize = u32PlaintextSize; + /* Encrypt blocks */ + stcCrypto.pu8In = pu8Plaintext; + stcCrypto.pu8Out = pu8Ciphertext; + i32Ret = SKE_CryptoBlocks(&stcCrypto); + } + + return i32Ret; +} + +static int32_t AES_Decrypt(const uint8_t *pu8Ciphertext, uint32_t u32CiphertextSize, \ + const uint8_t *pu8Key, uint8_t u8KeySize, uint8_t *pu8Plaintext) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + stc_ske_crypto_t stcCrypto; + + if ((pu8Plaintext != NULL) && (u32CiphertextSize > 0UL) && (pu8Key != NULL) && (pu8Ciphertext != NULL)) + { + if (u8KeySize == AES_KEY_SIZE_16BYTE) + { + stcSkeInit.u32Alg = SKE_ALG_AES_128; + } + else if (u8KeySize == AES_KEY_SIZE_24BYTE) + { + stcSkeInit.u32Alg = SKE_ALG_AES_192; + } + else + { + stcSkeInit.u32Alg = SKE_ALG_AES_256; + } + stcSkeInit.u32Crypto = SKE_CRYPTO_DECRYPT; + stcSkeInit.pu8Key = pu8Key; + /* Initialize SKE */ + i32Ret = SKE_Init(&stcSkeInit); + + stcCrypto.u32Alg = stcSkeInit.u32Alg; + stcCrypto.u32Mode = stcSkeInit.u32Mode; + stcCrypto.u32CryptoSize = u32CiphertextSize; + /* Decrypt blocks */ + stcCrypto.pu8In = pu8Ciphertext; + stcCrypto.pu8Out = pu8Plaintext; + i32Ret = SKE_CryptoBlocks(&stcCrypto); + } + + return i32Ret; +} +#endif + static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx, struct hwcrypto_symmetric_info *info) { rt_err_t result = RT_EOK; struct hc32_hwcrypto_device *hc32_hw_dev = (struct hc32_hwcrypto_device *)ctx->parent.device->user_data; rt_mutex_take(&hc32_hw_dev->mutex, RT_WAITING_FOREVER); +#if defined (HC32F4A8) + SKE_StructInit(&stcSkeInit); switch (ctx->parent.type) { case HWCRYPTO_TYPE_AES_ECB: LOG_D("AES type is ECB."); + stcSkeInit.u32Mode = SKE_MD_ECB; break; case HWCRYPTO_TYPE_AES_CBC: + stcSkeInit.u32Mode = SKE_MD_CBC; + break; case HWCRYPTO_TYPE_AES_CTR: - case HWCRYPTO_TYPE_DES_ECB: - case HWCRYPTO_TYPE_DES_CBC: + stcSkeInit.u32Mode = SKE_MD_CTR; + break; + case HWCRYPTO_TYPE_AES_CFB: + stcSkeInit.u32Mode = SKE_MD_CFB; + break; + case HWCRYPTO_TYPE_AES_OFB: + stcSkeInit.u32Mode = SKE_MD_OFB; + break; default : LOG_E("not support cryp type: %x", ctx->parent.type); break; } + stcSkeInit.pu8Iv = ctx->iv; +#endif #if defined (HC32F460) if (ctx->key_bitlen != (AES_KEY_SIZE_16BYTE * 8U)) @@ -252,7 +359,7 @@ static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx, struct hwcrypto_symm result = -RT_ERROR; goto _exit; } -#elif defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) +#elif defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) if (ctx->key_bitlen != (AES_KEY_SIZE_16BYTE * 8U) && ctx->key_bitlen != (AES_KEY_SIZE_24BYTE * 8U) && \ ctx->key_bitlen != (AES_KEY_SIZE_32BYTE * 8U)) { @@ -365,9 +472,13 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx) case HWCRYPTO_TYPE_RC4: case HWCRYPTO_TYPE_GCM: { +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) /* Enable AES peripheral clock. */ FCG_Fcg0PeriphClockCmd(PWC_FCG0_AES, ENABLE); - +#elif defined(HC32F4A8) + /* Enable SKE peripheral clock */ + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_SKE, ENABLE); +#endif ((struct hwcrypto_symmetric *)ctx)->ops = &cryp_ops; break; @@ -416,8 +527,13 @@ static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx) case HWCRYPTO_TYPE_3DES: case HWCRYPTO_TYPE_RC4: case HWCRYPTO_TYPE_GCM: +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) AES_DeInit(); FCG_Fcg0PeriphClockCmd(PWC_FCG0_AES, DISABLE); +#elif defined(HC32F4A8) + SKE_DeInit(); + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_SKE, DISABLE); +#endif break; #endif /* BSP_USING_AES */ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_dac.c b/bsp/hc32/libraries/hc32_drivers/drv_dac.c index afc1b4bd9c9..e2ef22abf49 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_dac.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_dac.c @@ -37,7 +37,7 @@ static dac_device _g_dac_dev_array[] = #ifdef BSP_USING_DAC1 { {0}, -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) CM_DAC1, #elif defined (HC32F448) CM_DAC, @@ -148,7 +148,7 @@ static const struct rt_dac_ops g_dac_ops = static void _dac_clock_enable(void) { #if defined(BSP_USING_DAC1) -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_DAC1, ENABLE); #elif defined (HC32F448) FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_DAC, ENABLE); @@ -179,16 +179,24 @@ int rt_hw_dac_init(void) for (; i < dev_cnt; i++) { DAC_DeInit(_g_dac_dev_array[i].instance); - stcDacInit.enOutput = _g_dac_dev_array[i].init.ch1_output_enable; + stcDacInit.enOutput = (en_functional_state_t)_g_dac_dev_array[i].init.ch1_output_enable; #if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) stcDacInit.u16Src = _g_dac_dev_array[i].init.ch1_data_src; #endif ll_ret = DAC_Init((void *)_g_dac_dev_array[i].instance, DAC_CH1, &stcDacInit); +#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F460) #if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) stcDacInit.u16Src = _g_dac_dev_array[i].init.ch2_data_src; #endif stcDacInit.enOutput = _g_dac_dev_array[i].init.ch2_output_enable; ll_ret = DAC_Init((void *)_g_dac_dev_array[i].instance, DAC_CH2, &stcDacInit); +#elif defined (HC32F334) + if (CM_DAC1 == (void *)_g_dac_dev_array[i].instance) + { + stcDacInit.enOutput = (en_functional_state_t)_g_dac_dev_array[i].init.ch2_output_enable; + ll_ret = DAC_Init((void *)_g_dac_dev_array[i].instance, DAC_CH2, &stcDacInit); + } +#endif DAC_DataRegAlignConfig(_g_dac_dev_array[i].instance, _g_dac_dev_array[i].init.data_align); if (ll_ret != LL_OK) @@ -198,15 +206,21 @@ int rt_hw_dac_init(void) } DAC_ADCPrioConfig(_g_dac_dev_array[i].instance, _g_dac_dev_array[i].init.dac_adp_sel, ENABLE); - DAC_ADCPrioCmd(_g_dac_dev_array[i].instance, _g_dac_dev_array[i].init.dac_adp_enable); + DAC_ADCPrioCmd(_g_dac_dev_array[i].instance, (en_functional_state_t)_g_dac_dev_array[i].init.dac_adp_enable); #if defined (HC32F472) DAC_SetAmpGain(_g_dac_dev_array[i].instance, DAC_CH1, _g_dac_dev_array[i].init.ch1_amp_gain); DAC_SetAmpGain(_g_dac_dev_array[i].instance, DAC_CH2, _g_dac_dev_array[i].init.ch2_amp_gain); #endif - DAC_AMPCmd(_g_dac_dev_array[i].instance, DAC_CH1, _g_dac_dev_array[i].init.ch1_amp_enable); + DAC_AMPCmd(_g_dac_dev_array[i].instance, DAC_CH1, (en_functional_state_t)_g_dac_dev_array[i].init.ch1_amp_enable); +#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F460) DAC_AMPCmd(_g_dac_dev_array[i].instance, DAC_CH2, _g_dac_dev_array[i].init.ch2_amp_enable); - +#elif defined (HC32F334) + if (CM_DAC1 == (void *)_g_dac_dev_array[i].instance) + { + DAC_AMPCmd(_g_dac_dev_array[i].instance, DAC_CH2, (en_functional_state_t)_g_dac_dev_array[i].init.ch2_amp_enable); + } +#endif rt_hw_board_dac_init(_g_dac_dev_array[i].instance); ret = rt_hw_dac_register(&_g_dac_dev_array[i].rt_dac, \ (const char *)_g_dac_dev_array[i].init.name, \ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_gpio.c b/bsp/hc32/libraries/hc32_drivers/drv_gpio.c index b2513c6e31f..a7217ec9e15 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_gpio.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_gpio.c @@ -573,6 +573,10 @@ static rt_base_t hc32_pin_get(const char *name) hw_pin_num *= 10; hw_pin_num += name[i] - '0'; } + if (hw_pin_num > 0xF) + { + return -RT_EINVAL; + } pin = PIN_NUM(hw_port_num, hw_pin_num); return pin; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_hwtimer.c b/bsp/hc32/libraries/hc32_drivers/drv_hwtimer.c index 0f4c862032d..2cac51d01f1 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_hwtimer.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_hwtimer.c @@ -150,7 +150,7 @@ static void _timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) TMRA_IntCmd(tmr_device->tmr_handle, TMRA_INT_OVF, ENABLE); #if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) hc32_install_irq_handler(&irq_config, tmr_device->isr.irq_callback, RT_TRUE); -#elif defined (HC32F448) || defined (HC32F472) +#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) hc32_install_irq_handler(&irq_config, NULL, RT_TRUE); #endif } @@ -159,7 +159,7 @@ static void _timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) TMRA_DeInit(tmr_device->tmr_handle); #if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) hc32_install_irq_handler(&irq_config, tmr_device->isr.irq_callback, RT_FALSE); -#elif defined (HC32F448) || defined (HC32F472) +#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) hc32_install_irq_handler(&irq_config, NULL, RT_FALSE); #endif FCG_Fcg2PeriphClockCmd(tmr_device->clock, DISABLE); @@ -251,7 +251,7 @@ static void TMRA_1_callback(void) rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_1_INDEX].time_device); } -#if defined (HC32F448) || defined (HC32F472) +#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) void TMRA_1_Ovf_Udf_Handler(void) { TMRA_1_callback(); @@ -266,7 +266,7 @@ static void TMRA_2_callback(void) rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_2_INDEX].time_device); } -#if defined (HC32F448) || defined (HC32F472) +#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) void TMRA_2_Ovf_Udf_Handler(void) { TMRA_2_callback(); @@ -281,7 +281,7 @@ static void TMRA_3_callback(void) rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_3_INDEX].time_device); } -#if defined (HC32F448) || defined (HC32F472) +#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) void TMRA_3_Ovf_Udf_Handler(void) { TMRA_3_callback(); @@ -296,7 +296,7 @@ static void TMRA_4_callback(void) rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_4_INDEX].time_device); } -#if defined (HC32F448) || defined (HC32F472) +#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) void TMRA_4_Ovf_Udf_Handler(void) { TMRA_4_callback(); @@ -311,7 +311,7 @@ static void TMRA_5_callback(void) rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_5_INDEX].time_device); } -#if defined (HC32F448) || defined (HC32F472) +#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) void TMRA_5_Ovf_Udf_Handler(void) { TMRA_5_callback(); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_irq.c b/bsp/hc32/libraries/hc32_drivers/drv_irq.c index 32eb5fa7b91..501717d5d37 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_irq.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_irq.c @@ -67,13 +67,13 @@ rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config, stcIrqSignConfig.enIntSrc = irq_config->int_src; stcIrqSignConfig.pfnCallback = irq_hdr; if (LL_OK == INTC_IrqSignIn(&stcIrqSignConfig)) -nvic_config: #elif defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) stcIrqSignConfig.enIRQn = irq_config->irq_num; stcIrqSignConfig.enIntSrc = irq_config->int_src; stcIrqSignConfig.pfnCallback = irq_hdr; if (LL_OK == INTC_IrqSignIn(&stcIrqSignConfig)) #endif +nvic_config: { NVIC_ClearPendingIRQ(irq_config->irq_num); NVIC_SetPriority(irq_config->irq_num, irq_config->irq_prio); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_mcan.c b/bsp/hc32/libraries/hc32_drivers/drv_mcan.c index 6e88fde32ab..5dc0217c1f9 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_mcan.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_mcan.c @@ -26,11 +26,8 @@ typedef struct hc32_mcan_config_struct uint32_t int0_sel; struct hc32_irq_config int0_cfg; /* MCAN interrupt line 0 configuration */ - uint32_t int1_sel; - struct hc32_irq_config int1_cfg; /* MCAN interrupt line 1 configuration */ #if defined(HC32F4A8) func_ptr_t irq_callback0; - func_ptr_t irq_callback1; #endif } hc32_mcan_config_t; @@ -85,13 +82,12 @@ typedef struct mcan_baud_rate_struct #define MCAN_TX_INT (MCAN_INT_TX_CPLT) #define MCAN_ERR_INT (MCAN_INT_ARB_PHASE_ERROR | MCAN_INT_DATA_PHASE_ERROR | MCAN_INT_ERR_LOG_OVF | \ MCAN_INT_ERR_PASSIVE | MCAN_INT_ERR_WARNING | MCAN_INT_BUS_OFF) -#define MCAN_INT0_SEL (MCAN_RX_INT) -#define MCAN_INT1_SEL (MCAN_TX_INT | MCAN_ERR_INT) +#define MCAN_INT0_SEL (MCAN_RX_INT | MCAN_TX_INT | MCAN_ERR_INT) /**************************************************************************************** * Baud rate(bit timing) configuration based on 80MHz clock ****************************************************************************************/ -#ifdef RT_CAN_USING_CANFD +#if defined(RT_CAN_USING_CANFD) static const mcan_baud_rate_t m_mcan_fd_baud_rate[] = { {CAN500kBaud, CANFD_DATA_BAUD_1M, MCAN_FD_CFG_500K_1M}, @@ -127,9 +123,9 @@ static const uint8_t m_mcan_data_size[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20 static const rt_uint32_t m_mcan_tx_priv_mode[] = {MCAN_TX_FIFO_MD, MCAN_TX_QUEUE_MD}; -static const rt_uint32_t m_mcan_work_mode[] = {MCAN_MD_NORMAL, MCAN_MD_BUS_MON, MCAN_MD_EXTERN_LOOPBACK, MCAN_MD_RESTRICTED_OP}; +static const rt_uint32_t m_mcan_work_mode[] = {MCAN_MD_NORMAL, MCAN_MD_BUS_MON, MCAN_MD_EXTERN_LOOPBACK, MCAN_MD_INTERN_LOOPBACK}; -#ifdef RT_CAN_USING_CANFD +#if defined(RT_CAN_USING_CANFD) static const rt_uint32_t m_mcan_fd_mode[] = {MCAN_FRAME_CLASSIC, MCAN_FRAME_ISO_FD_NO_BRS, MCAN_FRAME_ISO_FD_BRS, \ MCAN_FRAME_NON_ISO_FD_NO_BRS, MCAN_FRAME_NON_ISO_FD_BRS }; @@ -140,10 +136,10 @@ static const rt_uint32_t m_mcan_fd_mode[] = {MCAN_FRAME_CLASSIC, MCAN_FRAME_ISO_ ****************************************************************************************/ enum { -#ifdef BSP_USING_MCAN1 +#if defined(BSP_USING_MCAN1) MCAN1_INDEX, #endif -#ifdef BSP_USING_MCAN2 +#if defined(BSP_USING_MCAN2) MCAN2_INDEX, #endif MCAN_DEV_CNT, @@ -151,7 +147,7 @@ enum static hc32_mcan_driver_t m_mcan_driver_list[] = { -#ifdef BSP_USING_MCAN1 +#if defined(BSP_USING_MCAN1) { { .name = MCAN1_NAME, @@ -159,12 +155,10 @@ static hc32_mcan_driver_t m_mcan_driver_list[] = .init_para = {.stcBitTime = MCAN1_BAUD_RATE_CFG}, .int0_sel = MCAN_INT0_SEL, .int0_cfg = {BSP_MCAN1_INT0_IRQ_NUM, BSP_MCAN1_INT0_IRQ_PRIO, INT_SRC_MCAN1_INT0}, - .int1_sel = MCAN_INT1_SEL, - .int1_cfg = {BSP_MCAN1_INT1_IRQ_NUM, BSP_MCAN1_INT0_IRQ_PRIO, INT_SRC_MCAN1_INT1}, } }, #endif -#ifdef BSP_USING_MCAN2 +#if defined(BSP_USING_MCAN2) { { .name = MCAN2_NAME, @@ -172,19 +166,17 @@ static hc32_mcan_driver_t m_mcan_driver_list[] = .init_para = {.stcBitTime = MCAN2_BAUD_RATE_CFG}, .int0_sel = MCAN_INT0_SEL, .int0_cfg = {BSP_MCAN2_INT0_IRQ_NUM, BSP_MCAN2_INT0_IRQ_PRIO, INT_SRC_MCAN2_INT0}, - .int1_sel = MCAN_INT1_SEL, - .int1_cfg = {BSP_MCAN2_INT1_IRQ_NUM, BSP_MCAN2_INT1_IRQ_PRIO, INT_SRC_MCAN2_INT1}, } }, #endif }; -#ifdef BSP_USING_MCAN1 +#if defined(BSP_USING_MCAN1) static stc_mcan_filter_t m_mcan1_std_filters[MCAN1_STD_FILTER_NUM]; static stc_mcan_filter_t m_mcan1_ext_filters[MCAN1_EXT_FILTER_NUM]; #endif -#ifdef BSP_USING_MCAN2 +#if defined(BSP_USING_MCAN2) static stc_mcan_filter_t m_mcan2_std_filters[MCAN2_STD_FILTER_NUM]; static stc_mcan_filter_t m_mcan2_ext_filters[MCAN2_EXT_FILTER_NUM]; #endif @@ -234,7 +226,7 @@ static rt_ssize_t mcan_sendmsg(struct rt_can_device *device, const void *buf, rt */ static rt_ssize_t mcan_recvmsg(struct rt_can_device *device, void *buf, rt_uint32_t boxno); -#ifdef RT_CAN_USING_CANFD +#if defined(RT_CAN_USING_CANFD) static void mcan_copy_bt_to_cfg(struct can_configure *cfg, const stc_mcan_bit_time_config_t *ll_bt); #endif @@ -269,7 +261,7 @@ static rt_err_t mcan_configure(struct rt_can_device *device, struct can_configur hard->init_para.u32Mode = m_mcan_work_mode[cfg->mode]; hard->init_para.u32FrameFormat = MCAN_FRAME_CLASSIC; hard->init_para.stcMsgRam.u32TxFifoQueueMode = m_mcan_tx_priv_mode[cfg->privmode]; -#ifdef RT_CAN_USING_CANFD +#if defined(RT_CAN_USING_CANFD) RT_ASSERT(IS_MCAN_FD_MODE(cfg->enable_canfd)); hard->init_para.u32FrameFormat = m_mcan_fd_mode[cfg->enable_canfd]; if (cfg->use_bit_timing) @@ -365,7 +357,7 @@ static rt_err_t mcan_configure(struct rt_can_device *device, struct can_configur driver->can_device.config.msgboxsz = pre_config.msgboxsz; driver->can_device.config.ticks = pre_config.ticks; } -#ifdef RT_CAN_USING_HDR +#if defined(RT_CAN_USING_HDR) driver->can_device.config.maxhdr = pre_config.maxhdr; #endif driver->can_device.config.sndboxnumber = pre_config.sndboxnumber; @@ -396,10 +388,6 @@ static void mcan_control_set_int(hc32_mcan_driver_t *driver, int cmd, void *arg) { MCAN_IntCmd(hard->instance, MCAN_RX_INT & hard->int0_sel, MCAN_INT_LINE0, new_state); } - if (MCAN_RX_INT & hard->int1_sel) - { - MCAN_IntCmd(hard->instance, MCAN_RX_INT & hard->int1_sel, MCAN_INT_LINE1, new_state); - } break; case RT_DEVICE_FLAG_INT_TX: tmp = hard->init_para.stcMsgRam.u32TxBufferNum + hard->init_para.stcMsgRam.u32TxFifoQueueNum; @@ -417,20 +405,12 @@ static void mcan_control_set_int(hc32_mcan_driver_t *driver, int cmd, void *arg) { MCAN_IntCmd(hard->instance, MCAN_TX_INT & hard->int0_sel, MCAN_INT_LINE0, new_state); } - if (MCAN_TX_INT & hard->int1_sel) - { - MCAN_IntCmd(hard->instance, MCAN_TX_INT & hard->int1_sel, MCAN_INT_LINE1, new_state); - } break; case RT_DEVICE_CAN_INT_ERR: if (MCAN_ERR_INT & hard->int0_sel) { MCAN_IntCmd(hard->instance, MCAN_ERR_INT & hard->int0_sel, MCAN_INT_LINE0, new_state); } - if (MCAN_ERR_INT & hard->int1_sel) - { - MCAN_IntCmd(hard->instance, MCAN_ERR_INT & hard->int1_sel, MCAN_INT_LINE1, new_state); - } break; default: break; @@ -536,7 +516,7 @@ static rt_err_t mcan_control_set_priv(hc32_mcan_driver_t *driver, int cmd, void return RT_EOK; } -#ifdef RT_CAN_USING_CANFD +#if defined(RT_CAN_USING_CANFD) static void mcan_copy_bt_to_cfg(struct can_configure *cfg, const stc_mcan_bit_time_config_t *ll_bt) { cfg->can_timing.prescaler = ll_bt->u32NominalPrescaler; @@ -556,12 +536,12 @@ static rt_err_t mcan_control_set_fd(hc32_mcan_driver_t *driver, int cmd, void *a { rt_uint32_t i, len; rt_uint32_t argval = (rt_uint32_t)arg; -#ifdef RT_CAN_USING_CANFD +#if defined(RT_CAN_USING_CANFD) struct rt_can_bit_timing_config *timing_configs = NULL; #endif switch (cmd) { -#ifdef RT_CAN_USING_CANFD +#if defined(RT_CAN_USING_CANFD) case RT_CAN_CMD_SET_BAUD: default: RT_ASSERT(IS_MCAN_NOMINAL_BAUD_RATE(argval)); @@ -713,7 +693,7 @@ static rt_err_t mcan_control(struct rt_can_device *device, int cmd, void *arg) break; case RT_CAN_CMD_SET_BAUD: -#ifdef RT_CAN_USING_CANFD +#if defined(RT_CAN_USING_CANFD) case RT_CAN_CMD_SET_CANFD: case RT_CAN_CMD_SET_BAUD_FD: case RT_CAN_CMD_SET_BITTIMING: @@ -759,7 +739,7 @@ static rt_ssize_t mcan_sendmsg(struct rt_can_device *device, const void *buf, rt /* Parameter validity check */ RT_ASSERT(IS_CAN_VALID_ID(tx_msg->ide, tx_msg->id)); -#ifdef RT_CAN_USING_CANFD +#if defined(RT_CAN_USING_CANFD) RT_ASSERT(tx_msg->len <= MCAN_DLC64); #else RT_ASSERT(tx_msg->len <= MCAN_DLC8); @@ -770,7 +750,7 @@ static rt_ssize_t mcan_sendmsg(struct rt_can_device *device, const void *buf, rt ll_tx_msg.IDE = tx_msg->ide; ll_tx_msg.RTR = tx_msg->rtr; ll_tx_msg.DLC = tx_msg->len; -#ifdef RT_CAN_USING_CANFD +#if defined(RT_CAN_USING_CANFD) ll_tx_msg.FDF = tx_msg->fd_frame; ll_tx_msg.BRS = tx_msg->brs; #endif @@ -824,22 +804,22 @@ static rt_ssize_t mcan_recvmsg(struct rt_can_device *device, void *buf, rt_uint3 rx_msg->id = ll_rx_msg.ID; rx_msg->ide = ll_rx_msg.IDE; rx_msg->rtr = ll_rx_msg.RTR; - rx_msg->len = ll_rx_msg.u32DataSize; + rx_msg->len = ll_rx_msg.DLC; rx_msg->priv = 0; -#ifdef RT_CAN_USING_HDR +#if defined(RT_CAN_USING_HDR) /* Hardware filter messages are valid */ rx_msg->hdr_index = ll_rx_msg.u32FilterIndex; device->hdr[rx_msg->hdr_index].connected = 1; #endif -#ifdef RT_CAN_USING_CANFD +#if defined(RT_CAN_USING_CANFD) rx_msg->fd_frame = ll_rx_msg.FDF; rx_msg->brs = ll_rx_msg.BRS; #endif if (rx_msg->len > 0) { - rt_memcpy(&rx_msg->data[0], &ll_rx_msg.au8Data[0], rx_msg->len); + rt_memcpy(&rx_msg->data[0], &ll_rx_msg.au8Data[0], m_mcan_data_size[ll_rx_msg.DLC]); } return RT_EOK; @@ -869,7 +849,11 @@ rt_inline void mcan_isr(hc32_mcan_driver_t *driver, uint32_t int_sel) uint32_t ndat2 = MCANx->NDAT2; int rx_buf_index; - MCAN_ClearStatus(MCANx, ir_status & int_sel); + int_sel &= ~(MCAN_FLAG_RX_FIFO0_NEW_MSG | MCAN_FLAG_RX_FIFO1_NEW_MSG | MCAN_FLAG_RX_BUF_NEW_MSG); + if (0U != (ir_status & int_sel)) + { + MCAN_ClearStatus(MCANx, ir_status & int_sel); + } /* Check normal status flag */ /* Transmission completed */ @@ -967,7 +951,7 @@ rt_inline void mcan_isr(hc32_mcan_driver_t *driver, uint32_t int_sel) /**************************************************************************************** * mcan irq handler ****************************************************************************************/ -#if defined(HC32F448) || defined(HC32F4A8) +#if defined(HC32F448) || defined(HC32F4A8) || defined(HC32F334) #if defined(BSP_USING_MCAN1) void MCAN1_INT0_Handler(void) { @@ -979,18 +963,7 @@ void MCAN1_INT0_Handler(void) /* leave interrupt */ rt_interrupt_leave(); } - -void MCAN1_INT1_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - mcan_isr(&m_mcan_driver_list[MCAN1_INDEX], m_mcan_driver_list[MCAN1_INDEX].mcan.int1_sel); - - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* #if defined(BSP_USING_MCAN1) */ +#endif /* BSP_USING_MCAN1 */ #if defined(BSP_USING_MCAN2) void MCAN2_INT0_Handler(void) @@ -1003,18 +976,7 @@ void MCAN2_INT0_Handler(void) /* leave interrupt */ rt_interrupt_leave(); } - -void MCAN2_INT1_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - mcan_isr(&m_mcan_driver_list[MCAN2_INDEX], m_mcan_driver_list[MCAN2_INDEX].mcan.int1_sel); - - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* #if defined(BSP_USING_MCAN2) */ +#endif /* BSP_USING_MCAN2 */ #endif /**************************************************************************************** @@ -1022,33 +984,16 @@ void MCAN2_INT1_Handler(void) ****************************************************************************************/ static void mcan_irq_config(hc32_mcan_config_t *hard) { -#if defined(HC32F448) +#if defined(HC32F448) || defined(HC32F334) if (hard->int0_sel != 0) { - INTC_IntSrcCmd(hard->int0_cfg.int_src, ENABLE); - - NVIC_ClearPendingIRQ(hard->int0_cfg.irq_num); - NVIC_SetPriority(hard->int0_cfg.irq_num, hard->int0_cfg.irq_prio); - NVIC_EnableIRQ(hard->int0_cfg.irq_num); - } - - if (hard->int1_sel != 0) - { - INTC_IntSrcCmd(hard->int1_cfg.int_src, ENABLE); - - NVIC_ClearPendingIRQ(hard->int1_cfg.irq_num); - NVIC_SetPriority(hard->int1_cfg.irq_num, hard->int1_cfg.irq_prio); - NVIC_EnableIRQ(hard->int1_cfg.irq_num); + hc32_install_irq_handler(&hard->int0_cfg, RT_NULL, RT_TRUE); } #elif defined(HC32F4A8) if (hard->int0_sel != 0) { hc32_install_irq_handler(&hard->int0_cfg, hard->irq_callback0, RT_TRUE); } - if (hard->int1_sel != 0) - { - hc32_install_irq_handler(&hard->int1_cfg, hard->irq_callback1, RT_TRUE); - } #endif } @@ -1061,9 +1006,7 @@ static void mcan_enable_periph_clock(void) #if defined(BSP_USING_MCAN2) FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_MCAN2, ENABLE); #endif -#endif - -#if defined(HC32F334) +#elif defined(HC32F334) #if defined(BSP_USING_MCAN1) || defined(BSP_USING_MCAN2) FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_MCAN1 | FCG1_PERIPH_MCAN2, ENABLE); #endif @@ -1166,10 +1109,10 @@ static void init_can_cfg(hc32_mcan_driver_t *driver) can_cfg.privmode = RT_CAN_MODE_NOPRIV; can_cfg.ticks = 50; -#ifdef RT_CAN_USING_HDR +#if defined(RT_CAN_USING_HDR) can_cfg.maxhdr = MCAN_TOTAL_FILTER_NUM; #endif -#ifdef RT_CAN_USING_CANFD +#if defined(RT_CAN_USING_CANFD) can_cfg.baud_rate_fd = CANFD_DATA_BAUD_4M; can_cfg.enable_canfd = MCAN_FD_SEL; #endif @@ -1185,20 +1128,18 @@ static void init_can_cfg(hc32_mcan_driver_t *driver) */ static void mcan_get_irq_callback(void) { -#ifdef BSP_USING_MCAN1 +#if defined(BSP_USING_MCAN1) m_mcan_driver_list[MCAN1_INDEX].mcan.irq_callback0 = MCAN1_INT0_Handler; - m_mcan_driver_list[MCAN1_INDEX].mcan.irq_callback1 = MCAN1_INT1_Handler; #endif -#ifdef BSP_USING_MCAN2 +#if defined(BSP_USING_MCAN2) m_mcan_driver_list[MCAN2_INDEX].mcan.irq_callback0 = MCAN2_INT0_Handler; - m_mcan_driver_list[MCAN2_INDEX].mcan.irq_callback1 = MCAN2_INT1_Handler; #endif } #endif extern rt_err_t rt_hw_board_mcan_init(CM_MCAN_TypeDef *MCANx); extern void CanPhyEnable(void); -static rt_err_t rt_hw_mcan_init(void) +static int rt_hw_mcan_init(void) { rt_uint32_t i, filter; rt_uint32_t tx_boxnum; @@ -1239,7 +1180,6 @@ static rt_err_t rt_hw_mcan_init(void) MCAN_TxBufferNotificationCmd(hard->instance, tx_boxnum, MCAN_INT_TX_CPLT, ENABLE); MCAN_IntCmd(hard->instance, hard->int0_sel, MCAN_INT_LINE0, ENABLE); - MCAN_IntCmd(hard->instance, hard->int1_sel, MCAN_INT_LINE1, ENABLE); if (i > 0) { diff --git a/bsp/hc32/libraries/hc32_drivers/drv_pm.c b/bsp/hc32/libraries/hc32_drivers/drv_pm.c index 7d5a3308ac4..cc84e14200a 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_pm.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_pm.c @@ -58,46 +58,10 @@ static void _uart_console_reconfig(void) rt_device_control(rt_console_get_device(), RT_DEVICE_CTRL_CONFIG, &config); } -/** - * @brief Enter sleep mode. - * @param [in] u8SleepType specifies the type of enter sleep's command. - * @arg PWC_SLEEP_WFI Enter sleep mode by WFI, and wake-up by interrupt handle. - * @arg PWC_SLEEP_WFE_INT Enter sleep mode by WFE, and wake-up by interrupt request(SEVONPEND=1) - * @arg PWC_SLEEP_WFE_EVT Enter sleep mode by WFE, and wake-up by event(SEVONPEND=0). - - * @retval None - */ -__WEAKDEF void pwc_sleep_enter(uint8_t u8SleepType) -{ - DDL_ASSERT(IS_PWC_UNLOCKED()); - - CLR_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_STOP); - CLR_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_PWDN); - - if (PWC_SLEEP_WFI == u8SleepType) - { - __WFI(); - } - else - { - if (PWC_SLEEP_WFE_INT == u8SleepType) - { - SET_REG32_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); - } - else - { - CLR_REG32_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); - } - __SEV(); - __WFE(); - __WFE(); - } -} - static void _sleep_enter_idle(void) { struct pm_sleep_mode_idle_config sleep_idle_cfg = PM_SLEEP_IDLE_CFG; - pwc_sleep_enter(sleep_idle_cfg.pwc_sleep_type); + PWC_SLEEP_Enter(sleep_idle_cfg.pwc_sleep_type); } static void _sleep_enter_deep(void) diff --git a/bsp/hc32/libraries/hc32_drivers/drv_pm.h b/bsp/hc32/libraries/hc32_drivers/drv_pm.h index 6ef620b1a83..cba3d8f0669 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_pm.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_pm.h @@ -91,13 +91,17 @@ struct pm_sleep_mode_shutdown_config ******************************************************************************/ #if defined(HC32F4A0) || defined(HC32F4A8) #define PM_CHECK_EFM() ((EFM_GetStatus(EFM_FLAG_RDY) == SET) && (EFM_GetStatus(EFM_FLAG_RDY1) == SET)) -#elif defined(HC32F460) || defined (HC32F448) || defined (HC32F472) +#elif defined(HC32F460) || defined (HC32F448) || defined (HC32F472) || defined (HC32F334) #define PM_CHECK_EFM() ((EFM_GetStatus(EFM_FLAG_RDY) == SET)) #endif #define PM_CHECK_XTAL() ((CM_CMU->XTALSTDCR & CLK_XTALSTD_ON) == 0) +#if defined(HC32F334) +#define PM_CHECK_DMA() (DMA_GetTransStatus(CM_DMA, DMA_STAT_TRANS_DMA) == RESET) +#elif defined(HC32F4A0) || defined(HC32F4A8) || defined(HC32F460) || defined (HC32F448) || defined (HC32F472) #define PM_CHECK_DMA() \ ( (DMA_GetTransStatus(CM_DMA1, DMA_STAT_TRANS_DMA) == RESET) && \ (DMA_GetTransStatus(CM_DMA2, DMA_STAT_TRANS_DMA) == RESET)) +#endif #define PM_CHECK_SWDT() \ ( ((CM_ICG->ICG0 & ICG_SWDT_RST_START) != ICG_SWDT_RST_START) || \ ((CM_ICG->ICG0 & ICG_SWDT_LPM_CNT_STOP) == ICG_SWDT_LPM_CNT_STOP)) @@ -124,24 +128,6 @@ struct pm_sleep_mode_shutdown_config ( (mode == PM_SLEEP_MODE_SHUTDOWN && PM_SLEEP_SHUTDOWN_CHECK()) || \ (mode == PM_SLEEP_MODE_DEEP && PM_SLEEP_DEEP_CHECK())|| \ (mode <= PM_SLEEP_MODE_IDLE))) - -/** - * @defgroup PWC_Sleep_Type PWC sleep mode type. - * @{ - */ -#ifndef PWC_SLEEP_WFI -#define PWC_SLEEP_WFI (0x00U) /*!< Enter sleep mode by WFI, and wake-up by interrupt handle. */ -#endif -#ifndef PWC_SLEEP_WFE_INT -#define PWC_SLEEP_WFE_INT (0x01U) /*!< Enter sleep mode by WFE, and wake-up by interrupt request(SEVONPEND=1). */ -#endif -#ifndef PWC_SLEEP_WFE_EVT -#define PWC_SLEEP_WFE_EVT (0x02U) /*!< Enter sleep mode by WFE, and wake-up by event(SEVONPEND=0). */ -#endif -/** - * @} - */ - /******************************************************************************* * Global function prototypes (definition in C source) ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_pulse_encoder.c b/bsp/hc32/libraries/hc32_drivers/drv_pulse_encoder.c index c005e9aad68..fc825d52648 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_pulse_encoder.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_pulse_encoder.c @@ -146,7 +146,7 @@ static void TMRA_1_Udf_callback(void) TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_1_INDEX].tmr_handler, TMRA_FLAG_UDF); hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_1_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F448) || defined (HC32F472) +#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) void TMRA_1_Ovf_Udf_Handler(void) { CM_TMRA_TypeDef *tmr_handler = hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_1_INDEX].tmr_handler; @@ -173,7 +173,7 @@ static void TMRA_2_Udf_callback(void) TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_2_INDEX].tmr_handler, TMRA_FLAG_UDF); hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_2_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F448) || defined (HC32F472) +#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) void TMRA_2_Ovf_Udf_Handler(void) { CM_TMRA_TypeDef *tmr_handler = hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_2_INDEX].tmr_handler; @@ -200,7 +200,7 @@ static void TMRA_3_Udf_callback(void) TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_3_INDEX].tmr_handler, TMRA_FLAG_UDF); hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_3_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F448) || defined (HC32F472) +#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) void TMRA_3_Ovf_Udf_Handler(void) { CM_TMRA_TypeDef *tmr_handler = hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_3_INDEX].tmr_handler; @@ -227,7 +227,7 @@ static void TMRA_4_Udf_callback(void) TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_4_INDEX].tmr_handler, TMRA_FLAG_UDF); hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_4_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F448) || defined (HC32F472) +#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) void TMRA_4_Ovf_Udf_Handler(void) { CM_TMRA_TypeDef *tmr_handler = hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_4_INDEX].tmr_handler; @@ -254,7 +254,7 @@ static void TMRA_5_Udf_callback(void) TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_5_INDEX].tmr_handler, TMRA_FLAG_UDF); hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_5_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F448) || defined (HC32F472) +#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) void TMRA_5_Ovf_Udf_Handler(void) { CM_TMRA_TypeDef *tmr_handler = hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_5_INDEX].tmr_handler; @@ -647,7 +647,7 @@ void TMR6_1_Udf_callback(void) TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_1_INDEX].tmr_handler, TMR6_FLAG_UDF); hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_1_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F448) || defined (HC32F472) +#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) void TMR6_1_Ovf_Udf_Handler(void) { CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_1_INDEX].tmr_handler; @@ -674,7 +674,7 @@ void TMR6_2_Udf_callback(void) TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_2_INDEX].tmr_handler, TMR6_FLAG_UDF); hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_2_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F448) || defined (HC32F472) +#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) void TMR6_2_Ovf_Udf_Handler(void) { CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_2_INDEX].tmr_handler; @@ -701,7 +701,7 @@ void TMR6_3_Udf_callback(void) TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_3_INDEX].tmr_handler, TMR6_FLAG_UDF); hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_3_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F472) +#if defined (HC32F472) || defined (HC32F334) void TMR6_3_Ovf_Udf_Handler(void) { CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_3_INDEX].tmr_handler; @@ -728,7 +728,7 @@ void TMR6_4_Udf_callback(void) TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_4_INDEX].tmr_handler, TMR6_FLAG_UDF); hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_4_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F472) +#if defined (HC32F472) || defined (HC32F334) void TMR6_4_Ovf_Udf_Handler(void) { CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_4_INDEX].tmr_handler; @@ -755,7 +755,7 @@ void TMR6_5_Udf_callback(void) TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_5_INDEX].tmr_handler, TMR6_FLAG_UDF); hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_5_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F472) +#if defined (HC32F472) || defined (HC32F334) void TMR6_5_Ovf_Udf_Handler(void) { CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_5_INDEX].tmr_handler; @@ -782,7 +782,7 @@ void TMR6_6_Udf_callback(void) TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_6_INDEX].tmr_handler, TMR6_FLAG_UDF); hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_6_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F472) +#if defined (HC32F472) || defined (HC32F334) void TMR6_6_Ovf_Udf_Handler(void) { CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_6_INDEX].tmr_handler; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_pwm.c b/bsp/hc32/libraries/hc32_drivers/drv_pwm.c index 3573609540b..bfad2524123 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_pwm.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_pwm.c @@ -27,7 +27,7 @@ #if defined(HC32F460) || defined(HC32F448) #define TMRA_CHANNEL_NUM_MAX 8U -#elif defined(HC32F4A0) || defined(HC32F472) || defined(HC32F4A8) +#elif defined(HC32F4A0) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) #define TMRA_CHANNEL_NUM_MAX 4U #endif @@ -129,7 +129,7 @@ static rt_uint32_t tmra_get_clk_notdiv(CM_TMRA_TypeDef *TMRAx) rt_uint32_t u32clkFreq; rt_uint32_t u32BusName; -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) switch ((rt_uint32_t)TMRAx) { case (rt_uint32_t)CM_TMRA_1: @@ -682,8 +682,11 @@ static struct rt_pwm_ops _tmra_ops = #endif /* BSP_USING_PWM_TMRA */ #if defined(BSP_USING_PWM_TMR4) - -#define TMR4_CHANNEL_NUM_MAX 6U +#if defined (HC32F4A8) || defined (HC32F472) || defined (HC32F4A0) || defined (HC32F460) + #define TMR4_CHANNEL_NUM_MAX 6U +#elif defined (HC32F448) || defined (HC32F334) + #define TMR4_CHANNEL_NUM_MAX 8U +#endif enum { @@ -728,7 +731,7 @@ static struct hc32_pwm_tmr4 g_pwm_tmr4_array[] = static rt_uint32_t tmr4_get_clk_notdiv(CM_TMR4_TypeDef *TMR4x) { rt_uint32_t u32clkFreq; -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) u32clkFreq = CLK_GetBusClockFreq(CLK_BUS_PCLK0); #elif defined(HC32F460) u32clkFreq = CLK_GetBusClockFreq(CLK_BUS_PCLK1); @@ -932,7 +935,7 @@ static rt_err_t tmr4_pwm_set(struct rt_device_pwm *device, struct rt_pwm_configu static void enable_tmr4_unit_clk(void) { #ifdef BSP_USING_PWM_TMR4_1 -#if defined(HC32F472) +#if defined(HC32F472) || defined (HC32F334) FCG_Fcg2PeriphClockCmd(FCG2_PERIPH_TMR4, ENABLE); #else FCG_Fcg2PeriphClockCmd(FCG2_PERIPH_TMR4_1, ENABLE); @@ -960,13 +963,13 @@ static rt_err_t pwm_tmr4_init(struct hc32_pwm_tmr4 *device) { TMR4_OC_Init(TMR4x, i, &device->stcTmr4OcInit); TMR4_PWM_Init(TMR4x, (i >> 1), &device->stcTmr4PwmInit); -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) TMR4_PWM_SetPortOutputMode(TMR4x, i, TMR4_PWM_PIN_OUTPUT_NORMAL); #endif tmr4_pwm_set_cmpmode(TMR4x, i); } } -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) TMR4_PWM_MainOutputCmd(TMR4x, ENABLE); #endif TMR4_Start(TMR4x); @@ -995,6 +998,14 @@ static void pwm_tmr4_get_channel(void) #ifdef BSP_USING_PWM_TMR4_1_OWL g_pwm_tmr4_array[PWM_TMR4_1_INDEX].channel |= (1 << 5); #endif +#if defined (HC32F448) || defined (HC32F334) +#ifdef BSP_USING_PWM_TMR4_1_OXH + g_pwm_tmr4_array[PWM_TMR4_1_INDEX].channel |= (1 << 6); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OXL + g_pwm_tmr4_array[PWM_TMR4_1_INDEX].channel |= (1 << 7); +#endif +#endif #endif #ifdef BSP_USING_PWM_TMR4_2 #ifdef BSP_USING_PWM_TMR4_2_OUH @@ -1196,7 +1207,7 @@ static rt_uint32_t tmr6_get_clk_bydiv(CM_TMR6_TypeDef *TMR6x) case (TMR6_CLK_DIV1024): u32clkFreq /= 1024; break; -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) case (TMR6_CLK_DIV32): u32clkFreq /= 32; break; @@ -1217,7 +1228,7 @@ static void tmr6_duyt100or0_output(CM_TMR6_TypeDef *TMR6x, rt_uint32_t channel, { if (compare_value <= 1) { -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) TMR6_PWM_SetPolarity(TMR6x, channel, TMR6_STAT_OVF, TMR6_PWM_LOW); #elif defined(HC32F460) TMR6_PWM_SetPolarity(TMR6x, channel, TMR6_STAT_MATCH_PERIOD, TMR6_PWM_LOW); @@ -1225,7 +1236,7 @@ static void tmr6_duyt100or0_output(CM_TMR6_TypeDef *TMR6x, rt_uint32_t channel, } else { -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) TMR6_PWM_SetPolarity(TMR6x, channel, TMR6_STAT_OVF, TMR6_PWM_HIGH); #elif defined(HC32F460) TMR6_PWM_SetPolarity(TMR6x, channel, TMR6_STAT_MATCH_PERIOD, TMR6_PWM_HIGH); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_rtc.c b/bsp/hc32/libraries/hc32_drivers/drv_rtc.c index 179333ce30d..6896fb675c6 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_rtc.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_rtc.c @@ -186,7 +186,7 @@ static rt_err_t hc32_rtc_set_time_stamp(time_t time_stamp) #else #define RTC_CLK_SRC_SEL (RTC_CLK_SRC_LRC) #endif -#elif defined(HC32F472) +#elif defined(HC32F472) || defined (HC32F334) #if defined(BSP_RTC_USING_XTAL32) #define RTC_CLK_SRC_SEL (RTC_CLK_SRC_XTAL32) #elif defined(BSP_RTC_USING_XTAL_DIV) @@ -219,7 +219,7 @@ static rt_err_t _rtc_init(void) if ((SET == VBAT_PowerDownCheck()) || (LL_OK != _bakup_reg_check()) || (LL_OK != _hc32_rtc_rw_check())) #elif defined(HC32F4A0) if ((LL_OK != _bakup_reg_check()) || (LL_OK != _hc32_rtc_rw_check())) -#elif defined(HC32F460) || defined(HC32F448) || defined(HC32F472) +#elif defined(HC32F460) || defined(HC32F448) || defined(HC32F472) || defined (HC32F334) if (DISABLE == RTC_GetCounterState()) #endif { @@ -297,7 +297,7 @@ static void _rtc_alarm_irq_handler(void) rt_interrupt_leave(); } -#if defined(HC32F448) || defined(HC32F472) +#if defined(HC32F448) || defined(HC32F472) || defined (HC32F334) void RTC_Handler(void) { if (RTC_GetStatus(RTC_FLAG_ALARM) != RESET) diff --git a/bsp/hc32/libraries/hc32_drivers/drv_sdio.c b/bsp/hc32/libraries/hc32_drivers/drv_sdio.c index 4d49c721e88..85375e5832f 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_sdio.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_sdio.c @@ -987,7 +987,6 @@ static struct rt_mmcsd_host *_sdio_host_create(struct hc32_sdio_config *config, host->ops = &_mmcsd_host_ops; host->freq_min = 400 * 1000; host->freq_max = SDIO_MAX_FREQ; - host->valid_ocr = VDD_26_27 | VDD_27_28 | VDD_28_29 | VDD_29_30 | VDD_30_31 | VDD_31_32 | VDD_32_33 | VDD_33_34;/* The voltage range supported is 2.6v-3.4v */ host->valid_ocr = VDD_32_33 | VDD_33_34; #ifndef SDIO_USING_1_BIT host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_spi.c b/bsp/hc32/libraries/hc32_drivers/drv_spi.c index 9c3d40e8c5e..2e4209106d4 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_spi.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_spi.c @@ -5,11 +5,12 @@ * * Change Logs: * Date Author Notes - * 2022-04-28 CDT first version + * 2022-04-28 CDT First version * 2023-09-30 CDT Delete dma transmit interrupt - * 2024-02-20 CDT support HC32F448 - * 2024-04-16 CDT support HC32F472 - * 2025-04-09 CDT support HC32F4A8 + * 2024-02-20 CDT Support HC32F448 + * 2024-04-16 CDT Support HC32F472 + * 2025-04-09 CDT Support HC32F4A8 + * 2025-07-18 CDT Support HC32F334 */ /******************************************************************************* @@ -40,7 +41,7 @@ /* SPI max division */ #if defined(HC32F4A0) || defined(HC32F460) #define SPI_MAX_DIV_VAL (0x7U) /* Div256 */ -#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) #define SPI_MAX_DIV_VAL (0x39U) #endif @@ -212,7 +213,7 @@ static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configurat } #if defined(HC32F4A0) || defined(HC32F460) stcSpiInit.u32BaudRatePrescaler = (u32Cnt << SPI_CFG2_MBR_POS); -#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) if (u32Cnt <= 15U) { stcSpiInit.u32BaudRatePrescaler = (u32Cnt << SPI_CFG1_CLKDIV_POS); @@ -328,7 +329,7 @@ static void hc32_spi_enable(CM_SPI_TypeDef *SPIx) { SPI_Cmd(SPIx, ENABLE); } -#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) +#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) if ((SPIx->CR & SPI_CR_SPE) != SPI_CR_SPE) { SPI_Cmd(SPIx, ENABLE); @@ -349,7 +350,7 @@ static void hc32_spi_set_trans_mode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode) { CLR_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS); } -#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) +#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) if (SPI_SEND_ONLY == u32Mode) { SET_REG32_BIT(SPIx->CR, SPI_CR_TXMDS); @@ -368,7 +369,7 @@ static uint32_t hc32_spi_get_trans_mode(CM_SPI_TypeDef *SPIx) { #if defined (HC32F460) || defined (HC32F4A0) return READ_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS); -#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) +#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) return READ_REG32_BIT(SPIx->CR, SPI_CR_TXMDS); #else #error "Please select first the target HC32xxxx device used in your application." @@ -714,8 +715,12 @@ void SPI1_Handler(void) { hc32_spi1_err_irq_handler(); } -#endif /* HC32F448, HC32F472 */ - +#elif defined (HC32F334) +void SPI_Handler(void) +{ + hc32_spi1_err_irq_handler(); +} +#endif /* HC32F334 */ #endif /* BSP_USING_SPI1 */ #if defined(BSP_USING_SPI2) @@ -727,13 +732,13 @@ static void hc32_spi2_err_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } + #if defined (HC32F448) ||defined (HC32F472) void SPI2_Handler(void) { hc32_spi2_err_irq_handler(); } #endif /* HC32F448, HC32F472 */ - #endif /* BSP_USING_SPI2 */ #if defined(BSP_USING_SPI3) @@ -745,13 +750,13 @@ static void hc32_spi3_err_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } + #if defined (HC32F448) ||defined (HC32F472) void SPI3_Handler(void) { hc32_spi3_err_irq_handler(); } #endif /* HC32F448, HC32F472 */ - #endif /* BSP_USING_SPI3 */ #if defined(BSP_USING_SPI4) @@ -763,7 +768,7 @@ static void hc32_spi4_err_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif /* BSP_USING_SPI4 */ + #if defined (HC32F472) void SPI4_Handler(void) { @@ -771,6 +776,8 @@ void SPI4_Handler(void) } #endif /* HC32F472 */ +#endif /* BSP_USING_SPI4 */ + #if defined(BSP_USING_SPI5) static void hc32_spi5_err_irq_handler(void) { @@ -908,7 +915,7 @@ static int hc32_hw_spi_bus_init(void) /* register the handle */ #if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) hc32_install_irq_handler(&spi_config[i].err_irq.irq_config, spi_config[i].err_irq.irq_callback, RT_FALSE); -#elif defined (HC32F448) || defined (HC32F472) +#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) INTC_IntSrcCmd(spi_config[i].err_irq.irq_config.int_src, DISABLE); NVIC_DisableIRQ(spi_config[i].err_irq.irq_config.irq_num); #endif diff --git a/bsp/hc32/libraries/hc32_drivers/drv_tmr_capture.c b/bsp/hc32/libraries/hc32_drivers/drv_tmr_capture.c index e908c379e83..16b70b13a02 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_tmr_capture.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_tmr_capture.c @@ -12,8 +12,9 @@ #if defined(BSP_USING_INPUT_CAPTURE) #if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) || defined(BSP_USING_INPUT_CAPTURE_TMR6_2) || defined(BSP_USING_INPUT_CAPTURE_TMR6_3) \ -|| defined(BSP_USING_INPUT_CAPTURE_TMR6_4) || defined(BSP_USING_INPUT_CAPTURE_TMR6_5) || defined(BSP_USING_INPUT_CAPTURE_TMR6_6) \ -|| defined(BSP_USING_INPUT_CAPTURE_TMR6_7) || defined(BSP_USING_INPUT_CAPTURE_TMR6_8) +|| defined(BSP_USING_INPUT_CAPTURE_TMR6_4) || defined(BSP_USING_INPUT_CAPTURE_TMR6_5) || defined(BSP_USING_INPUT_CAPTURE_TMR6_6) \ +|| defined(BSP_USING_INPUT_CAPTURE_TMR6_7) || defined(BSP_USING_INPUT_CAPTURE_TMR6_8) || defined(BSP_USING_INPUT_CAPTURE_TMR6_9) \ +|| defined(BSP_USING_INPUT_CAPTURE_TMR6_10) #include #include @@ -65,6 +66,12 @@ enum #endif #ifdef BSP_USING_INPUT_CAPTURE_TMR6_8 TMR_CAPTURE_IDX_TMR6_8, +#endif +#ifdef BSP_USING_INPUT_CAPTURE_TMR6_9 + TMR_CAPTURE_IDX_TMR6_9, +#endif +#ifdef BSP_USING_INPUT_CAPTURE_TMR6_10 + TMR_CAPTURE_IDX_TMR6_10, #endif TMR_CAPTURE_IDX_MAX, }; @@ -106,6 +113,14 @@ static rt_err_t _tmr_capture_get_pulsewidth(struct rt_inputcapture_device *input static void _tmr6_8_isr_ovf(void); static void _tmr6_8_isr_cap(void); #endif +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_9) + static void _tmr6_9_isr_ovf(void); + static void _tmr6_9_isr_cap(void); +#endif +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_10) + static void _tmr6_10_isr_ovf(void); + static void _tmr6_10_isr_cap(void); +#endif /* Private define ---------------------------------------------------------------*/ #define TMR6_INSTANCE_MIN ((uint32_t)CM_TMR6_1) @@ -113,6 +128,12 @@ static rt_err_t _tmr_capture_get_pulsewidth(struct rt_inputcapture_device *input #define TMR6_INSTANCE_MAX ((uint32_t)CM_TMR6_8) #elif defined (HC32F460) #define TMR6_INSTANCE_MAX ((uint32_t)CM_TMR6_3) +#elif defined (HC32F334) + #define TMR6_INSTANCE_MAX ((uint32_t)CM_TMR6_4) +#elif defined (HC32F448) + #define TMR6_INSTANCE_MAX ((uint32_t)CM_TMR6_2) +#elif defined (HC32F472) + #define TMR6_INSTANCE_MAX ((uint32_t)CM_TMR6_10) #endif #define TMR6_INSTANCE_ADDR_ALIGN (0x400UL) #define TMR6_PERIOD_VALUE_MAX (0xFFFFUL) @@ -120,24 +141,24 @@ static rt_err_t _tmr_capture_get_pulsewidth(struct rt_inputcapture_device *input #if defined (BSP_USING_INPUT_CAPTURE_TMR6) #define IS_CAPTURE_COND_RASING_EDGE(bit_pos) ((bit_pos) % 2U == 0U) - #if defined (HC32F4A0) || defined (HC32F4A8) + #if defined (HC32F4A0) || defined (HC32F4A8) || defined (HC32F334) || defined (HC32F472) #define VALID_CAPTURE_COND (TMR6_CAPT_COND_ALL & (~(TMR6_CAPT_COND_EVT0 | TMR6_CAPT_COND_EVT1 | TMR6_CAPT_COND_EVT2 | TMR6_CAPT_COND_EVT3))) - #elif defined (HC32F460) + #elif defined (HC32F460) || defined (HC32F448) #define VALID_CAPTURE_COND (TMR6_CAPT_COND_ALL & (~(TMR6_CAPT_COND_EVT0 | TMR6_CAPT_COND_EVT1))) #endif #endif -#define TMR6_ISR_OVF(U) \ +#define TMR6_ISR_OVF(U,N) \ static void _tmr6_##U##_isr_ovf(void)\ {\ - g_tmr_capturers[TMR_CAPTURE_IDX_TMR6_##U].ovf_cnt++;\ + g_tmr_capturers[N].ovf_cnt++;\ TMR6_ClearStatus(CM_TMR6_##U, TMR6_FLAG_OVF);\ } -#define TMR6_ISR_CAP(U) \ +#define TMR6_ISR_CAP(U,N) \ static void _tmr6_##U##_isr_cap(void)\ {\ - _tmr6_irq_cap_handler(&g_tmr_capturers[TMR_CAPTURE_IDX_TMR6_##U]);\ + _tmr6_irq_cap_handler(&g_tmr_capturers[N]);\ } #define TMR6_CAPTURE_CFG(U) \ @@ -172,6 +193,12 @@ static tmr_capture_t g_tmr_capturers[] = #if defined (BSP_USING_INPUT_CAPTURE_TMR6_8) TMR6_CAPTURE_CFG(8), #endif +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_9) + TMR6_CAPTURE_CFG(9), +#endif +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_10) + TMR6_CAPTURE_CFG(10), +#endif }; static struct rt_inputcapture_ops tmr_capture_ops = @@ -204,36 +231,44 @@ static void _tmr6_irq_cap_handler(tmr_capture_t *p_capture) } #if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) - TMR6_ISR_OVF(1) - TMR6_ISR_CAP(1) + TMR6_ISR_OVF(1, TMR_CAPTURE_IDX_TMR6_1) + TMR6_ISR_CAP(1, TMR_CAPTURE_IDX_TMR6_1) #endif #if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) - TMR6_ISR_OVF(2) - TMR6_ISR_CAP(2) + TMR6_ISR_OVF(2, TMR_CAPTURE_IDX_TMR6_2) + TMR6_ISR_CAP(2, TMR_CAPTURE_IDX_TMR6_2) #endif #if defined (BSP_USING_INPUT_CAPTURE_TMR6_3) - TMR6_ISR_OVF(3) - TMR6_ISR_CAP(3) + TMR6_ISR_OVF(3, TMR_CAPTURE_IDX_TMR6_3) + TMR6_ISR_CAP(3, TMR_CAPTURE_IDX_TMR6_3) #endif #if defined (BSP_USING_INPUT_CAPTURE_TMR6_4) - TMR6_ISR_OVF(4) - TMR6_ISR_CAP(4) + TMR6_ISR_OVF(4, TMR_CAPTURE_IDX_TMR6_4) + TMR6_ISR_CAP(4, TMR_CAPTURE_IDX_TMR6_4) #endif #if defined (BSP_USING_INPUT_CAPTURE_TMR6_5) - TMR6_ISR_OVF(5) - TMR6_ISR_CAP(5) + TMR6_ISR_OVF(5, TMR_CAPTURE_IDX_TMR6_5) + TMR6_ISR_CAP(5, TMR_CAPTURE_IDX_TMR6_5) #endif #if defined (BSP_USING_INPUT_CAPTURE_TMR6_6) - TMR6_ISR_OVF(6) - TMR6_ISR_CAP(6) + TMR6_ISR_OVF(6, TMR_CAPTURE_IDX_TMR6_6) + TMR6_ISR_CAP(6, TMR_CAPTURE_IDX_TMR6_6) #endif #if defined (BSP_USING_INPUT_CAPTURE_TMR6_7) - TMR6_ISR_OVF(7) - TMR6_ISR_CAP(7) + TMR6_ISR_OVF(7, TMR_CAPTURE_IDX_TMR6_7) + TMR6_ISR_CAP(7, TMR_CAPTURE_IDX_TMR6_7) #endif #if defined (BSP_USING_INPUT_CAPTURE_TMR6_8) - TMR6_ISR_OVF(8) - TMR6_ISR_CAP(8) + TMR6_ISR_OVF(8, TMR_CAPTURE_IDX_TMR6_8) + TMR6_ISR_CAP(8, TMR_CAPTURE_IDX_TMR6_8) +#endif +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_9) + TMR6_ISR_OVF(9, TMR_CAPTURE_IDX_TMR6_9) + TMR6_ISR_CAP(9, TMR_CAPTURE_IDX_TMR6_9) +#endif +#if defined (BSP_USING_INPUT_CAPTURE_TMR6_10) + TMR6_ISR_OVF(10, TMR_CAPTURE_IDX_TMR6_10) + TMR6_ISR_CAP(10, TMR_CAPTURE_IDX_TMR6_10) #endif static void _tmr_irq_init_cap(tmr_capture_t *p_capture) @@ -323,7 +358,7 @@ static void _tmr_capture_init_tmr6(tmr_capture_t *p_capture, CM_TMR6_TypeDef *in uint32_t pin; uint32_t bit_pos = _get_capture_cond_bit_pos(init_params->first_edge); -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F4A8) || defined (HC32F334) || defined (HC32F448) || defined (HC32F472) if (bit_pos <= TMR6_HCPAR_HCPA3_POS) { pin = TMR6_IO_PWMA + (bit_pos / 2U); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usbd.c b/bsp/hc32/libraries/hc32_drivers/drv_usbd.c index b2347ae60c4..b1324771683 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_usbd.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_usbd.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2023-02-14 CDT first version + * 2025-07-25 CDT support HC32F4A8 */ /******************************************************************************* @@ -52,7 +53,7 @@ static struct ep_id _ep_pool[] = {0x4, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, {0x5, USB_EP_ATTR_ISOC, USB_DIR_IN, 64, ID_UNASSIGNED}, {0x5, USB_EP_ATTR_ISOC, USB_DIR_OUT, 64, ID_UNASSIGNED}, -#if defined (HC32F4A0) +#if defined (HC32F4A0) || defined(HC32F4A8) {0x6, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, {0x6, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, {0x7, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, @@ -399,7 +400,7 @@ static void usb_wrblanktxfifo(usb_core_instance *pdev, uint32_t epnum) } } -#if defined(HC32F4A0) || defined(HC32F460) +#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F4A8) #ifdef VBUS_SENSING_ENABLED static void usb_sessionrequest_isr(usb_core_instance *pdev) { @@ -492,7 +493,6 @@ static void usb_inep_isr(usb_core_instance *pdev) if ((u32diepint & TXFEMP) != 0UL) { usb_wrblanktxfifo(pdev, u8epnum); - WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, TXFEMP); } } u8epnum++; @@ -505,7 +505,7 @@ static void usb_outep_isr(usb_core_instance *pdev) uint32_t u32EpIntr; uint32_t u32doepint; uint8_t u8epnum = 0U; - uint32_t u8Xfer; + uint32_t u32Xfer; uint32_t u32ReadEpSize; u32EpIntr = usb_getalloepintr(&pdev->regs); @@ -520,8 +520,8 @@ static void usb_outep_isr(usb_core_instance *pdev) if (pdev->basic_cfgs.dmaen == 1U) { u32ReadEpSize = (READ_REG32(pdev->regs.OUTEP_REGS[u8epnum]->DOEPTSIZ) & USBFS_DOEPTSIZ_XFRSIZ); - u8Xfer = LL_MIN(pdev->dev.out_ep[u8epnum].maxpacket, pdev->dev.out_ep[u8epnum].xfer_len); - pdev->dev.out_ep[u8epnum].xfer_count = u8Xfer - u32ReadEpSize; + u32Xfer = LL_MIN(pdev->dev.out_ep[u8epnum].maxpacket, pdev->dev.out_ep[u8epnum].xfer_len); + pdev->dev.out_ep[u8epnum].xfer_count = u32Xfer - u32ReadEpSize; if (u8epnum != 0U) { pdev->dev.out_ep[u8epnum].xfer_count = pdev->dev.out_ep[u8epnum].xfer_len - u32ReadEpSize; @@ -585,6 +585,7 @@ static void usb_rxstsqlvl_isr(usb_core_instance *pdev) case STS_DATA_UPDT: if (0U != u16ByteCnt) { + RT_ASSERT(RT_IS_ALIGN((uint32_t)ep->xfer_buff, 4UL)); usb_rdpkt(&pdev->regs, ep->xfer_buff, u16ByteCnt); ep->xfer_buff += u16ByteCnt; ep->xfer_count += u16ByteCnt; @@ -717,7 +718,7 @@ static void usb_isr_handler(usb_core_instance *pdev) { usb_isooutincomplt_isr(pdev); } -#if defined(HC32F4A0) || defined(HC32F460) +#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F4A8) #ifdef VBUS_SENSING_ENABLED if ((u32gintsts & VBUSV_INT) != 0UL) { @@ -851,7 +852,7 @@ static rt_err_t _usbd_init(rt_device_t device) #else stcPortIdentify.u8CoreID = USBHS_CORE_ID; #endif -#if defined (HC32F4A0) +#if defined (HC32F4A0) || defined(HC32F4A8) #if !defined(BSP_USING_USBHS_PHY_EXTERN) stcPortIdentify.u8PhyType = USBHS_PHY_EMBED; #else diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usbh.c b/bsp/hc32/libraries/hc32_drivers/drv_usbh.c index 47d47bf775e..8c0b11c6d85 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_usbh.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_usbh.c @@ -112,7 +112,7 @@ static void usb_host_chx_out_isr(usb_core_instance *pdev, uint8_t chnum) { usb_host_clrint(pdev, chnum, USBFS_HCINT_ACK); } -#if defined (HC32F4A0) +#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) else if (0UL != (u32hcint & USBFS_HCINT_AHBERR)) { usb_host_clrint(pdev, chnum, USBFS_HCINT_AHBERR); @@ -236,7 +236,7 @@ static void usb_host_chx_in_isr(usb_core_instance *pdev, uint8_t chnum) { usb_host_clrint(pdev, chnum, USBFS_HCINT_ACK); } -#if defined (HC32F4A0) +#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) else if (0UL != (u32hcint & USBFS_HCINT_AHBERR)) { usb_host_clrint(pdev, chnum, USBFS_HCINT_AHBERR); @@ -1106,7 +1106,7 @@ static rt_err_t _usbh_init(rt_device_t device) #else stcPortIdentify.u8CoreID = USBHS_CORE_ID; #endif -#if defined (HC32F4A0) +#if defined (HC32F4A0) || defined (HC32F4A8) #if !defined(BSP_USING_USBHS_PHY_EXTERN) stcPortIdentify.u8PhyType = USBHS_PHY_EMBED; #else diff --git a/bsp/hc32/libraries/hc32_drivers/drv_wktm.c b/bsp/hc32/libraries/hc32_drivers/drv_wktm.c index 549b698c63e..8b8b9ed3e59 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_wktm.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_wktm.c @@ -30,7 +30,7 @@ #else #if defined(HC32F4A0) || defined(HC32F4A8) #define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_RTCLRC) - #elif defined(HC32F460) || defined(HC32F448) || defined(HC32F472) + #elif defined(HC32F460) || defined(HC32F448) || defined(HC32F472) || defined(HC32F334) #define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_LRC) #endif #define PWC_WKT_COUNT_FRQ (32768UL) diff --git a/bsp/hc32/platform/cherryusb/SConscript b/bsp/hc32/platform/cherryusb/SConscript new file mode 100644 index 00000000000..317440a1b70 --- /dev/null +++ b/bsp/hc32/platform/cherryusb/SConscript @@ -0,0 +1,18 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = [] +path = [cwd] + +if GetDepend(['RT_USING_CHERRYUSB']): + src += Glob('cherryusb_port.c') + +group = DefineGroup('Platform', src, depend = ['RT_USING_CHERRYUSB'], CPPPATH = path) + +Return('group') diff --git a/bsp/hc32/platform/cherryusb/cherryusb_port.c b/bsp/hc32/platform/cherryusb/cherryusb_port.c new file mode 100644 index 00000000000..a5adc74b06d --- /dev/null +++ b/bsp/hc32/platform/cherryusb/cherryusb_port.c @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-08 CDT first version + */ + +#include "usb_config.h" +#include "usbd_core.h" +#include "usbh_core.h" +#include "port/dwc2/usb_dwc2_param.h" + +#include "board_config.h" + +#if defined(RT_CHERRYUSB_HOST) && defined(RT_CHERRYUSB_DEVICE) + #if defined(HC32F460) || defined(HC32F472) + #error "Only one USB role can be selected!" + #endif +#endif + +const struct dwc2_user_params param_fs_core = +{ + .phy_type = DWC2_PHY_TYPE_PARAM_FS, +#ifdef CONFIG_USB_DWC2_DMA_ENABLE + .device_dma_enable = true, +#else + .device_dma_enable = false, +#endif + .device_dma_desc_enable = false, + .device_rx_fifo_size = CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE, + .device_tx_fifo_size = { + [0] = CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE, + [1] = CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE, + [2] = CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE, + [3] = CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE, + [4] = CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE, + [5] = CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE, +#if defined(HC32F4A0) || defined(HC32F4A8) + [6] = CONFIG_USB_FS_CORE_DEVICE_TX6_FIFO_SIZE, + [7] = CONFIG_USB_FS_CORE_DEVICE_TX7_FIFO_SIZE, + [8] = CONFIG_USB_FS_CORE_DEVICE_TX8_FIFO_SIZE, + [9] = CONFIG_USB_FS_CORE_DEVICE_TX9_FIFO_SIZE, + [10] = CONFIG_USB_FS_CORE_DEVICE_TX10_FIFO_SIZE, + [11] = CONFIG_USB_FS_CORE_DEVICE_TX11_FIFO_SIZE, + [12] = CONFIG_USB_FS_CORE_DEVICE_TX12_FIFO_SIZE, + [13] = CONFIG_USB_FS_CORE_DEVICE_TX13_FIFO_SIZE, + [14] = CONFIG_USB_FS_CORE_DEVICE_TX14_FIFO_SIZE, + [15] = CONFIG_USB_FS_CORE_DEVICE_TX15_FIFO_SIZE +#elif defined(HC32F460) || defined(HC32F472) + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 +#endif + }, + .total_fifo_size = CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE, + + .host_dma_desc_enable = false, + .host_rx_fifo_size = CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE, + .host_nperio_tx_fifo_size = CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE, + .host_perio_tx_fifo_size = CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE, + .device_gccfg = 0, + .host_gccfg = 0, +#if defined(HC32F4A0) || defined(HC32F4A8) || defined(HC32F460) + .b_session_valid_override = false, +#elif defined(HC32F472) + .b_session_valid_override = true, +#endif +}; + +#if defined(HC32F4A0) || defined(HC32F4A8) +const struct dwc2_user_params param_hs_core = +{ +#ifdef CONFIG_USB_HS + .phy_type = DWC2_PHY_TYPE_PARAM_UTMI, +#else + .phy_type = DWC2_PHY_TYPE_PARAM_FS, +#endif +#ifdef CONFIG_USB_DWC2_DMA_ENABLE + .device_dma_enable = true, +#else + .device_dma_enable = false, +#endif + .device_dma_desc_enable = false, + .device_rx_fifo_size = CONFIG_USB_HS_CORE_DEVICE_RX_FIFO_SIZE, + .device_tx_fifo_size = { + [0] = CONFIG_USB_HS_CORE_DEVICE_TX0_FIFO_SIZE, + [1] = CONFIG_USB_HS_CORE_DEVICE_TX1_FIFO_SIZE, + [2] = CONFIG_USB_HS_CORE_DEVICE_TX2_FIFO_SIZE, + [3] = CONFIG_USB_HS_CORE_DEVICE_TX3_FIFO_SIZE, + [4] = CONFIG_USB_HS_CORE_DEVICE_TX4_FIFO_SIZE, + [5] = CONFIG_USB_HS_CORE_DEVICE_TX5_FIFO_SIZE, + [6] = CONFIG_USB_HS_CORE_DEVICE_TX6_FIFO_SIZE, + [7] = CONFIG_USB_HS_CORE_DEVICE_TX7_FIFO_SIZE, + [8] = CONFIG_USB_HS_CORE_DEVICE_TX8_FIFO_SIZE, + [9] = CONFIG_USB_HS_CORE_DEVICE_TX9_FIFO_SIZE, + [10] = CONFIG_USB_HS_CORE_DEVICE_TX10_FIFO_SIZE, + [11] = CONFIG_USB_HS_CORE_DEVICE_TX11_FIFO_SIZE, + [12] = CONFIG_USB_HS_CORE_DEVICE_TX12_FIFO_SIZE, + [13] = CONFIG_USB_HS_CORE_DEVICE_TX13_FIFO_SIZE, + [14] = CONFIG_USB_HS_CORE_DEVICE_TX14_FIFO_SIZE, + [15] = CONFIG_USB_HS_CORE_DEVICE_TX15_FIFO_SIZE + }, + .total_fifo_size = CONFIG_USB_HS_CORE_TOTAL_FIFO_SIZE, + + .host_dma_desc_enable = false, + .host_rx_fifo_size = CONFIG_USB_HS_CORE_HOST_RX_FIFO_SIZE, + .host_nperio_tx_fifo_size = CONFIG_USB_HS_CORE_HOST_NP_FIFO_SIZE, + .host_perio_tx_fifo_size = CONFIG_USB_HS_CORE_HOST_PE_FIFO_SIZE, + .device_gccfg = 0, + .host_gccfg = 0, + .b_session_valid_override = false, +}; +#endif + +#ifndef CONFIG_USB_DWC2_CUSTOM_PARAM +void dwc2_get_user_params(uint32_t reg_base, struct dwc2_user_params *params) +{ +#if defined(HC32F4A0) || defined(HC32F4A8) + if (reg_base == CM_USBHS_BASE) + { + memcpy(params, ¶m_hs_core, sizeof(struct dwc2_user_params)); + } + else +#endif + { + memcpy(params, ¶m_fs_core, sizeof(struct dwc2_user_params)); + } +#ifdef CONFIG_USB_DWC2_CUSTOM_FIFO + struct usb_dwc2_user_fifo_config s_dwc2_fifo_config; + + dwc2_get_user_fifo_config(reg_base, &s_dwc2_fifo_config); + + params->device_rx_fifo_size = s_dwc2_fifo_config.device_rx_fifo_size; + for (uint8_t i = 0; i < MAX_EPS_CHANNELS; i++) + { + params->device_tx_fifo_size[i] = s_dwc2_fifo_config.device_tx_fifo_size[i]; + } +#endif +} +#endif + +#define BOARD_INIT_USB_HOST_MODE (0U) +#define BOARD_INIT_USB_DEVICE_MODE (1U) +extern rt_err_t rt_hw_usbfs_board_init(uint8_t devmode); +static uint8_t g_usb_fs_busid = 0U; +#if defined(HC32F4A0) || defined(HC32F4A8) + extern rt_err_t rt_hw_usbhs_board_init(uint8_t devmode); + static uint8_t g_usb_hs_busid = 0U; +#endif + +#if defined(RT_CHERRYUSB_HOST) +static void usbh_fs_irq_handler(void) +{ + USBH_IRQHandler(g_usb_fs_busid); +} + +#if defined(HC32F4A0) || defined(HC32F4A8) +static void usbh_hs_irq_handler(void) +{ + USBH_IRQHandler(g_usb_hs_busid); +} +#endif + +#if defined(HC32F472) +void USBFS_Handler(void) +{ + usbh_fs_irq_handler(); +} +#endif + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + struct hc32_irq_config irq_config; + +#if defined(HC32F4A0) || defined(HC32F4A8) + if (bus->hcd.reg_base == CM_USBHS_BASE) + { + g_usb_hs_busid = bus->hcd.hcd_id; + + rt_hw_usbhs_board_init(BOARD_INIT_USB_HOST_MODE); + FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_USBHS, ENABLE); +#ifndef CONFIG_USB_HS + /* enable the embedded PHY in USBHS mode */ + CM_PERIC->USB_SYCTLREG |= PERIC_USB_SYCTLREG_USBHS_FSPHYE; +#endif + + irq_config.irq_num = BSP_USBHS_GLB_IRQ_NUM; + irq_config.int_src = INT_SRC_USBHS_GLB; + irq_config.irq_prio = BSP_USBHS_GLB_IRQ_PRIO; + /* register interrupt */ + hc32_install_irq_handler(&irq_config, + usbh_hs_irq_handler, + RT_TRUE); + } + else +#endif + { + g_usb_fs_busid = bus->hcd.hcd_id; + + rt_hw_usbfs_board_init(BOARD_INIT_USB_HOST_MODE); + FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_USBFS, ENABLE); + + irq_config.irq_num = BSP_USBFS_GLB_IRQ_NUM; + irq_config.int_src = INT_SRC_USBFS_GLB; + irq_config.irq_prio = BSP_USBFS_GLB_IRQ_PRIO; + /* register interrupt */ + hc32_install_irq_handler(&irq_config, + usbh_fs_irq_handler, + RT_TRUE); + } + +} +#endif + +#if defined(RT_CHERRYUSB_DEVICE) +static void usbd_fs_irq_handler(void) +{ + USBD_IRQHandler(g_usb_fs_busid); +} + +#if defined(HC32F4A0) || defined(HC32F4A8) +static void usbd_hs_irq_handler(void) +{ + USBD_IRQHandler(g_usb_hs_busid); +} +#endif + +#if defined(HC32F472) +void USBFS_Handler(void) +{ + usbd_fs_irq_handler(); +} +#endif + +void usb_dc_low_level_init(uint8_t busid) +{ + struct hc32_irq_config irq_config; + +#if defined(HC32F4A0) || defined(HC32F4A8) + if (g_usbdev_bus[busid].reg_base == CM_USBHS_BASE) + { + g_usb_hs_busid = busid; + + rt_hw_usbhs_board_init(BOARD_INIT_USB_DEVICE_MODE); + FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_USBHS, ENABLE); + +#ifndef CONFIG_USB_HS + /* enable the embedded PHY in USBHS mode */ + CM_PERIC->USB_SYCTLREG |= PERIC_USB_SYCTLREG_USBHS_FSPHYE; +#endif + + irq_config.irq_num = BSP_USBHS_GLB_IRQ_NUM; + irq_config.int_src = INT_SRC_USBHS_GLB; + irq_config.irq_prio = BSP_USBHS_GLB_IRQ_PRIO; + /* register interrupt */ + hc32_install_irq_handler(&irq_config, + usbd_hs_irq_handler, + RT_TRUE); + } + else +#endif + { + g_usb_fs_busid = busid; + + rt_hw_usbfs_board_init(BOARD_INIT_USB_DEVICE_MODE); + FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_USBFS, ENABLE); + + irq_config.irq_num = BSP_USBFS_GLB_IRQ_NUM; + irq_config.int_src = INT_SRC_USBFS_GLB; + irq_config.irq_prio = BSP_USBFS_GLB_IRQ_PRIO; + /* register interrupt */ + hc32_install_irq_handler(&irq_config, + usbd_fs_irq_handler, + RT_TRUE); + } +} + +void usb_dc_low_level_deinit(uint8_t busid) +{ + (void)busid; + /* reserved */ +} + +#endif diff --git a/bsp/hc32/platform/sfud/drv_spi_flash.c b/bsp/hc32/platform/sfud/drv_spi_flash.c index 9e2a58af7f2..70ccd18f715 100644 --- a/bsp/hc32/platform/sfud/drv_spi_flash.c +++ b/bsp/hc32/platform/sfud/drv_spi_flash.c @@ -38,6 +38,11 @@ #define SPI_FLASH_DEVICE_NAME "spi10" #define SPI_FLASH_CHIP "w25q64" #define SPI_FLASH_SS_PIN GET_PIN(B,12) +#elif defined(HC32F334) + #define SPI_BUS_NAME "spi1" + #define SPI_FLASH_DEVICE_NAME "spi10" + #define SPI_FLASH_CHIP "w25q64" + #define SPI_FLASH_SS_PIN GET_PIN(C,1) #endif #define SPI_FLASH_CMD_ENABLE_RESET 0x66 #define SPI_FLASH_CMD_RESET_DEVICE 0x99 diff --git a/bsp/hc32/tests/SConscript b/bsp/hc32/tests/SConscript index 5f775d21553..fd00268e783 100644 --- a/bsp/hc32/tests/SConscript +++ b/bsp/hc32/tests/SConscript @@ -91,6 +91,9 @@ if GetDepend(['BSP_USING_ON_CHIP_FLASH']): if GetDepend(['BSP_USING_GPIO']): src += ['test_gpio.c'] +if GetDepend(['RT_USING_CHERRYUSB']): + src += ['test_cherryusb.c'] + path = [cwd] group = DefineGroup('Tests', src, depend = [''], CPPPATH = path) diff --git a/bsp/hc32/tests/test_adc.c b/bsp/hc32/tests/test_adc.c index 101bbce90fa..abe95b0c9da 100644 --- a/bsp/hc32/tests/test_adc.c +++ b/bsp/hc32/tests/test_adc.c @@ -41,6 +41,10 @@ #define ADC1_CH_MAX (16U) #define ADC2_CH_MAX (8U) #define ADC3_CH_MAX (12U) +#elif defined (HC32F334) + #define ADC1_CH_MAX (16U) + #define ADC2_CH_MAX (12U) + #define ADC3_CH_MAX (10U) #endif @@ -55,7 +59,7 @@ rt_err_t adc_dma_trig_config(void) { stc_tmr0_init_t stcTmr0Init; -#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F472) || defined(HC32F448) || defined(HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F472) || defined(HC32F448) || defined(HC32F4A8) || defined (HC32F334) FCG_Fcg2PeriphClockCmd(FCG2_PERIPH_TMR0_1, ENABLE); #endif (void)TMR0_StructInit(&stcTmr0Init); @@ -101,7 +105,7 @@ static int adc_vol_sample(int argc, char **argv) rt_strcpy(adc_device, "adc2"); adc_max_channel = ADC2_CH_MAX; } -#if defined (HC32F472) || defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) +#if defined (HC32F472) || defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) else if (0 == rt_strcmp(argv[1], "adc3")) { rt_strcpy(adc_device, "adc3"); diff --git a/bsp/hc32/tests/test_can.c b/bsp/hc32/tests/test_can.c index 4424c265276..b96471eacae 100644 --- a/bsp/hc32/tests/test_can.c +++ b/bsp/hc32/tests/test_can.c @@ -70,6 +70,10 @@ static struct rt_semaphore can_rx_sem; static rt_mutex_t can_mutex = RT_NULL; static rt_thread_t rx_thread; +#ifdef RT_CAN_USING_CANFD +static const uint8_t mcan_data_size[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}; +#endif + #define CAN_IF_INIT() do { \ if (can_dev == RT_NULL || can_mutex == RT_NULL) { \ rt_kprintf("failed! please first execute can_sample cmd!\n"); \ @@ -99,10 +103,27 @@ static void _set_default_filter(void) #endif } +static uint8_t _get_can_data_bytes_len(uint32_t dlc) +{ + uint8_t data_bytes = 0; + + dlc &= 0xFU; + if (dlc <= 8U) + { + data_bytes = dlc; + } +#ifdef RT_CAN_USING_CANFD + data_bytes = mcan_data_size[dlc]; +#endif + + return data_bytes; +} + static void can_rx_thread(void *parameter) { struct rt_can_msg rxmsg = {0}; rt_size_t size; + uint8_t data_len; while (1) { @@ -115,7 +136,8 @@ static void can_rx_thread(void *parameter) rt_device_read(can_dev, 0, &rxmsg, sizeof(rxmsg)); /* 打印数据 ID 及内容 */ rt_kprintf("ID:%x Data:", rxmsg.id); - for (int i = 0; i < rxmsg.len; i++) + data_len = _get_can_data_bytes_len(rxmsg.len); + for (int i = 0; i < data_len; i++) { rt_kprintf("%2x ", rxmsg.data[i]); } diff --git a/bsp/hc32/tests/test_cherryusb.c b/bsp/hc32/tests/test_cherryusb.c new file mode 100644 index 00000000000..d8223826e70 --- /dev/null +++ b/bsp/hc32/tests/test_cherryusb.c @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-08 CDT first version + */ +#include +#include +#include + +/* 请关注并阅读bsp/hc32/ev_hc32xxxx/README.md中，关于USB使用的相关注意事项 +*/ + +#if defined(RT_CHERRYUSB_HOST) && defined(RT_CHERRYUSB_DEVICE) + #if defined(HC32F4A0) || defined(HC32F4A8) + #define TEST_USBH_CORE_BASE (CM_USBFS_BASE) + #define TEST_USBD_CORE_BASE (CM_USBHS_BASE) + #else + #error "Only one USB role can be selected" + #endif +#else + #if defined(RT_CHERRYUSB_HOST) + #define TEST_USBH_CORE_BASE (CM_USBFS_BASE) + #elif defined(RT_CHERRYUSB_DEVICE) + #define TEST_USBD_CORE_BASE (CM_USBFS_BASE) + #endif +#endif + +#if defined(RT_CHERRYUSB_HOST) +#include "usbh_core.h" +#if defined(RT_CHERRYUSB_HOST_CDC_ECM) || defined(RT_CHERRYUSB_HOST_CDC_RNDIS) || defined(RT_CHERRYUSB_HOST_MSC) +/* 使用USB Host 时，应确保主机对设备供电充足 + + menuconfig: ECM 关键配置 + + RT-Thread Kernel --->[*] Enable soft timer with a timer thread + (4096) The stack size of timer thread + + RT-Thread Components--->Devicee Drivers--->[*] Using USB with CherryUSB + [*] Enable usb host mode + Selectot usb host ip.... ---> + [*]dwc2_hc + [*] Enable usb cdc ecm driver + + RT-Thread Components--->Network---> lwIP--->lwIP version ---> v2.1.2 + ... + [*] Enable alloc ip address through DHCP + ... + (4096) the stack size of lwIP thread + [*] Not use Rx thread + [*] Not use Tx thread + ... + [*] Enable ping features + + 备注:CherryUSB Host枚举设备时，默认选择Configuration 1，若指定设备(如CH397A模组CDC-ECM模式)需要选择Configuration 2，需在 + components/drivers/usb/cherryusb/core/usbh_core.c文件中usbh_enumerate()函数内添加如下代码： + int usbh_enumerate(struct usbh_hubport *hport) + { + ... + config_index = 0; + // Add code start + if((0x1A86 == ((struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid])->idVendor) && \ + (0x5397 == ((struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid])->idProduct)) { + config_index = 1; // For CH397, we need to select configuration 2 + } + // Add code end + USB_LOG_DBG("The device selects config %d\r\n", config_index); + ... + } + + + menuconfig: MSC 关键配置 + + RT-Thread Kernel --->[*] Enable soft timer with a timer thread + (4096) The stack size of timer thread + + RT-Thread Components--->Devicee Drivers--->[*] Using USB with CherryUSB + [*] Enable usb host mode + Selectot usb host ip.... ---> + [*]dwc2_hc + [*] Enable usb msc driver + ... + (/)usb host dfs mount point + +*/ + + +/* ECM 测试 +msh />ipconfig + network interface: u0 (Default) + MTU: 1500 + MAC: 4e 61 e9 06 9b ff + FLAGS: UP LINK_UP ETHARP BROADCAST IGMP + ip address: 192.168.225.29 + gw address: 192.168.225.1 + net mask : 255.255.255.0 + dns server #0: 108.7.254.31 + dns server #1: 112.7.254.31 +msh />ping www.baidu.com + 60 bytes from 183.2.172.177 icmp_seq=0 ttl=51 time=149 ms + 60 bytes from 183.2.172.177 icmp_seq=1 ttl=51 time=69 ms + 60 bytes from 183.2.172.177 icmp_seq=2 ttl=51 time=51 ms + 60 bytes from 183.2.172.177 icmp_seq=3 ttl=51 time=52 ms +*/ +static int cherryusb_host_init(void) +{ + usbh_initialize(0, TEST_USBH_CORE_BASE); + return 0; +} +INIT_APP_EXPORT(cherryusb_host_init); + +#if defined(RT_CHERRYUSB_HOST_CDC_ECM) || defined(RT_CHERRYUSB_HOST_CDC_RNDIS) +void ipconfig(void) +{ + extern void list_if(void); + list_if(); +} +MSH_CMD_EXPORT(ipconfig, list network interface information); +#endif + +#endif +#endif + +#if defined(RT_CHERRYUSB_DEVICE) +#if defined(RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM) +/* + menuconfig:关键配置 + + RT-Thread Components--->Devicee Drivers--->[*] Using USB with CherryUSB + [*] Enable usb device mode + Selectot usb host ip.... ---> + [*]dwc2_hc + [*] Enable usb cdc acm device + Select usb device template...---> + [*] cdc acm +*/ + +static int cherryusb_device_cdc_acm_init(void) +{ + extern void cdc_acm_init(uint8_t busid, uint32_t reg_base); + cdc_acm_init(0, TEST_USBD_CORE_BASE); + return 0; +} +INIT_APP_EXPORT(cherryusb_device_cdc_acm_init); + +static void cherryusb_cdc_send(int argc, char **argv) +{ + extern void cdc_acm_data_send_with_dtr_test(uint8_t busid); + cdc_acm_data_send_with_dtr_test(0); +} +MSH_CMD_EXPORT(cherryusb_cdc_send, cdc acm data send with dtr test); + +#endif +#endif diff --git a/bsp/hc32/tests/test_crypto.c b/bsp/hc32/tests/test_crypto.c index 79744f441a6..439433723af 100644 --- a/bsp/hc32/tests/test_crypto.c +++ b/bsp/hc32/tests/test_crypto.c @@ -11,6 +11,7 @@ #include #include #include +#include #if defined(BSP_USING_HWCRYPTO) @@ -43,7 +44,7 @@ static void _crypto_cmd_print_usage(void) rt_kprintf(" aes: test aes module. \n"); #if defined(HC32F460) rt_kprintf(" e.g. msh >crypto_sample aes 128 \n"); -#elif defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) +#elif defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) rt_kprintf(" e.g. msh >crypto_sample aes 128/192/256 \n"); #endif #endif @@ -56,6 +57,14 @@ static void _crypto_cmd_print_usage(void) } #if defined(BSP_USING_CRC) +/* menuconfig: + Hardware Drivers Config--->On-Chip Peripheral Driver--->Using Hardware Crypto ---> + [*]Enable Hardeware CRC + * CRC16命令调用：crypto_sample crc 16 + * CRC32命令调用：crypto_sample crc 32 + * 程序功能：打印CRC输入数据和计数结果，使用第三方软件计算数据，再做比较 + */ + #define CRC16_WIDTH 16U #define CRC32_WIDTH 32U static void crc_test(rt_uint32_t width) @@ -125,65 +134,91 @@ static void aes_test(rt_uint16_t key_bitlen) const char *key192 = "1234567890abcdefghijklmn"; const char *key256 = "1234567890abcdefghijklmnopqrstuv"; const char *key; - - ctx = rt_hwcrypto_symmetric_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_AES_ECB); - if (ctx == RT_NULL) + rt_uint8_t type_max = 1U; + hwcrypto_type types[] = { - rt_kprintf("create AES-CBC context err!"); - return; - } - switch (key_bitlen) + HWCRYPTO_TYPE_AES_ECB, + HWCRYPTO_TYPE_AES_CBC, + HWCRYPTO_TYPE_AES_CTR, + HWCRYPTO_TYPE_AES_CFB, + HWCRYPTO_TYPE_AES_OFB, + }; + const char *type_str[] = { - case 128: - key = key128; - break; - case 192: - key = key192; - break; - case 256: - key = key256; - break; - default: - key = key128; - break; - } - result = rt_hwcrypto_symmetric_setkey(ctx, (rt_uint8_t *)key, key_bitlen); - if (result == RT_EOK) + "aes_ecb", + "aes_cbc", + "aes_ctr", + "aes_cfb", + "aes_ofb", + }; +#if defined (HC32F4A8) + type_max = 5U; +#endif + for (int i = 0; i < type_max; i++) { - result = rt_hwcrypto_symmetric_crypt(ctx, HWCRYPTO_MODE_ENCRYPT, AES_DATA_LEN, (rt_uint8_t *)enc_in, enc_out); - if (result != RT_EOK) + ctx = rt_hwcrypto_symmetric_create(rt_hwcrypto_dev_default(), types[i]); + if (ctx == RT_NULL) { - goto _exit; + rt_kprintf("create AES context err!"); + return; } - - rt_kprintf("aes src data:"); - for (int i = 0; i < AES_DATA_LEN; i++) + switch (key_bitlen) { - rt_kprintf("%c", enc_in[i]); + case 128: + key = key128; + break; + case 192: + key = key192; + break; + case 256: + key = key256; + break; + default: + key = key128; + break; } - rt_kprintf("\n"); - - rt_kprintf("aes enc data:"); - for (int i = 0; i < AES_DATA_LEN; i++) + result = rt_hwcrypto_symmetric_setkey(ctx, (rt_uint8_t *)key, key_bitlen); +#if defined (HC32F4A8) + const char *iv = "1234567812345678"; + result = rt_hwcrypto_symmetric_setiv(ctx, (const rt_uint8_t *)iv, strlen(iv)); +#endif + if (result == RT_EOK) { - rt_kprintf("%x ", enc_out[i]); - } - rt_kprintf("\n"); + result = rt_hwcrypto_symmetric_crypt(ctx, HWCRYPTO_MODE_ENCRYPT, AES_DATA_LEN, (rt_uint8_t *)enc_in, enc_out); + if (result != RT_EOK) + { + goto _exit; + } - result = rt_hwcrypto_symmetric_crypt(ctx, HWCRYPTO_MODE_DECRYPT, AES_DATA_LEN, (rt_uint8_t *)enc_out, dec_out); - if (result != RT_EOK) - { - goto _exit; - } - rt_kprintf("aes dec data:"); - for (int i = 0; i < AES_DATA_LEN; i++) - { - rt_kprintf("%c", dec_out[i]); - } - rt_kprintf("\n"); + rt_kprintf("%s src data:", type_str[i]); + for (int i = 0; i < AES_DATA_LEN; i++) + { + rt_kprintf("%c", enc_in[i]); + } + rt_kprintf("\n"); + + rt_kprintf("%s enc data:", type_str[i]); + for (int i = 0; i < AES_DATA_LEN; i++) + { + rt_kprintf("%02x ", enc_out[i]); + } + rt_kprintf("\n"); + + result = rt_hwcrypto_symmetric_crypt(ctx, HWCRYPTO_MODE_DECRYPT, AES_DATA_LEN, (rt_uint8_t *)enc_out, dec_out); + if (result != RT_EOK) + { + goto _exit; + } + rt_kprintf("%s dec data:", type_str[i]); + for (int i = 0; i < AES_DATA_LEN; i++) + { + rt_kprintf("%c", dec_out[i]); + } + rt_kprintf("\n"); _exit: - rt_hwcrypto_symmetric_destroy(ctx); + rt_hwcrypto_symmetric_destroy(ctx); + } } } #endif diff --git a/bsp/hc32/tests/test_dac.c b/bsp/hc32/tests/test_dac.c index 36e3e134bff..9821993bfa6 100644 --- a/bsp/hc32/tests/test_dac.c +++ b/bsp/hc32/tests/test_dac.c @@ -32,6 +32,7 @@ static int dac_vol_sample(int argc, char *argv[]) { char dac_device_name[] = "dac1"; rt_uint8_t channel = 1; + rt_uint8_t max_channel = 2; rt_dac_device_t dac_dev; rt_uint32_t value = 1365; /* 默认1.1V */ rt_uint32_t convertBits; @@ -44,21 +45,29 @@ static int dac_vol_sample(int argc, char *argv[]) if (0 == rt_strcmp(argv[1], "dac1")) { rt_strcpy(dac_device_name, "dac1"); + max_channel = 2; } -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) +#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) else if (0 == rt_strcmp(argv[1], "dac2")) { rt_strcpy(dac_device_name, "dac2"); +#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) + max_channel = 2; +#elif defined (HC32F334) + max_channel = 1; +#endif } #endif #if defined (HC32F472) else if (0 == rt_strcmp(argv[1], "dac3")) { rt_strcpy(dac_device_name, "dac3"); + max_channel = 2; } else if (0 == rt_strcmp(argv[1], "dac4")) { rt_strcpy(dac_device_name, "dac4"); + max_channel = 2; } #endif else @@ -84,7 +93,7 @@ static int dac_vol_sample(int argc, char *argv[]) return -RT_ERROR; } convertBits = (1 << (rt_uint8_t)convertBits); - for (channel = 1; channel < 3; channel++) + for (channel = 1; channel <= max_channel; channel++) { /* 打开通道 */ ret = rt_dac_enable(dac_dev, channel); diff --git a/bsp/hc32/tests/test_fal.c b/bsp/hc32/tests/test_fal.c index dce299a5230..6acb246a4ad 100644 --- a/bsp/hc32/tests/test_fal.c +++ b/bsp/hc32/tests/test_fal.c @@ -29,6 +29,7 @@ #define FAL_PART_NAME "app" #define TEST_BUF_SIZE 1024UL #define TEST_RW_CNT 32UL + #define TEST_RW_START_ADDR HC32_FLASH_END_ADDRESS - (TEST_BUF_SIZE * TEST_RW_CNT) diff --git a/bsp/hc32/tests/test_pfc8563_i2c.c b/bsp/hc32/tests/test_pfc8563_i2c.c deleted file mode 100644 index 93b29ac5e45..00000000000 --- a/bsp/hc32/tests/test_pfc8563_i2c.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2024-12-30 CDT first version - */ - -/* - * 程序清单：这是一个 I2C 设备使用例程 - * 例程导出了 pcf8563 命令到控制终端 - * 命令调用格式：i2c_pcf8563_sample i2c1 - * 命令解释：命令第二个参数是要使用的I2C总线设备名称，为空则使用默认的I2C总线设备 - * 程序功能：通过 I2C 设备读取时间信息并打印 -*/ - -#include -#include - -#if defined(BSP_USING_I2C) - -#define PFC8563_I2C_BUS_NAME "i2c1" /* I2C总线设备名称 */ -#define PFC8563_ADDR 0x51 /* 从机地址 */ -#define PFC8563_REG_SEC 0x02 /* 校准命令 */ -#define PFC8563_REG_CTRL_SR1 0x00 /* 校准命令 */ - -#define PFC8563_TIME_LEN 0x7 /* 获取数据长度 */ - - -#define RTC_DEC2BCD(__DATA__) ((((__DATA__) / 10U) << 4U) + ((__DATA__) % 10U)) -#define RTC_BCD2DEC(__DATA__) ((((__DATA__) >> 4U) * 10U) + ((__DATA__) & 0x0FU)) - - -static struct rt_i2c_bus_device *i2c_bus = RT_NULL; /* I2C总线设备句柄 */ -static rt_bool_t initialized = RT_FALSE; /* 传感器初始化状态 */ - -/* 写传感器寄存器 */ -static rt_err_t write_regs(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint8_t len) -{ - rt_uint8_t buf[16 + 1]; - struct rt_i2c_msg msgs; - rt_uint32_t buf_size = 1; - - buf[0] = reg; // cmd - if (data != RT_NULL) - { - memcpy(&buf[1], data, len); - buf_size += len; - } - - msgs.addr = PFC8563_ADDR; - msgs.flags = RT_I2C_WR; - msgs.buf = buf; - msgs.len = buf_size; - - /* 调用I2C设备接口传输数据 */ - if (rt_i2c_transfer(bus, &msgs, 1) == 1) - { - return RT_EOK; - } - else - { - rt_kprintf("write regs failed!\n"); - return -RT_ERROR; - } -} - -/* 读传感器寄存器数据 */ -static rt_err_t read_regs(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint8_t len) -{ - struct rt_i2c_msg msgs[2]; - rt_uint8_t buf[16 + 1]; - rt_uint32_t buf_size = 1; - - buf[0] = reg; // cmd - msgs[0].addr = PFC8563_ADDR; - msgs[0].flags = RT_I2C_WR; - msgs[0].buf = buf; - msgs[0].len = buf_size; - - msgs[1].addr = PFC8563_ADDR; - msgs[1].flags = RT_I2C_RD; - msgs[1].buf = data; - msgs[1].len = len; - - /* 调用I2C设备接口传输数据 */ - if (rt_i2c_transfer(bus, &msgs[0], 2) == 2) - { - return RT_EOK; - } - else - { - rt_kprintf("read regs failed!\n"); - return -RT_ERROR; - } -} - -static void pcf8563_init(const char *name) -{ - rt_uint8_t temp[16]; - - /* 查找I2C总线设备，获取I2C总线设备句柄 */ - i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(name); - - if (i2c_bus == RT_NULL) - { - rt_kprintf("can't find %s device!\n", name); - } - else - { - rt_thread_mdelay(500); - temp[0] = 0x28U; - write_regs(i2c_bus, PFC8563_REG_CTRL_SR1, temp, 1); - rt_thread_mdelay(100); - temp[0] = 0x08U; - write_regs(i2c_bus, PFC8563_REG_CTRL_SR1, temp, 1); - rt_thread_mdelay(100); - - temp[0] = RTC_DEC2BCD(55); - temp[1] = RTC_DEC2BCD(59); - temp[2] = RTC_DEC2BCD(23); - temp[3] = RTC_DEC2BCD(1); - temp[4] = RTC_DEC2BCD(3); - temp[5] = RTC_DEC2BCD(1); - temp[6] = RTC_DEC2BCD(20); - write_regs(i2c_bus, PFC8563_REG_SEC, temp, PFC8563_TIME_LEN); - rt_thread_mdelay(100); - initialized = RT_TRUE; - } -} - -static void serial_thread_entry(void *parameter) -{ - rt_uint8_t time[16]; - - memset(time, 0, 16); - rt_thread_mdelay(500); - rt_thread_mdelay(500); - - while (1) - { - // if (RT_EOK == read_regs(i2c_bus, PFC8563_REG_SEC, time, PFC8563_TIME_LEN)) - if (RT_EOK == read_regs(i2c_bus, PFC8563_REG_SEC, time, 1)) - { - time[0] &= 0x7FU; - time[1] &= 0x7FU; - time[2] &= 0x3FU; - time[3] &= 0x3FU; - time[4] &= 0x7U; - time[5] &= 0x1FU; - time[6] &= 0xFFU; - /* Print current date and time */ - rt_kprintf("Time: 20%02d/%02d/%02d %02d:%02d:%02d\n", RTC_BCD2DEC(time[6]), RTC_BCD2DEC(time[5]), - RTC_BCD2DEC(time[3]), RTC_BCD2DEC(time[2]), RTC_BCD2DEC(time[1]), RTC_BCD2DEC(time[0])); - } - else - { - rt_kprintf("Get time failed!\n"); - } - rt_thread_mdelay(100); - } -} - -void i2c_pcf8563_sample(int argc, char *argv[]) -{ - char bus_name[RT_NAME_MAX]; - - if (argc == 2) - { - rt_strncpy(bus_name, argv[1], RT_NAME_MAX); - } - else - { - rt_strncpy(bus_name, PFC8563_I2C_BUS_NAME, RT_NAME_MAX); - } - - if (!initialized) - { - /* 传感器初始化 */ - pcf8563_init(bus_name); - } - if (initialized) - { - /* 创建 serial 线程 */ - rt_thread_t thread = rt_thread_create("serial", serial_thread_entry, RT_NULL, 1024, 25, 10); - /* 创建成功则启动线程 */ - if (thread != RT_NULL) - { - rt_thread_startup(thread); - } - else - { - rt_kprintf("startup thread failed!\n"); - } - } - else - { - rt_kprintf("initialize sensor failed!\n"); - } -} -/* 导出到 msh 命令列表中 */ -MSH_CMD_EXPORT(i2c_pcf8563_sample, i2c aht10 sample); - -#endif diff --git a/bsp/hc32/tests/test_pm.c b/bsp/hc32/tests/test_pm.c index 8b41616363f..cb334e2b55d 100644 --- a/bsp/hc32/tests/test_pm.c +++ b/bsp/hc32/tests/test_pm.c @@ -113,6 +113,20 @@ #define LED_GREEN_PORT (GPIO_PORT_C) #define LED_GREEN_PIN (GPIO_PIN_09) +#elif defined (HC32F334) + #define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) + #define BSP_KEY_PORT (GPIO_PORT_B) /* Key5 */ + #define BSP_KEY_PIN (GPIO_PIN_09) + #define BSP_KEY_EXTINT (EXTINT_CH09) + #define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ9) + #define BSP_KEY_IRQn (INT001_IRQn) + #define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH9) + #define BSP_KEY_EVT (EVT_SRC_PORT_EIRQ9) + #define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP2) + #define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP21) + + #define LED_GREEN_PORT (GPIO_PORT_C) + #define LED_GREEN_PIN (GPIO_PIN_13) #endif #define KEYCNT_BACKUP_ADDR (uint32_t *)(0x200F0010) @@ -421,7 +435,7 @@ static void _vbat_init(void) rt_thread_delay(10); } FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_SRAMB, ENABLE); -#elif defined (HC32F448) +#elif defined (HC32F448) || defined (HC32F334) FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_SRAMB, ENABLE); #elif defined (HC32F460) FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_SRAMRET, ENABLE); diff --git a/bsp/hc32/tests/test_pulse_encoder.c b/bsp/hc32/tests/test_pulse_encoder.c index 000699e85e2..641e45d00f0 100644 --- a/bsp/hc32/tests/test_pulse_encoder.c +++ b/bsp/hc32/tests/test_pulse_encoder.c @@ -30,7 +30,7 @@ #ifdef BSP_USING_PULSE_ENCODER -#if defined (HC32F4A0) +#if defined (HC32F4A0) || defined (HC32F4A8) #define TEST_IO_A_PIN GET_PIN(A, 5) #define TEST_IO_B_PIN GET_PIN(A, 6) #else @@ -42,7 +42,7 @@ static rt_device_t pulse_encoder_dev = RT_NULL; static void printf_connect(void) { -#if defined (HC32F4A0) +#if defined (HC32F4A0) || defined (HC32F4A8) #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) rt_kprintf(" [tmra]*connect PA5-->PA8 PA6-->PA9\n"); #endif @@ -74,6 +74,14 @@ static void printf_connect(void) rt_kprintf(" [tmr6]*connect PB0-->PA3 PB1-->PA7\n"); #endif #endif +#if defined (HC32F334) +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) + rt_kprintf(" [tmra]*connect PB0-->PA0 PB1-->PA1\n"); +#endif +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) + rt_kprintf(" [tmr6]*connect PB0-->PA7 PB1-->PA3\n"); +#endif +#endif } static void _pulse_cmd_print_usage(void) diff --git a/bsp/hc32/tests/test_spi.c b/bsp/hc32/tests/test_spi.c index eebc16b94d0..171c70da8d4 100644 --- a/bsp/hc32/tests/test_spi.c +++ b/bsp/hc32/tests/test_spi.c @@ -37,7 +37,11 @@ #define W25Q_MAX_ADDR (0x800000UL) #define W25Q_SPI_WR_RD_ADDR 0x4000 -#define W25Q_SPI_DATA_BUF_LEN 0x2000 +#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) + #define W25Q_SPI_DATA_BUF_LEN 0x2000 +#elif defined (HC32F334) + #define W25Q_SPI_DATA_BUF_LEN 0x1000 +#endif #if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F4A8) @@ -61,6 +65,13 @@ #define W25Q_SPI_BUS_NAME "spi3" #define W25Q_SPI_DEVICE_NAME "spi30" +#elif defined(HC32F334) + #define SPI_CS_PORT SPI1_CS_PORT + #define SPI_CS_PIN SPI1_CS_PIN + #define SPI_CS_PORT_PIN GET_PIN(C, 1) + + #define W25Q_SPI_BUS_NAME "spi1" + #define W25Q_SPI_DEVICE_NAME "spi10" #endif diff --git a/bsp/hc32/tests/test_tmr_capture.c b/bsp/hc32/tests/test_tmr_capture.c index 96929389683..2a94e5aee78 100644 --- a/bsp/hc32/tests/test_tmr_capture.c +++ b/bsp/hc32/tests/test_tmr_capture.c @@ -10,14 +10,13 @@ /* * 功能 -* 展示捕获单元 ic1、ic2、ic3 的捕获输入功能 +* 展示捕获单元 icx (x=1~IC_DEV_CNT) 的捕获输入功能 * 当捕获单元捕获到设定数量（watermark）的数据(电平宽度-单位为us)后，终端将输出这些已捕获的数据 * * 默认配置 * input pin： -* ic1: INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN -* ic2: INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN -* ic3: INPUT_CAPTURE_TMR6_3_PORT, INPUT_CAPTURE_TMR6_3_PIN +* icx: INPUT_CAPTURE_TMR6_x_PORT, INPUT_CAPTURE_TMR6_x_PIN (x=1~IC_DEV_CNT) + 注：该引脚配置位于 board_config.h，若测试单元的input pin未配置，需测试人员自行添加 * watermark： * 默认值为 5 * @@ -63,8 +62,13 @@ #define IC_DEV_CNT (8) #elif defined (HC32F460) #define IC_DEV_CNT (3) +#elif defined (HC32F334) + #define IC_DEV_CNT (4) +#elif defined (HC32F448) + #define IC_DEV_CNT (2) +#elif defined (HC32F472) + #define IC_DEV_CNT (10) #endif -#define IC_NAME_LEN (3) #define DEFAULT_WATER_MARK (5) #ifdef BSP_USING_INPUT_CAPTURE @@ -107,20 +111,22 @@ static void ic_rx_thread(void *parameter) { rt_size_t size; rt_device_t ic_dev; - rt_uint32_t id = *(uint32_t *)parameter; - test_ic_t *p_test_ic = &g_arr_test_ic[id]; + test_ic_t *p_test_ic = parameter; ic_dev = p_test_ic->ic_dev; struct rt_inputcapture_data *pData = RT_NULL; struct rt_inputcapture_data *pItem = RT_NULL; int i = 0; + char *p_thrd_name = rt_thread_self()->parent.name; + while (1) { rt_sem_take((p_test_ic->rx_sem), RT_WAITING_FOREVER); - pData = (struct rt_inputcapture_data *)rt_malloc(sizeof(struct rt_inputcapture_data) * p_test_ic->ic_data_size); + size = p_test_ic->ic_data_size; + pData = (struct rt_inputcapture_data *)rt_malloc(sizeof(struct rt_inputcapture_data) * size); if (pData) { rt_mutex_take(p_test_ic->mutex, RT_WAITING_FOREVER); - size = rt_device_read(ic_dev, 0, pData, p_test_ic->ic_data_size); + size = rt_device_read(ic_dev, 0, pData, size); rt_mutex_release(p_test_ic->mutex); if (size == 0) { @@ -128,7 +134,7 @@ static void ic_rx_thread(void *parameter) pData = RT_NULL; continue; } - rt_kprintf("ic%d captured %d data:\n", id + 1, size); + rt_kprintf("%s captured %d data:\n", p_thrd_name, size); for (i = 0; i < size; i++) { pItem = pData + i; @@ -147,9 +153,13 @@ static rt_int32_t _ic_test_open(rt_int32_t id) uint32_t def_wm = DEFAULT_WATER_MARK; rt_device_t ic_dev; - - char ic_name[IC_NAME_LEN] = "ic"; - ic_name[IC_NAME_LEN - 1] = 0x30 + id + 1; + char ic_name[RT_NAME_MAX] = "ic"; + uint32_t name_idx = 2; + if (id >= 9 && id < 100) + { + ic_name[name_idx++] = 0x30 + (id + 1) / 10; + } + ic_name[name_idx++] = 0x30 + (id + 1) % 10; ic_dev = rt_device_find(ic_name); RT_ASSERT(ic_dev != RT_NULL); @@ -161,14 +171,14 @@ static rt_int32_t _ic_test_open(rt_int32_t id) RT_ASSERT(ret == RT_EOK); rt_device_set_rx_indicate(ic_dev, ic_rx_all); - g_arr_test_ic[id].thread = rt_thread_create(ic_name, ic_rx_thread, &id, 2048, 5, 10); + g_arr_test_ic[id].thread = rt_thread_create(ic_name, ic_rx_thread, &g_arr_test_ic[id], 2048, 5, 10); RT_ASSERT(g_arr_test_ic[id].thread != RT_NULL); rt_thread_startup(g_arr_test_ic[id].thread); - ret = rt_device_open(ic_dev, 0); - RT_ASSERT(ret == RT_EOK); ret = rt_device_control(ic_dev, INPUTCAPTURE_CMD_SET_WATERMARK, &def_wm); RT_ASSERT(ret == RT_EOK); + ret = rt_device_open(ic_dev, 0); + RT_ASSERT(ret == RT_EOK); return RT_EOK; } diff --git a/bsp/hc32/tests/test_uart_v2.c b/bsp/hc32/tests/test_uart_v2.c index 1aafab95297..11ab6c466de 100644 --- a/bsp/hc32/tests/test_uart_v2.c +++ b/bsp/hc32/tests/test_uart_v2.c @@ -20,8 +20,8 @@ * 输出输入的字符 * * 命令调用格式： - * uart1 中断，命令调用格式：uart_sample_v1 uart1 int - * uart1 DMA，命令调用格式：uart_sample_v1 uart1 dma + * uart1 中断，命令调用格式：uart_sample_v2 uart1 int + * uart1 DMA，命令调用格式：uart_sample_v2 uart1 dma * * 中断方式，rtconfig.h修改如下 * #define BSP_USING_GPIO diff --git a/bsp/hc32/tests/test_usbd.c b/bsp/hc32/tests/test_usbd.c index 11cb23851fd..5a4a19027bd 100644 --- a/bsp/hc32/tests/test_usbd.c +++ b/bsp/hc32/tests/test_usbd.c @@ -49,7 +49,7 @@ static int cdc_sample(void) rt_err_t ret = RT_EOK; rt_device_t cdc_dev = RT_NULL; /* usb device设备句柄 */ rt_uint8_t str_write[] = "This is a usb cdc device test!\r\n"; - + rt_size_t str_len = rt_strlen((const char *)str_write); /* 查找USB虚拟串口设备 */ cdc_dev = rt_device_find(USBD_DEV_NAME); @@ -71,7 +71,7 @@ static int cdc_sample(void) for (i = 1; i < 4; i++) { rt_kprintf("Start to send test message 3 timers :%d.\n", i); - if (rt_device_write(cdc_dev, 0, str_write, sizeof(str_write)) != sizeof(str_write)) + if (rt_device_write(cdc_dev, 0, str_write, str_len) != str_len) { rt_kprintf("send test message failed\n"); return -RT_ERROR; @@ -91,7 +91,7 @@ MSH_CMD_EXPORT(cdc_sample, usbd cdc sample); #if defined(RT_USB_DEVICE_MSTORAGE) /* F4A0 only FS can used with spi flash */ -#if (defined(HC32F4A0) && defined(BSP_USING_USBFS)) || \ +#if ((defined(HC32F4A0) || defined(HC32F4A8)) && defined(BSP_USING_USBFS)) || \ defined(HC32F460) || defined(HC32F472) /* Enable spibus1, SFUD, usb msc */ @@ -117,7 +117,7 @@ MSH_CMD_EXPORT(cdc_sample, usbd cdc sample); #include "dev_spi_flash_sfud.h" #define SPI_FLASH_CHIP RT_USB_MSTORAGE_DISK_NAME /* msc class disk name */ -#if defined(HC32F4A0) +#if defined(HC32F4A0) || defined(HC32F4A8) #define SPI_FLASH_SS_PORT GPIO_PORT_C #define SPI_FLASH_SS_PIN GPIO_PIN_07 #define SPI_BUS_NAME "spi1" @@ -157,7 +157,7 @@ static void rt_hw_spi_flash_reset(char *spi_dev_name) static int rt_hw_spi_flash_with_sfud_init(void) { -#if defined(HC32F4A0) || defined(HC32F460) +#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F4A8) rt_hw_spi_device_attach(SPI_BUS_NAME, SPI_FLASH_DEVICE_NAME, GET_PIN(C, 7)); #elif defined(HC32F472) rt_hw_spi_device_attach(SPI_BUS_NAME, SPI_FLASH_DEVICE_NAME, GET_PIN(B, 12)); @@ -201,7 +201,7 @@ INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init); */ #define USBD_DEV_NAME "hidd" /* 名称 */ -#if defined(HC32F4A0) +#if defined(HC32F4A0) || defined(HC32F4A8) #define KEY_PIN_NUM GET_PIN(A,0) /* PA0 */ #elif defined(HC32F460) #define KEY_PIN_NUM GET_PIN(B,1) /* PB1 */ @@ -270,11 +270,11 @@ MSH_CMD_EXPORT(hid_sample, usbd hid sample); * 命令调用格式：winusb_sample * 软件：llcom.exe * 程序功能：MSH命令发送winusb_sample，运行测试程序。 - * 打开llcom.exe软件，选择小工具-WinUSB设备-选择对应RTT Win USB设备-打开-勾选Hex发送-发送数据。 + * 打开llcom.exe软件，选择小工具-WinUSB设备-选择对应RTT Win USB设备-打开-勾选Hex发送-发送数据（注意：每次发送数据长度为4的整数倍）。 * 通过llcom.exe可发送bulk数据（100字符以内）到设备，设备收到后会回发给主机(llcom.exe)，同时通过MSH终端显示收到的HEX数据。 * 注意：1、llcom.exe中的GUID与驱动程序中设定保持一致(通过设备管理器选择RTT Win USB设备的属性来查看)； - * 2、win_usb_read()函数中的UIO_REQUEST_READ_FULL改为UIO_REQUEST_READ_BEST，实现数据即读即取; - * 否则需要接满传入的size数量，才会回调接收函数。 + * 2、win_usb_read()函数中的UIO_REQUEST_READ_FULL改为UIO_REQUEST_READ_BEST，实现数据即读即取; + * 否则需要接满传入的size数量，才会回调接收函数。 * */ #define WINUSB_DEV_NAME "winusb" /* 名称 */ diff --git a/bsp/hc32/tests/test_usbh.c b/bsp/hc32/tests/test_usbh.c index c4877b59761..e5cddafc61d 100644 --- a/bsp/hc32/tests/test_usbh.c +++ b/bsp/hc32/tests/test_usbh.c @@ -22,9 +22,10 @@ (/) Udisk mount dir 2. RT-Thread Components ---> DFS: device virtual files system ---> ...... - [*] Enable elm0chan fatfs + [*] Enable elm-chan fatfs ...... 3.如果命令执行不成功，需参考对应Board目录下的README.md文件(注意事项中的USB Host部分) + 4.命令成功创建文件后，可以通过ls命令查看、通过cat命令查看文件内容、通过rm命令删除文件等操作 */ /* diff --git a/bsp/hc32/tests/test_wdt.c b/bsp/hc32/tests/test_wdt.c index 5827be269b7..c3c17151427 100644 --- a/bsp/hc32/tests/test_wdt.c +++ b/bsp/hc32/tests/test_wdt.c @@ -50,7 +50,7 @@ static void _wdt_cmd_print_usage(void) static int wdt_sample(int argc, char *argv[]) { - rt_err_t ret = RT_EOK; + int ret = RT_EOK; rt_uint32_t timeleft; rt_uint32_t timeout = atoi(argv[2]); @@ -114,7 +114,7 @@ static int wdt_sample(int argc, char *argv[]) else { _wdt_cmd_print_usage(); - return -RT_ERROR; + ret = -RT_ERROR; } return ret; diff --git a/bsp/hc32/tools/sdk_dist.py b/bsp/hc32/tools/sdk_dist.py index 4bbeb459505..300e66ab528 100644 --- a/bsp/hc32/tools/sdk_dist.py +++ b/bsp/hc32/tools/sdk_dist.py @@ -13,8 +13,9 @@ def dist_do_building(BSP_ROOT, dist_dir): print("=> copy hc32 bsp library") library_dir = os.path.join(dist_dir, 'libraries') library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries') - bsp_copy_files(os.path.join(library_path, rtconfig.BSP_LIBRARY_TYPE), - os.path.join(library_dir, rtconfig.BSP_LIBRARY_TYPE)) + if rtconfig.BSP_LIBRARY_TYPE is not None: + bsp_copy_files(os.path.join(library_path, rtconfig.BSP_LIBRARY_TYPE), + os.path.join(library_dir, rtconfig.BSP_LIBRARY_TYPE)) print("=> copy bsp drivers") bsp_copy_files(os.path.join(library_path, 'hc32_drivers'), os.path.join(library_dir, 'hc32_drivers'))