From 516826b93a0ae32b7492430930a81ce3de368ed7 Mon Sep 17 00:00:00 2001 From: Rbb666 Date: Wed, 20 Aug 2025 18:13:15 +0800 Subject: [PATCH] [libcpu][cortex-m33]Added HardFault_Handler to save floating point registers --- libcpu/arm/cortex-m33/context_gcc.S | 6 ++++++ libcpu/arm/cortex-m33/context_iar.S | 7 +++++++ libcpu/arm/cortex-m33/context_rvds.S | 11 ++++++++--- 3 files changed, 21 insertions(+), 3 deletions(-) diff --git a/libcpu/arm/cortex-m33/context_gcc.S b/libcpu/arm/cortex-m33/context_gcc.S index adf162f2d3b..8b850cd1c00 100644 --- a/libcpu/arm/cortex-m33/context_gcc.S +++ b/libcpu/arm/cortex-m33/context_gcc.S @@ -281,6 +281,12 @@ HardFault_Handler: MRS r0, psp /* get fault context from thread. */ get_sp_done: +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + TST lr, #0x10 /* if(!EXC_RETURN[4]) */ + IT EQ + VSTMDBEQ r0!, {d8 - d15} /* push FPU register s16~s31 */ +#endif + STMFD r0!, {r4 - r11} /* push r4 - r11 register */ LDR r2, =rt_trustzone_current_context /* r2 = &rt_secure_current_context */ diff --git a/libcpu/arm/cortex-m33/context_iar.S b/libcpu/arm/cortex-m33/context_iar.S index c9c2ed671d5..404aa0b0535 100644 --- a/libcpu/arm/cortex-m33/context_iar.S +++ b/libcpu/arm/cortex-m33/context_iar.S @@ -275,6 +275,13 @@ HardFault_Handler: MRS r0, psp ; get fault context from thread. get_sp_done +#if defined ( __ARMVFP__ ) + TST lr, #0x10 ; if(!EXC_RETURN[4]) + BNE skip_push_fpu + VSTMDB r0!, {d8 - d15} ; push FPU register s16~s31 +skip_push_fpu +#endif + STMFD r0!, {r4 - r11} ; push r4 - r11 register LDR r2, =rt_trustzone_current_context ; r2 = &rt_secure_current_context diff --git a/libcpu/arm/cortex-m33/context_rvds.S b/libcpu/arm/cortex-m33/context_rvds.S index 5b527b537c1..d18ec18d8c3 100644 --- a/libcpu/arm/cortex-m33/context_rvds.S +++ b/libcpu/arm/cortex-m33/context_rvds.S @@ -272,12 +272,17 @@ rt_hw_interrupt_thread_switch PROC HardFault_Handler PROC ; get current context - MRS r0, msp ;get fault context from handler - TST lr, #0x04 ;if(!EXC_RETURN[2]) + MRS r0, msp ; get fault context from handler + TST lr, #0x04 ; if(!EXC_RETURN[2]) BEQ get_sp_done - MRS r0, psp ;get fault context from thread + MRS r0, psp ; get fault context from thread get_sp_done + IF {FPU} != "SoftVFP" + TST lr, #0x10 ; if(!EXC_RETURN[4]) + VSTMFDEQ r0!, {d8 - d15} ; push FPU register s16~s31 + ENDIF + STMFD r0!, {r4 - r11} ; push r4 - r11 register LDR r2, =rt_trustzone_current_context ; r2 = &rt_secure_current_context