From 4222d5f11e853d5d5df3e9761f014f7c178d6eb7 Mon Sep 17 00:00:00 2001 From: Yilin Sun Date: Tue, 26 Aug 2025 16:23:52 +0800 Subject: [PATCH 1/7] bsp/nxp/mcx/mcxe: Initial support for MCXE247. Signed-off-by: Yilin Sun --- bsp/nxp/mcx/mcxe/.clang-format | 242 +++ bsp/nxp/mcx/mcxe/Libraries/Kconfig | 6 + bsp/nxp/mcx/mcxe/Libraries/drivers/SConscript | 41 + bsp/nxp/mcx/mcxe/Libraries/drivers/drv_i2c.c | 169 ++ bsp/nxp/mcx/mcxe/Libraries/drivers/drv_pin.c | 213 +++ bsp/nxp/mcx/mcxe/Libraries/drivers/drv_pin.h | 22 + bsp/nxp/mcx/mcxe/Libraries/drivers/drv_uart.c | 222 +++ bsp/nxp/mcx/mcxe/Libraries/drivers/drv_uart.h | 17 + bsp/nxp/mcx/mcxe/frdm-mcxe247/.config | 1461 +++++++++++++++++ bsp/nxp/mcx/mcxe/frdm-mcxe247/Kconfig | 17 + bsp/nxp/mcx/mcxe/frdm-mcxe247/SConscript | 14 + bsp/nxp/mcx/mcxe/frdm-mcxe247/SConstruct | 83 + .../mcxe/frdm-mcxe247/applications/SConscript | 15 + .../mcx/mcxe/frdm-mcxe247/applications/main.c | 63 + bsp/nxp/mcx/mcxe/frdm-mcxe247/board/Kconfig | 163 ++ .../board/MCUX_Config/board/clock_config.c | 550 +++++++ .../board/MCUX_Config/board/clock_config.h | 326 ++++ .../board/MCUX_Config/board/pin_mux.c | 87 + .../board/MCUX_Config/board/pin_mux.h | 27 + .../mcx/mcxe/frdm-mcxe247/board/SConscript | 25 + bsp/nxp/mcx/mcxe/frdm-mcxe247/board/board.c | 104 ++ bsp/nxp/mcx/mcxe/frdm-mcxe247/board/board.h | 50 + .../board/linker_scripts/MCXE247_flash.ld | 229 +++ .../board/linker_scripts/MCXE247_flash.scf | 81 + bsp/nxp/mcx/mcxe/frdm-mcxe247/rtconfig.h | 437 +++++ bsp/nxp/mcx/mcxe/frdm-mcxe247/rtconfig.py | 198 +++ bsp/nxp/mcx/mcxe/frdm-mcxe247/template.uvoptx | 184 +++ .../mcx/mcxe/frdm-mcxe247/template.uvprojx | 401 +++++ 28 files changed, 5447 insertions(+) create mode 100644 bsp/nxp/mcx/mcxe/.clang-format create mode 100644 bsp/nxp/mcx/mcxe/Libraries/Kconfig create mode 100644 bsp/nxp/mcx/mcxe/Libraries/drivers/SConscript create mode 100644 bsp/nxp/mcx/mcxe/Libraries/drivers/drv_i2c.c create mode 100644 bsp/nxp/mcx/mcxe/Libraries/drivers/drv_pin.c create mode 100644 bsp/nxp/mcx/mcxe/Libraries/drivers/drv_pin.h create mode 100644 bsp/nxp/mcx/mcxe/Libraries/drivers/drv_uart.c create mode 100644 bsp/nxp/mcx/mcxe/Libraries/drivers/drv_uart.h create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/.config create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/Kconfig create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/SConscript create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/SConstruct create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/applications/SConscript create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/applications/main.c create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/board/Kconfig create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/clock_config.c create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/clock_config.h create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/pin_mux.c create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/pin_mux.h create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/board/SConscript create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/board/board.c create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/board/board.h create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/board/linker_scripts/MCXE247_flash.ld create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/board/linker_scripts/MCXE247_flash.scf create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/rtconfig.h create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/rtconfig.py create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/template.uvoptx create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/template.uvprojx diff --git a/bsp/nxp/mcx/mcxe/.clang-format b/bsp/nxp/mcx/mcxe/.clang-format new file mode 100644 index 00000000000..aa43aae1f3d --- /dev/null +++ b/bsp/nxp/mcx/mcxe/.clang-format @@ -0,0 +1,242 @@ +# Available style options are described in https://clang.llvm.org/docs/ClangFormatStyleOptions.html +# +# An easy way to create the .clang-format file is: +# +# clang-format -style=llvm -dump-config > .clang-format +# +--- +Language: Cpp +BasedOnStyle: LLVM +AccessModifierOffset: -1 +AlignAfterOpenBracket: Align +AlignArrayOfStructures: Right +AlignConsecutiveAssignments: + Enabled: true + AcrossEmptyLines: false + AcrossComments: false + AlignCompound: true + PadOperators: true +AlignConsecutiveBitFields: + Enabled: true + AcrossEmptyLines: false + AcrossComments: false + AlignCompound: true + PadOperators: true +AlignConsecutiveDeclarations: + Enabled: true + AcrossEmptyLines: false + AcrossComments: false + AlignCompound: false + PadOperators: false +AlignConsecutiveMacros: + Enabled: true + AcrossEmptyLines: false + AcrossComments: false + AlignCompound: false + PadOperators: false +AlignConsecutiveShortCaseStatements: + Enabled: false + AcrossEmptyLines: false + AcrossComments: false + AlignCaseColons: false +AlignEscapedNewlines: Left +AlignOperands: Align +AlignTrailingComments: + Kind: Always + OverEmptyLines: 1 +AllowAllArgumentsOnNextLine: false +AllowAllParametersOfDeclarationOnNextLine: false +AllowShortBlocksOnASingleLine: Always +AllowShortCaseLabelsOnASingleLine: false +AllowShortEnumsOnASingleLine: false +AllowShortFunctionsOnASingleLine: None +AllowShortIfStatementsOnASingleLine: WithoutElse +AllowShortLambdasOnASingleLine: All +AllowShortLoopsOnASingleLine: true +AlwaysBreakAfterDefinitionReturnType: None +AlwaysBreakAfterReturnType: None +AlwaysBreakBeforeMultilineStrings: false +AlwaysBreakTemplateDeclarations: MultiLine +AttributeMacros: + - __capability +BinPackArguments: true +BinPackParameters: true +BitFieldColonSpacing: Both +BraceWrapping: + AfterCaseLabel: false + AfterClass: true + AfterControlStatement: Always + AfterEnum: true + AfterExternBlock: false + AfterFunction: true + AfterNamespace: true + AfterObjCDeclaration: true + AfterStruct: true + AfterUnion: false + BeforeCatch: true + BeforeElse: true + BeforeLambdaBody: false + BeforeWhile: false + IndentBraces: false + SplitEmptyFunction: true + SplitEmptyRecord: true + SplitEmptyNamespace: true +BreakAfterAttributes: Never +BreakAfterJavaFieldAnnotations: false +BreakArrays: false +BreakBeforeBinaryOperators: NonAssignment +BreakBeforeConceptDeclarations: Always +BreakBeforeBraces: Custom +BreakBeforeInlineASMColon: OnlyMultiline +BreakBeforeTernaryOperators: true +BreakConstructorInitializers: AfterColon +BreakInheritanceList: AfterColon +BreakStringLiterals: true +ColumnLimit: 0 +CommentPragmas: "^ IWYU pragma:" +CompactNamespaces: false +ConstructorInitializerIndentWidth: 4 +ContinuationIndentWidth: 4 +Cpp11BracedListStyle: true +DerivePointerAlignment: false +DisableFormat: false +EmptyLineAfterAccessModifier: Never +EmptyLineBeforeAccessModifier: Always +ExperimentalAutoDetectBinPacking: false +FixNamespaceComments: true +ForEachMacros: + - foreach + - Q_FOREACH + - BOOST_FOREACH +IfMacros: + - KJ_IF_MAYBE +IncludeBlocks: Preserve +IncludeCategories: + - Regex: '^"(llvm|llvm-c|clang|clang-c)/' + Priority: 2 + SortPriority: 0 + CaseSensitive: false + - Regex: '^(<|"(gtest|gmock|isl|json)/)' + Priority: 3 + SortPriority: 0 + CaseSensitive: false + - Regex: ".*" + Priority: 1 + SortPriority: 0 + CaseSensitive: false +IncludeIsMainRegex: "(Test)?$" +IncludeIsMainSourceRegex: "" +IndentAccessModifiers: false +IndentCaseBlocks: false +IndentCaseLabels: false +IndentExternBlock: NoIndent +IndentGotoLabels: true +IndentPPDirectives: None +IndentRequiresClause: true +IndentWidth: 4 +IndentWrappedFunctionNames: false +InsertBraces: false +InsertNewlineAtEOF: true +InsertTrailingCommas: None +IntegerLiteralSeparator: + Binary: 0 + BinaryMinDigits: 0 + Decimal: 0 + DecimalMinDigits: 0 + Hex: 0 + HexMinDigits: 0 +JavaScriptQuotes: Leave +JavaScriptWrapImports: true +KeepEmptyLinesAtTheStartOfBlocks: false +KeepEmptyLinesAtEOF: true +LambdaBodyIndentation: Signature +LineEnding: DeriveLF +MacroBlockBegin: "" +MacroBlockEnd: "" +MaxEmptyLinesToKeep: 2 +NamespaceIndentation: None +ObjCBinPackProtocolList: Auto +ObjCBlockIndentWidth: 2 +ObjCBreakBeforeNestedBlockParam: true +ObjCSpaceAfterProperty: false +ObjCSpaceBeforeProtocolList: true +PackConstructorInitializers: BinPack +PenaltyBreakAssignment: 1000 +PenaltyBreakBeforeFirstCallParameter: 19 +PenaltyBreakComment: 300 +PenaltyBreakFirstLessLess: 120 +PenaltyBreakOpenParenthesis: 0 +PenaltyBreakString: 1000 +PenaltyBreakTemplateDeclaration: 10 +PenaltyExcessCharacter: 1000000 +PenaltyIndentedWhitespace: 0 +PenaltyReturnTypeOnItsOwnLine: 1000 +PointerAlignment: Right +PPIndentWidth: 4 +QualifierAlignment: Leave +ReferenceAlignment: Pointer +ReflowComments: false +RemoveBracesLLVM: false +RemoveParentheses: Leave +RemoveSemicolon: false +RequiresClausePosition: OwnLine +RequiresExpressionIndentation: OuterScope +SeparateDefinitionBlocks: Leave +ShortNamespaceLines: 1 +SortIncludes: Never +SortJavaStaticImport: Before +SortUsingDeclarations: LexicographicNumeric +SpaceAfterCStyleCast: false +SpaceAfterLogicalNot: false +SpaceAfterTemplateKeyword: true +SpaceAroundPointerQualifiers: Both +SpaceBeforeAssignmentOperators: true +SpaceBeforeCaseColon: false +SpaceBeforeCpp11BracedList: false +SpaceBeforeCtorInitializerColon: true +SpaceBeforeInheritanceColon: true +SpaceBeforeJsonColon: false +SpaceBeforeParens: ControlStatements +SpaceBeforeParensOptions: + AfterControlStatements: true + AfterForeachMacros: true + AfterFunctionDefinitionName: false + AfterFunctionDeclarationName: false + AfterIfMacros: true + AfterOverloadedOperator: false + AfterRequiresInClause: false + AfterRequiresInExpression: false + BeforeNonEmptyParentheses: false +SpaceBeforeRangeBasedForLoopColon: true +SpaceBeforeSquareBrackets: false +SpaceInEmptyBlock: false +SpacesBeforeTrailingComments: 1 +SpacesInAngles: Never +SpacesInContainerLiterals: true +SpacesInLineCommentPrefix: + Minimum: 1 + Maximum: -1 +SpacesInParens: Never +SpacesInParensOptions: + InCStyleCasts: false + InConditionalStatements: false + InEmptyParentheses: false + Other: false +SpacesInSquareBrackets: false +Standard: Latest +StatementAttributeLikeMacros: + - Q_EMIT +StatementMacros: + - Q_UNUSED + - QT_REQUIRE_VERSION +TabWidth: 4 +UseTab: Never +VerilogBreakBetweenInstancePorts: true +WhitespaceSensitiveMacros: + - BOOST_PP_STRINGIZE + - CF_SWIFT_NAME + - NS_SWIFT_NAME + - PP_STRINGIZE + - STRINGIZE +--- + diff --git a/bsp/nxp/mcx/mcxe/Libraries/Kconfig b/bsp/nxp/mcx/mcxe/Libraries/Kconfig new file mode 100644 index 00000000000..cb954255738 --- /dev/null +++ b/bsp/nxp/mcx/mcxe/Libraries/Kconfig @@ -0,0 +1,6 @@ +config SOC_MCX + bool + select ARCH_ARM_CORTEX_M4 + select ARCH_ARM_CORTEX_FPU + select PKG_USING_NXP_MCX_CMSIS_DRIVER + select PKG_USING_NXP_MCX_SERIES_DRIVER \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxe/Libraries/drivers/SConscript b/bsp/nxp/mcx/mcxe/Libraries/drivers/SConscript new file mode 100644 index 00000000000..9a9f0979d13 --- /dev/null +++ b/bsp/nxp/mcx/mcxe/Libraries/drivers/SConscript @@ -0,0 +1,41 @@ +from building import * + +cwd = GetCurrentDir() + +src = [] + +if GetDepend('BSP_USING_PIN'): + src += ['drv_pin.c'] + +if GetDepend('BSP_USING_UART'): + src += ['drv_uart.c'] + +if GetDepend('BSP_USING_RTC'): + src += ['drv_rtc.c'] + +if GetDepend('BSP_USING_SPI'): + src += ['drv_spi.c'] + +if GetDepend('BSP_USING_I2C'): + src += ['drv_i2c.c'] + +if GetDepend('BSP_USING_ADC'): + src += ['drv_adc.c'] + +if GetDepend('BSP_USING_HWTIMER'): + src += ['drv_hwtimer.c'] + +if GetDepend('BSP_USING_WDT'): + src += ['drv_wdt.c'] + +if GetDepend('BSP_USING_PWM'): + src += ['drv_pwm.c'] + +if GetDepend('BSP_USING_FLASH'): + src += ['drv_chipflash.c'] + +path = [cwd,cwd + '/config'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_i2c.c b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_i2c.c new file mode 100644 index 00000000000..bb6e68fc962 --- /dev/null +++ b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_i2c.c @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-08-21 hywing The first version + */ + +#include +#include "fsl_lpi2c.h" + +#ifdef RT_USING_I2C + +#define DBG_TAG "drv.i2c" +#define DBG_LVL DBG_INFO +#include + +enum +{ +#ifdef BSP_USING_I2C0 + I2C0_INDEX, +#endif +#ifdef BSP_USING_I2C1 + I2C1_INDEX, +#endif +}; + + +struct mcx_i2c_bus +{ + struct rt_i2c_bus_device i2c_bus; + LPI2C_Type *i2c_base; + uint32_t baud; + clock_ip_name_t clock_ip_name; + clock_ip_src_t clock_ip_src; + char *name; +}; + + +static struct mcx_i2c_bus i2c_buses[] = + { +#ifdef BSP_USING_I2C0 + { + .i2c_base = LPI2C0, + .baud = 100000U, + .clock_ip_name = kCLOCK_Lpi2c0, + .clock_ip_src = kCLOCK_IpSrcSysOscAsync, + .name = "i2c0", + }, +#endif +#ifdef BSP_USING_I2C1 + { + .i2c_base = LPI2C1, + .baud = 100000U, + .clock_ip_name = kCLOCK_Lpi2c1, + .clock_ip_src = kCLOCK_IpSrcSysOscAsync, + .name = "i2c1", + }, +#endif +}; + +static rt_ssize_t lpc_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) +{ + struct rt_i2c_msg *msg; + lpi2c_master_transfer_t xfer = {0}; + rt_uint32_t i; + rt_ssize_t ret = 0; + + struct mcx_i2c_bus *priv = (struct mcx_i2c_bus *)bus; + + for (i = 0; i < num; i++) + { + msg = &msgs[i]; + + if (msg->flags & RT_I2C_RD) + { + xfer.slaveAddress = msg->addr; + xfer.direction = kLPI2C_Read; + xfer.subaddress = 0; + xfer.subaddressSize = 0; + xfer.data = msg->buf; + xfer.dataSize = msg->len; + + xfer.flags = kLPI2C_TransferDefaultFlag; + + if (i != 0) + { + xfer.flags |= kLPI2C_TransferRepeatedStartFlag; + } + + if (i != num - 1) + { + xfer.flags |= kLPI2C_TransferNoStopFlag; + } + + if (LPI2C_MasterTransferBlocking(priv->i2c_base, &xfer) != kStatus_Success) + { + LOG_D("i2c bus read failed!\n"); + return i; + } + } + else + { + xfer.slaveAddress = msg->addr; + xfer.direction = kLPI2C_Write; + xfer.subaddress = 0; + xfer.subaddressSize = 0; + xfer.data = msg->buf; + xfer.dataSize = msg->len; + + xfer.flags = kLPI2C_TransferDefaultFlag; + + if (i != 0) + { + xfer.flags |= kLPI2C_TransferRepeatedStartFlag; + } + + if (i != num - 1) + { + xfer.flags |= kLPI2C_TransferNoStopFlag; + } + + if (LPI2C_MasterTransferBlocking(priv->i2c_base, &xfer) != kStatus_Success) + { + LOG_D("i2c bus write failed!\n"); + return i; + } + } + } + ret = i; + + return ret; +} + +static const struct rt_i2c_bus_device_ops i2c_ops = { + .master_xfer = lpc_i2c_xfer, + .slave_xfer = RT_NULL, + .i2c_bus_control = RT_NULL, +}; + +int rt_hw_i2c_init(void) +{ + int i; + lpi2c_master_config_t masterConfig; + + for (i = 0; i < ARRAY_SIZE(i2c_buses); i++) + { + struct mcx_i2c_bus *priv = &i2c_buses[i]; + CLOCK_SetIpSrc(i2c_buses[i].clock_ip_name, priv->clock_ip_src); + + LPI2C_MasterGetDefaultConfig(&masterConfig); + masterConfig.baudRate_Hz = priv->baud; + + LPI2C_MasterInit(priv->i2c_base, &masterConfig, CLOCK_GetIpFreq(priv->clock_ip_name)); + + priv->i2c_bus.ops = &i2c_ops; + + rt_i2c_bus_device_register(&priv->i2c_bus, priv->name); + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); + +#endif /* RT_USING_I2C */ + + diff --git a/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_pin.c b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_pin.c new file mode 100644 index 00000000000..3cb8fff1ea8 --- /dev/null +++ b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_pin.c @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-03-24 YangXi the first version. + */ + +#include "drv_pin.h" + +#include "fsl_common.h" +#include "fsl_gpio.h" +#include "fsl_port.h" + +#ifdef RT_USING_PIN + +#define DBG_TAG "drv.pin" +#define DBG_LVL DBG_INFO +#include + +#define GET_GPIO_PORT(x) ((x) / 32) +#define GET_GPIO_PIN(x) ((x) % 32) + +static struct rt_pin_ops mcx_pin_ops; + +static GPIO_Type *GPIO_TYPE_TBL[] = GPIO_BASE_PTRS; +static PORT_Type *PORT_TYPE_TBL[] = PORT_BASE_PTRS; +static IRQn_Type IRQ_TYPE_TBL[] = PORT_IRQS; + + +#define PIN2GPIO(x) GPIO_TYPE_TBL[GET_GPIO_PORT(x)] +#define PIN2PORT(x) PORT_TYPE_TBL[GET_GPIO_PORT(x)] +#define PIN2IRQ(x) IRQ_TYPE_TBL[GET_GPIO_PORT(x)] + +struct rt_pin_irq_hdr pin_irq_hdr_tab[32*5] = {0}; + +static void mcx_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) +{ + port_pin_config_t port_pin_config = {0}; + gpio_pin_config_t gpio_pin_config = {0}; + + port_pin_config.mux = kPORT_MuxAsGpio; + + switch (mode) + { + case PIN_MODE_OUTPUT: + case PIN_MODE_OUTPUT_OD: /* MCX E2 does not support OD. */ + { + gpio_pin_config.pinDirection = kGPIO_DigitalOutput; + port_pin_config.pullSelect = kPORT_PullDisable; + } + break; + + case PIN_MODE_INPUT: + { + gpio_pin_config.pinDirection = kGPIO_DigitalInput; + port_pin_config.pullSelect = kPORT_PullDisable; + } + break; + + case PIN_MODE_INPUT_PULLDOWN: + { + gpio_pin_config.pinDirection = kGPIO_DigitalInput; + port_pin_config.pullSelect = kPORT_PullDown; + } + break; + + case PIN_MODE_INPUT_PULLUP: + { + gpio_pin_config.pinDirection = kGPIO_DigitalInput; + port_pin_config.pullSelect = kPORT_PullUp; + } + break; + + default: + break; + } + + PORT_SetPinConfig(PIN2PORT(pin), GET_GPIO_PIN(pin), &port_pin_config); + GPIO_PinInit(PIN2GPIO(pin), GET_GPIO_PIN(pin) , &gpio_pin_config); +} + + +static void mcx_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) +{ + GPIO_PinWrite(PIN2GPIO(pin), GET_GPIO_PIN(pin), value); +} + +static rt_ssize_t mcx_pin_read(rt_device_t dev, rt_base_t pin) +{ + return GPIO_PinRead(PIN2GPIO(pin), GET_GPIO_PIN(pin)) ? 1 : 0; +} + + +rt_inline void pin_irq_handler(uint8_t gpio_idx) +{ + int i; + + rt_interrupt_enter(); + + uint32_t INTFLAG = PORT_GetPinsInterruptFlags(PORT_TYPE_TBL[gpio_idx]); + PORT_ClearPinsInterruptFlags(PORT_TYPE_TBL[gpio_idx], INTFLAG); + + + for(i=0; i +#include + + +extern int rt_hw_pin_init(void); + +#endif /* __DRV_PIN_H__ */ diff --git a/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_uart.c b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_uart.c new file mode 100644 index 00000000000..78da2374298 --- /dev/null +++ b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_uart.c @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 yandld The first version for MCX + * 2024-11-11 hywing add more UART channels + */ +#include +#include "drv_uart.h" +#include "fsl_lpuart.h" + +#ifdef RT_USING_SERIAL + +#define DBG_TAG "drv.uart" +#define DBG_LVL DBG_INFO +#include + +struct mcx_uart +{ + struct rt_serial_device *serial; + LPUART_Type *uart_base; + IRQn_Type irqn; + clock_ip_name_t clock_ip_name; + clock_ip_src_t clock_ip_src; + char *device_name; +}; + +static void uart_isr(struct rt_serial_device *serial); + +#if defined(BSP_USING_UART0) +struct rt_serial_device serial0; + +void LPUART0_IRQHandler(void) +{ + uart_isr(&serial0); +} +#endif +#if defined(BSP_USING_UART1) +struct rt_serial_device serial1; + +void LPUART1_IRQHandler(void) +{ + uart_isr(&serial1); +} +#endif +#if defined(BSP_USING_UART2) +struct rt_serial_device serial2; + +void LPUART2_IRQHandler(void) +{ + uart_isr(&serial2); +} +#endif + +static const struct mcx_uart uarts[] = + { +#ifdef BSP_USING_UART0 + { + .serial = &serial0, + .uart_base = LPUART0, + .irqn = LPUART0_IRQn, + .clock_ip_name = kCLOCK_Lpuart0, + .clock_ip_src = kCLOCK_IpSrcSysOscAsync, + .device_name = "uart0", + }, +#endif +#ifdef BSP_USING_UART1 + { + .serial = &serial1, + .uart_base = LPUART1, + .irqn = LPUART1_IRQn, + .clock_ip_name = kCLOCK_Lpuart1, + .clock_ip_src = kCLOCK_IpSrcSysOscAsync, + .device_name = "uart1", + }, +#endif +#ifdef BSP_USING_UART2 + { + .serial = &serial2, + .uart_base = LPUART2, + .irqn = LPUART2_IRQn, + .clock_ip_name = kCLOCK_Lpuart2, + .clock_ip_src = kCLOCK_IpSrcSysOscAsync, + .device_name = "uart2", + }, +#endif +}; + +static rt_err_t mcx_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct mcx_uart *uart; + lpuart_config_t config; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart = (struct mcx_uart *)serial->parent.user_data; + + CLOCK_SetIpSrc(uart->clock_ip_name, uart->clock_ip_src); + + LPUART_GetDefaultConfig(&config); + config.baudRate_Bps = cfg->baud_rate; + + switch (cfg->data_bits) + { + case DATA_BITS_7: + config.dataBitsCount = kLPUART_SevenDataBits; + break; + + default: + config.dataBitsCount = kLPUART_EightDataBits; + break; + } + + config.enableTx = true; + config.enableRx = true; + + LPUART_Init(uart->uart_base, &config, CLOCK_GetIpFreq(uart->clock_ip_name)); + + return RT_EOK; +} + +static rt_err_t mcx_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct mcx_uart *uart = (struct mcx_uart *)serial->parent.user_data; + + RT_ASSERT(uart != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + LPUART_DisableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable); + DisableIRQ(uart->irqn); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + LPUART_EnableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable); + EnableIRQ(uart->irqn); + break; + } + + return RT_EOK; +} + +static int mcx_putc(struct rt_serial_device *serial, char ch) +{ + struct mcx_uart *uart = (struct mcx_uart *)serial->parent.user_data; + + while (!(kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(uart->uart_base))); + LPUART_WriteByte(uart->uart_base, ch); + + return 1; +} + +static int mcx_getc(struct rt_serial_device *serial) +{ + struct mcx_uart *uart = (struct mcx_uart *)serial->parent.user_data; + + if (kLPUART_RxDataRegFullInterruptEnable & LPUART_GetStatusFlags(uart->uart_base)) + { + return LPUART_ReadByte(uart->uart_base); + } + else + { + return -1; + } +} + +/** + * Uart common interrupt process. This need add to uart ISR. + * + * @param serial serial device + */ +static void uart_isr(struct rt_serial_device *serial) +{ + struct mcx_uart *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = (struct mcx_uart *)serial->parent.user_data; + RT_ASSERT(uart != RT_NULL); + + /* enter interrupt */ + rt_interrupt_enter(); + + /* UART in mode Receiver -------------------------------------------------*/ + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static const struct rt_uart_ops mcx_uart_ops = + { + mcx_configure, + mcx_control, + mcx_putc, + mcx_getc, +}; + +int rt_hw_uart_init(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + int i; + + for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) + { + uarts[i].serial->ops = &mcx_uart_ops; + uarts[i].serial->config = config; + + /* register UART device */ + rt_hw_serial_register(uarts[i].serial, uarts[i].device_name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, (void *)&uarts[i]); + } + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); +#endif /*BSP_USING_SERIAL */ diff --git a/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_uart.h b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_uart.h new file mode 100644 index 00000000000..c5e214492db --- /dev/null +++ b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_uart.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 yandld The first version for MCX + */ + +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +extern int rt_hw_uart_init(void); + + +#endif /* __DRV_UART_H__ */ diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/.config b/bsp/nxp/mcx/mcxe/frdm-mcxe247/.config new file mode 100644 index 00000000000..fb0f4a06f3e --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/.config @@ -0,0 +1,1461 @@ +CONFIG_SOC_MCX=y + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options + +# CONFIG_RT_UTEST_TC_USING_KLIBC is not set +# end of klibc options + +CONFIG_RT_NAME_MAX=16 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" +CONFIG_RT_VER_NUM=0x50201 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_FPU=y +CONFIG_ARCH_ARM_CORTEX_M4=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V1=y +# CONFIG_RT_USING_DFS_V2 is not set +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_MQUEUE is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_SOFT_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +CONFIG_RT_USING_ADC=y +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_SOFT_SPI is not set +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +CONFIG_RT_USING_HWTIMER=y +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER=y +CONFIG_PKG_NXP_MCX_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/nxp/nxp-mcx-cmsis" +CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER_LATEST_VERSION=y +CONFIG_PKG_NXP_MCX_CMSIS_DRIVER_VER="latest" +CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER=y +CONFIG_PKG_NXP_MCX_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/nxp/nxp-mcx-series" +CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER_LATEST_VERSION=y +CONFIG_PKG_NXP_MCX_SERIES_DRIVER_VER="latest" +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +# +# Hardware Drivers Config +# +CONFIG_SOC_MCXE247=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_PIN=y +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART0 is not set +# CONFIG_BSP_USING_UART1 is not set +CONFIG_BSP_USING_UART2=y +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_HWTIMER is not set +# CONFIG_BSP_USING_PWM is not set +# end of On-chip Peripheral Drivers + +# +# Board extended module Drivers +# +# CONFIG_BSP_USING_RW007 is not set +# end of Board extended module Drivers +# end of Hardware Drivers Config diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/Kconfig b/bsp/nxp/mcx/mcxe/frdm-mcxe247/Kconfig new file mode 100644 index 00000000000..182cf41c4ae --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/Kconfig @@ -0,0 +1,17 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../../../.. + +PKGS_DIR := packages + +config SOC_MCX + bool + select ARCH_ARM_CORTEX_M4 + default y + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../Libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/SConscript b/bsp/nxp/mcx/mcxe/frdm-mcxe247/SConscript new file mode 100644 index 00000000000..c7ef7659ece --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/SConstruct b/bsp/nxp/mcx/mcxe/frdm-mcxe247/SConstruct new file mode 100644 index 00000000000..7df8f67c895 --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/SConstruct @@ -0,0 +1,83 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "nxp-mcx-cmsis-latest"), + os.path.join("packages", "nxp-mcx-series-latest"), + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +if rtconfig.PLATFORM == 'armcc': + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + # overwrite cflags, because cflags has '--C99' + CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES') +else: + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/Libraries'): + libraries_path_prefix = SDK_ROOT + '/Libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/Libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/applications/SConscript b/bsp/nxp/mcx/mcxe/frdm-mcxe247/applications/SConscript new file mode 100644 index 00000000000..f11833c8d8d --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/applications/SConscript @@ -0,0 +1,15 @@ +from building import * +import os + +cwd = GetCurrentDir() +CPPPATH = [cwd] +src = Glob('*.c') + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/applications/main.c b/bsp/nxp/mcx/mcxe/frdm-mcxe247/applications/main.c new file mode 100644 index 00000000000..ea25912026a --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/applications/main.c @@ -0,0 +1,63 @@ +/* +* Copyright (c) 2006-2024, RT-Thread Development Team + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-24 Magicoe first version + * 2020-01-10 Kevin/Karl Add PS demo + * 2020-09-21 supperthomas fix the main.c + * + */ + +#include +#include + +#include "drv_pin.h" + +#define LED_PIN ((2 * 32) + 13) /* PTC13, RGB LED RED */ +#define BTN_PIN ((2 * 32) + 10) /* PTC10, SW3 (User) */ + +static rt_bool_t s_led_state = RT_FALSE; /* Current LED state */ + +static void app_btn_irq_callback(void *args) +{ + RT_UNUSED(args); + + rt_kprintf("SW3 pressed\n"); +} + +int main(void) +{ + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + rt_pin_write(LED_PIN, PIN_LOW); + + rt_pin_mode(BTN_PIN, PIN_MODE_INPUT_PULLUP); + rt_pin_attach_irq(BTN_PIN, PIN_IRQ_MODE_FALLING, app_btn_irq_callback, RT_NULL); + rt_pin_irq_enable(BTN_PIN, PIN_IRQ_ENABLE); + +#if defined(__CC_ARM) + rt_kprintf("using armcc, version: %d\n", __ARMCC_VERSION); +#elif defined(__clang__) + rt_kprintf("using armclang, version: %d\n", __ARMCC_VERSION); +#elif defined(__ICCARM__) + rt_kprintf("using iccarm, version: %d\n", __VER__); +#elif defined(__GNUC__) + rt_kprintf("using gcc, version: %d.%d\n", __GNUC__, __GNUC_MINOR__); +#endif + + rt_kprintf("NXP MCXE247\r\n"); + + while (1) + { + /* Toggle LED state */ + s_led_state = !s_led_state; + rt_pin_write(LED_PIN, s_led_state ? PIN_HIGH : PIN_LOW); + + rt_thread_mdelay(500); /* Delay 500mS */ + } +} + +// end file diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/Kconfig b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/Kconfig new file mode 100644 index 00000000000..232ad035380 --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/Kconfig @@ -0,0 +1,163 @@ +menu "Hardware Drivers Config" + +config SOC_MCXE247 + bool + select SOC_MCXE247_SERIES + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + config BSP_USING_PIN + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + config BSP_USING_UART + bool "Enable UART" + select RT_USING_UART + default y + + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable LPUART0" + default n + + config BSP_USING_UART1 + bool "Enable LPUART1" + default n + + config BSP_USING_UART2 + bool "Enable LPUART2" + default y + + endif + + menuconfig BSP_USING_I2C + config BSP_USING_I2C + bool "Enable I2C" + select RT_USING_I2C + default y + + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable LPI2C0" + default n + + config BSP_USING_I2C1 + bool "Enable LPI2C1" + default y + endif + + menuconfig BSP_USING_SPI + config BSP_USING_SPI + bool "Enable SPI" + select RT_USING_SPI + default y + + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable LPSPI1" + default n + endif + + menuconfig BSP_USING_ADC + config BSP_USING_ADC + bool "Enable ADC Channel" + select RT_USING_ADC + default y + + if BSP_USING_ADC + config BSP_USING_ADC0_CH22 + bool "Enable ADC0 Channel22" + default n + + endif + + config BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default y + + config BSP_USING_WDT + bool "Enable WatchDog" + select RT_USING_WDT + default n + + menuconfig BSP_USING_HWTIMER + config BSP_USING_HWTIMER + bool "Enable Timer" + select RT_USING_HWTIMER + default y + + if BSP_USING_HWTIMER + config BSP_USING_CTIMER0 + bool "Enable CIMER0" + default y + + config BSP_USING_CTIMER1 + bool "Enable CIMER1" + default n + + config BSP_USING_CTIMER3 + bool "Enable CIMER3" + default n + + config BSP_USING_CTIMER4 + bool "Enable CIMER4" + default n + endif + + menuconfig BSP_USING_PWM + config BSP_USING_PWM + bool "Enable PWM" + select RT_USING_PWM + default n + + if BSP_USING_PWM + config BSP_USING_PWM0 + bool "Enable eFlex PWM0" + default n + config BSP_USING_PWM1 + bool "Enable eFlex PWM1" + default n + config BSP_USING_PWM2 + bool "Enable eFlex PWM2" + default n + endif +endmenu + + +menu "Board extended module Drivers" + menuconfig BSP_USING_RW007 + bool "Enable RW007" + default n + select BSP_USING_SPI + select BSP_USING_SPI1 + select PKG_USING_RW007 + select RT_USING_MEMPOOL + select RW007_NOT_USE_EXAMPLE_DRIVERS + + if BSP_USING_RW007 + config BOARD_RW007_SPI_BUS_NAME + string "RW007 BUS NAME" + default "spi1" + + config BOARD_RW007_CS_PIN + hex "CS pin index" + default 107 + + config BOARD_RW007_INT_BUSY_PIN + hex "INT/BUSY pin index" + default 109 + + config BOARD_RW007_RST_PIN + hex "RESET pin index" + default 131 + endif + + +endmenu + +endmenu diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/clock_config.c b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/clock_config.c new file mode 100644 index 00000000000..4925d7ba3b6 --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/clock_config.c @@ -0,0 +1,550 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source. + * Note: The clock could not be set when it is being used as system clock. + * In default out of reset, the CPU is clocked from FIRC(IRC48M), + * so before setting FIRC, change to use another avaliable clock source. + * + * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings. + * + * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode. + * Wait until the system clock source is changed to target source. + * + * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow + * corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode. + * Supported run mode and clock restrictions could be found in Reference Manual. + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v15.0 +processor: MCXE247 +package_id: MCXE247VLQ +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_smc.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define SIM_LPOCLKS_RTCCLKSEL_LPO32K_CLK 1U /*!< 32 kHz clock source select: LPO32K clock */ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : CLOCK_CONFIG_SetRtcClock + * Description : Selects RTC clock source. + * Param src : The selected clock source. + * + *END**************************************************************************/ +static void CLOCK_CONFIG_SetRtcClock(uint8_t src) +{ + uint32_t temp; + temp = SIM->LPOCLKS; + temp &= ~SIM_LPOCLKS_RTCCLKSEL_MASK; + temp |= SIM_LPOCLKS_RTCCLKSEL(src); + SIM->LPOCLKS = temp; +} + +/*FUNCTION********************************************************************** + * + * Function Name : CLOCK_CONFIG_FircSafeConfig + * Description : This function is used to safely configure FIRC clock. + * In default out of reset, the CPU is clocked from FIRC(IRC48M). + * Before setting FIRC, change to use SIRC as system clock, + * then configure FIRC. After FIRC is set, change back to use FIRC + * in case SIRC need to be configured. + * Param fircConfig : FIRC configuration. + * + *END**************************************************************************/ +static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig) +{ + scg_sys_clk_config_t curConfig; + const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable, + .div1 = kSCG_AsyncClkDisable, + .div2 = kSCG_AsyncClkDivBy2, + .range = kSCG_SircRangeHigh}; + scg_sys_clk_config_t sysClkSafeConfigSource = { + .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */ + .divBus = kSCG_SysClkDivBy1, /* Bus clock divider */ + .divCore = kSCG_SysClkDivBy1, /* Core clock divider */ + .src = kSCG_SysClkSrcSirc /* System clock source */ + }; + /* Init Sirc. */ + CLOCK_InitSirc(&scgSircConfig); + /* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */ + CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource); + /* Wait for clock source switch finished. */ + do + { + CLOCK_GetCurSysClkConfig(&curConfig); + } while (curConfig.src != sysClkSafeConfigSource.src); + + /* Init Firc. */ + CLOCK_InitFirc(fircConfig); + /* Change back to use FIRC as system clock source in order to configure SIRC if needed. */ + sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc; + CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource); + /* Wait for clock source switch finished. */ + do + { + CLOCK_GetCurSysClkConfig(&curConfig); + } while (curConfig.src != sysClkSafeConfigSource.src); +} + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: Bus_clock.outFreq, value: 48 MHz} +- {id: Core_clock.outFreq, value: 48 MHz} +- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz} +- {id: FIRCDIV2_CLK.outFreq, value: 48 MHz} +- {id: Flash_clock.outFreq, value: 24 MHz} +- {id: LPO1K_CLK.outFreq, value: 1 kHz} +- {id: LPO_CLK.outFreq, value: 128 kHz} +- {id: LPO_clock.outFreq, value: 128 kHz} +- {id: Prediv_system_clock.outFreq, value: 48 MHz} +- {id: RTC_CLK.outFreq, value: 32 kHz} +- {id: SIRCDIV1_CLK.outFreq, value: 8 MHz} +- {id: SIRCDIV2_CLK.outFreq, value: 4 MHz} +- {id: SIRC_CLK.outFreq, value: 8 MHz} +- {id: SOSCDIV1_CLK.outFreq, value: 8 MHz} +- {id: SOSCDIV2_CLK.outFreq, value: 8 MHz} +- {id: SOSC_CLK.outFreq, value: 8 MHz} +- {id: System_clock.outFreq, value: 48 MHz} +settings: +- {id: SCG.FIRCDIV1.scale, value: '1', locked: true} +- {id: SCG.FIRCDIV2.scale, value: '1', locked: true} +- {id: SCG.SIRCDIV1.scale, value: '1', locked: true} +- {id: SCG.SIRCDIV2.scale, value: '2', locked: true} +- {id: SCG.SOSCDIV1.scale, value: '1', locked: true} +- {id: SCG.SOSCDIV2.scale, value: '1', locked: true} +- {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower} +- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled} +- {id: SIM.RTCCLKSEL.sel, value: SIM.LPO32KCLK_DIV} +- {id: SIM_CLKDIV4_TRACEDIVEN_CFG, value: Disabled} +- {id: SIM_CLKDIV4_TRACEDIVEN_DIV_CFG, value: Disabled} +sources: +- {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN = + { + .divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */ + .divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */ + .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */ + .src = kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */ +}; +const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN = + { + .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */ + .enableMode = kSCG_SysOscEnable, /* Enable System OSC clock */ + .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */ + .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */ + .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */ + .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */ +}; +const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN = + { + .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower, /* Enable SIRC clock, Enable SIRC in low power mode */ + .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */ + .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */ + .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */ +}; +const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN = + { + .enableMode = kSCG_FircEnable, /* Enable FIRC clock */ + .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */ + .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */ + .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */ + .trimConfig = NULL, /* Disable trim */ +}; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN_InitClockModule(clock_module_t module) +{ + scg_sys_clk_config_t curConfig; + + switch (module) + { + case kClockModule_SOSC: + /* Init SOSC according to board configuration. */ + CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockRUN); + /* Set the XTAL0 frequency based on board settings. */ + CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockRUN.freq); + break; + case kClockModule_FIRC: + /* Init FIRC.*/ + CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN); + break; + case kClockModule_PowerMode: + /* The RUN power mode is set after reset - no initialization code is provided. */ + break; + case kClockModule_SIRC: + /* Init SIRC. */ + CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN); + break; + case kClockModule_SystemClkSrc: + /* Set SCG to FIRC mode. */ + CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN); + /* Wait for clock source switch finished. */ + do + { + CLOCK_GetCurSysClkConfig(&curConfig); + } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src); + break; + case kClockModule_SCG_CLKOUTSEL: + /* Set SCG CLKOUT selection. */ + CLOCK_SetClkOutSel(kClockClkoutSelFirc); + break; + case kClockModule_LPO: + /* Enable LPO (enabled by default after power on reset). */ + PMC->REGSC &= ~PMC_REGSC_LPODIS_MASK; + break; + case kClockModule_RTCClkOut: + /* Set RTC clock source. */ + CLOCK_CONFIG_SetRtcClock(SIM_LPOCLKS_RTCCLKSEL_LPO32K_CLK); + break; + default: + assert(false); + break; + } +} + +void BOARD_BootClockRUN(void) +{ + BOARD_BootClockRUN_InitClockModule(kClockModule_SOSC); + BOARD_BootClockRUN_InitClockModule(kClockModule_FIRC); + BOARD_BootClockRUN_InitClockModule(kClockModule_SIRC); + BOARD_BootClockRUN_InitClockModule(kClockModule_SystemClkSrc); + BOARD_BootClockRUN_InitClockModule(kClockModule_SCG_CLKOUTSEL); + BOARD_BootClockRUN_InitClockModule(kClockModule_RTCClkOut); + BOARD_BootClockRUN_InitClockModule(kClockModule_LPO); + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} + +/******************************************************************************* + ********************* Configuration BOARD_BootClockVLPR *********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockVLPR +outputs: +- {id: Bus_clock.outFreq, value: 4 MHz} +- {id: Core_clock.outFreq, value: 4 MHz} +- {id: Flash_clock.outFreq, value: 1 MHz} +- {id: LPO1K_CLK.outFreq, value: 1 kHz} +- {id: LPO_CLK.outFreq, value: 128 kHz} +- {id: LPO_clock.outFreq, value: 128 kHz} +- {id: Prediv_system_clock.outFreq, value: 8 MHz} +- {id: RTC_CLK.outFreq, value: 32 kHz} +- {id: SIRCDIV1_CLK.outFreq, value: 4 MHz} +- {id: SIRCDIV2_CLK.outFreq, value: 4 MHz} +- {id: SIRC_CLK.outFreq, value: 8 MHz} +- {id: System_clock.outFreq, value: 4 MHz} +settings: +- {id: SCGMode, value: SIRC} +- {id: powerMode, value: VLPR} +- {id: SCG.DIVBUS.scale, value: '1', locked: true} +- {id: SCG.DIVCORE.scale, value: '2', locked: true} +- {id: SCG.DIVSLOW.scale, value: '4', locked: true} +- {id: SCG.SCSSEL.sel, value: SCG.SIRC} +- {id: SCG.SIRCDIV1.scale, value: '2', locked: true} +- {id: SCG.SIRCDIV2.scale, value: '2', locked: true} +- {id: SIM.RTCCLKSEL.sel, value: SIM.LPO32KCLK_DIV} +- {id: SIM_CLKDIV4_TRACEDIVEN_CFG, value: Disabled} +- {id: SIM_CLKDIV4_TRACEDIVEN_DIV_CFG, value: Disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockVLPR configuration + ******************************************************************************/ +const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR = + { + .divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */ + .divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */ + .divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */ + .src = kSCG_SysClkSrcSirc, /* Slow IRC is selected as System Clock Source */ +}; +const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR = + { + .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower, /* Enable SIRC clock, Enable SIRC in low power mode */ + .div1 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 1: divided by 2 */ + .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */ + .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */ +}; +/******************************************************************************* + * Code for BOARD_BootClockVLPR configuration + ******************************************************************************/ +void BOARD_BootClockVLPR_InitClockModule(clock_module_t module) +{ + scg_sys_clk_config_t curConfig; + + switch (module) + { + case kClockModule_PowerMode: + /* Allow SMC all power modes. */ + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); + /* Set VLPR power mode. */ + SMC_SetPowerModeVlpr(SMC); + while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr) + { + } + break; + case kClockModule_SIRC: + /* Init SIRC. */ + CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockVLPR); + break; + case kClockModule_SystemClkSrc: + /* Set SCG to SIRC mode. */ + CLOCK_SetVlprModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockVLPR); + /* Wait for clock source switch finished. */ + do + { + CLOCK_GetCurSysClkConfig(&curConfig); + } while (curConfig.src != g_sysClkConfig_BOARD_BootClockVLPR.src); + break; + case kClockModule_LPO: + /* Enable LPO (enabled by default after power on reset). */ + PMC->REGSC &= ~PMC_REGSC_LPODIS_MASK; + break; + case kClockModule_RTCClkOut: + /* Set RTC clock source. */ + CLOCK_CONFIG_SetRtcClock(SIM_LPOCLKS_RTCCLKSEL_LPO32K_CLK); + break; + default: + assert(false); + break; + } +} + +void BOARD_BootClockVLPR(void) +{ + BOARD_BootClockVLPR_InitClockModule(kClockModule_SIRC); + BOARD_BootClockVLPR_InitClockModule(kClockModule_PowerMode); + BOARD_BootClockVLPR_InitClockModule(kClockModule_SystemClkSrc); + BOARD_BootClockVLPR_InitClockModule(kClockModule_RTCClkOut); + BOARD_BootClockVLPR_InitClockModule(kClockModule_LPO); + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK; +} + +/******************************************************************************* + ********************* Configuration BOARD_BootClockHSRUN ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockHSRUN +outputs: +- {id: Bus_clock.outFreq, value: 56 MHz} +- {id: Core_clock.outFreq, value: 112 MHz} +- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz} +- {id: FIRCDIV2_CLK.outFreq, value: 48 MHz} +- {id: Flash_clock.outFreq, value: 28 MHz} +- {id: LPO1K_CLK.outFreq, value: 1 kHz} +- {id: LPO_CLK.outFreq, value: 128 kHz} +- {id: LPO_clock.outFreq, value: 128 kHz} +- {id: PLLDIV1_CLK.outFreq, value: 112 MHz} +- {id: PLLDIV2_CLK.outFreq, value: 56 MHz} +- {id: Prediv_system_clock.outFreq, value: 112 MHz} +- {id: RTC_CLK.outFreq, value: 32 kHz} +- {id: SIRCDIV1_CLK.outFreq, value: 8 MHz} +- {id: SIRCDIV2_CLK.outFreq, value: 8 MHz} +- {id: SIRC_CLK.outFreq, value: 8 MHz} +- {id: SOSCDIV1_CLK.outFreq, value: 8 MHz} +- {id: SOSCDIV2_CLK.outFreq, value: 8 MHz} +- {id: SOSC_CLK.outFreq, value: 8 MHz} +- {id: System_clock.outFreq, value: 112 MHz} +settings: +- {id: SCGMode, value: SPLL} +- {id: powerMode, value: HSRUN} +- {id: SCG.DIVBUS.scale, value: '2', locked: true} +- {id: SCG.DIVCORE.scale, value: '1', locked: true} +- {id: SCG.DIVSLOW.scale, value: '4', locked: true} +- {id: SCG.FIRCDIV1.scale, value: '1', locked: true} +- {id: SCG.FIRCDIV2.scale, value: '1', locked: true} +- {id: SCG.PREDIV.scale, value: '1', locked: true} +- {id: SCG.SCSSEL.sel, value: SCG.SPLL_DIV2_CLK} +- {id: SCG.SIRCDIV1.scale, value: '1', locked: true} +- {id: SCG.SIRCDIV2.scale, value: '1', locked: true} +- {id: SCG.SOSCDIV1.scale, value: '1', locked: true} +- {id: SCG.SOSCDIV2.scale, value: '1', locked: true} +- {id: SCG.SPLLDIV1.scale, value: '1', locked: true} +- {id: SCG.SPLLDIV2.scale, value: '2', locked: true} +- {id: SCG.SPLL_mul.scale, value: '28', locked: true} +- {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower} +- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled} +- {id: SCG_SPLLCSR_SPLLEN_CFG, value: Enabled} +- {id: SIM.RTCCLKSEL.sel, value: SIM.LPO32KCLK_DIV} +- {id: SIM_CLKDIV4_TRACEDIVEN_CFG, value: Disabled} +- {id: SIM_CLKDIV4_TRACEDIVEN_DIV_CFG, value: Disabled} +sources: +- {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockHSRUN configuration + ******************************************************************************/ +const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN = + { + .divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */ + .divBus = kSCG_SysClkDivBy2, /* Bus Clock Divider: divided by 2 */ + .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */ + .src = kSCG_SysClkSrcSysPll, /* System PLL is selected as System Clock Source */ +}; +const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN = + { + .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */ + .enableMode = kSCG_SysOscEnable, /* Enable System OSC clock */ + .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */ + .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */ + .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */ + .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */ +}; +const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN = + { + .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower, /* Enable SIRC clock, Enable SIRC in low power mode */ + .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */ + .div2 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 2: divided by 1 */ + .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */ +}; +const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN = + { + .enableMode = kSCG_FircEnable, /* Enable FIRC clock */ + .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */ + .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */ + .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */ + .trimConfig = NULL, /* Disable trim */ +}; +const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockHSRUN = + { + .enableMode = kSCG_SysPllEnable, /* Enable SPLL clock */ + .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */ + .div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */ + .div2 = kSCG_AsyncClkDivBy2, /* System PLL Clock Divider 2: divided by 2 */ + .prediv = 0, /* Divided by 1 */ + .mult = 12, /* Multiply Factor is 28 */ +}; +/******************************************************************************* + * Code for BOARD_BootClockHSRUN configuration + ******************************************************************************/ +void BOARD_BootClockHSRUN_InitClockModule(clock_module_t module) +{ + scg_sys_clk_config_t curConfig; + + switch (module) + { + case kClockModule_SOSC: + /* Init SOSC according to board configuration. */ + CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockHSRUN); + /* Set the XTAL0 frequency based on board settings. */ + CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockHSRUN.freq); + break; + case kClockModule_FIRC: + /* Init FIRC.*/ + CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN); + break; + case kClockModule_PowerMode: + /* Set HSRUN power mode. */ + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); + SMC_SetPowerModeHsrun(SMC); + while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun) + { + } + + break; + case kClockModule_SIRC: + /* Init SIRC. */ + CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN); + break; + case kClockModule_SPLL: + /* Init SysPll. */ + CLOCK_InitSysPll(&g_scgSysPllConfig_BOARD_BootClockHSRUN); + break; + case kClockModule_SystemClkSrc: + /* Set SCG to SPLL mode. */ + CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN); + /* Wait for clock source switch finished. */ + do + { + CLOCK_GetCurSysClkConfig(&curConfig); + } while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src); + break; + case kClockModule_SCG_CLKOUTSEL: + /* Set SCG CLKOUT selection. */ + CLOCK_SetClkOutSel(kClockClkoutSelFirc); + break; + case kClockModule_LPO: + /* Enable LPO (enabled by default after power on reset). */ + PMC->REGSC &= ~PMC_REGSC_LPODIS_MASK; + break; + case kClockModule_RTCClkOut: + /* Set RTC clock source. */ + CLOCK_CONFIG_SetRtcClock(SIM_LPOCLKS_RTCCLKSEL_LPO32K_CLK); + break; + default: + assert(false); + break; + } +} + +void BOARD_BootClockHSRUN(void) +{ + BOARD_BootClockHSRUN_InitClockModule(kClockModule_SOSC); + BOARD_BootClockHSRUN_InitClockModule(kClockModule_FIRC); + BOARD_BootClockHSRUN_InitClockModule(kClockModule_SIRC); + BOARD_BootClockHSRUN_InitClockModule(kClockModule_PowerMode); + BOARD_BootClockHSRUN_InitClockModule(kClockModule_SPLL); + BOARD_BootClockHSRUN_InitClockModule(kClockModule_SystemClkSrc); + BOARD_BootClockHSRUN_InitClockModule(kClockModule_SCG_CLKOUTSEL); + BOARD_BootClockHSRUN_InitClockModule(kClockModule_RTCClkOut); + BOARD_BootClockHSRUN_InitClockModule(kClockModule_LPO); + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK; +} diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/clock_config.h b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/clock_config.h new file mode 100644 index 00000000000..c82e6baafb9 --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/clock_config.h @@ -0,0 +1,326 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +typedef enum +{ + kClockModule_SOSC, + kClockModule_FIRC, + kClockModule_SIRC, + kClockModule_PowerMode, + kClockModule_SPLL, + kClockModule_SystemClkSrc, + kClockModule_SCG_CLKOUTSEL, + kClockModule_SIM_CLKOUTSEL, + kClockModule_LPOClkOut, + kClockModule_RTCClkOut, + kClockModule_TRACEClkOut, + kClockModule_RMIIClkOut, + kClockModule_PCC_FTM3, + kClockModule_PCC_ADC1, + kClockModule_PCC_LPSPI0, + kClockModule_PCC_LPSPI1, + kClockModule_PCC_LPSPI2, + kClockModule_PCC_LPIT, + kClockModule_PCC_FTM0, + kClockModule_PCC_FTM1, + kClockModule_PCC_FTM2, + kClockModule_PCC_ADC0, + kClockModule_PCC_LPTMR0, + kClockModule_PCC_FlexIO, + kClockModule_PCC_LPI2C0, + kClockModule_PCC_LPI2C1, + kClockModule_PCC_LPUART0, + kClockModule_PCC_LPUART1, + kClockModule_PCC_LPUART2, + kClockModule_PCC_FTM4, + kClockModule_PCC_FTM5, + kClockModule_PCC_FTM6, + kClockModule_PCC_FTM7, + kClockModule_PCC_ENET, + kClockModule_LPO, + kClockModule_QSPIClkSrc, +} clock_module_t; + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 8000000U /*!< Board xtal0 frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_BUS_CLOCK 48000000UL /* Clock consumers of Bus_clock output : ADC0, ADC1, CMP0, CRC, ENET, EWM, FLEXIO, I2S0, I2S1, LPI2C0, LPI2C1, LPIT0, LPSPI0, LPSPI1, LPSPI2, LPTMR0, LPUART0, LPUART1, LPUART2, PORTA, PORTB, PORTC, PORTD, PORTE, QuadSPI, RCM, RTC, WDOG */ +#define BOARD_BOOTCLOCKRUN_CLKOUT 0UL /* Clock consumers of CLKOUT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000UL /* Clock consumers of Core_clock output : N/A */ +#define BOARD_BOOTCLOCKRUN_FIRCDIV1_CLK 48000000UL /* Clock consumers of FIRCDIV1_CLK output : QuadSPI */ +#define BOARD_BOOTCLOCKRUN_FIRCDIV2_CLK 48000000UL /* Clock consumers of FIRCDIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_FLASH_CLOCK 24000000UL /* Clock consumers of Flash_clock output : FTFC */ +#define BOARD_BOOTCLOCKRUN_LPO1K_CLK 1000UL /* Clock consumers of LPO1K_CLK output : LPTMR0, RTC */ +#define BOARD_BOOTCLOCKRUN_LPO_CLK 128000UL /* Clock consumers of LPO_CLK output : WDOG */ +#define BOARD_BOOTCLOCKRUN_LPO_CLOCK 128000UL /* Clock consumers of LPO_clock output : EWM, PORTA, PORTB, PORTC, PORTD, PORTE, RCM */ +#define BOARD_BOOTCLOCKRUN_PCC_ADC0_CLK 0UL /* Clock consumers of PCC.PCC_ADC0_CLK output : ADC0 */ +#define BOARD_BOOTCLOCKRUN_PCC_ADC1_CLK 0UL /* Clock consumers of PCC.PCC_ADC1_CLK output : ADC1 */ +#define BOARD_BOOTCLOCKRUN_PCC_ENET_CLK 0UL /* Clock consumers of PCC.PCC_ENET_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_PCC_FTM0_CLK 0UL /* Clock consumers of PCC.PCC_FTM0_CLK output : FTM0 */ +#define BOARD_BOOTCLOCKRUN_PCC_FTM1_CLK 0UL /* Clock consumers of PCC.PCC_FTM1_CLK output : FTM1 */ +#define BOARD_BOOTCLOCKRUN_PCC_FTM2_CLK 0UL /* Clock consumers of PCC.PCC_FTM2_CLK output : FTM2 */ +#define BOARD_BOOTCLOCKRUN_PCC_FTM3_CLK 0UL /* Clock consumers of PCC.PCC_FTM3_CLK output : FTM3 */ +#define BOARD_BOOTCLOCKRUN_PCC_FTM4_CLK 0UL /* Clock consumers of PCC.PCC_FTM4_CLK output : FTM4 */ +#define BOARD_BOOTCLOCKRUN_PCC_FTM5_CLK 0UL /* Clock consumers of PCC.PCC_FTM5_CLK output : FTM5 */ +#define BOARD_BOOTCLOCKRUN_PCC_FTM6_CLK 0UL /* Clock consumers of PCC.PCC_FTM6_CLK output : FTM6 */ +#define BOARD_BOOTCLOCKRUN_PCC_FTM7_CLK 0UL /* Clock consumers of PCC.PCC_FTM7_CLK output : FTM7 */ +#define BOARD_BOOTCLOCKRUN_PCC_FLEXIO_CLK 0UL /* Clock consumers of PCC.PCC_FlexIO_CLK output : FLEXIO */ +#define BOARD_BOOTCLOCKRUN_PCC_LPI2C0_CLK 0UL /* Clock consumers of PCC.PCC_LPI2C0_CLK output : LPI2C0 */ +#define BOARD_BOOTCLOCKRUN_PCC_LPI2C1_CLK 0UL /* Clock consumers of PCC.PCC_LPI2C1_CLK output : LPI2C1 */ +#define BOARD_BOOTCLOCKRUN_PCC_LPIT_CLK 0UL /* Clock consumers of PCC.PCC_LPIT_CLK output : LPIT0 */ +#define BOARD_BOOTCLOCKRUN_PCC_LPSPI0_CLK 0UL /* Clock consumers of PCC.PCC_LPSPI0_CLK output : LPSPI0 */ +#define BOARD_BOOTCLOCKRUN_PCC_LPSPI1_CLK 0UL /* Clock consumers of PCC.PCC_LPSPI1_CLK output : LPSPI1 */ +#define BOARD_BOOTCLOCKRUN_PCC_LPSPI2_CLK 0UL /* Clock consumers of PCC.PCC_LPSPI2_CLK output : LPSPI2 */ +#define BOARD_BOOTCLOCKRUN_PCC_LPTMR0_CLK 0UL /* Clock consumers of PCC.PCC_LPTMR0_CLK output : LPTMR0 */ +#define BOARD_BOOTCLOCKRUN_PCC_LPUART0_CLK 0UL /* Clock consumers of PCC.PCC_LPUART0_CLK output : LPUART0 */ +#define BOARD_BOOTCLOCKRUN_PCC_LPUART1_CLK 0UL /* Clock consumers of PCC.PCC_LPUART1_CLK output : LPUART1 */ +#define BOARD_BOOTCLOCKRUN_PCC_LPUART2_CLK 0UL /* Clock consumers of PCC.PCC_LPUART2_CLK output : LPUART2 */ +#define BOARD_BOOTCLOCKRUN_PLLDIV1_CLK 0UL /* Clock consumers of PLLDIV1_CLK output : QuadSPI */ +#define BOARD_BOOTCLOCKRUN_PLLDIV2_CLK 0UL /* Clock consumers of PLLDIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PREDIV_SYSTEM_CLOCK 48000000UL /* Clock consumers of Prediv_system_clock output : QuadSPI */ +#define BOARD_BOOTCLOCKRUN_RMIICLK 0UL /* Clock consumers of RMIICLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_RTC_CLK 32000UL /* Clock consumers of RTC_CLK output : FTM0, FTM1, FTM2, FTM3, FTM4, FTM5, FTM6, FTM7, LPTMR0, RTC */ +#define BOARD_BOOTCLOCKRUN_SIRCDIV1_CLK 8000000UL /* Clock consumers of SIRCDIV1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SIRCDIV2_CLK 4000000UL /* Clock consumers of SIRCDIV2_CLK output : LPTMR0 */ +#define BOARD_BOOTCLOCKRUN_SIRC_CLK 8000000UL /* Clock consumers of SIRC_CLK output : WDOG */ +#define BOARD_BOOTCLOCKRUN_SOSCDIV1_CLK 8000000UL /* Clock consumers of SOSCDIV1_CLK output : I2S0, I2S1 */ +#define BOARD_BOOTCLOCKRUN_SOSCDIV2_CLK 8000000UL /* Clock consumers of SOSCDIV2_CLK output : CAN0, CAN1, CAN2 */ +#define BOARD_BOOTCLOCKRUN_SOSC_CLK 8000000UL /* Clock consumers of SOSC_CLK output : WDOG */ +#define BOARD_BOOTCLOCKRUN_SYSTEM_CLOCK 48000000UL /* Clock consumers of System_clock output : CAN0, CAN1, CAN2, DMA0, ENET, FTM0, FTM1, FTM2, FTM3, FTM4, FTM5, FTM6, FTM7, PDB0, PDB1, QuadSPI */ +#define BOARD_BOOTCLOCKRUN_TRACECLKIN 0UL /* Clock consumers of TRACECLKIN output : N/A */ + +/*! @brief SCG set for BOARD_BootClockRUN configuration. + */ +extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN; +/*! @brief System OSC set for BOARD_BootClockRUN configuration. + */ +extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN; +/*! @brief SIRC set for BOARD_BootClockRUN configuration. + */ +extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN; +/*! @brief FIRC set for BOARD_BootClockRUN configuration. + */ +extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************* Configuration BOARD_BootClockVLPR *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockVLPR configuration + ******************************************************************************/ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKVLPR_BUS_CLOCK 4000000UL /* Clock consumers of Bus_clock output : ADC0, ADC1, CMP0, CRC, ENET, EWM, FLEXIO, I2S0, I2S1, LPI2C0, LPI2C1, LPIT0, LPSPI0, LPSPI1, LPSPI2, LPTMR0, LPUART0, LPUART1, LPUART2, PORTA, PORTB, PORTC, PORTD, PORTE, QuadSPI, RCM, RTC, WDOG */ +#define BOARD_BOOTCLOCKVLPR_CLKOUT 0UL /* Clock consumers of CLKOUT output : N/A */ +#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 4000000UL /* Clock consumers of Core_clock output : N/A */ +#define BOARD_BOOTCLOCKVLPR_FIRCDIV1_CLK 0UL /* Clock consumers of FIRCDIV1_CLK output : QuadSPI */ +#define BOARD_BOOTCLOCKVLPR_FIRCDIV2_CLK 0UL /* Clock consumers of FIRCDIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKVLPR_FLASH_CLOCK 1000000UL /* Clock consumers of Flash_clock output : FTFC */ +#define BOARD_BOOTCLOCKVLPR_LPO1K_CLK 1000UL /* Clock consumers of LPO1K_CLK output : LPTMR0, RTC */ +#define BOARD_BOOTCLOCKVLPR_LPO_CLK 128000UL /* Clock consumers of LPO_CLK output : WDOG */ +#define BOARD_BOOTCLOCKVLPR_LPO_CLOCK 128000UL /* Clock consumers of LPO_clock output : EWM, PORTA, PORTB, PORTC, PORTD, PORTE, RCM */ +#define BOARD_BOOTCLOCKVLPR_PCC_ADC0_CLK 0UL /* Clock consumers of PCC.PCC_ADC0_CLK output : ADC0 */ +#define BOARD_BOOTCLOCKVLPR_PCC_ADC1_CLK 0UL /* Clock consumers of PCC.PCC_ADC1_CLK output : ADC1 */ +#define BOARD_BOOTCLOCKVLPR_PCC_ENET_CLK 0UL /* Clock consumers of PCC.PCC_ENET_CLK output : ENET */ +#define BOARD_BOOTCLOCKVLPR_PCC_FTM0_CLK 0UL /* Clock consumers of PCC.PCC_FTM0_CLK output : FTM0 */ +#define BOARD_BOOTCLOCKVLPR_PCC_FTM1_CLK 0UL /* Clock consumers of PCC.PCC_FTM1_CLK output : FTM1 */ +#define BOARD_BOOTCLOCKVLPR_PCC_FTM2_CLK 0UL /* Clock consumers of PCC.PCC_FTM2_CLK output : FTM2 */ +#define BOARD_BOOTCLOCKVLPR_PCC_FTM3_CLK 0UL /* Clock consumers of PCC.PCC_FTM3_CLK output : FTM3 */ +#define BOARD_BOOTCLOCKVLPR_PCC_FTM4_CLK 0UL /* Clock consumers of PCC.PCC_FTM4_CLK output : FTM4 */ +#define BOARD_BOOTCLOCKVLPR_PCC_FTM5_CLK 0UL /* Clock consumers of PCC.PCC_FTM5_CLK output : FTM5 */ +#define BOARD_BOOTCLOCKVLPR_PCC_FTM6_CLK 0UL /* Clock consumers of PCC.PCC_FTM6_CLK output : FTM6 */ +#define BOARD_BOOTCLOCKVLPR_PCC_FTM7_CLK 0UL /* Clock consumers of PCC.PCC_FTM7_CLK output : FTM7 */ +#define BOARD_BOOTCLOCKVLPR_PCC_FLEXIO_CLK 0UL /* Clock consumers of PCC.PCC_FlexIO_CLK output : FLEXIO */ +#define BOARD_BOOTCLOCKVLPR_PCC_LPI2C0_CLK 0UL /* Clock consumers of PCC.PCC_LPI2C0_CLK output : LPI2C0 */ +#define BOARD_BOOTCLOCKVLPR_PCC_LPI2C1_CLK 0UL /* Clock consumers of PCC.PCC_LPI2C1_CLK output : LPI2C1 */ +#define BOARD_BOOTCLOCKVLPR_PCC_LPIT_CLK 0UL /* Clock consumers of PCC.PCC_LPIT_CLK output : LPIT0 */ +#define BOARD_BOOTCLOCKVLPR_PCC_LPSPI0_CLK 0UL /* Clock consumers of PCC.PCC_LPSPI0_CLK output : LPSPI0 */ +#define BOARD_BOOTCLOCKVLPR_PCC_LPSPI1_CLK 0UL /* Clock consumers of PCC.PCC_LPSPI1_CLK output : LPSPI1 */ +#define BOARD_BOOTCLOCKVLPR_PCC_LPSPI2_CLK 0UL /* Clock consumers of PCC.PCC_LPSPI2_CLK output : LPSPI2 */ +#define BOARD_BOOTCLOCKVLPR_PCC_LPTMR0_CLK 0UL /* Clock consumers of PCC.PCC_LPTMR0_CLK output : LPTMR0 */ +#define BOARD_BOOTCLOCKVLPR_PCC_LPUART0_CLK 0UL /* Clock consumers of PCC.PCC_LPUART0_CLK output : LPUART0 */ +#define BOARD_BOOTCLOCKVLPR_PCC_LPUART1_CLK 0UL /* Clock consumers of PCC.PCC_LPUART1_CLK output : LPUART1 */ +#define BOARD_BOOTCLOCKVLPR_PCC_LPUART2_CLK 0UL /* Clock consumers of PCC.PCC_LPUART2_CLK output : LPUART2 */ +#define BOARD_BOOTCLOCKVLPR_PLLDIV1_CLK 0UL /* Clock consumers of PLLDIV1_CLK output : QuadSPI */ +#define BOARD_BOOTCLOCKVLPR_PLLDIV2_CLK 0UL /* Clock consumers of PLLDIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKVLPR_PREDIV_SYSTEM_CLOCK 8000000UL /* Clock consumers of Prediv_system_clock output : QuadSPI */ +#define BOARD_BOOTCLOCKVLPR_RMIICLK 0UL /* Clock consumers of RMIICLK output : ENET */ +#define BOARD_BOOTCLOCKVLPR_RTC_CLK 32000UL /* Clock consumers of RTC_CLK output : FTM0, FTM1, FTM2, FTM3, FTM4, FTM5, FTM6, FTM7, LPTMR0, RTC */ +#define BOARD_BOOTCLOCKVLPR_SIRCDIV1_CLK 4000000UL /* Clock consumers of SIRCDIV1_CLK output : N/A */ +#define BOARD_BOOTCLOCKVLPR_SIRCDIV2_CLK 4000000UL /* Clock consumers of SIRCDIV2_CLK output : LPTMR0 */ +#define BOARD_BOOTCLOCKVLPR_SIRC_CLK 8000000UL /* Clock consumers of SIRC_CLK output : WDOG */ +#define BOARD_BOOTCLOCKVLPR_SOSCDIV1_CLK 0UL /* Clock consumers of SOSCDIV1_CLK output : I2S0, I2S1 */ +#define BOARD_BOOTCLOCKVLPR_SOSCDIV2_CLK 0UL /* Clock consumers of SOSCDIV2_CLK output : CAN0, CAN1, CAN2 */ +#define BOARD_BOOTCLOCKVLPR_SOSC_CLK 0UL /* Clock consumers of SOSC_CLK output : WDOG */ +#define BOARD_BOOTCLOCKVLPR_SYSTEM_CLOCK 4000000UL /* Clock consumers of System_clock output : CAN0, CAN1, CAN2, DMA0, ENET, FTM0, FTM1, FTM2, FTM3, FTM4, FTM5, FTM6, FTM7, PDB0, PDB1, QuadSPI */ +#define BOARD_BOOTCLOCKVLPR_TRACECLKIN 0UL /* Clock consumers of TRACECLKIN output : N/A */ + +/*! @brief SCG set for BOARD_BootClockVLPR configuration. + */ +extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR; +/*! @brief SIRC set for BOARD_BootClockVLPR configuration. + */ +extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR; + +/******************************************************************************* + * API for BOARD_BootClockVLPR configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockVLPR(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************* Configuration BOARD_BootClockHSRUN ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockHSRUN configuration + ******************************************************************************/ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKHSRUN_BUS_CLOCK 56000000UL /* Clock consumers of Bus_clock output : ADC0, ADC1, CMP0, CRC, ENET, EWM, FLEXIO, I2S0, I2S1, LPI2C0, LPI2C1, LPIT0, LPSPI0, LPSPI1, LPSPI2, LPTMR0, LPUART0, LPUART1, LPUART2, PORTA, PORTB, PORTC, PORTD, PORTE, QuadSPI, RCM, RTC, WDOG */ +#define BOARD_BOOTCLOCKHSRUN_CLKOUT 0UL /* Clock consumers of CLKOUT output : N/A */ +#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK 112000000UL /* Clock consumers of Core_clock output : N/A */ +#define BOARD_BOOTCLOCKHSRUN_FIRCDIV1_CLK 48000000UL /* Clock consumers of FIRCDIV1_CLK output : QuadSPI */ +#define BOARD_BOOTCLOCKHSRUN_FIRCDIV2_CLK 48000000UL /* Clock consumers of FIRCDIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKHSRUN_FLASH_CLOCK 28000000UL /* Clock consumers of Flash_clock output : FTFC */ +#define BOARD_BOOTCLOCKHSRUN_LPO1K_CLK 1000UL /* Clock consumers of LPO1K_CLK output : LPTMR0, RTC */ +#define BOARD_BOOTCLOCKHSRUN_LPO_CLK 128000UL /* Clock consumers of LPO_CLK output : WDOG */ +#define BOARD_BOOTCLOCKHSRUN_LPO_CLOCK 128000UL /* Clock consumers of LPO_clock output : EWM, PORTA, PORTB, PORTC, PORTD, PORTE, RCM */ +#define BOARD_BOOTCLOCKHSRUN_PCC_ADC0_CLK 0UL /* Clock consumers of PCC.PCC_ADC0_CLK output : ADC0 */ +#define BOARD_BOOTCLOCKHSRUN_PCC_ADC1_CLK 0UL /* Clock consumers of PCC.PCC_ADC1_CLK output : ADC1 */ +#define BOARD_BOOTCLOCKHSRUN_PCC_ENET_CLK 0UL /* Clock consumers of PCC.PCC_ENET_CLK output : ENET */ +#define BOARD_BOOTCLOCKHSRUN_PCC_FTM0_CLK 0UL /* Clock consumers of PCC.PCC_FTM0_CLK output : FTM0 */ +#define BOARD_BOOTCLOCKHSRUN_PCC_FTM1_CLK 0UL /* Clock consumers of PCC.PCC_FTM1_CLK output : FTM1 */ +#define BOARD_BOOTCLOCKHSRUN_PCC_FTM2_CLK 0UL /* Clock consumers of PCC.PCC_FTM2_CLK output : FTM2 */ +#define BOARD_BOOTCLOCKHSRUN_PCC_FTM3_CLK 0UL /* Clock consumers of PCC.PCC_FTM3_CLK output : FTM3 */ +#define BOARD_BOOTCLOCKHSRUN_PCC_FTM4_CLK 0UL /* Clock consumers of PCC.PCC_FTM4_CLK output : FTM4 */ +#define BOARD_BOOTCLOCKHSRUN_PCC_FTM5_CLK 0UL /* Clock consumers of PCC.PCC_FTM5_CLK output : FTM5 */ +#define BOARD_BOOTCLOCKHSRUN_PCC_FTM6_CLK 0UL /* Clock consumers of PCC.PCC_FTM6_CLK output : FTM6 */ +#define BOARD_BOOTCLOCKHSRUN_PCC_FTM7_CLK 0UL /* Clock consumers of PCC.PCC_FTM7_CLK output : FTM7 */ +#define BOARD_BOOTCLOCKHSRUN_PCC_FLEXIO_CLK 0UL /* Clock consumers of PCC.PCC_FlexIO_CLK output : FLEXIO */ +#define BOARD_BOOTCLOCKHSRUN_PCC_LPI2C0_CLK 0UL /* Clock consumers of PCC.PCC_LPI2C0_CLK output : LPI2C0 */ +#define BOARD_BOOTCLOCKHSRUN_PCC_LPI2C1_CLK 0UL /* Clock consumers of PCC.PCC_LPI2C1_CLK output : LPI2C1 */ +#define BOARD_BOOTCLOCKHSRUN_PCC_LPIT_CLK 0UL /* Clock consumers of PCC.PCC_LPIT_CLK output : LPIT0 */ +#define BOARD_BOOTCLOCKHSRUN_PCC_LPSPI0_CLK 0UL /* Clock consumers of PCC.PCC_LPSPI0_CLK output : LPSPI0 */ +#define BOARD_BOOTCLOCKHSRUN_PCC_LPSPI1_CLK 0UL /* Clock consumers of PCC.PCC_LPSPI1_CLK output : LPSPI1 */ +#define BOARD_BOOTCLOCKHSRUN_PCC_LPSPI2_CLK 0UL /* Clock consumers of PCC.PCC_LPSPI2_CLK output : LPSPI2 */ +#define BOARD_BOOTCLOCKHSRUN_PCC_LPTMR0_CLK 0UL /* Clock consumers of PCC.PCC_LPTMR0_CLK output : LPTMR0 */ +#define BOARD_BOOTCLOCKHSRUN_PCC_LPUART0_CLK 0UL /* Clock consumers of PCC.PCC_LPUART0_CLK output : LPUART0 */ +#define BOARD_BOOTCLOCKHSRUN_PCC_LPUART1_CLK 0UL /* Clock consumers of PCC.PCC_LPUART1_CLK output : LPUART1 */ +#define BOARD_BOOTCLOCKHSRUN_PCC_LPUART2_CLK 0UL /* Clock consumers of PCC.PCC_LPUART2_CLK output : LPUART2 */ +#define BOARD_BOOTCLOCKHSRUN_PLLDIV1_CLK 112000000UL /* Clock consumers of PLLDIV1_CLK output : QuadSPI */ +#define BOARD_BOOTCLOCKHSRUN_PLLDIV2_CLK 56000000UL /* Clock consumers of PLLDIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKHSRUN_PREDIV_SYSTEM_CLOCK 112000000UL /* Clock consumers of Prediv_system_clock output : QuadSPI */ +#define BOARD_BOOTCLOCKHSRUN_RMIICLK 0UL /* Clock consumers of RMIICLK output : ENET */ +#define BOARD_BOOTCLOCKHSRUN_RTC_CLK 32000UL /* Clock consumers of RTC_CLK output : FTM0, FTM1, FTM2, FTM3, FTM4, FTM5, FTM6, FTM7, LPTMR0, RTC */ +#define BOARD_BOOTCLOCKHSRUN_SIRCDIV1_CLK 8000000UL /* Clock consumers of SIRCDIV1_CLK output : N/A */ +#define BOARD_BOOTCLOCKHSRUN_SIRCDIV2_CLK 8000000UL /* Clock consumers of SIRCDIV2_CLK output : LPTMR0 */ +#define BOARD_BOOTCLOCKHSRUN_SIRC_CLK 8000000UL /* Clock consumers of SIRC_CLK output : WDOG */ +#define BOARD_BOOTCLOCKHSRUN_SOSCDIV1_CLK 8000000UL /* Clock consumers of SOSCDIV1_CLK output : I2S0, I2S1 */ +#define BOARD_BOOTCLOCKHSRUN_SOSCDIV2_CLK 8000000UL /* Clock consumers of SOSCDIV2_CLK output : CAN0, CAN1, CAN2 */ +#define BOARD_BOOTCLOCKHSRUN_SOSC_CLK 8000000UL /* Clock consumers of SOSC_CLK output : WDOG */ +#define BOARD_BOOTCLOCKHSRUN_SYSTEM_CLOCK 112000000UL /* Clock consumers of System_clock output : CAN0, CAN1, CAN2, DMA0, ENET, FTM0, FTM1, FTM2, FTM3, FTM4, FTM5, FTM6, FTM7, PDB0, PDB1, QuadSPI */ +#define BOARD_BOOTCLOCKHSRUN_TRACECLKIN 0UL /* Clock consumers of TRACECLKIN output : N/A */ + +/*! @brief SCG set for BOARD_BootClockHSRUN configuration. + */ +extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN; +/*! @brief System OSC set for BOARD_BootClockHSRUN configuration. + */ +extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN; +/*! @brief SIRC set for BOARD_BootClockHSRUN configuration. + */ +extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN; +/*! @brief FIRC set for BOARD_BootClockHSRUN configuration. + */ +extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockHSRUN; +/*! @brief Low Power FLL set for BOARD_BootClockHSRUN configuration. + */ +extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockHSRUN; + +/******************************************************************************* + * API for BOARD_BootClockHSRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockHSRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/pin_mux.c b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/pin_mux.c new file mode 100644 index 00000000000..6428ed2ad21 --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/pin_mux.c @@ -0,0 +1,87 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* RT-Thread Configuration */ +#include "rtconfig.h" + +/* SDK drivers */ +#include "fsl_common.h" +#include "fsl_port.h" +#include "pin_mux.h" + +static void BOARD_InitUARTPins(void); +static void BOARD_InitI2CPins(void); + +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); + BOARD_InitUARTPins(); + BOARD_InitI2CPins(); +} + +static void BOARD_InitUARTPins(void) +{ +#if defined(BSP_USING_UART0) + BOARD_InitUART0Pins(); +#endif + +#if defined(BSP_USING_UART1) + BOARD_InitUART1Pins(); +#endif + +#if defined(BSP_USING_UART2) + BOARD_InitUART2Pins(); +#endif +} + +static void BOARD_InitI2CPins(void) +{ +#if defined(BSP_USING_I2C0) + BOARD_InitI2C0Pins(); +#endif + +#if defined(BSP_USING_I2C1) + BOARD_InitI2C1Pins(); +#endif +} + +void BOARD_InitPins(void) +{ + CLOCK_EnableClock(kCLOCK_PortA); + CLOCK_EnableClock(kCLOCK_PortB); + CLOCK_EnableClock(kCLOCK_PortC); + CLOCK_EnableClock(kCLOCK_PortD); + CLOCK_EnableClock(kCLOCK_PortE); +} + +void BOARD_InitUART0Pins(void) +{ + /* UART 0 pins are not used on this board. */ +} + +void BOARD_InitUART1Pins(void) +{ + PORT_SetPinMux(PORTC, 8U, kPORT_MuxAlt2); /* Default route to UART TX/RX pins on MikroBUS */ + PORT_SetPinMux(PORTC, 9U, kPORT_MuxAlt2); /* Default route to UART TX/RX pins on MikroBUS */ +} + +void BOARD_InitUART2Pins(void) +{ + PORT_SetPinMux(PORTD, 17U, kPORT_MuxAlt3); /* Default route to Arduino D0/D1 and MCU-Link Virtual COM Port */ + PORT_SetPinMux(PORTE, 12U, kPORT_MuxAlt3); /* Default route to Arduino D0/D1 and MCU-Link Virtual COM Port */ +} + +void BOARD_InitI2C0Pins(void) +{ + PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt3); /* Default route to I2C SCL/SDA pins on MikroBUS */ + PORT_SetPinMux(PORTA, 3U, kPORT_MuxAlt3); /* Default route to I2C SCL/SDA pins on MikroBUS */ +} + +void BOARD_InitI2C1Pins(void) +{ + PORT_SetPinMux(PORTD, 8U, kPORT_MuxAlt2); /* Default route to Arduino D18/D19 */ + PORT_SetPinMux(PORTD, 9U, kPORT_MuxAlt2); /* Default route to Arduino D18/D19 */ +} diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/pin_mux.h b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/pin_mux.h new file mode 100644 index 00000000000..4c2ca921a0a --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/pin_mux.h @@ -0,0 +1,27 @@ +/* +* Copyright 2025 NXP +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + + +#ifndef PIN_MUX_H +#define PIN_MUX_H + +#if defined(__cplusplus) +extern "C" { +#endif + +void BOARD_InitBootPins(void); +void BOARD_InitPins(void); +void BOARD_InitUART0Pins(void); +void BOARD_InitUART1Pins(void); +void BOARD_InitUART2Pins(void); +void BOARD_InitI2C0Pins(void); +void BOARD_InitI2C1Pins(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* PIN_MUX_H */ diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/SConscript b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/SConscript new file mode 100644 index 00000000000..625498da21a --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/SConscript @@ -0,0 +1,25 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +board.c +MCUX_Config/board/clock_config.c +MCUX_Config/board/pin_mux.c +""") + +if GetDepend(['BSP_USING_RW007']): + src += Glob('ports/drv_spi_sample_rw007.c') + +CPPPATH = [cwd, cwd + '/MCUX_Config/board'] +CPPDEFINES = ['DEBUG', 'CPU_MCXE247VLQ'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/board.c b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/board.c new file mode 100644 index 00000000000..f9680e424b1 --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/board.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 yandld first implementation + */ + +#include +#include + +#include "board.h" +#include "clock_config.h" +#include "drv_uart.h" + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial board. + */ +void rt_hw_board_init() +{ + BOARD_InitBootPins(); + BOARD_InitBootClocks(); + + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + /* set pend exception priority */ + NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1); + + /*init uart device*/ + rt_hw_uart_init(); + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + /* initialization board with RT-Thread Components */ + rt_components_board_init(); +#endif + +#ifdef RT_USING_HEAP + rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); + rt_system_heap_init((void *)HEAP_BEGIN, (void *)(HEAP_END)); +#endif +} + + +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + +/** + * This function will called when memory fault. + */ +void MemManage_Handler(void) +{ + extern void HardFault_Handler(void); + + rt_kprintf("Memory Fault!\n"); + HardFault_Handler(); +} diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/board.h b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/board.h new file mode 100644 index 00000000000..c27d6e95636 --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/board.h @@ -0,0 +1,50 @@ +/* +* Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2010-02-04 Magicoe add board.h to LPC176x bsp + * 2013-12-18 Bernard porting to LPC4088 bsp + * 2017-08-02 XiaoYang porting to LPC54608 bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + + +#include + +#include + +#include "clock_config.h" +#include "fsl_common.h" +#include "fsl_gpio.h" +#include "pin_mux.h" +#include "fsl_edma.h" + +// + +// +#if defined(__ARMCC_VERSION) +extern int Image$$ARM_LIB_HEAP$$ZI$$Base; +extern int Image$$ARM_LIB_STACK$$ZI$$Base; +#define HEAP_BEGIN ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base) +#define HEAP_END ((void *)&Image$$ARM_LIB_STACK$$ZI$$Base) +#elif defined(__ICCARM__) +#pragma section = "HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +extern void __RTT_HEAP_END; +#define HEAP_END (&__RTT_HEAP_END) +#elif defined(__GNUC__) +extern int __HeapBase; +extern int __HeapLimit; +#define HEAP_BEGIN ((void *)&__HeapBase) +#define HEAP_END ((void *)&__HeapLimit) +#endif + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/linker_scripts/MCXE247_flash.ld b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/linker_scripts/MCXE247_flash.ld new file mode 100644 index 00000000000..ae242504805 --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/linker_scripts/MCXE247_flash.ld @@ -0,0 +1,229 @@ +/* +** ################################################################### +** Processors: MCXE247VLL +** MCXE247VLQ +** +** Compiler: GNU C Compiler +** Reference manual: MCXE24x RM Rev.1 +** Version: rev. 1.0, 2025-02-21 +** Build: b250311 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010 + m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x0017FBF0 + m_data (RW) : ORIGIN = 0x1FFE0000, LENGTH = 0x00020000 + m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x0001F000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .flash_config : + { + . = ALIGN(4); + KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_flash_config + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .rtt_const_tables : + { + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(NonCacheable.init) /* NonCacheable init section */ + *(NonCacheable) /* NonCacheable section */ + *(CodeQuickAccess) /* quick access code section */ + *(DataQuickAccess) /* quick access data section */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data_2 + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data_2 + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap") +} + diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/linker_scripts/MCXE247_flash.scf b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/linker_scripts/MCXE247_flash.scf new file mode 100644 index 00000000000..a188bb40851 --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/linker_scripts/MCXE247_flash.scf @@ -0,0 +1,81 @@ +#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m4 -E -x c +/* +** ################################################################### +** Processors: MCXE247VLL +** MCXE247VLQ +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: MCXE24x RM Rev.1 +** Version: rev. 1.0, 2025-02-21 +** Build: b250311 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000400 + +#define m_flash_config_start 0x00000400 +#define m_flash_config_size 0x00000010 + +#define m_text_start 0x00000410 +#define m_text_size 0x0017FBF0 + +#define m_data_start 0x1FFE0000 +#define m_data_size 0x00020000 + +#define m_data_2_start 0x20000000 +#define m_data_2_size 0x0001F000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (.isr_vector,+FIRST) + } + ER_m_flash_config m_flash_config_start FIXED m_flash_config_size { ; load address = execution address + * (.FlashConfig,+FIRST) + } + ER_m_text m_text_start m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start m_data_size { ; RW data + .ANY (+RW +ZI) + * (RamFunction) + * (NonCacheable.init) + * (*NonCacheable) + * (CodeQuickAccess) + * (DataQuickAccess) + } + RW_m_data_2 m_data_2_start m_data_2_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + } + ARM_LIB_HEAP ((ImageLimit(RW_m_data_2) == m_data_2_start) ? m_data_2_start : +0) EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_2_start+m_data_2_size EMPTY -Stack_Size { ; Stack region growing down + } +} + diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/rtconfig.h b/bsp/nxp/mcx/mcxe/frdm-mcxe247/rtconfig.h new file mode 100644 index 00000000000..f3c072c2e16 --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/rtconfig.h @@ -0,0 +1,437 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +#define SOC_MCX + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 16 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart2" +#define RT_VER_NUM 0x50201 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_FPU +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FD_MAX 16 +#define RT_USING_DFS_V1 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_DEVFS +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_ADC +#define RT_USING_RTC +#define RT_USING_SPI +#define RT_USING_PIN +#define RT_USING_HWTIMER +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +#define PKG_USING_NXP_MCX_CMSIS_DRIVER +#define PKG_USING_NXP_MCX_CMSIS_DRIVER_LATEST_VERSION +#define PKG_USING_NXP_MCX_SERIES_DRIVER +#define PKG_USING_NXP_MCX_SERIES_DRIVER_LATEST_VERSION +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ + +/* Hardware Drivers Config */ + +#define SOC_MCXE247 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_PIN +#define BSP_USING_UART +#define BSP_USING_UART2 +/* end of On-chip Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Board extended module Drivers */ +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/rtconfig.py b/bsp/nxp/mcx/mcxe/frdm-mcxe247/rtconfig.py new file mode 100644 index 00000000000..487cdc160fe --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/rtconfig.py @@ -0,0 +1,198 @@ +import os +import sys + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' +BOARD_NAME = 'frdm-mcxe247' +BSP_LIBRARY_TYPE = 'MCXE247' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armclang' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:\Program Files\IAR Systems\Embedded Workbench 9.1' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__START=entry -D__STARTUP_CLEAR_BSS' + LFLAGS = DEVICE + ' -specs=nano.specs -specs=nosys.specs -Wl,--defsym=__heap_size__=0x10000,--gc-sections,-Map=rtthread.map,--print-memory-usage -Tboard/linker_scripts/MCXE247_flash.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + else: + CFLAGS += ' -O2 -Os' + + POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti' + CXXFLAGS += CFLAGS + + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' + \ + ' -shared -fPIC -nostartfiles -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + '.fp.sp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '/ARM/ARMCC/lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "./MCXE247_flash.scf" ' + + LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' + + CFLAGS += ' --diag_suppress=66,1296,186,6134' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' --c99' + + POST_ACTION = 'fromelf -z $TARGET' + # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4 ' + CFLAGS = ' --target=arm-arm-none-eabi' + CFLAGS += ' -mcpu=' + CPU + CFLAGS += ' -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\MCXE247_flash.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D__FPU_PRESENT' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=' + CPU + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu ' + CPU + AFLAGS += ' --fpu None' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/MCXE247_flash.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), '..', 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/template.uvoptx b/bsp/nxp/mcx/mcxe/frdm-mcxe247/template.uvoptx new file mode 100644 index 00000000000..2ee820b2d82 --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/template.uvoptx @@ -0,0 +1,184 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread-frdm-mcxa346 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 14 + + + + + + + + + + + BIN\CMSIS_AGDI_V8M.DLL + + + + 0 + CMSIS_AGDI_V8M + -X"Any" -UAny -O206 -S9 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0MCXA34X_1024.FLM -FS00 -FL0FE000 -FP0($$Device:MCXA346VLQ$devices\MCXA346\arm\MCXA34X_1024.FLM) + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0MCXA34X_1024 -FL0FE000 -FS00 -FP0($$Device:MCXA346VLQ$devices\MCXA346\arm\MCXA34X_1024.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 5000000 + + + + + diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/template.uvprojx b/bsp/nxp/mcx/mcxe/frdm-mcxe247/template.uvprojx new file mode 100644 index 00000000000..5d597a72464 --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/template.uvprojx @@ -0,0 +1,401 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-frdm-mcxa346 + 0x4 + ARM-ADS + 6230000::V6.23::ARMCLANG + 1 + + + MCXA346VLQ + NXP + NXP.MCXA346_DFP.25.06.00 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20000000,0x03c000) IRAM2(0x04000000,0x2000) IROM(0x03000000,0x2000) IROM2(0x00000000,0x0fe000) XRAM(0x04002000,0x2000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP CLOCK(12000000) ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0MCXA34X_1024 -FS00 -FL0FE000 -FP0($$Device:MCXA346VLQ$devices\MCXA346\arm\MCXA34X_1024.FLM)) + 0 + $$Device:MCXA346VLQ$devices\MCXA346\fsl_device_registers.h + + + + + + + + + + $$Device:MCXA346VLQ$devices\MCXA346\MCXA346.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 2 + 0 + 0 + 0 + 1 + 1 + 16 + 0 + 0 + 0 + 0 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x3c000 + + + 1 + 0x3000000 + 0x2000 + + + 1 + 0x4002000 + 0x2000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x3000000 + 0x2000 + + + 1 + 0x0 + 0xfe000 + + + 0 + 0x4002000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x3c000 + + + 0 + 0x4000000 + 0x2000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + --target=arm-arm-none-eabi + CPU_MCXA346VLQ, ARM_MATH_CM33, RT_USING_ARM_LIBC + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + -x assembler-with-cpp + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x02000000 + + .\board\linker_scripts\MCXA346_flash.scf + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + + + + + + + + + + + + + + + + + + template + 1 + + + + + From cab050415bcff2832e04fc05ba6e45af883c41df Mon Sep 17 00:00:00 2001 From: Yilin Sun Date: Tue, 26 Aug 2025 18:32:29 +0800 Subject: [PATCH 2/7] bsp/nxp/mcx/mcxe: Add SPI driver and RW007 sample. Signed-off-by: Yilin Sun --- bsp/nxp/mcx/mcxe/Libraries/drivers/drv_i2c.c | 9 +- bsp/nxp/mcx/mcxe/Libraries/drivers/drv_spi.c | 162 ++++++++++++++++++ bsp/nxp/mcx/mcxe/Libraries/drivers/drv_spi.h | 20 +++ .../applications/drv_spi_sample_rw007.c | 73 ++++++++ bsp/nxp/mcx/mcxe/frdm-mcxe247/board/Kconfig | 18 +- .../board/MCUX_Config/board/pin_mux.c | 38 ++++ .../board/MCUX_Config/board/pin_mux.h | 3 + 7 files changed, 314 insertions(+), 9 deletions(-) create mode 100644 bsp/nxp/mcx/mcxe/Libraries/drivers/drv_spi.c create mode 100644 bsp/nxp/mcx/mcxe/Libraries/drivers/drv_spi.h create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/applications/drv_spi_sample_rw007.c diff --git a/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_i2c.c b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_i2c.c index bb6e68fc962..9faf1e6b8a7 100644 --- a/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_i2c.c +++ b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_i2c.c @@ -135,9 +135,9 @@ static rt_ssize_t lpc_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg } static const struct rt_i2c_bus_device_ops i2c_ops = { - .master_xfer = lpc_i2c_xfer, - .slave_xfer = RT_NULL, - .i2c_bus_control = RT_NULL, + .master_xfer = lpc_i2c_xfer, + .slave_xfer = RT_NULL, + .i2c_bus_control = RT_NULL, }; int rt_hw_i2c_init(void) @@ -148,7 +148,8 @@ int rt_hw_i2c_init(void) for (i = 0; i < ARRAY_SIZE(i2c_buses); i++) { struct mcx_i2c_bus *priv = &i2c_buses[i]; - CLOCK_SetIpSrc(i2c_buses[i].clock_ip_name, priv->clock_ip_src); + + CLOCK_SetIpSrc(priv->clock_ip_name, priv->clock_ip_src); LPI2C_MasterGetDefaultConfig(&masterConfig); masterConfig.baudRate_Hz = priv->baud; diff --git a/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_spi.c b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_spi.c new file mode 100644 index 00000000000..a2e647f866f --- /dev/null +++ b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_spi.c @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-08-1 hywing The first version for MCXA + */ +#include "rtdevice.h" +#include "drv_spi.h" +#include "fsl_lpspi.h" + + +#ifdef RT_USING_SPI + +#define DBG_TAG "drv.spi" +#define DBG_LVL DBG_INFO +#include + +enum +{ +#ifdef BSP_USING_SPI0 + SPI0_INDEX, +#endif +#ifdef BSP_USING_SPI1 + SPI1_INDEX, +#endif +}; + +struct mcx_spi_bus +{ + struct rt_spi_bus spi_bus; + LPSPI_Type *spi_base; + clock_ip_name_t clock_ip_name; + clock_ip_src_t clock_ip_src; + clock_name_t clock_name; + + + rt_sem_t sem; + char *name; +}; + +static struct mcx_spi_bus mcx_spi_buses[] = + { +#ifdef BSP_USING_SPI0 + { + .spi_base = LPSPI0, + .clock_ip_name = kCLOCK_Lpspi0, + .clock_ip_src = kCLOCK_IpSrcSysOscAsync, + .name = "spi0", + }, +#endif +#ifdef BSP_USING_SPI1 + { + .spi_base = LPSPI1, + .clock_ip_name = kCLOCK_Lpspi1, + .clock_ip_src = kCLOCK_IpSrcSysOscAsync, + .name = "spi1", + }, +#endif +#ifdef BSP_USING_SPI2 + { + .spi_base = LPSPI2, + .clock_ip_name = kCLOCK_Lpspi2, + .clock_ip_src = kCLOCK_IpSrcSysOscAsync, + .name = "spi2", + }, +#endif +}; + +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin) +{ + struct rt_spi_device *spi_device = rt_malloc(sizeof(struct rt_spi_device)); + if (!spi_device) + { + return -RT_ENOMEM; + } + + return rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, pin, NULL); +} + +static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) +{ + return RT_EOK; +} + + +static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + lpspi_transfer_t transfer = {0}; + status_t status; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + + struct mcx_spi_bus *spi = device->bus->parent.user_data; + + if (message->cs_take) + { + rt_pin_write(device->cs_pin, PIN_LOW); + } + + transfer.dataSize = message->length; + transfer.rxData = (uint8_t *)(message->recv_buf); + transfer.txData = (uint8_t *)(message->send_buf); + transfer.configFlags = kLPSPI_MasterPcs0; + + // Use blocking transfer instead of DMA + status = LPSPI_MasterTransferBlocking(spi->spi_base, &transfer); + + if (message->cs_release) + { + rt_pin_write(device->cs_pin, PIN_HIGH); + } + + if (status != kStatus_Success) + { + return 0; // Transfer failed + } + + return message->length; +} + + +static struct rt_spi_ops lpc_spi_ops = + { + .configure = spi_configure, + .xfer = spixfer}; + +int rt_hw_spi_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mcx_spi_buses); i++) + { + struct mcx_spi_bus *priv = &mcx_spi_buses[i]; + + + CLOCK_SetIpSrc(priv->clock_ip_name, priv->clock_ip_src); + + priv->spi_bus.parent.user_data = &mcx_spi_buses[i]; + priv->sem = rt_sem_create("sem_spi", 0, RT_IPC_FLAG_FIFO); + + lpspi_master_config_t masterConfig; + LPSPI_MasterGetDefaultConfig(&masterConfig); + masterConfig.baudRate = 10 * 1000 * 1000; + masterConfig.pcsToSckDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U; + masterConfig.lastSckToPcsDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U; + masterConfig.betweenTransferDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U; + + LPSPI_MasterInit(priv->spi_base, &masterConfig, CLOCK_GetFreq(priv->clock_name)); + + rt_spi_bus_register(&priv->spi_bus, priv->name, &lpc_spi_ops); + } + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_spi_init); + +#endif /* RT_USING_SPI */ + diff --git a/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_spi.h b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_spi.h new file mode 100644 index 00000000000..81e4f479f5d --- /dev/null +++ b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_spi.h @@ -0,0 +1,20 @@ +/* +* Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-03-22 Jisheng Zhang The first version for mcxn + */ + +#ifndef DRV_SPI_H +#define DRV_SPI_H + +#include + +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin); + +int rt_hw_spi_init(void); + +#endif //DRV_SPI_H diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/applications/drv_spi_sample_rw007.c b/bsp/nxp/mcx/mcxe/frdm-mcxe247/applications/drv_spi_sample_rw007.c new file mode 100644 index 00000000000..c2a89b91d4b --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/applications/drv_spi_sample_rw007.c @@ -0,0 +1,73 @@ +#include + +#ifdef BSP_USING_RW007 +#include +#include +#include +#include + +#define BOARD_RW007_DEVICE_NAME "rw007" + +extern void spi_wifi_isr(int vector); + +static void rw007_gpio_init(void) +{ + /* Configure IO */ + rt_pin_mode(BOARD_RW007_RST_PIN, PIN_MODE_OUTPUT); + rt_pin_mode(BOARD_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLDOWN); + + /* Reset rw007 and config mode */ + rt_pin_write(BOARD_RW007_RST_PIN, PIN_LOW); + + rt_thread_delay(rt_tick_from_millisecond(100)); + rt_pin_write(BOARD_RW007_RST_PIN, PIN_HIGH); + + /* Wait rw007 ready(exit busy stat) */ + while (!rt_pin_read(BOARD_RW007_INT_BUSY_PIN)) + { + rt_thread_delay(5); + } + + rt_thread_delay(rt_tick_from_millisecond(200)); + rt_pin_mode(BOARD_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLUP); +} + +int wifi_spi_device_init(void) +{ + int ret = 0; + char sn_version[32]; + + struct rt_spi_device *spi_device = rt_malloc(sizeof(struct rt_spi_device)); + if (!spi_device) return -1; + + rw007_gpio_init(); + ret = rt_spi_bus_attach_device_cspin(spi_device, BOARD_RW007_DEVICE_NAME, BOARD_RW007_SPI_BUS_NAME, BOARD_RW007_CS_PIN, RT_NULL); + if (ret != RT_EOK) return -2; + + rt_hw_wifi_init("rw007"); + + rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION); + rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP); + + rw007_sn_get(sn_version); + rt_kprintf("\nrw007 sn: [%s]\n", sn_version); + rw007_version_get(sn_version); + rt_kprintf("rw007 ver: [%s]\n\n", sn_version); + + return 0; +} +INIT_APP_EXPORT(wifi_spi_device_init); + +static void int_wifi_irq(void *p) +{ + ((void)p); + spi_wifi_isr(0); +} + +void spi_wifi_hw_init(void) +{ + rt_pin_attach_irq(BOARD_RW007_INT_BUSY_PIN, PIN_IRQ_MODE_FALLING, int_wifi_irq, 0); + rt_pin_irq_enable(BOARD_RW007_INT_BUSY_PIN, RT_TRUE); +} + +#endif diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/Kconfig b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/Kconfig index 232ad035380..7c9b35e3cf8 100644 --- a/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/Kconfig +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/Kconfig @@ -57,8 +57,16 @@ menu "On-chip Peripheral Drivers" default y if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable LPSPI0" + default n + config BSP_USING_SPI1 bool "Enable LPSPI1" + default y + + config BSP_USING_SPI2 + bool "Enable LPSPI2" default n endif @@ -145,16 +153,16 @@ menu "Board extended module Drivers" default "spi1" config BOARD_RW007_CS_PIN - hex "CS pin index" - default 107 + int "CS pin index" + default 16 config BOARD_RW007_INT_BUSY_PIN - hex "INT/BUSY pin index" - default 109 + int "INT/BUSY pin index" + default 143 config BOARD_RW007_RST_PIN hex "RESET pin index" - default 131 + default 42 endif diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/pin_mux.c b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/pin_mux.c index 6428ed2ad21..3e55ea6e2d6 100644 --- a/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/pin_mux.c +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/pin_mux.c @@ -14,12 +14,14 @@ static void BOARD_InitUARTPins(void); static void BOARD_InitI2CPins(void); +static void BOARD_InitSPIPins(void); void BOARD_InitBootPins(void) { BOARD_InitPins(); BOARD_InitUARTPins(); BOARD_InitI2CPins(); + BOARD_InitSPIPins(); } static void BOARD_InitUARTPins(void) @@ -48,6 +50,21 @@ static void BOARD_InitI2CPins(void) #endif } +static void BOARD_InitSPIPins(void) +{ +#if defined(BSP_USING_SPI0) + BOARD_InitSPI0Pins(); +#endif + +#if defined(BSP_USING_SPI1) + BOARD_InitSPI1Pins(); +#endif + +#if defined(BSP_USING_SPI2) + BOARD_InitSPI2Pins(); +#endif +} + void BOARD_InitPins(void) { CLOCK_EnableClock(kCLOCK_PortA); @@ -85,3 +102,24 @@ void BOARD_InitI2C1Pins(void) PORT_SetPinMux(PORTD, 8U, kPORT_MuxAlt2); /* Default route to Arduino D18/D19 */ PORT_SetPinMux(PORTD, 9U, kPORT_MuxAlt2); /* Default route to Arduino D18/D19 */ } + +void BOARD_InitSPI0Pins(void) +{ + PORT_SetPinMux(PORTB, 3U, kPORT_MuxAlt3); /* Default route to SPI SCK/SIN/SOUT pins on MikroBUS */ + PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt2); /* Default route to SPI SCK/SIN/SOUT pins on MikroBUS */ + PORT_SetPinMux(PORTE, 2U, kPORT_MuxAlt2); /* Default route to SPI SCK/SIN/SOUT pins on MikroBUS */ +} + +void BOARD_InitSPI1Pins(void) +{ + PORT_SetPinMux(PORTB, 14U, kPORT_MuxAlt3); /* Default route to Arduino D11/D12/D13 */ + PORT_SetPinMux(PORTB, 15U, kPORT_MuxAlt3); /* Default route to Arduino D11/D12/D13 */ + PORT_SetPinMux(PORTD, 2U, kPORT_MuxAlt3); /* Default route to Arduino D11/D12/D13 */ +} + +void BOARD_InitSPI2Pins(void) +{ + PORT_SetPinMux(PORTA, 8U, kPORT_MuxAlt3); /* Default route to SPI SCK/SIN/SOUT pins on PMOD (DNP by default) */ + PORT_SetPinMux(PORTC, 15U, kPORT_MuxAlt3); /* Default route to SPI SCK/SIN/SOUT pins on PMOD (DNP by default) */ + PORT_SetPinMux(PORTE, 16U, kPORT_MuxAlt3); /* Default route to SPI SCK/SIN/SOUT pins on PMOD (DNP by default) */ +} diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/pin_mux.h b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/pin_mux.h index 4c2ca921a0a..d1e19a29f32 100644 --- a/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/pin_mux.h +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/MCUX_Config/board/pin_mux.h @@ -19,6 +19,9 @@ void BOARD_InitUART1Pins(void); void BOARD_InitUART2Pins(void); void BOARD_InitI2C0Pins(void); void BOARD_InitI2C1Pins(void); +void BOARD_InitSPI0Pins(void); +void BOARD_InitSPI1Pins(void); +void BOARD_InitSPI2Pins(void); #if defined(__cplusplus) } From c53c57884c35e186ecd2b7ec964de2dd81f09597 Mon Sep 17 00:00:00 2001 From: Yilin Sun Date: Wed, 27 Aug 2025 15:35:03 +0800 Subject: [PATCH 3/7] bsp:nxp/mcx/mcxe: Add RTC driver. Signed-off-by: Yilin Sun --- bsp/nxp/mcx/mcxe/Libraries/drivers/drv_rtc.c | 278 +++++++++++++++++++ 1 file changed, 278 insertions(+) create mode 100644 bsp/nxp/mcx/mcxe/Libraries/drivers/drv_rtc.c diff --git a/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_rtc.c b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_rtc.c new file mode 100644 index 00000000000..9a0ea065803 --- /dev/null +++ b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_rtc.c @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-19 Alex Yang Add MCXA346 RTC driver for RT-Thread + */ + +#include +#include +#include + +#ifdef BSP_USING_RTC + +#define DBG_TAG "drv.rtc" +#define DBG_LVL DBG_INFO +#include + +#include "fsl_rtc.h" +#include "fsl_clock.h" + + +/* Get RTC timestamp */ +static time_t get_rtc_timestamp(void) +{ + rtc_datetime_t datetime; + struct tm tm_new; + + /* Get current time from RTC */ + RTC_GetDatetime(RTC, &datetime); + + tm_new.tm_sec = datetime.second; + tm_new.tm_min = datetime.minute; + tm_new.tm_hour = datetime.hour; + tm_new.tm_mday = datetime.day; + tm_new.tm_mon = datetime.month - 1; + tm_new.tm_year = datetime.year - 1900; + tm_new.tm_isdst = 0; + + LOG_D("get rtc time: %04d-%02d-%02d %02d:%02d:%02d", + datetime.year, datetime.month, datetime.day, + datetime.hour, datetime.minute, datetime.second); + + return mktime(&tm_new); +} + +/* Set RTC timestamp */ +static rt_err_t set_rtc_time_stamp(time_t time_stamp) +{ + rtc_datetime_t datetime; + struct tm *time_tm; + + time_tm = gmtime(&time_stamp); + if (time_tm->tm_year < 70) /* Year should be >= 1970 */ + { + LOG_E("Invalid year: %d", time_tm->tm_year + 1900); + return -RT_ERROR; + } + + /* Convert to RTC datetime format */ + datetime.year = time_tm->tm_year + 1900; + datetime.month = time_tm->tm_mon + 1; + datetime.day = time_tm->tm_mday; + datetime.hour = time_tm->tm_hour; + datetime.minute = time_tm->tm_min; + datetime.second = time_tm->tm_sec; + + /* Set RTC time */ + RTC_StopTimer(RTC); + + RTC_SetDatetime(RTC, &datetime); + + RTC_StartTimer(RTC); + + LOG_D("set rtc time: %04d-%02d-%02d %02d:%02d:%02d", + datetime.year, datetime.month, datetime.day, + datetime.hour, datetime.minute, datetime.second); + + return RT_EOK; +} + +/* RTC configuration */ +static rt_err_t rt_rtc_config(void) +{ + rtc_config_t rtc_config; + + /* Get default RTC configuration */ + RTC_GetDefaultConfig(&rtc_config); + + /* Initialize RTC - Note: RTC_Init returns void, not status */ + RTC_Init(RTC, &rtc_config); + + /* Start RTC timer */ + RTC_StartTimer(RTC); + + return RT_EOK; +} + +/* RTC initialization */ +static rt_err_t rtc_init(void) +{ + + /* Configure RTC */ + if (rt_rtc_config() != RT_EOK) + { + LOG_E("RTC config failed."); + return -RT_ERROR; + } + + LOG_D("RTC initialized successfully"); + return RT_EOK; +} + +/* Get RTC seconds */ +static rt_err_t rtc_get_secs(time_t *args) +{ + RT_ASSERT(args != RT_NULL); + + *args = get_rtc_timestamp(); + LOG_D("RTC: get rtc_time %x", *args); + + return RT_EOK; +} + +/* Set RTC seconds */ +static rt_err_t rtc_set_secs(time_t *args) +{ + rt_err_t result = RT_EOK; + + RT_ASSERT(args != RT_NULL); + + if (set_rtc_time_stamp(*args) != RT_EOK) + { + result = -RT_ERROR; + } + LOG_D("RTC: set rtc_time %x", *args); + + return result; +} + +/* Get RTC alarm */ +static rt_err_t rtc_get_alarm(struct rt_rtc_wkalarm *wkalarm) +{ + rtc_datetime_t datetime; + + RT_ASSERT(wkalarm != RT_NULL); + + /* Get alarm time from RTC */ + RTC_GetAlarm(RTC, &datetime); + + /* Convert to wkalarm format */ + wkalarm->tm_sec = datetime.second; + wkalarm->tm_min = datetime.minute; + wkalarm->tm_hour = datetime.hour; + wkalarm->tm_mday = datetime.day; + wkalarm->tm_mon = datetime.month - 1; + wkalarm->tm_year = datetime.year - 1900; + + /* Check if alarm is enabled */ + wkalarm->enable = (RTC_GetEnabledInterrupts(RTC) & kRTC_AlarmInterruptEnable) ? 1 : 0; + + LOG_D("RTC: get alarm %04d-%02d-%02d %02d:%02d:%02d (%s)", + datetime.year, datetime.month, datetime.day, + datetime.hour, datetime.minute, datetime.second, + wkalarm->enable ? "ENABLED" : "DISABLED"); + + return RT_EOK; +} + +/* Set RTC alarm */ +static rt_err_t rtc_set_alarm(struct rt_rtc_wkalarm *wkalarm) +{ + rtc_datetime_t datetime; + + RT_ASSERT(wkalarm != RT_NULL); + + /* Convert from wkalarm format */ + datetime.year = wkalarm->tm_year + 1900; + datetime.month = wkalarm->tm_mon + 1; + datetime.day = wkalarm->tm_mday; + datetime.hour = wkalarm->tm_hour; + datetime.minute = wkalarm->tm_min; + datetime.second = wkalarm->tm_sec; + + /* Set alarm time */ + RTC_SetAlarm(RTC, &datetime); + + /* Enable/disable alarm interrupt */ + if (wkalarm->enable) + { + RTC_EnableInterrupts(RTC, kRTC_AlarmInterruptEnable); + EnableIRQ(RTC_IRQn); /* Use RTC_IRQn instead of RTC0_IRQn */ + LOG_D("RTC alarm enabled"); + } + else + { + RTC_DisableInterrupts(RTC, kRTC_AlarmInterruptEnable); + LOG_D("RTC alarm disabled"); + } + + LOG_D("RTC: set alarm %04d-%02d-%02d %02d:%02d:%02d", + datetime.year, datetime.month, datetime.day, + datetime.hour, datetime.minute, datetime.second); + + return RT_EOK; +} + +/* RTC operations structure */ +static const struct rt_rtc_ops rtc_ops = +{ + rtc_init, + rtc_get_secs, + rtc_set_secs, + rtc_get_alarm, + rtc_set_alarm, + RT_NULL, /* get_timeval */ + RT_NULL, /* set_timeval */ +}; + +static rt_rtc_dev_t mcxa_rtc_dev; + +/* RTC interrupt handler */ +void RTC_IRQHandler(void) +{ + rt_interrupt_enter(); + + /* Get interrupt status */ + uint32_t status = RTC_GetStatusFlags(RTC); + + /* Handle alarm interrupt */ + if (status & kRTC_AlarmFlag) + { + /* Clear alarm flag */ + RTC_ClearStatusFlags(RTC, kRTC_AlarmFlag); + + LOG_D("RTC alarm triggered"); + + /* If alarm framework is available, notify it */ +#ifdef RT_USING_ALARM + /* Send alarm event to alarm thread */ + rt_event_send(&_container.event, 1); +#endif + } + + /* Handle seconds interrupt if needed */ + if (status & kRTC_SecondsInterruptEnable) + { + LOG_D("RTC seconds interrupt"); + } + + rt_interrupt_leave(); +} + +/* Hardware RTC initialization */ +int rt_hw_rtc_init(void) +{ + rt_err_t result; + + /* Set RTC operations */ + mcxa_rtc_dev.ops = &rtc_ops; + + /* Register RTC device */ + result = rt_hw_rtc_register(&mcxa_rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR, RT_NULL); + if (result != RT_EOK) + { + LOG_E("RTC register failed, err code: %d", result); + return result; + } + + LOG_D("RTC init success"); + return RT_EOK; +} + +INIT_DEVICE_EXPORT(rt_hw_rtc_init); + +#endif /* BSP_USING_RTC */ From c8130daf8179b3a305e519273c3d83c1f6b134dd Mon Sep 17 00:00:00 2001 From: Yilin Sun Date: Thu, 28 Aug 2025 18:03:27 +0800 Subject: [PATCH 4/7] bsp/nxp/mcx/mcxe: Add ADC driver. Signed-off-by: Yilin Sun --- bsp/nxp/mcx/mcxe/Libraries/drivers/drv_adc.c | 167 +++ bsp/nxp/mcx/mcxe/Libraries/drivers/drv_spi.c | 9 +- bsp/nxp/mcx/mcxe/frdm-mcxe247/.config | 1035 ------------------ bsp/nxp/mcx/mcxe/frdm-mcxe247/board/Kconfig | 10 +- bsp/nxp/mcx/mcxe/frdm-mcxe247/rtconfig.h | 3 + 5 files changed, 180 insertions(+), 1044 deletions(-) create mode 100644 bsp/nxp/mcx/mcxe/Libraries/drivers/drv_adc.c diff --git a/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_adc.c b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_adc.c new file mode 100644 index 00000000000..7f99a057616 --- /dev/null +++ b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_adc.c @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-05-16 shelton first version + * 2024-07-21 liujianhua added mcxa153 + * + */ +#include +#include + +#include "fsl_adc12.h" +#include "fsl_pmc.h" + +#define DBG_TAG "drv.adc" +#define DBG_LVL DBG_INFO +#include + +#ifdef RT_USING_ADC + +#define ADC_VBG_CH 27 +#define ADC_VBG_VOLT 1000 + +struct mcx_adc +{ + struct rt_adc_device adc_device; + ADC_Type *adc_base; + clock_ip_name_t clock_ip_name; + clock_ip_src_t clock_ip_src; + uint8_t resolution_bits; + uint8_t max_channels; + uint32_t vref; + char *name; +}; + +static struct mcx_adc mcx_adc_obj[] = + { +#ifdef BSP_USING_ADC0 + { + .adc_base = ADC0, + .clock_ip_name = kCLOCK_Adc0, + .clock_ip_src = kCLOCK_IpSrcSysOscAsync, + .resolution_bits = 12, + .max_channels = 32, + .name = "adc0", + }, +#endif +#ifdef BSP_USING_ADC1 + { + .adc_base = ADC1, + .clock_ip_name = kCLOCK_Adc1, + .clock_ip_src = kCLOCK_IpSrcSysOscAsync, + .resolution_bits = 12, + .max_channels = 32, + .name = "adc1", + }, +#endif +}; + +static uint16_t mcx_adc_get_raw(struct mcx_adc *adc, uint32_t channel) +{ + adc12_channel_config_t chnl_cfg = {0}; + + chnl_cfg.channelNumber = channel; + chnl_cfg.enableInterruptOnConversionCompleted = false; + + ADC12_SetChannelConfig(adc->adc_base, 0, &chnl_cfg); + while ((ADC12_GetChannelStatusFlags(adc->adc_base, 0) & kADC12_ChannelConversionCompletedFlag) == 0U) + { + } + + return ADC12_GetChannelConversionValue(adc->adc_base, 0); +} + +static rt_err_t mcx_adc_set_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled) +{ + RT_ASSERT(device != RT_NULL); + + struct mcx_adc *adc = device->parent.user_data; + /* ADC is enabled by global probe. */ + + RT_UNUSED(adc); + + return RT_EOK; +} + +static rt_int16_t mcx_get_vref(struct rt_adc_device *device) +{ + RT_ASSERT(device != RT_NULL); + + struct mcx_adc *adc = device->parent.user_data; + + return (int16_t)adc->vref; +} + +static rt_err_t mcx_adc_get_value(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value) +{ + RT_ASSERT(device != RT_NULL); + + struct mcx_adc *adc = device->parent.user_data; + + *value = mcx_adc_get_raw(adc, channel); + + return RT_EOK; +} + +static rt_uint8_t mcx_adc_get_resolution(struct rt_adc_device *device) +{ + RT_ASSERT(device != RT_NULL); + + struct mcx_adc *adc = device->parent.user_data; + + return adc->resolution_bits; +} + +static const struct rt_adc_ops mcx_adc_ops = + { + .get_resolution = mcx_adc_get_resolution, + .enabled = mcx_adc_set_enabled, + .convert = mcx_adc_get_value, + .get_vref = mcx_get_vref, +}; + +static int rt_hw_adc_init(void) +{ + int result = RT_EOK; + int i = 0; + + for (i = 0; i < sizeof(mcx_adc_obj) / sizeof(mcx_adc_obj[0]); i++) + { + struct mcx_adc *adc = &mcx_adc_obj[i]; + + CLOCK_SetIpSrc(adc->clock_ip_name, adc->clock_ip_src); + + adc12_config_t cfg; + ADC12_GetDefaultConfig(&cfg); + + cfg.clockSource = kADC12_ClockSourceAlt0; /* Only available selection. */ + cfg.resolution = kADC12_Resolution12Bit; + cfg.sampleClockCount = 64; + + ADC12_Init(adc->adc_base, &cfg); + ADC12_EnableHardwareTrigger(adc->adc_base, false); + + if (ADC12_DoAutoCalibration(adc->adc_base) != kStatus_Success) + { + return -RT_ERROR; + } + + uint32_t vref_raw = mcx_adc_get_raw(adc, ADC_VBG_CH); + adc->vref = (1U << adc->resolution_bits) * ADC_VBG_VOLT / vref_raw; + + if (rt_hw_adc_register(&mcx_adc_obj[i].adc_device, mcx_adc_obj[i].name, &mcx_adc_ops, &mcx_adc_obj[i]) != RT_EOK) + { + return -RT_ERROR; + } + } + + return result; +} + +INIT_BOARD_EXPORT(rt_hw_adc_init); + +#endif /* BSP_USING_ADC */ diff --git a/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_spi.c b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_spi.c index a2e647f866f..bd401f33ce0 100644 --- a/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_spi.c +++ b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_spi.c @@ -34,11 +34,8 @@ struct mcx_spi_bus LPSPI_Type *spi_base; clock_ip_name_t clock_ip_name; clock_ip_src_t clock_ip_src; - clock_name_t clock_name; - - - rt_sem_t sem; - char *name; + rt_sem_t sem; + char *name; }; static struct mcx_spi_bus mcx_spi_buses[] = @@ -150,7 +147,7 @@ int rt_hw_spi_init(void) masterConfig.lastSckToPcsDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U; masterConfig.betweenTransferDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U; - LPSPI_MasterInit(priv->spi_base, &masterConfig, CLOCK_GetFreq(priv->clock_name)); + LPSPI_MasterInit(priv->spi_base, &masterConfig, CLOCK_GetIpFreq(priv->clock_ip_name)); rt_spi_bus_register(&priv->spi_bus, priv->name, &lpc_spi_ops); } diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/.config b/bsp/nxp/mcx/mcxe/frdm-mcxe247/.config index fb0f4a06f3e..b30434eb09f 100644 --- a/bsp/nxp/mcx/mcxe/frdm-mcxe247/.config +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/.config @@ -396,1041 +396,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_UTESTCASES is not set # end of RT-Thread Utestcases -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_NANOPB is not set -# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set -# CONFIG_PKG_USING_ESP_HOSTED is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set -# end of Marvell WiFi - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# end of Wiced WiFi - -# CONFIG_PKG_USING_RW007 is not set - -# -# CYW43012 WiFi -# -# CONFIG_PKG_USING_WLAN_CYW43012 is not set -# end of CYW43012 WiFi - -# -# BL808 WiFi -# -# CONFIG_PKG_USING_WLAN_BL808 is not set -# end of BL808 WiFi - -# -# CYW43439 WiFi -# -# CONFIG_PKG_USING_WLAN_CYW43439 is not set -# end of CYW43439 WiFi -# end of Wi-Fi - -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set -# CONFIG_PKG_USING_ZB_COORDINATOR is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set -# CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_IOTSHARP_SDK is not set -# end of IoT Cloud - -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set -# CONFIG_PKG_USING_LIBCURL2RTT is not set -# CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_PDULIB is not set -# CONFIG_PKG_USING_BTSTACK is not set -# CONFIG_PKG_USING_BT_CYW43012 is not set -# CONFIG_PKG_USING_CYW43XX is not set -# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set -# CONFIG_PKG_USING_WAYZ_IOTKIT is not set -# CONFIG_PKG_USING_MAVLINK is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_AGILE_MODBUS is not set -# CONFIG_PKG_USING_AGILE_FTP is not set -# CONFIG_PKG_USING_EMBEDDEDPROTO is not set -# CONFIG_PKG_USING_RT_LINK_HW is not set -# CONFIG_PKG_USING_RYANMQTT is not set -# CONFIG_PKG_USING_RYANW5500 is not set -# CONFIG_PKG_USING_LORA_PKT_FWD is not set -# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set -# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set -# CONFIG_PKG_USING_HM is not set -# CONFIG_PKG_USING_SMALL_MODBUS is not set -# CONFIG_PKG_USING_NET_SERVER is not set -# CONFIG_PKG_USING_ZFTP is not set -# CONFIG_PKG_USING_WOL is not set -# CONFIG_PKG_USING_ZEPHYR_POLLING is not set -# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set -# CONFIG_PKG_USING_LHC_MODBUS is not set -# CONFIG_PKG_USING_QMODBUS is not set -# CONFIG_PKG_USING_PNET is not set -# CONFIG_PKG_USING_OPENER is not set -# CONFIG_PKG_USING_FREEMQTT is not set -# end of IoT - internet of things - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_LIBSODIUM is not set -# CONFIG_PKG_USING_LIBHYDROGEN is not set -# CONFIG_PKG_USING_TINYCRYPT is not set -# CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set -# end of security packages - -# -# language packages -# - -# -# JSON: JavaScript Object Notation, a lightweight data-interchange format -# -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set -# CONFIG_PKG_USING_RAPIDJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set -# CONFIG_PKG_USING_PARSON is not set -# CONFIG_PKG_USING_RYAN_JSON is not set -# end of JSON: JavaScript Object Notation, a lightweight data-interchange format - -# -# XML: Extensible Markup Language -# -# CONFIG_PKG_USING_SIMPLE_XML is not set -# CONFIG_PKG_USING_EZXML is not set -# end of XML: Extensible Markup Language - -# CONFIG_PKG_USING_LUATOS_SOC is not set -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set -# CONFIG_PKG_USING_PIKASCRIPT is not set -# CONFIG_PKG_USING_RTT_RUST is not set -# end of language packages - -# -# multimedia packages -# - -# -# LVGL: powerful and easy-to-use embedded GUI library -# -# CONFIG_PKG_USING_LVGL is not set -# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set -# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set -# end of LVGL: powerful and easy-to-use embedded GUI library - -# -# u8g2: a monochrome graphic library -# -# CONFIG_PKG_USING_U8G2_OFFICIAL is not set -# CONFIG_PKG_USING_U8G2 is not set -# end of u8g2: a monochrome graphic library - -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set -# CONFIG_PKG_USING_PDFGEN is not set -# CONFIG_PKG_USING_HELIX is not set -# CONFIG_PKG_USING_AZUREGUIX is not set -# CONFIG_PKG_USING_TOUCHGFX2RTT is not set -# CONFIG_PKG_USING_NUEMWIN is not set -# CONFIG_PKG_USING_MP3PLAYER is not set -# CONFIG_PKG_USING_TINYJPEG is not set -# CONFIG_PKG_USING_UGUI is not set -# CONFIG_PKG_USING_MCURSES is not set -# CONFIG_PKG_USING_TERMBOX is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_PERSIMMON is not set -# CONFIG_PKG_USING_3GPP_AMRNB is not set -# end of multimedia packages - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_MCOREDUMP is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_SEGGER_RTT is not set -# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_LOGMGR is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_MEMORYPERF is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set -# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set -# CONFIG_PKG_USING_LUNAR_CALENDAR is not set -# CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set -# CONFIG_PKG_USING_UMCN is not set -# CONFIG_PKG_USING_LWRB2RTT is not set -# CONFIG_PKG_USING_CPU_USAGE is not set -# CONFIG_PKG_USING_GBK2UTF8 is not set -# CONFIG_PKG_USING_VCONSOLE is not set -# CONFIG_PKG_USING_KDB is not set -# CONFIG_PKG_USING_WAMR is not set -# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set -# CONFIG_PKG_USING_LWLOG is not set -# CONFIG_PKG_USING_ANV_TRACE is not set -# CONFIG_PKG_USING_ANV_MEMLEAK is not set -# CONFIG_PKG_USING_ANV_TESTSUIT is not set -# CONFIG_PKG_USING_ANV_BENCH is not set -# CONFIG_PKG_USING_DEVMEM is not set -# CONFIG_PKG_USING_REGEX is not set -# CONFIG_PKG_USING_MEM_SANDBOX is not set -# CONFIG_PKG_USING_SOLAR_TERMS is not set -# CONFIG_PKG_USING_GAN_ZHI is not set -# CONFIG_PKG_USING_FDT is not set -# CONFIG_PKG_USING_CBOX is not set -# CONFIG_PKG_USING_SNOWFLAKE is not set -# CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set -# CONFIG_PKG_USING_VOFA_PLUS is not set -# CONFIG_PKG_USING_RT_TRACE is not set -# CONFIG_PKG_USING_ZDEBUG is not set -# CONFIG_PKG_USING_RVBACKTRACE is not set -# CONFIG_PKG_USING_HPATCHLITE is not set -# CONFIG_PKG_USING_THREAD_METRIC is not set -# end of tools packages - -# -# system packages -# - -# -# enhanced kernel services -# -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set -# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# end of enhanced kernel services - -# CONFIG_PKG_USING_AUNITY is not set - -# -# acceleration: Assembly language or algorithmic acceleration packages -# -# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set -# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set -# CONFIG_PKG_USING_QFPLIB_M3 is not set -# end of acceleration: Assembly language or algorithmic acceleration packages - -# -# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard -# -# CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_CORE is not set -# CONFIG_PKG_USING_CMSIS_NN is not set -# CONFIG_PKG_USING_CMSIS_RTOS1 is not set -# CONFIG_PKG_USING_CMSIS_RTOS2 is not set -# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard - -# -# Micrium: Micrium software products porting for RT-Thread -# -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UCOSII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set -# CONFIG_PKG_USING_UC_MODBUS is not set -# end of Micrium: Micrium software products porting for RT-Thread - -# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set -# CONFIG_PKG_USING_LITEOS_SDK is not set -# CONFIG_PKG_USING_TZ_DATABASE is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_PERF_COUNTER is not set -# CONFIG_PKG_USING_FILEX is not set -# CONFIG_PKG_USING_LEVELX is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_DFS_JFFS2 is not set -# CONFIG_PKG_USING_DFS_UFFS is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_PPOOL is not set -# CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_RPMSG_LITE is not set -# CONFIG_PKG_USING_LPM is not set -# CONFIG_PKG_USING_TLSF is not set -# CONFIG_PKG_USING_EVENT_RECORDER is not set -# CONFIG_PKG_USING_ARM_2D is not set -# CONFIG_PKG_USING_MCUBOOT is not set -# CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_KMULTI_RTIMER is not set -# CONFIG_PKG_USING_TFDB is not set -# CONFIG_PKG_USING_QPC is not set -# CONFIG_PKG_USING_AGILE_UPGRADE is not set -# CONFIG_PKG_USING_FLASH_BLOB is not set -# CONFIG_PKG_USING_MLIBC is not set -# CONFIG_PKG_USING_TASK_MSG_BUS is not set -# CONFIG_PKG_USING_UART_FRAMEWORK is not set -# CONFIG_PKG_USING_SFDB is not set -# CONFIG_PKG_USING_RTP is not set -# CONFIG_PKG_USING_REB is not set -# CONFIG_PKG_USING_RMP is not set -# CONFIG_PKG_USING_R_RHEALSTONE is not set -# CONFIG_PKG_USING_HEARTBEAT is not set -# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set -# end of system packages - -# -# peripheral libraries and drivers -# - -# -# HAL & SDK Drivers -# - -# -# STM32 HAL & SDK Drivers -# -# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set -# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set -# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set -# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set -# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set -# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set -# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set -# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set -# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set -# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set -# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set -# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set -# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set -# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set -# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set -# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set -# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set -# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set -# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set -# end of STM32 HAL & SDK Drivers - -# -# Infineon HAL Packages -# -# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set -# CONFIG_PKG_USING_INFINEON_CMSIS is not set -# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set -# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set -# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set -# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set -# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set -# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set -# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set -# CONFIG_PKG_USING_INFINEON_USBDEV is not set -# end of Infineon HAL Packages - -# CONFIG_PKG_USING_BLUETRUM_SDK is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_ESP_IDF is not set - -# -# Kendryte SDK -# -# CONFIG_PKG_USING_K210_SDK is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# end of Kendryte SDK - -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set - -# -# WCH HAL & SDK Drivers -# -# CONFIG_PKG_USING_CH32V20x_SDK is not set -# CONFIG_PKG_USING_CH32V307_SDK is not set -# end of WCH HAL & SDK Drivers - -# -# AT32 HAL & SDK Drivers -# -# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set -# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set -# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set -# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set -# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set -# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set -# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set -# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set -# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set -# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set -# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set -# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set -# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set -# end of AT32 HAL & SDK Drivers - -# -# HC32 DDL Drivers -# -# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set -# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set -# end of HC32 DDL Drivers - -# -# NXP HAL & SDK Drivers -# -CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER=y -CONFIG_PKG_NXP_MCX_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/nxp/nxp-mcx-cmsis" -CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER_LATEST_VERSION=y -CONFIG_PKG_NXP_MCX_CMSIS_DRIVER_VER="latest" -CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER=y -CONFIG_PKG_NXP_MCX_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/nxp/nxp-mcx-series" -CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER_LATEST_VERSION=y -CONFIG_PKG_NXP_MCX_SERIES_DRIVER_VER="latest" -# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set -# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set -# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set -# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set -# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set -# end of NXP HAL & SDK Drivers - -# -# NUVOTON Drivers -# -# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set -# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set -# end of NUVOTON Drivers - -# -# GD32 Drivers -# -# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set -# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set -# end of GD32 Drivers -# end of HAL & SDK Drivers - -# -# sensors drivers -# -# CONFIG_PKG_USING_LSM6DSM is not set -# CONFIG_PKG_USING_LSM6DSL is not set -# CONFIG_PKG_USING_LPS22HB is not set -# CONFIG_PKG_USING_HTS221 is not set -# CONFIG_PKG_USING_LSM303AGR is not set -# CONFIG_PKG_USING_BME280 is not set -# CONFIG_PKG_USING_BME680 is not set -# CONFIG_PKG_USING_BMA400 is not set -# CONFIG_PKG_USING_BMI160_BMX160 is not set -# CONFIG_PKG_USING_SPL0601 is not set -# CONFIG_PKG_USING_MS5805 is not set -# CONFIG_PKG_USING_DA270 is not set -# CONFIG_PKG_USING_DF220 is not set -# CONFIG_PKG_USING_HSHCAL001 is not set -# CONFIG_PKG_USING_BH1750 is not set -# CONFIG_PKG_USING_MPU6XXX is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set -# CONFIG_PKG_USING_TSL4531 is not set -# CONFIG_PKG_USING_DS18B20 is not set -# CONFIG_PKG_USING_DHT11 is not set -# CONFIG_PKG_USING_DHTXX is not set -# CONFIG_PKG_USING_GY271 is not set -# CONFIG_PKG_USING_GP2Y10 is not set -# CONFIG_PKG_USING_SGP30 is not set -# CONFIG_PKG_USING_HDC1000 is not set -# CONFIG_PKG_USING_BMP180 is not set -# CONFIG_PKG_USING_BMP280 is not set -# CONFIG_PKG_USING_SHTC1 is not set -# CONFIG_PKG_USING_BMI088 is not set -# CONFIG_PKG_USING_HMC5883 is not set -# CONFIG_PKG_USING_MAX6675 is not set -# CONFIG_PKG_USING_MAX31855 is not set -# CONFIG_PKG_USING_TMP1075 is not set -# CONFIG_PKG_USING_SR04 is not set -# CONFIG_PKG_USING_CCS811 is not set -# CONFIG_PKG_USING_PMSXX is not set -# CONFIG_PKG_USING_RT3020 is not set -# CONFIG_PKG_USING_MLX90632 is not set -# CONFIG_PKG_USING_MLX90382 is not set -# CONFIG_PKG_USING_MLX90393 is not set -# CONFIG_PKG_USING_MLX90392 is not set -# CONFIG_PKG_USING_MLX90394 is not set -# CONFIG_PKG_USING_MLX90397 is not set -# CONFIG_PKG_USING_MS5611 is not set -# CONFIG_PKG_USING_MAX31865 is not set -# CONFIG_PKG_USING_VL53L0X is not set -# CONFIG_PKG_USING_INA260 is not set -# CONFIG_PKG_USING_MAX30102 is not set -# CONFIG_PKG_USING_INA226 is not set -# CONFIG_PKG_USING_LIS2DH12 is not set -# CONFIG_PKG_USING_HS300X is not set -# CONFIG_PKG_USING_ZMOD4410 is not set -# CONFIG_PKG_USING_ISL29035 is not set -# CONFIG_PKG_USING_MMC3680KJ is not set -# CONFIG_PKG_USING_QMP6989 is not set -# CONFIG_PKG_USING_BALANCE is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_SHT4X is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_ADT74XX is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_AS7341 is not set -# CONFIG_PKG_USING_CW2015 is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_PAJ7620 is not set -# CONFIG_PKG_USING_STHS34PF80 is not set -# CONFIG_PKG_USING_P3T1755 is not set -# CONFIG_PKG_USING_QMI8658 is not set -# CONFIG_PKG_USING_ICM20948 is not set -# end of sensors drivers - -# -# touch drivers -# -# CONFIG_PKG_USING_GT9147 is not set -# CONFIG_PKG_USING_GT1151 is not set -# CONFIG_PKG_USING_GT917S is not set -# CONFIG_PKG_USING_GT911 is not set -# CONFIG_PKG_USING_FT6206 is not set -# CONFIG_PKG_USING_FT5426 is not set -# CONFIG_PKG_USING_FT6236 is not set -# CONFIG_PKG_USING_XPT2046_TOUCH is not set -# CONFIG_PKG_USING_CST816X is not set -# CONFIG_PKG_USING_CST812T is not set -# end of touch drivers - -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_MULTI_INFRARED is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_ILI9341 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_RPLIDAR is not set -# CONFIG_PKG_USING_AS608 is not set -# CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set -# CONFIG_PKG_USING_MULTI_RTIMER is not set -# CONFIG_PKG_USING_MAX7219 is not set -# CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_EASYBLINK is not set -# CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set -# CONFIG_PKG_USING_LD3320 is not set -# CONFIG_PKG_USING_WK2124 is not set -# CONFIG_PKG_USING_LY68L6400 is not set -# CONFIG_PKG_USING_DM9051 is not set -# CONFIG_PKG_USING_SSD1306 is not set -# CONFIG_PKG_USING_QKEY is not set -# CONFIG_PKG_USING_RS485 is not set -# CONFIG_PKG_USING_RS232 is not set -# CONFIG_PKG_USING_NES is not set -# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set -# CONFIG_PKG_USING_VDEVICE is not set -# CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_RDA58XX is not set -# CONFIG_PKG_USING_LIBNFC is not set -# CONFIG_PKG_USING_MFOC is not set -# CONFIG_PKG_USING_TMC51XX is not set -# CONFIG_PKG_USING_TCA9534 is not set -# CONFIG_PKG_USING_KOBUKI is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_MICRO_ROS is not set -# CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_MISAKA_AT24CXX is not set -# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set -# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_SOFT_SERIAL is not set -# CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_RFM300 is not set -# CONFIG_PKG_USING_IO_INPUT_FILTER is not set -# CONFIG_PKG_USING_LRF_NV7LIDAR is not set -# CONFIG_PKG_USING_AIP650 is not set -# CONFIG_PKG_USING_FINGERPRINT is not set -# CONFIG_PKG_USING_BT_ECB02C is not set -# CONFIG_PKG_USING_UAT is not set -# CONFIG_PKG_USING_ST7789 is not set -# CONFIG_PKG_USING_VS1003 is not set -# CONFIG_PKG_USING_X9555 is not set -# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set -# CONFIG_PKG_USING_BT_MX01 is not set -# CONFIG_PKG_USING_RGPOWER is not set -# CONFIG_PKG_USING_BT_MX02 is not set -# CONFIG_PKG_USING_GC9A01 is not set -# CONFIG_PKG_USING_IK485 is not set -# CONFIG_PKG_USING_SERVO is not set -# CONFIG_PKG_USING_SEAN_WS2812B is not set -# CONFIG_PKG_USING_IC74HC165 is not set -# CONFIG_PKG_USING_IST8310 is not set -# CONFIG_PKG_USING_ST7789_SPI is not set -# CONFIG_PKG_USING_SPI_TOOLS is not set -# end of peripheral libraries and drivers - -# -# AI packages -# -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_QUEST is not set -# CONFIG_PKG_USING_NAXOS is not set -# CONFIG_PKG_USING_R_TINYMAIX is not set -# CONFIG_PKG_USING_LLMCHAT is not set -# end of AI packages - -# -# Signal Processing and Control Algorithm Packages -# -# CONFIG_PKG_USING_APID is not set -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set -# CONFIG_PKG_USING_QPID is not set -# CONFIG_PKG_USING_UKAL is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_KISSFFT is not set -# CONFIG_PKG_USING_CMSIS_DSP is not set -# end of Signal Processing and Control Algorithm Packages - -# -# miscellaneous packages -# - -# -# project laboratory -# -# end of project laboratory - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set -# end of samples: kernel and components samples - -# -# entertainment: terminal games and other interesting software packages -# -# CONFIG_PKG_USING_CMATRIX is not set -# CONFIG_PKG_USING_SL is not set -# CONFIG_PKG_USING_CAL is not set -# CONFIG_PKG_USING_ACLOCK is not set -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_DONUT is not set -# CONFIG_PKG_USING_COWSAY is not set -# CONFIG_PKG_USING_MORSE is not set -# CONFIG_PKG_USING_TINYSQUARE is not set -# end of entertainment: terminal games and other interesting software packages - -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_LZMA is not set -# CONFIG_PKG_USING_RALARAM is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_MINIZIP is not set -# CONFIG_PKG_USING_HEATSHRINK is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_CRCLIB is not set -# CONFIG_PKG_USING_LIBCRC is not set -# CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_STATE_MACHINE is not set -# CONFIG_PKG_USING_DESIGN_PATTERN is not set -# CONFIG_PKG_USING_CONTROLLER is not set -# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set -# CONFIG_PKG_USING_MFBD is not set -# CONFIG_PKG_USING_SLCAN2RTT is not set -# CONFIG_PKG_USING_SOEM is not set -# CONFIG_PKG_USING_QPARAM is not set -# CONFIG_PKG_USING_CorevMCU_CLI is not set -# CONFIG_PKG_USING_DRMP is not set -# end of miscellaneous packages - -# -# Arduino libraries -# -# CONFIG_PKG_USING_RTDUINO is not set - -# -# Projects and Demos -# -# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set -# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set -# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set -# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set -# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set -# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set -# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set -# end of Projects and Demos - -# -# Sensors -# -# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set -# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set -# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set -# end of Sensors - -# -# Display -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_U8G2 is not set -# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set -# CONFIG_PKG_USING_SEEED_TM1637 is not set -# end of Display - -# -# Timing -# -# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set -# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set -# CONFIG_PKG_USING_ARDUINO_TICKER is not set -# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set -# end of Timing - -# -# Data Processing -# -# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set -# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set -# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set -# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set -# end of Data Processing - -# -# Data Storage -# - -# -# Communication -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set -# end of Communication - -# -# Device Control -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set -# end of Device Control - -# -# Other -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set -# end of Other - -# -# Signal IO -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set -# end of Signal IO - -# -# Uncategorized -# -# end of Arduino libraries -# end of RT-Thread online packages - # # Hardware Drivers Config # diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/Kconfig b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/Kconfig index 7c9b35e3cf8..2738f1136a0 100644 --- a/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/Kconfig +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/Kconfig @@ -72,13 +72,17 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_ADC config BSP_USING_ADC - bool "Enable ADC Channel" + bool "Enable ADC" select RT_USING_ADC default y if BSP_USING_ADC - config BSP_USING_ADC0_CH22 - bool "Enable ADC0 Channel22" + config BSP_USING_ADC0 + bool "Enable ADC0" + default n + + config BSP_USING_ADC1 + bool "Enable ADC1" default n endif diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/rtconfig.h b/bsp/nxp/mcx/mcxe/frdm-mcxe247/rtconfig.h index f3c072c2e16..3da4f10d3b9 100644 --- a/bsp/nxp/mcx/mcxe/frdm-mcxe247/rtconfig.h +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/rtconfig.h @@ -427,6 +427,9 @@ #define BSP_USING_PIN #define BSP_USING_UART #define BSP_USING_UART2 +#define BSP_USING_ADC +#define BSP_USING_ADC0 +#define BSP_USING_ADC1 /* end of On-chip Peripheral Drivers */ /* Board extended module Drivers */ From 21d4418d3c7dd096f5f1a5c5ea4f920bf55aa45e Mon Sep 17 00:00:00 2001 From: Yilin Sun Date: Fri, 29 Aug 2025 16:31:45 +0800 Subject: [PATCH 5/7] bsp/nxp/mcx/mcxe: MCXE2: Add WDT driver. Signed-off-by: Yilin Sun --- bsp/nxp/mcx/mcxe/Libraries/drivers/drv_wdt.c | 121 +++++++++++++++++++ bsp/nxp/mcx/mcxe/Libraries/drivers/drv_wdt.h | 19 +++ 2 files changed, 140 insertions(+) create mode 100644 bsp/nxp/mcx/mcxe/Libraries/drivers/drv_wdt.c create mode 100644 bsp/nxp/mcx/mcxe/Libraries/drivers/drv_wdt.h diff --git a/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_wdt.c b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_wdt.c new file mode 100644 index 00000000000..32b2c81efdb --- /dev/null +++ b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_wdt.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-11-25 hywing The first version for NXP MCXA153 Board + */ + +#include +#include "drv_wdt.h" + +#include "fsl_wdog32.h" +#include "fsl_clock.h" + +#ifdef RT_USING_WDT + +#define WDT WDOG +#define WDT_CLOCK_SOURCE kWDOG32_ClockSource1 /* 0: Bus, 1: LPO, 2: SOSC, 3: SIRC */ +#define WDT_CLOCK_SOURCE_FREQ (128 * 1000 / 256) /* 128kHz LPO divided by 256 */ + +#define APP_WDT_IRQn WDOG_EWM_IRQn +#define APP_WDT_IRQ_HANDLER WDOG_EWM_IRQHandler + +struct mcx_wdt +{ + rt_watchdog_t watchdog; + WDOG_Type *wdt_base; +}; + +static struct mcx_wdt wdt_dev; + +void APP_WDT_IRQ_HANDLER(void) +{ + /* ---- There's no WARN feature for WDOG32, will reset. ---- */ + for (;;) + { + } +} + +static rt_err_t wdt_init(rt_watchdog_t *wdt) +{ + wdog32_config_t config; + + WDOG32_GetDefaultConfig(&config); + + config.enableWdog32 = false; + config.clockSource = WDT_CLOCK_SOURCE; + config.prescaler = kWDOG32_ClockPrescalerDivide256; + config.timeoutValue = WDT_CLOCK_SOURCE_FREQ * 5; + config.enableInterrupt = true; + + WDOG32_Init(WDT, &config); + NVIC_EnableIRQ(APP_WDT_IRQn); + + return RT_EOK; +} + +static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg) +{ + /* Feed fast path */ + if (cmd == RT_DEVICE_CTRL_WDT_KEEPALIVE) + { + WDOG32_Refresh(wdt_dev.wdt_base); + return RT_EOK; + } + + __disable_irq(); + WDOG32_Unlock(wdt_dev.wdt_base); + + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_START: + WDOG32_Enable(wdt_dev.wdt_base); + break; + + case RT_DEVICE_CTRL_WDT_STOP: + WDOG32_Disable(wdt_dev.wdt_base); + break; + + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + if (arg != RT_NULL) + { + uint32_t timeout = *((uint32_t *)arg); + timeout = timeout * WDT_CLOCK_SOURCE_FREQ; + WDOG32_SetTimeoutValue(wdt_dev.wdt_base, timeout); + } + break; + + default: + break; + } + + __enable_irq(); + return RT_EOK; +} + +static struct rt_watchdog_ops wdt_ops = + { + wdt_init, + wdt_control, +}; + +int rt_hw_wdt_init(void) +{ + wdt_dev.wdt_base = WDT; + wdt_dev.watchdog.ops = &wdt_ops; + + if (rt_hw_watchdog_register(&wdt_dev.watchdog, "wdt", RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK) + { + rt_kprintf("wdt register failed\n"); + return -RT_ERROR; + } + + return RT_EOK; +} + +INIT_BOARD_EXPORT(rt_hw_wdt_init); + +#endif /* RT_USING_WDT */ diff --git a/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_wdt.h b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_wdt.h new file mode 100644 index 00000000000..4a6e58e822b --- /dev/null +++ b/bsp/nxp/mcx/mcxe/Libraries/drivers/drv_wdt.h @@ -0,0 +1,19 @@ +/* +* Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-11-25 hywing The first version for NXP MCXA153 Board + */ + +#ifndef __DRV_WDT_H__ +#define __DRV_WDT_H__ + +#include +#include + +int rt_hw_wdt_init(void); + +#endif /* __DRV_WDT_H__ */ From d478105c087c6fcf64c51804be86bf22d9806d13 Mon Sep 17 00:00:00 2001 From: Yilin Sun Date: Mon, 1 Sep 2025 15:32:25 +0800 Subject: [PATCH 6/7] ci: Add build for FRDM-MCXE247. Signed-off-by: Yilin Sun --- .github/ALL_BSP_COMPILE.json | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index 496aa9ce064..c6b664bd7b8 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -247,6 +247,7 @@ "nxp/mcx/mcxa/frdm-mcxa153", "nxp/mcx/mcxa/frdm-mcxa156", "nxp/mcx/mcxa/frdm-mcxa346", + "nxp/mcx/mcxe/frdm-mcxe247", "renesas/ebf_qi_min_6m5", "renesas/ra6m4-cpk", "renesas/ra6m4-iot", From aab2b30332e98772e23372d95b2695ddbfb27630 Mon Sep 17 00:00:00 2001 From: yandld <1453363089@qq.com> Date: Tue, 2 Sep 2025 13:53:56 +0800 Subject: [PATCH 7/7] update mcxe247 keil file --- bsp/nxp/mcx/mcxe/frdm-mcxe247/project.uvoptx | 1697 +++++++++ bsp/nxp/mcx/mcxe/frdm-mcxe247/project.uvprojx | 3093 +++++++++++++++++ bsp/nxp/mcx/mcxe/frdm-mcxe247/template.uvoptx | 24 +- .../mcx/mcxe/frdm-mcxe247/template.uvprojx | 68 +- 4 files changed, 4830 insertions(+), 52 deletions(-) create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/project.uvoptx create mode 100644 bsp/nxp/mcx/mcxe/frdm-mcxe247/project.uvprojx diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/project.uvoptx b/bsp/nxp/mcx/mcxe/frdm-mcxe247/project.uvoptx new file mode 100644 index 00000000000..d8f793c2436 --- /dev/null +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/project.uvoptx @@ -0,0 +1,1697 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread-frdm-mcxe247 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD1FFE0000 -FC3F000 -FN1 -FF0MCXE247_P1536_4KB_SEC.FLM -FS00 -FL0180000 -FP0($$Device:MCXE247VLQ$devices\MCXE247\arm\MCXE247_P1536_4KB_SEC.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC3F000 -FN1 -FF0MCXE247_P1536_4KB_SEC -FS00 -FL0180000 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### uVision Project, (C) Keil Software
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packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_ftfx_flexnvm.c + + + fsl_ftm.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_ftm.c + + + fsl_gpio.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_gpio.c + + + fsl_lpi2c.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_lpi2c.c + + + fsl_lpi2c_edma.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_lpi2c_edma.c + + + fsl_lpit.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_lpit.c + + + fsl_lpspi.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_lpspi.c + + + fsl_lpspi_edma.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_lpspi_edma.c + + + fsl_lptmr.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_lptmr.c + + + fsl_lpuart.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_lpuart.c + + + fsl_lpuart_edma.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_lpuart_edma.c + + + fsl_pdb.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_pdb.c + + + fsl_pmc.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_pmc.c + + + fsl_qspi.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_qspi.c + + + fsl_qspi_edma.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_qspi_edma.c + + + fsl_qspi_soc.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_qspi_soc.c + + + fsl_rcm.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_rcm.c + + + fsl_rtc.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_rtc.c + + + fsl_sim.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_sim.c + + + fsl_smc.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_smc.c + + + fsl_sysmpu.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_sysmpu.c + + + fsl_trgmux.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_trgmux.c + + + fsl_wdog32.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\fsl_wdog32.c + + + fsl_cache.c + 1 + packages\nxp-mcx-series-latest\MCXE247\drivers\lmem\fsl_cache.c + + + system_MCXE247.c + 1 + packages\nxp-mcx-series-latest\MCXE247\system_MCXE247.c + + + + + + + + + + + + + + + + + template + 1 + + + + + diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/template.uvoptx b/bsp/nxp/mcx/mcxe/frdm-mcxe247/template.uvoptx index 2ee820b2d82..ee96aa912b6 100644 --- a/bsp/nxp/mcx/mcxe/frdm-mcxe247/template.uvoptx +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/template.uvoptx @@ -22,7 +22,7 @@ - rtthread-frdm-mcxa346 + rtthread-frdm-mcxe247 0x4 ARM-ADS @@ -77,7 +77,7 @@ 0 1 - 8 + 0 0 1 @@ -103,7 +103,7 @@ 1 0 0 - 14 + 0 @@ -114,18 +114,13 @@ - BIN\CMSIS_AGDI_V8M.DLL + BIN\UL2CM3.DLL 0 - CMSIS_AGDI_V8M - -X"Any" -UAny -O206 -S9 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0MCXA34X_1024.FLM -FS00 -FL0FE000 -FP0($$Device:MCXA346VLQ$devices\MCXA346\arm\MCXA34X_1024.FLM) - - - 0 - UL2V8M - UL2V8M(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0MCXA34X_1024 -FL0FE000 -FS00 -FP0($$Device:MCXA346VLQ$devices\MCXA346\arm\MCXA34X_1024.FLM) + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC3F000 -FN1 -FF0MCXE247_P1536_4KB_SEC -FS00 -FL0180000 -FP0($$Device:MCXE247VLQ$devices\MCXE247\arm\MCXE247_P1536_4KB_SEC.FLM)) @@ -171,13 +166,6 @@ - - 1 - 1 - 0 - 2 - 5000000 - diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/template.uvprojx b/bsp/nxp/mcx/mcxe/frdm-mcxe247/template.uvprojx index 5d597a72464..c995c3b4cbe 100644 --- a/bsp/nxp/mcx/mcxe/frdm-mcxe247/template.uvprojx +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/template.uvprojx @@ -7,23 +7,23 @@ - rtthread-frdm-mcxa346 + rtthread-frdm-mcxe247 0x4 ARM-ADS 6230000::V6.23::ARMCLANG 1 - MCXA346VLQ + MCXE247VLQ NXP - NXP.MCXA346_DFP.25.06.00 + NXP.MCXE247_DFP.25.06.00 https://mcuxpresso.nxp.com/cmsis_pack/repo/ - IRAM(0x20000000,0x03c000) IRAM2(0x04000000,0x2000) IROM(0x03000000,0x2000) IROM2(0x00000000,0x0fe000) XRAM(0x04002000,0x2000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP CLOCK(12000000) ELITTLE + IRAM(0x14000000,0x1000) IRAM2(0x1ffe0000,0x020000) IROM(0x10000000,0x080000) IROM2(0x00000000,0x180000) XRAM(0x20000000,0x01f000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0MCXA34X_1024 -FS00 -FL0FE000 -FP0($$Device:MCXA346VLQ$devices\MCXA346\arm\MCXA34X_1024.FLM)) + UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC3F000 -FN1 -FF0MCXE247_P1536_4KB_SEC -FS00 -FL0180000 -FP0($$Device:MCXE247VLQ$devices\MCXE247\arm\MCXE247_P1536_4KB_SEC.FLM)) 0 - $$Device:MCXA346VLQ$devices\MCXA346\fsl_device_registers.h + $$Device:MCXE247VLQ$devices\MCXE247\fsl_device_registers.h @@ -33,7 +33,7 @@ - $$Device:MCXA346VLQ$devices\MCXA346\MCXA346.xml + $$Device:MCXE247VLQ$devices\MCXE247\MCXE247.xml 0 0 @@ -109,14 +109,14 @@ 1 - - - - - SARMV8M.DLL - -MPU + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + TCM.DLL - -pCM33 + -pCM4 @@ -137,7 +137,7 @@ 4102 1 - BIN\UL2V8M.DLL + BIN\UL2CM3.DLL @@ -174,7 +174,7 @@ 1 0 0 - "Cortex-M33" + "Cortex-M4" 0 0 @@ -206,7 +206,7 @@ 0 0 0 - 0 + 1 1 0 0 @@ -246,18 +246,18 @@ 0 - 0x20000000 - 0x3c000 + 0x14000000 + 0x1000 1 - 0x3000000 - 0x2000 + 0x10000000 + 0x80000 1 - 0x4002000 - 0x2000 + 0x20000000 + 0x1f000 1 @@ -276,18 +276,18 @@ 1 - 0x3000000 - 0x2000 + 0x10000000 + 0x80000 1 0x0 - 0xfe000 + 0x180000 0 - 0x4002000 - 0x2000 + 0x20000000 + 0x1f000 0 @@ -301,13 +301,13 @@ 0 - 0x20000000 - 0x3c000 + 0x14000000 + 0x1000 0 - 0x4000000 - 0x2000 + 0x1ffe0000 + 0x20000 @@ -338,7 +338,7 @@ 0 --target=arm-arm-none-eabi - CPU_MCXA346VLQ, ARM_MATH_CM33, RT_USING_ARM_LIBC + CPU_MCXE247VLQ, ARM_MATH_CM4, RT_USING_ARM_LIBC @@ -371,7 +371,7 @@ 0x00000000 0x02000000 - .\board\linker_scripts\MCXA346_flash.scf + .\board\linker_scripts\MCXE247_flash.scf --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)