From 9b0fa149cc261f4ca71f44c6c5c1db445ff6ecca Mon Sep 17 00:00:00 2001 From: MuChenger Date: Thu, 25 Sep 2025 16:06:04 +0800 Subject: [PATCH] =?UTF-8?q?[fix]=20=E4=BD=BF=E8=83=BDGD32H7=20I/D=20Cache?= =?UTF-8?q?=EF=BC=8C=E7=A7=BB=E9=99=A4Systick=E9=87=8D=E5=A4=8D=E9=85=8D?= =?UTF-8?q?=E7=BD=AE=E4=BB=A3=E7=A0=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/gd32/arm/gd32h759i-eval/board/board.c | 7 ++++++- bsp/gd32/arm/gd32h759i-start/board/board.c | 7 ++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/bsp/gd32/arm/gd32h759i-eval/board/board.c b/bsp/gd32/arm/gd32h759i-eval/board/board.c index 4a863c54791..8243e5e8c40 100644 --- a/bsp/gd32/arm/gd32h759i-eval/board/board.c +++ b/bsp/gd32/arm/gd32h759i-eval/board/board.c @@ -32,7 +32,6 @@ void Error_Handler(void) void SystemClock_Config(void) { SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - NVIC_SetPriority(SysTick_IRQn, 0); } /** @@ -65,6 +64,12 @@ void rt_hw_board_init() SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK); #endif + /* Enable IChace */ + rt_hw_cpu_icache_enable(); + + /* Enable DChace */ + rt_hw_cpu_dcache_enable(); + SystemClock_Config(); #ifdef RT_USING_SERIAL diff --git a/bsp/gd32/arm/gd32h759i-start/board/board.c b/bsp/gd32/arm/gd32h759i-start/board/board.c index 3ac8899e818..cc43ed08eed 100644 --- a/bsp/gd32/arm/gd32h759i-start/board/board.c +++ b/bsp/gd32/arm/gd32h759i-start/board/board.c @@ -32,7 +32,6 @@ void Error_Handler(void) void SystemClock_Config(void) { SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - NVIC_SetPriority(SysTick_IRQn, 0); } /** @@ -65,6 +64,12 @@ void rt_hw_board_init() SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK); #endif + /* Enable IChace */ + rt_hw_cpu_icache_enable(); + + /* Enable DChace */ + rt_hw_cpu_dcache_enable(); + SystemClock_Config(); #ifdef RT_USING_SERIAL