From 5768c9fec2116f2982b763e1fbd75b798ab02c1c Mon Sep 17 00:00:00 2001 From: kurisaw <2053731441@qq.com> Date: Thu, 13 Nov 2025 17:14:11 +0800 Subject: [PATCH 1/3] [gd32/arm][drivers]: add support for the H7 series and optimize the GPIO driver --- .../arm/libraries/gd32_drivers/drv_gpio.c | 380 +++++++++++++----- .../arm/libraries/gd32_drivers/drv_gpio.h | 11 +- 2 files changed, 285 insertions(+), 106 deletions(-) diff --git a/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.c b/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.c index cb43335dea1..01e800cb844 100644 --- a/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.c +++ b/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.c @@ -6,29 +6,30 @@ * Change Logs: * Date Author Notes * 2021-08-20 BruceOu the first version + * 2025-11-13 RealThread general GD driver adaptation */ #include #include #include +#include #ifdef RT_USING_PIN #include "drv_gpio.h" -static const struct pin_index pins[] = -{ +static const struct pin_index pins[] = { #ifdef GPIOA - GD32_PIN(0, A, 0), - GD32_PIN(1, A, 1), - GD32_PIN(2, A, 2), - GD32_PIN(3, A, 3), - GD32_PIN(4, A, 4), - GD32_PIN(5, A, 5), - GD32_PIN(6, A, 6), - GD32_PIN(7, A, 7), - GD32_PIN(8, A, 8), - GD32_PIN(9, A, 9), + GD32_PIN(0, A, 0), + GD32_PIN(1, A, 1), + GD32_PIN(2, A, 2), + GD32_PIN(3, A, 3), + GD32_PIN(4, A, 4), + GD32_PIN(5, A, 5), + GD32_PIN(6, A, 6), + GD32_PIN(7, A, 7), + GD32_PIN(8, A, 8), + GD32_PIN(9, A, 9), GD32_PIN(10, A, 10), GD32_PIN(11, A, 11), GD32_PIN(12, A, 12), @@ -183,65 +184,62 @@ static const struct pin_index pins[] = }; #if defined SOC_SERIES_GD32E23x -static const struct pin_irq_map pin_irq_map[] = -{ - {GPIO_PIN_0, EXTI0_1_IRQn}, - {GPIO_PIN_1, EXTI0_1_IRQn}, - {GPIO_PIN_2, EXTI2_3_IRQn}, - {GPIO_PIN_3, EXTI2_3_IRQn}, - {GPIO_PIN_4, EXTI4_15_IRQn}, - {GPIO_PIN_5, EXTI4_15_IRQn}, - {GPIO_PIN_6, EXTI4_15_IRQn}, - {GPIO_PIN_7, EXTI4_15_IRQn}, - {GPIO_PIN_8, EXTI4_15_IRQn}, - {GPIO_PIN_9, EXTI4_15_IRQn}, - {GPIO_PIN_10, EXTI4_15_IRQn}, - {GPIO_PIN_11, EXTI4_15_IRQn}, - {GPIO_PIN_12, EXTI4_15_IRQn}, - {GPIO_PIN_13, EXTI4_15_IRQn}, - {GPIO_PIN_14, EXTI4_15_IRQn}, - {GPIO_PIN_15, EXTI4_15_IRQn}, +static const struct pin_irq_map pin_irq_map[] = { + { GPIO_PIN_0, EXTI0_1_IRQn }, + { GPIO_PIN_1, EXTI0_1_IRQn }, + { GPIO_PIN_2, EXTI2_3_IRQn }, + { GPIO_PIN_3, EXTI2_3_IRQn }, + { GPIO_PIN_4, EXTI4_15_IRQn }, + { GPIO_PIN_5, EXTI4_15_IRQn }, + { GPIO_PIN_6, EXTI4_15_IRQn }, + { GPIO_PIN_7, EXTI4_15_IRQn }, + { GPIO_PIN_8, EXTI4_15_IRQn }, + { GPIO_PIN_9, EXTI4_15_IRQn }, + { GPIO_PIN_10, EXTI4_15_IRQn }, + { GPIO_PIN_11, EXTI4_15_IRQn }, + { GPIO_PIN_12, EXTI4_15_IRQn }, + { GPIO_PIN_13, EXTI4_15_IRQn }, + { GPIO_PIN_14, EXTI4_15_IRQn }, + { GPIO_PIN_15, EXTI4_15_IRQn }, }; #else -static const struct pin_irq_map pin_irq_map[] = -{ - {GPIO_PIN_0, EXTI0_IRQn}, - {GPIO_PIN_1, EXTI1_IRQn}, - {GPIO_PIN_2, EXTI2_IRQn}, - {GPIO_PIN_3, EXTI3_IRQn}, - {GPIO_PIN_4, EXTI4_IRQn}, - {GPIO_PIN_5, EXTI5_9_IRQn}, - {GPIO_PIN_6, EXTI5_9_IRQn}, - {GPIO_PIN_7, EXTI5_9_IRQn}, - {GPIO_PIN_8, EXTI5_9_IRQn}, - {GPIO_PIN_9, EXTI5_9_IRQn}, - {GPIO_PIN_10, EXTI10_15_IRQn}, - {GPIO_PIN_11, EXTI10_15_IRQn}, - {GPIO_PIN_12, EXTI10_15_IRQn}, - {GPIO_PIN_13, EXTI10_15_IRQn}, - {GPIO_PIN_14, EXTI10_15_IRQn}, - {GPIO_PIN_15, EXTI10_15_IRQn}, +static const struct pin_irq_map pin_irq_map[] = { + { GPIO_PIN_0, EXTI0_IRQn }, + { GPIO_PIN_1, EXTI1_IRQn }, + { GPIO_PIN_2, EXTI2_IRQn }, + { GPIO_PIN_3, EXTI3_IRQn }, + { GPIO_PIN_4, EXTI4_IRQn }, + { GPIO_PIN_5, EXTI5_9_IRQn }, + { GPIO_PIN_6, EXTI5_9_IRQn }, + { GPIO_PIN_7, EXTI5_9_IRQn }, + { GPIO_PIN_8, EXTI5_9_IRQn }, + { GPIO_PIN_9, EXTI5_9_IRQn }, + { GPIO_PIN_10, EXTI10_15_IRQn }, + { GPIO_PIN_11, EXTI10_15_IRQn }, + { GPIO_PIN_12, EXTI10_15_IRQn }, + { GPIO_PIN_13, EXTI10_15_IRQn }, + { GPIO_PIN_14, EXTI10_15_IRQn }, + { GPIO_PIN_15, EXTI10_15_IRQn }, }; #endif -struct rt_pin_irq_hdr pin_irq_hdr_tab[] = -{ - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = { + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, }; #define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) @@ -259,7 +257,7 @@ const struct pin_index *get_pin(rt_uint8_t pin) { index = &pins[pin]; if (index->index == -1) - index = RT_NULL; + index = RT_NULL; } else { @@ -269,6 +267,175 @@ const struct pin_index *get_pin(rt_uint8_t pin) return index; } +int get_pin_config(const char *pin_name, uint32_t *port, uint32_t *pin, rcu_periph_enum *clk) +{ + if (pin_name == NULL || port == NULL || pin == NULL || clk == NULL) + { + return -RT_ERROR; + } + + if (rt_strlen(pin_name) < 3 || pin_name[0] != 'P') + { + return -RT_ERROR; + } + + char port_letter = pin_name[1]; + switch (port_letter) + { +#ifdef GPIOA + case 'A': + *port = GPIOA; + *clk = RCU_GPIOA; + break; +#endif /* GPIOA */ +#ifdef GPIOB + case 'B': + *port = GPIOB; + *clk = RCU_GPIOB; + break; +#endif /* GPIOB */ +#ifdef GPIOC + case 'C': + *port = GPIOC; + *clk = RCU_GPIOC; + break; +#endif /* GPIOC */ +#ifdef GPIOD + case 'D': + *port = GPIOD; + *clk = RCU_GPIOD; + break; +#endif /* GPIOD */ +#ifdef GPIOE + case 'E': + *port = GPIOE; + *clk = RCU_GPIOE; + break; +#endif /* GPIOE */ +#ifdef GPIOF + case 'F': + *port = GPIOF; + *clk = RCU_GPIOF; + break; +#endif /* GPIOF */ +#ifdef GPIOG + case 'G': + *port = GPIOG; + *clk = RCU_GPIOG; + break; +#endif /* GPIOG */ +#ifdef GPIOH + case 'H': + *port = GPIOH; + *clk = RCU_GPIOH; + break; +#endif /* GPIOH */ +#ifdef GPIOI + case 'I': + *port = GPIOI; + *clk = RCU_GPIOI; + break; +#endif /* GPIOI */ +#ifdef GPIOJ + case 'J': + *port = GPIOJ; + *clk = RCU_GPIOJ; + break; +#endif /* GPIOJ */ +#ifdef GPIOK + case 'K': + *port = GPIOK; + *clk = RCU_GPIOK; + break; +#endif /* GPIOK */ + default: + return -RT_ERROR; + } + + int pin_num = atoi(pin_name + 2); + if (pin_num < 0 || pin_num > 15) + { + return -RT_ERROR; + } + *pin = GPIO_PIN_0 << pin_num; + + return 0; +} + +int pin_alternate_config(const char *alternate, uint32_t *af) +{ + if (alternate == NULL || af == NULL) + { + return -RT_ERROR; + } + + if (alternate[0] != 'A' || alternate[1] != 'F') + { + return -RT_ERROR; + } + + int af_num = atoi(alternate + 2); + if (af_num < 0 || af_num > 15) + { + return -RT_ERROR; + } + + switch (af_num) + { +#ifdef GPIO_AF_0 + case 0: *af = GPIO_AF_0; break; +#endif /* GPIO_AF_0 */ +#ifdef GPIO_AF_1 + case 1: *af = GPIO_AF_1; break; +#endif /* GPIO_AF_1 */ +#ifdef GPIO_AF_2 + case 2: *af = GPIO_AF_2; break; +#endif /* GPIO_AF_2 */ +#ifdef GPIO_AF_3 + case 3: *af = GPIO_AF_3; break; +#endif /* GPIO_AF_3 */ +#ifdef GPIO_AF_4 + case 4: *af = GPIO_AF_4; break; +#endif /* GPIO_AF_4 */ +#ifdef GPIO_AF_5 + case 5: *af = GPIO_AF_5; break; +#endif /* GPIO_AF_5 */ +#ifdef GPIO_AF_6 + case 6: *af = GPIO_AF_6; break; +#endif /* GPIO_AF_6 */ +#ifdef GPIO_AF_7 + case 7: *af = GPIO_AF_7; break; +#endif /* GPIO_AF_7 */ +#ifdef GPIO_AF_8 + case 8: *af = GPIO_AF_8; break; +#endif /* GPIO_AF_8 */ +#ifdef GPIO_AF_9 + case 9: *af = GPIO_AF_9; break; +#endif /* GPIO_AF_9 */ +#ifdef GPIO_AF_10 + case 10: *af = GPIO_AF_10; break; +#endif /* GPIO_AF_10 */ +#ifdef GPIO_AF_11 + case 11: *af = GPIO_AF_11; break; +#endif /* GPIO_AF_11 */ +#ifdef GPIO_AF_12 + case 12: *af = GPIO_AF_12; break; +#endif /* GPIO_AF_12 */ +#ifdef GPIO_AF_13 + case 13: *af = GPIO_AF_13; break; +#endif /* GPIO_AF_13 */ +#ifdef GPIO_AF_14 + case 14: *af = GPIO_AF_14; break; +#endif /* GPIO_AF_14 */ +#ifdef GPIO_AF_15 + case 15: *af = GPIO_AF_15; break; +#endif /* GPIO_AF_15 */ + default: return -1; + } + + return 0; +} + /** * @brief set pin mode * @param dev, pin, mode @@ -279,8 +446,8 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) const struct pin_index *index = RT_NULL; rt_uint32_t pin_mode = 0; -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x - rt_uint32_t pin_pupd = 0, pin_odpp = 0; +#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x + rt_uint32_t pin_pupd = 0, pin_odpp = 0; #endif index = get_pin(pin); @@ -291,17 +458,17 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) /* GPIO Periph clock enable */ rcu_periph_clock_enable(index->clk); -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x - pin_mode = GPIO_MODE_OUTPUT; +#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x + pin_mode = GPIO_MODE_OUTPUT; #else pin_mode = GPIO_MODE_OUT_PP; #endif - switch(mode) + switch (mode) { case PIN_MODE_OUTPUT: /* output setting */ -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x +#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x pin_mode = GPIO_MODE_OUTPUT; pin_pupd = GPIO_PUPD_NONE; pin_odpp = GPIO_OTYPE_PP; @@ -311,7 +478,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) break; case PIN_MODE_OUTPUT_OD: /* output setting: od. */ -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x +#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x pin_mode = GPIO_MODE_OUTPUT; pin_pupd = GPIO_PUPD_NONE; pin_odpp = GPIO_OTYPE_OD; @@ -321,7 +488,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) break; case PIN_MODE_INPUT: /* input setting: not pull. */ -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x +#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x pin_mode = GPIO_MODE_INPUT; pin_pupd = GPIO_PUPD_PULLUP | GPIO_PUPD_PULLDOWN; #else @@ -330,7 +497,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) break; case PIN_MODE_INPUT_PULLUP: /* input setting: pull up. */ -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x +#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x pin_mode = GPIO_MODE_INPUT; pin_pupd = GPIO_PUPD_PULLUP; #else @@ -339,7 +506,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) break; case PIN_MODE_INPUT_PULLDOWN: /* input setting: pull down. */ -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x +#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x pin_mode = GPIO_MODE_INPUT; pin_pupd = GPIO_PUPD_PULLDOWN; #else @@ -347,23 +514,23 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) #endif break; default: - break; + break; } #if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x gpio_mode_set(index->gpio_periph, pin_mode, pin_pupd, index->pin); - if(pin_mode == GPIO_MODE_OUTPUT) + if (pin_mode == GPIO_MODE_OUTPUT) { gpio_output_options_set(index->gpio_periph, pin_odpp, GPIO_OSPEED_50MHZ, index->pin); } -#elif defined SOC_SERIES_GD32H7xx +#elif defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E gpio_mode_set(index->gpio_periph, pin_mode, pin_pupd, index->pin); - if(pin_mode == GPIO_MODE_OUTPUT) + if (pin_mode == GPIO_MODE_OUTPUT) { gpio_output_options_set(index->gpio_periph, pin_odpp, GPIO_OSPEED_60MHZ, index->pin); } #else - gpio_init(index->gpio_periph, pin_mode, GPIO_OSPEED_50MHZ, index->pin); + gpio_init(index->gpio_periph, pin_mode, GPIO_OSPEED_50MHZ, index->pin); #endif } @@ -444,7 +611,7 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit) * @retval None */ static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_base_t pin, - rt_uint8_t mode, void (*hdr)(void *args), void *args) + rt_uint8_t mode, void (*hdr)(void *args), void *args) { const struct pin_index *index = RT_NULL; rt_base_t level; @@ -562,21 +729,21 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_ switch (pin_irq_hdr_tab[hdr_index].mode) { - case PIN_IRQ_MODE_RISING: - trigger_mode = EXTI_TRIG_RISING; - break; - case PIN_IRQ_MODE_FALLING: - trigger_mode = EXTI_TRIG_FALLING; - break; - case PIN_IRQ_MODE_RISING_FALLING: - trigger_mode = EXTI_TRIG_BOTH; - break; - default: - rt_hw_interrupt_enable(level); - return -RT_EINVAL; + case PIN_IRQ_MODE_RISING: + trigger_mode = EXTI_TRIG_RISING; + break; + case PIN_IRQ_MODE_FALLING: + trigger_mode = EXTI_TRIG_FALLING; + break; + case PIN_IRQ_MODE_RISING_FALLING: + trigger_mode = EXTI_TRIG_BOTH; + break; + default: + rt_hw_interrupt_enable(level); + return -RT_EINVAL; } -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx +#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32F5xx rcu_periph_clock_enable(RCU_SYSCFG); #elif defined SOC_SERIES_GD32E23x rcu_periph_clock_enable(RCU_CFGCMP); @@ -591,15 +758,15 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_ nvic_irq_enable(irqmap->irqno, 5U, 0U); #endif /* connect EXTI line to GPIO pin */ -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x +#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x syscfg_exti_line_config(index->port_src, index->pin_src); #else gpio_exti_source_select(index->port_src, index->pin_src); #endif /* configure EXTI line */ - exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode); - exti_interrupt_flag_clear((exti_line_enum)(index->pin)); + exti_init((exti_line_enum)(index->exit_line), EXTI_INTERRUPT, trigger_mode); + exti_interrupt_flag_clear((exti_line_enum)(index->exit_line)); rt_hw_interrupt_enable(level); } @@ -620,13 +787,12 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_ return RT_EOK; } -const static struct rt_pin_ops gd32_pin_ops = -{ +const static struct rt_pin_ops gd32_pin_ops = { .pin_mode = gd32_pin_mode, .pin_write = gd32_pin_write, .pin_read = gd32_pin_read, .pin_attach_irq = gd32_pin_attach_irq, - .pin_detach_irq= gd32_pin_detach_irq, + .pin_detach_irq = gd32_pin_detach_irq, .pin_irq_enable = gd32_pin_irq_enable, RT_NULL, }; @@ -651,10 +817,16 @@ rt_inline void pin_irq_hdr(int irqno) */ void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line) { - if(RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line))) +#if defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E) + exti_line_enum pin_exti_line = exti_line; +#else + exti_line_enum pin_exti_line = 1 << exti_line; +#endif + + if (RESET != exti_interrupt_flag_get(pin_exti_line)) { pin_irq_hdr(exti_line); - exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line)); + exti_interrupt_flag_clear(pin_exti_line); } } diff --git a/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.h b/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.h index 7e31b6c72d1..a79efc7d9c6 100644 --- a/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.h +++ b/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.h @@ -29,6 +29,8 @@ extern "C" { #include "gd32f4xx_gpio.h" #elif defined SOC_SERIES_GD32H7xx #include "gd32h7xx_gpio.h" +#elif defined SOC_SERIES_GD32H75e +#include "gd32h75e_gpio.h" #elif defined SOC_SERIES_GD32E50x #include "gd32e50x_gpio.h" #elif defined SOC_SERIES_GD32F5xx @@ -39,11 +41,12 @@ extern "C" { #define __GD32_PORT(port) GPIO##port -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x +#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32H7xx #define GD32_PIN(index, port, pin) {index, RCU_GPIO##port, \ GPIO##port, GPIO_PIN_##pin, \ EXTI_SOURCE_GPIO##port, \ - EXTI_SOURCE_PIN##pin} + EXTI_SOURCE_PIN##pin, \ + EXTI_##pin} #else #define GD32_PIN(index, port, pin) {index, RCU_GPIO##port, \ GPIO##port, GPIO_PIN_##pin, \ @@ -70,6 +73,7 @@ struct pin_index rt_uint32_t pin; rt_uint8_t port_src; rt_uint8_t pin_src; + rt_uint32_t exit_line; }; struct pin_irq_map @@ -78,6 +82,9 @@ struct pin_irq_map IRQn_Type irqno; }; +int get_pin_config(const char *pin_name, uint32_t *port, uint32_t *pin, rcu_periph_enum *clk); +int pin_alternate_config(const char *alternate, uint32_t *af); + #ifdef __cplusplus } #endif From 011133788add8147ca9ff008fbb725e12f1a1956 Mon Sep 17 00:00:00 2001 From: kurisaw <2053731441@qq.com> Date: Fri, 14 Nov 2025 10:44:21 +0800 Subject: [PATCH 2/3] [gd32/arm][drivers]: general GD serial driver adapter --- .../arm/libraries/gd32_drivers/SConscript | 1 + .../gd32_drivers/config/uart_config.h | 155 +++++++ .../arm/libraries/gd32_drivers/drv_usart.c | 382 +++++------------- .../arm/libraries/gd32_drivers/drv_usart.h | 39 +- 4 files changed, 267 insertions(+), 310 deletions(-) create mode 100644 bsp/gd32/arm/libraries/gd32_drivers/config/uart_config.h diff --git a/bsp/gd32/arm/libraries/gd32_drivers/SConscript b/bsp/gd32/arm/libraries/gd32_drivers/SConscript index 5d3a2a85de3..31a8d4458d7 100644 --- a/bsp/gd32/arm/libraries/gd32_drivers/SConscript +++ b/bsp/gd32/arm/libraries/gd32_drivers/SConscript @@ -65,6 +65,7 @@ if GetDepend('BSP_USING_SDRAM'): src += ['drv_sdram.c'] path = [cwd] +path += [cwd + "/config"] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) diff --git a/bsp/gd32/arm/libraries/gd32_drivers/config/uart_config.h b/bsp/gd32/arm/libraries/gd32_drivers/config/uart_config.h new file mode 100644 index 00000000000..4185e99762b --- /dev/null +++ b/bsp/gd32/arm/libraries/gd32_drivers/config/uart_config.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-10-09 WangShun optimize the serial driver + * 2025-11-13 kurisaw general GD driver adaptation + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_USING_UART0) +#ifndef UART0_CONFIG +#define UART0_CONFIG \ + { \ + .uart_periph = USART0, \ + .irqn = USART0_IRQn, \ + .per_clk = RCU_USART0, \ + .tx_pin_name = BSP_UART0_TX_PIN, \ + .rx_pin_name = BSP_UART0_RX_PIN, \ + .alternate = BSP_UART0_AFIO, \ + .serial = &serial0, \ + .device_name = "uart0", \ + } +#endif /* UART0_CONFIG */ +#endif /* BSP_USING_UART0 */ + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .uart_periph = USART1, \ + .irqn = USART1_IRQn, \ + .per_clk = RCU_USART1, \ + .tx_pin_name = BSP_UART1_TX_PIN, \ + .rx_pin_name = BSP_UART1_RX_PIN, \ + .alternate = BSP_UART1_AFIO, \ + .serial = &serial1, \ + .device_name = "uart1", \ + } +#endif /* UART1_CONFIG */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .uart_periph = USART2, \ + .irqn = USART2_IRQn, \ + .per_clk = RCU_USART2, \ + .tx_pin_name = BSP_UART2_TX_PIN, \ + .rx_pin_name = BSP_UART2_RX_PIN, \ + .alternate = BSP_UART2_AFIO, \ + .serial = &serial2, \ + .device_name = "uart2", \ + } +#endif /* UART2_CONFIG */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .uart_periph = UART3, \ + .irqn = UART3_IRQn, \ + .per_clk = RCU_UART3, \ + .tx_pin_name = BSP_UART3_TX_PIN, \ + .rx_pin_name = BSP_UART3_RX_PIN, \ + .alternate = BSP_UART3_AFIO, \ + .serial = &serial3, \ + .device_name = "uart3", \ + } +#endif /* UART3_CONFIG */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .uart_periph = UART4, \ + .irqn = UART4_IRQn, \ + .per_clk = RCU_UART4, \ + .tx_pin_name = BSP_UART4_TX_PIN, \ + .rx_pin_name = BSP_UART4_RX_PIN, \ + .alternate = BSP_UART4_AFIO, \ + .serial = &serial4, \ + .device_name = "uart4", \ + } +#endif /* UART4_CONFIG */ +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +#ifndef UART5_CONFIG +#define UART5_CONFIG \ + { \ + .uart_periph = USART5, \ + .irqn = USART5_IRQn, \ + .per_clk = RCU_USART5, \ + .tx_pin_name = BSP_UART5_TX_PIN, \ + .rx_pin_name = BSP_UART5_RX_PIN, \ + .alternate = BSP_UART5_AFIO, \ + .serial = &serial5, \ + .device_name = "uart5", \ + } +#endif /* UART5_CONFIG */ +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +#ifndef UART6_CONFIG +#define UART6_CONFIG \ + { \ + .uart_periph = UART6, \ + .irqn = UART6_IRQn, \ + .per_clk = RCU_UART6, \ + .tx_pin_name = BSP_UART6_TX_PIN, \ + .rx_pin_name = BSP_UART6_RX_PIN, \ + .alternate = BSP_UART6_AFIO, \ + .serial = &serial6, \ + .device_name = "uart6", \ + } +#endif /* UART6_CONFIG */ +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_USING_UART7) +#ifndef UART7_CONFIG +#define UART7_CONFIG \ + { \ + .uart_periph = UART7, \ + .irqn = UART7_IRQn, \ + .per_clk = RCU_UART7, \ + .tx_pin_name = BSP_UART7_TX_PIN, \ + .rx_pin_name = BSP_UART7_RX_PIN, \ + .alternate = BSP_UART7_AFIO, \ + .serial = &serial7, \ + .device_name = "uart7", \ + } +#endif /* UART7_CONFIG */ +#endif /* BSP_USING_UART7 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __UART_CONFIG_H__ */ + diff --git a/bsp/gd32/arm/libraries/gd32_drivers/drv_usart.c b/bsp/gd32/arm/libraries/gd32_drivers/drv_usart.c index 305d283613f..a1813420fcf 100644 --- a/bsp/gd32/arm/libraries/gd32_drivers/drv_usart.c +++ b/bsp/gd32/arm/libraries/gd32_drivers/drv_usart.c @@ -6,9 +6,13 @@ * Change Logs: * Date Author Notes * 2021-08-20 BruceOu first implementation + * 2025-09-29 WangShun optimize the serial driver + * 2025-11-13 kurisaw general GD driver adaptation */ - +#include "board.h" +#include #include "drv_usart.h" +#include "uart_config.h" #ifdef RT_USING_SERIAL @@ -17,7 +21,17 @@ !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && \ !defined(BSP_USING_UART6) && !defined(BSP_USING_UART7) #error "Please define at least one UARTx" +#endif +#if defined(SOC_SERIES_GD32E50x) || defined(SOC_SERIES_GD32F10x) || defined(SOC_SERIES_GD32F20x) || defined(SOC_SERIES_GD32F30x) + #define gpio_output_options_set gpio_init + #define GPIO_OTYPE GPIO_MODE_OUT_PP + #define GPIO_OSPEED GPIO_OSPEED_50MHZ +#elif defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E) + #define GPIO_OSPEED GPIO_OSPEED_60MHZ +#elif defined(SOC_SERIES_GD32F4xx) || defined(SOC_SERIES_GD32F5xx) || defined(SOC_SERIES_GD32E23x) + #define GPIO_OTYPE GPIO_OTYPE_PP + #define GPIO_OSPEED GPIO_OSPEED_50MHZ #endif #include @@ -39,7 +53,7 @@ struct rt_serial_device serial0; gd32_uart_dma uart0_rxdma = { DMA0, DMA_CH0, -#ifdef SOC_SERIES_GD32H7xx +#if defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E) DMA_REQUEST_USART0_RX, #endif DMA_INTF_FTFIF, @@ -49,7 +63,7 @@ gd32_uart_dma uart0_rxdma = { gd32_uart_dma uart0_txdma = { DMA1, DMA_CH0, -#ifdef SOC_SERIES_GD32H7xx +#if defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E) DMA_REQUEST_USART0_TX, #endif DMA_INTF_FTFIF, @@ -103,7 +117,7 @@ struct rt_serial_device serial1; gd32_uart_dma uart1_rxdma = { DMA0, DMA_CH1, -#ifdef SOC_SERIES_GD32H7xx +#if defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E) DMA_REQUEST_USART1_RX, #endif DMA_INTF_FTFIF, @@ -143,7 +157,7 @@ struct rt_serial_device serial2; gd32_uart_dma uart2_rxdma = { DMA0, DMA_CH2, -#ifdef SOC_SERIES_GD32H7xx +#if defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E) DMA_REQUEST_USART2_RX, #endif DMA_INTF_FTFIF, @@ -153,7 +167,7 @@ gd32_uart_dma uart2_rxdma = { gd32_uart_dma uart2_txdma = { DMA1, DMA_CH2, -#ifdef SOC_SERIES_GD32H7xx +#if defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E) DMA_REQUEST_USART2_TX, #endif DMA_INTF_FTFIF, @@ -207,7 +221,7 @@ struct rt_serial_device serial3; gd32_uart_dma uart3_rxdma = { DMA0, DMA_CH3, -#ifdef SOC_SERIES_GD32H7xx +#if defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E) DMA_REQUEST_UART3_RX, #endif DMA_INTF_FTFIF, @@ -247,7 +261,7 @@ struct rt_serial_device serial4; gd32_uart_dma uart4_rxdma = { DMA0, DMA_CH4, -#ifdef SOC_SERIES_GD32H7xx +#if defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E) DMA_REQUEST_UART4_RX, #endif DMA_INTF_FTFIF, @@ -286,7 +300,7 @@ struct rt_serial_device serial5; gd32_uart_dma uart5_rxdma = { DMA0, DMA_CH5, -#ifdef SOC_SERIES_GD32H7xx +#if defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E) DMA_REQUEST_USART5_RX, #endif DMA_INTF_FTFIF, @@ -326,7 +340,7 @@ struct rt_serial_device serial6; gd32_uart_dma uart6_rxdma = { DMA0, DMA_CH6, -#ifdef SOC_SERIES_GD32H7xx +#if defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E) DMA_REQUEST_UART6_RX, #endif DMA_INTF_FTFIF, @@ -366,7 +380,7 @@ struct rt_serial_device serial7; gd32_uart_dma uart7_rxdma = { DMA0, DMA_CH7, -#ifdef SOC_SERIES_GD32H7xx +#if defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E) DMA_REQUEST_UART7_RX, #endif DMA_INTF_FTFIF, @@ -399,224 +413,34 @@ void UART7_IRQHandler(void) #endif /* BSP_USING_UART7 */ -static const struct gd32_uart uart_obj[] = { - #ifdef BSP_USING_UART0 - { - USART0, /* uart peripheral index */ - USART0_IRQn, /* uart iqrn */ - RCU_USART0, /* uart periph clock */ -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32H7xx - RCU_GPIOA, RCU_GPIOA, /* tx gpio clock, rx gpio clock */ - GPIOA, GPIO_AF_7, GPIO_PIN_9, /* tx port, tx alternate, tx pin */ - GPIOA, GPIO_AF_7, GPIO_PIN_10, /* rx port, rx alternate, rx pin */ -#elif defined SOC_SERIES_GD32E50x - RCU_GPIOA, RCU_GPIOA, /* tx gpio clock, rx gpio clock */ - GPIOA, 0, GPIO_PIN_9, /* tx port, tx alternate, tx pin */ - GPIOA, 0, GPIO_PIN_10, /* rx port, rx alternate, rx pin */ - 0, /* afio remap cfg */ -#elif defined SOC_SERIES_GD32E23x - RCU_GPIOA, RCU_GPIOA, - GPIOA, GPIO_AF_1, GPIO_PIN_9, - GPIOA, GPIO_AF_1, GPIO_PIN_10, -#else - RCU_GPIOA, RCU_GPIOA, /* tx gpio clock, rx gpio clock */ - GPIOA, GPIO_PIN_9, /* tx port, tx pin */ - GPIOA, GPIO_PIN_10, /* rx port, rx pin */ -#endif -#ifdef RT_SERIAL_USING_DMA - &uart0_rxdma, -#ifdef RT_SERIAL_USING_TX_DMA - &uart0_txdma, -#endif -#endif - &serial0, - "uart0", - }, - #endif - - #ifdef BSP_USING_UART1 - { - USART1, /* uart peripheral index */ - USART1_IRQn, /* uart iqrn */ - RCU_USART1, /* uart periph clock */ -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx - RCU_GPIOA, RCU_GPIOA, /* tx gpio clock, rx gpio clock */ - GPIOA, GPIO_AF_7, GPIO_PIN_2, /* tx port, tx alternate, tx pin */ - GPIOA, GPIO_AF_7, GPIO_PIN_3, /* rx port, rx alternate, rx pin */ -#elif defined SOC_SERIES_GD32E50x - RCU_GPIOA, RCU_GPIOA, /* tx gpio clock, rx gpio clock */ - GPIOA, 0, GPIO_PIN_2, /* tx port, tx alternate, tx pin */ - GPIOA, 0, GPIO_PIN_3, /* rx port, rx alternate, rx pin */ - 0, /* afio remap cfg */ -#elif defined SOC_SERIES_GD32E23x - RCU_GPIOA, RCU_GPIOA, - GPIOA, GPIO_AF_1, GPIO_PIN_14, - GPIOA, GPIO_AF_1, GPIO_PIN_15, -#else - RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ - GPIOA, GPIO_PIN_2, /* tx port, tx pin */ - RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ - GPIOA, GPIO_PIN_2, /* tx port, tx pin */ - GPIOA, GPIO_PIN_3, /* rx port, rx pin */ -#endif -#ifdef RT_SERIAL_USING_DMA - &uart1_rxdma, -#endif - &serial1, - "uart1", - }, - #endif - - #ifdef BSP_USING_UART2 - { - USART2, /* uart peripheral index */ - USART2_IRQn, /* uart iqrn */ - RCU_USART2, /* uart periph clock */ -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx - RCU_GPIOB, RCU_GPIOB, /* tx gpio clock, rt gpio clock */ - GPIOB, GPIO_AF_7, GPIO_PIN_10, /* tx port, tx alternate, tx pin */ - GPIOB, GPIO_AF_7, GPIO_PIN_11, /* rx port, rx alternate, rx pin */ -#elif defined SOC_SERIES_GD32E50x - RCU_GPIOB, RCU_GPIOB, /* tx gpio clock, rx gpio clock */ - GPIOB, 0, GPIO_PIN_10, /* tx port, tx alternate, tx pin */ - GPIOB, 0, GPIO_PIN_11, /* rx port, rx alternate, rx pin */ - 0, /* afio remap cfg */ -#else - RCU_GPIOB, RCU_GPIOB, /* tx gpio clock, rt gpio clock */ - GPIOB, GPIO_PIN_10, /* tx port, tx pin */ - GPIOB, GPIO_PIN_11, /* rx port, rx pin */ -#endif -#ifdef RT_SERIAL_USING_DMA - &uart2_rxdma, -#ifdef RT_SERIAL_USING_TX_DMA - &uart2_txdma, -#endif -#endif - &serial2, - "uart2", - }, - #endif - - #ifdef BSP_USING_UART3 - { - UART3, /* uart peripheral index */ - UART3_IRQn, /* uart iqrn */ - RCU_UART3, /* uart periph clock */ -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32H7xx - RCU_GPIOC, RCU_GPIOC, /* tx gpio clock, rt gpio clock */ - GPIOC, GPIO_AF_8, GPIO_PIN_10, /* tx port, tx alternate, tx pin */ - GPIOC, GPIO_AF_8, GPIO_PIN_11, /* rx port, rx alternate, rx pin */ -#elif defined SOC_SERIES_GD32E50x - RCU_GPIOC, RCU_GPIOC, /* tx gpio clock, rx gpio clock */ - GPIOC, 0, GPIO_PIN_10, /* tx port, tx alternate, tx pin */ - GPIOC, 0, GPIO_PIN_11, /* rx port, rx alternate, rx pin */ - 0, /* afio remap cfg */ -#else - RCU_GPIOC, RCU_GPIOC, /* periph clock, tx gpio clock, rt gpio clock */ - GPIOC, GPIO_PIN_10, /* tx port, tx pin */ - GPIOC, GPIO_PIN_11, /* rx port, rx pin */ +static const struct gd32_uart uart_obj[] = +{ +#ifdef BSP_USING_UART0 + UART0_CONFIG, #endif -#ifdef RT_SERIAL_USING_DMA - &uart3_rxdma, +#ifdef BSP_USING_UART1 + UART1_CONFIG, #endif - &serial3, - "uart3", - }, - #endif - - #ifdef BSP_USING_UART4 - { - UART4, /* uart peripheral index */ - UART4_IRQn, /* uart iqrn */ - RCU_UART4, RCU_GPIOC, RCU_GPIOD, /* periph clock, tx gpio clock, rt gpio clock */ -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32H7xx - GPIOC, GPIO_AF_8, GPIO_PIN_12, /* tx port, tx alternate, tx pin */ - GPIOD, GPIO_AF_8, GPIO_PIN_2, /* rx port, rx alternate, rx pin */ -#elif defined SOC_SERIES_GD32E50x - GPIOC, 0, GPIO_PIN_12, /* tx port, tx alternate, tx pin */ - GPIOD, 0, GPIO_PIN_2, /* rx port, rx alternate, rx pin */ - 0, /* afio remap cfg */ -#else - GPIOC, GPIO_PIN_12, /* tx port, tx pin */ - GPIOD, GPIO_PIN_2, /* rx port, rx pin */ +#ifdef BSP_USING_UART2 + UART2_CONFIG, #endif - &serial4, - "uart4", - }, - #endif - - #ifdef BSP_USING_UART5 - { - USART5, /* uart peripheral index */ - USART5_IRQn, /* uart iqrn */ - RCU_USART5, RCU_GPIOC, RCU_GPIOC, /* periph clock, tx gpio clock, rt gpio clock */ -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx - GPIOC, GPIO_AF_8, GPIO_PIN_6, /* tx port, tx alternate, tx pin */ - GPIOC, GPIO_AF_8, GPIO_PIN_7, /* rx port, rx alternate, rx pin */ -#elif defined (SOC_SERIES_GD32H7xx) - GPIOC, GPIO_AF_7, GPIO_PIN_6, /* tx port, tx alternate, tx pin */ - GPIOC, GPIO_AF_7, GPIO_PIN_7, /* rx port, rx alternate, rx pin */ -#elif defined SOC_SERIES_GD32E50x - GPIOC, AFIO_PC6_USART5_CFG, GPIO_PIN_6, /* tx port, tx alternate, tx pin */ - GPIOC, AFIO_PC7_USART5_CFG, GPIO_PIN_7, /* rx port, rx alternate, rx pin */ - 0, /* afio remap cfg */ -#else - GPIOC, GPIO_PIN_6, /* tx port, tx pin */ - GPIOC, GPIO_PIN_7, /* rx port, rx pin */ +#ifdef BSP_USING_UART3 + UART3_CONFIG, #endif -#ifdef RT_SERIAL_USING_DMA - &uart5_rxdma, -#endif - &serial5, - "uart5", - }, - #endif - - #ifdef BSP_USING_UART6 - { - UART6, /* uart peripheral index */ - UART6_IRQn, /* uart iqrn */ - RCU_UART6, RCU_GPIOE, RCU_GPIOE, /* periph clock, tx gpio clock, rt gpio clock */ -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx - GPIOE, GPIO_AF_8, GPIO_PIN_7, /* tx port, tx alternate, tx pin */ - GPIOE, GPIO_AF_8, GPIO_PIN_8, /* rx port, rx alternate, rx pin */ -#elif defined (SOC_SERIES_GD32H7xx) - GPIOE, GPIO_AF_7, GPIO_PIN_8, // tx port, tx alternate, tx pin - GPIOE, GPIO_AF_7, GPIO_PIN_7, // rx port, rx alternate, rx pin -#else - GPIOE, GPIO_PIN_7, /* tx port, tx pin */ - GPIOE, GPIO_PIN_8, /* rx port, rx pin */ +#ifdef BSP_USING_UART4 + UART4_CONFIG, #endif -#ifdef RT_SERIAL_USING_DMA - &uart6_rxdma, +#ifdef BSP_USING_UART5 + UART5_CONFIG, #endif - &serial6, - "uart6", - }, - #endif - - #ifdef BSP_USING_UART7 - { - UART7, /* uart peripheral index */ - UART7_IRQn, /* uart iqrn */ - RCU_UART7, RCU_GPIOE, RCU_GPIOE, /* periph clock, tx gpio clock, rt gpio clock */ -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32H7xx - GPIOE, GPIO_AF_8, GPIO_PIN_1, /* tx port, tx alternate, tx pin */ - GPIOE, GPIO_AF_8, GPIO_PIN_0, /* rx port, rx alternate, rx pin */ -#else - GPIOE, GPIO_PIN_0, /* tx port, tx pin */ - GPIOE, GPIO_PIN_1, /* rx port, rx pin */ +#ifdef BSP_USING_UART6 + UART6_CONFIG, #endif -#ifdef RT_SERIAL_USING_DMA - &uart7_rxdma, +#ifdef BSP_USING_UART7 + UART7_CONFIG, #endif - &serial7, - "uart7", - }, - #endif }; - /** * @brief UART MSP Initialization * This function configures the hardware resources used in this example: @@ -628,70 +452,46 @@ static const struct gd32_uart uart_obj[] = { */ void gd32_uart_gpio_init(struct gd32_uart *uart) { - /* enable USART clock */ - rcu_periph_clock_enable(uart->tx_gpio_clk); - rcu_periph_clock_enable(uart->rx_gpio_clk); - rcu_periph_clock_enable(uart->per_clk); + rt_uint32_t tx_port, rx_port; + rt_uint32_t tx_pin, rx_pin; + rt_uint32_t pin_af; + rcu_periph_enum tx_periph, rx_periph; -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x - /* connect port to USARTx_Tx */ - gpio_af_set(uart->tx_port, uart->tx_af, uart->tx_pin); + if (get_pin_config(uart->tx_pin_name, &tx_port, &tx_pin, &tx_periph) != RT_EOK) + { + return; + } - /* connect port to USARTx_Rx */ - gpio_af_set(uart->rx_port, uart->rx_af, uart->rx_pin); + if (get_pin_config(uart->rx_pin_name, &rx_port, &rx_pin, &rx_periph) != RT_EOK) + { + return; + } - /* configure USART Tx as alternate function push-pull */ - gpio_mode_set(uart->tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, uart->tx_pin); - gpio_output_options_set(uart->tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, uart->tx_pin); + pin_alternate_config(uart->alternate, &pin_af); - /* configure USART Rx as alternate function push-pull */ - gpio_mode_set(uart->rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, uart->rx_pin); - gpio_output_options_set(uart->rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, uart->rx_pin); + /* enable USART clock */ + rcu_periph_clock_enable(tx_periph); + rcu_periph_clock_enable(rx_periph); + rcu_periph_clock_enable(uart->per_clk); -#elif defined SOC_SERIES_GD32H7xx +#if !defined(SOC_SERIES_GD32E50x) && !defined(SOC_SERIES_GD32F10x) && !defined(SOC_SERIES_GD32F20x) && !defined(SOC_SERIES_GD32F30x) /* connect port to USARTx_Tx */ - gpio_af_set(uart->tx_port, uart->tx_af, uart->tx_pin); - + gpio_af_set(tx_port, pin_af, tx_pin); /* connect port to USARTx_Rx */ - gpio_af_set(uart->rx_port, uart->rx_af, uart->rx_pin); + gpio_af_set(rx_port, pin_af, rx_pin); +#endif /* configure USART Tx as alternate function push-pull */ - gpio_mode_set(uart->tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, uart->tx_pin); - gpio_output_options_set(uart->tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_60MHZ, uart->tx_pin); +#if !defined(SOC_SERIES_GD32E50x) && !defined(SOC_SERIES_GD32F10x) && !defined(SOC_SERIES_GD32F20x) && !defined(SOC_SERIES_GD32F30x) + gpio_mode_set(tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, tx_pin); +#endif + gpio_output_options_set(tx_port, GPIO_OTYPE, GPIO_OSPEED, tx_pin); /* configure USART Rx as alternate function push-pull */ - gpio_mode_set(uart->rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, uart->rx_pin); - gpio_output_options_set(uart->rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_60MHZ, uart->rx_pin); - -#elif defined SOC_SERIES_GD32E50x - /* configure remap function */ - if (uart->uart_remap != 0 || uart->tx_af != 0 || uart->rx_af != 0) - { - rcu_periph_clock_enable(RCU_AF); - gpio_pin_remap_config(uart->uart_remap, ENABLE); - } - - /* connect port to USARTx_Tx */ - gpio_init(uart->tx_port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, uart->tx_pin); - - /* connect port to USARTx_Rx */ - gpio_init(uart->rx_port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, uart->rx_pin); - - /* configure alternate1 function */ - if (uart->tx_af != 0 || uart->rx_af != 0) - { - rcu_periph_clock_enable(RCU_AF); - gpio_afio_port_config(uart->tx_af, ENABLE); - gpio_afio_port_config(uart->rx_af, ENABLE); - } - -#else - /* connect port to USARTx_Tx */ - gpio_init(uart->tx_port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, uart->tx_pin); - - /* connect port to USARTx_Rx */ - gpio_init(uart->rx_port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, uart->rx_pin); +#if !defined(SOC_SERIES_GD32E50x) && !defined(SOC_SERIES_GD32F10x) && !defined(SOC_SERIES_GD32F20x) && !defined(SOC_SERIES_GD32F30x) + gpio_mode_set(rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, rx_pin); #endif + gpio_output_options_set(rx_port, GPIO_OTYPE, GPIO_OSPEED, rx_pin); NVIC_SetPriority(uart->irqn, 0); NVIC_EnableIRQ(uart->irqn); @@ -782,7 +582,8 @@ static rt_err_t gd32_uart_control(struct rt_serial_device *serial, int cmd, void #ifdef RT_SERIAL_USING_DMA /* disable DMA */ - if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) { + if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) + { nvic_irq_disable(uart->uart_dma->rx_irq_ch); /* disable interrupt */ @@ -795,7 +596,8 @@ static rt_err_t gd32_uart_control(struct rt_serial_device *serial, int cmd, void uart->uart_dma->last_recv_index = 0; } #ifdef RT_SERIAL_USING_TX_DMA - else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) { + else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) + { nvic_irq_disable(uart->uart_tx_dma->rx_irq_ch); dma_channel_disable(uart->uart_tx_dma->dma_periph, uart->uart_tx_dma->dma_ch); @@ -815,11 +617,13 @@ static rt_err_t gd32_uart_control(struct rt_serial_device *serial, int cmd, void #ifdef RT_SERIAL_USING_DMA case RT_DEVICE_CTRL_CONFIG: - if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) { + if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) + { gd32_dma_config(serial, ctrl_arg); } #ifdef RT_SERIAL_USING_TX_DMA - else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) { + else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) + { gd32_dma_tx_config(serial, ctrl_arg); } #endif @@ -909,7 +713,8 @@ static void gd32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; /* wait IDLEF set and clear it */ - while(RESET == usart_flag_get(uart->uart_periph, USART_FLAG_IDLE)) { + while(RESET == usart_flag_get(uart->uart_periph, USART_FLAG_IDLE)) + { rt_thread_mdelay(10); } @@ -917,9 +722,11 @@ static void gd32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) /* enable transmit idle interrupt */ usart_interrupt_enable(uart->uart_periph, USART_INT_IDLE); /* DMA clock enable */ - if(DMA0 == uart->uart_dma->dma_periph) { + if(DMA0 == uart->uart_dma->dma_periph) + { rcu_periph_clock_enable(RCU_DMA0); - } else if(DMA1 == uart->uart_dma->dma_periph) { + } else if(DMA1 == uart->uart_dma->dma_periph) + { rcu_periph_clock_enable(RCU_DMA1); } else { Error_Handler(); @@ -951,9 +758,11 @@ static void gd32_dma_tx_config(struct rt_serial_device *serial, rt_ubase_t flag) struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; /* DMA clock enable */ - if(DMA0 == uart->uart_tx_dma->dma_periph) { + if(DMA0 == uart->uart_tx_dma->dma_periph) + { rcu_periph_clock_enable(RCU_DMA0); - } else if(DMA1 == uart->uart_tx_dma->dma_periph) { + } else if(DMA1 == uart->uart_tx_dma->dma_periph) + { rcu_periph_clock_enable(RCU_DMA1); } else { Error_Handler(); @@ -1076,7 +885,8 @@ static void dma_uart_rx_idle_isr(struct rt_serial_device *serial) recv_total_index = uart->uart_dma->setting_recv_len - dma_transfer_number_get(uart->uart_dma->dma_periph, uart->uart_dma->dma_ch); - if (recv_total_index >= uart->uart_dma->last_recv_index) { + if (recv_total_index >= uart->uart_dma->last_recv_index) + { recv_len = recv_total_index - uart->uart_dma->last_recv_index; } else { recv_len = uart->uart_dma->setting_recv_len - uart->uart_dma->last_recv_index + recv_total_index; @@ -1114,14 +924,16 @@ static void dma_rx_done_isr(struct rt_serial_device *serial) rt_memcpy(rx_fifo_end_ptr, rx_fifo_buf_cache_bk, sizeof(rx_fifo_buf_cache_bk)); #endif - if (dma_flag_get(uart->uart_dma->dma_periph, uart->uart_dma->dma_ch, uart->uart_dma->rx_flag) != RESET) { + if (dma_flag_get(uart->uart_dma->dma_periph, uart->uart_dma->dma_ch, uart->uart_dma->rx_flag) != RESET) + { /* disable dma, stop receive data */ dma_channel_disable(uart->uart_dma->dma_periph, uart->uart_dma->dma_ch); recv_total_index = uart->uart_dma->setting_recv_len - dma_transfer_number_get(uart->uart_dma->dma_periph, uart->uart_dma->dma_ch); - if (recv_total_index >= uart->uart_dma->last_recv_index) { + if (recv_total_index >= uart->uart_dma->last_recv_index) + { recv_len = recv_total_index - uart->uart_dma->last_recv_index; } else { recv_len = uart->uart_dma->setting_recv_len - uart->uart_dma->last_recv_index + recv_total_index; @@ -1172,6 +984,7 @@ static void GD32_UART_IRQHandler(struct rt_serial_device *serial) usart_interrupt_disable(uart->uart_periph, USART_INT_TC); rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE); } + if (usart_flag_get(uart->uart_periph, USART_FLAG_ORERR) == SET) { usart_flag_clear(uart->uart_periph, USART_FLAG_ORERR); @@ -1216,7 +1029,7 @@ int rt_hw_usart_init(void) flag |= RT_DEVICE_FLAG_DMA_TX; #endif #endif - /* register UART1 device */ + /* register device */ result = rt_hw_serial_register(uart_obj[i].serial, uart_obj[i].device_name, flag, @@ -1228,3 +1041,4 @@ int rt_hw_usart_init(void) } #endif + diff --git a/bsp/gd32/arm/libraries/gd32_drivers/drv_usart.h b/bsp/gd32/arm/libraries/gd32_drivers/drv_usart.h index 774657b5818..8257a879dd3 100644 --- a/bsp/gd32/arm/libraries/gd32_drivers/drv_usart.h +++ b/bsp/gd32/arm/libraries/gd32_drivers/drv_usart.h @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2021-08-20 BruceOu first implementation + * 2025-10-09 WangShun optimize the serial driver + * 2025-11-13 kurisaw general GD driver adaptation */ #ifndef __DRV_USART_H__ @@ -19,7 +21,7 @@ extern "C" { #endif -#ifndef SOC_SERIES_GD32H7xx +#if !defined(SOC_SERIES_GD32H7xx) || !defined(SOC_SERIES_GD32H75E) #undef RT_SERIAL_USING_DMA #endif #define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) @@ -33,7 +35,7 @@ typedef struct uint32_t dma_periph; /* dma channel */ dma_channel_enum dma_ch; -#ifdef SOC_SERIES_GD32H7xx +#if defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E) /* rx dma request */ uint32_t dma_mux_req_rx; #endif @@ -49,31 +51,16 @@ typedef struct #endif /* GD32 uart driver */ -/* Todo: compress uart info */ + struct gd32_uart { - uint32_t uart_periph; /* Todo: 3bits */ - IRQn_Type irqn; /* Todo: 7bits */ - rcu_periph_enum per_clk; /* Todo: 5bits */ - rcu_periph_enum tx_gpio_clk; /* Todo: 5bits */ - rcu_periph_enum rx_gpio_clk; /* Todo: 5bits */ - uint32_t tx_port; /* Todo: 4bits */ -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x - uint16_t tx_af; /* Todo: 4bits */ -#elif defined SOC_SERIES_GD32E50x - uint32_t tx_af; /* alternate1 cfg */ -#endif - uint16_t tx_pin; /* Todo: 4bits */ - uint32_t rx_port; /* Todo: 4bits */ -#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x - uint16_t rx_af; /* Todo: 4bits */ -#elif defined SOC_SERIES_GD32E50x - uint32_t rx_af; /* alternate1 cfg */ -#endif - uint16_t rx_pin; /* Todo: 4bits */ -#if defined SOC_SERIES_GD32E50x - uint32_t uart_remap; /* remap */ -#endif + uint32_t uart_periph; /* Instance */ + IRQn_Type irqn; /* irqn */ + rcu_periph_enum per_clk; /* uart_clk */ + + const char *tx_pin_name; /* tx pin name */ + const char *rx_pin_name; /* rx pin name */ + const char *alternate; /* pin alternate */ #ifdef RT_SERIAL_USING_DMA gd32_uart_dma *uart_dma; @@ -82,7 +69,7 @@ struct gd32_uart #endif #endif - struct rt_serial_device * serial; + struct rt_serial_device * serial; /* serial device */ char *device_name; }; From 7f1d392d49416997f367718a3888b9a38ad613e1 Mon Sep 17 00:00:00 2001 From: kurisaw <2053731441@qq.com> Date: Wed, 26 Nov 2025 14:09:15 +0800 Subject: [PATCH 3/3] [gd32/arm][bsp]: synchronous kconfig update --- bsp/gd32/arm/gd32103c-eval/.config | 22 +- bsp/gd32/arm/gd32103c-eval/board/Kconfig | 222 ++- bsp/gd32/arm/gd32103c-eval/project.ewp | 108 +- bsp/gd32/arm/gd32103c-eval/project.uvoptx | 794 +-------- bsp/gd32/arm/gd32103c-eval/project.uvprojx | 1354 +++------------ bsp/gd32/arm/gd32103c-eval/rtconfig.h | 10 +- bsp/gd32/arm/gd32105c-eval/.config | 22 +- bsp/gd32/arm/gd32105c-eval/board/Kconfig | 222 ++- bsp/gd32/arm/gd32105c-eval/project.ewp | 120 +- bsp/gd32/arm/gd32105c-eval/project.uvoptx | 794 +-------- bsp/gd32/arm/gd32105c-eval/project.uvprojx | 1366 +++------------ bsp/gd32/arm/gd32105c-eval/rtconfig.h | 10 +- bsp/gd32/arm/gd32105r-start/.config | 22 +- bsp/gd32/arm/gd32105r-start/board/Kconfig | 222 ++- bsp/gd32/arm/gd32105r-start/project.ewp | 110 +- bsp/gd32/arm/gd32105r-start/rtconfig.h | 10 +- bsp/gd32/arm/gd32107c-eval/.config | 22 +- bsp/gd32/arm/gd32107c-eval/board/Kconfig | 222 ++- bsp/gd32/arm/gd32107c-eval/project.ewp | 120 +- bsp/gd32/arm/gd32107c-eval/project.uvoptx | 842 +--------- bsp/gd32/arm/gd32107c-eval/project.uvprojx | 1448 +++------------- bsp/gd32/arm/gd32107c-eval/rtconfig.h | 10 +- bsp/gd32/arm/gd32205r-start/.config | 22 +- bsp/gd32/arm/gd32205r-start/board/Kconfig | 222 ++- bsp/gd32/arm/gd32205r-start/project.ewp | 112 +- bsp/gd32/arm/gd32205r-start/project.uvoptx | 794 +-------- bsp/gd32/arm/gd32205r-start/project.uvprojx | 1353 +++------------ bsp/gd32/arm/gd32205r-start/rtconfig.h | 10 +- bsp/gd32/arm/gd32207i-eval/.config | 28 +- bsp/gd32/arm/gd32207i-eval/board/Kconfig | 252 ++- bsp/gd32/arm/gd32207i-eval/project.ewp | 110 +- bsp/gd32/arm/gd32207i-eval/project.uvoptx | 794 +-------- bsp/gd32/arm/gd32207i-eval/project.uvprojx | 1347 +++------------ bsp/gd32/arm/gd32207i-eval/rtconfig.h | 11 +- bsp/gd32/arm/gd32303c-start/.config | 24 +- bsp/gd32/arm/gd32303c-start/board/Kconfig | 194 ++- bsp/gd32/arm/gd32303c-start/project.ewp | 118 +- bsp/gd32/arm/gd32303c-start/project.uvoptx | 794 +-------- bsp/gd32/arm/gd32303c-start/project.uvprojx | 1355 +++------------ bsp/gd32/arm/gd32303c-start/rtconfig.h | 10 +- bsp/gd32/arm/gd32303e-eval/.config | 22 +- bsp/gd32/arm/gd32303e-eval/board/Kconfig | 222 ++- bsp/gd32/arm/gd32303e-eval/project.ewp | 110 +- bsp/gd32/arm/gd32303e-eval/project.uvprojx | 36 +- bsp/gd32/arm/gd32303e-eval/rtconfig.h | 10 +- bsp/gd32/arm/gd32305r-start/.config | 22 +- bsp/gd32/arm/gd32305r-start/board/Kconfig | 222 ++- bsp/gd32/arm/gd32305r-start/project.ewp | 116 +- bsp/gd32/arm/gd32305r-start/project.uvoptx | 796 +-------- bsp/gd32/arm/gd32305r-start/project.uvprojx | 1348 +++------------ bsp/gd32/arm/gd32305r-start/rtconfig.h | 10 +- bsp/gd32/arm/gd32307e-start/.config | 22 +- bsp/gd32/arm/gd32307e-start/board/Kconfig | 223 ++- bsp/gd32/arm/gd32307e-start/project.ewp | 110 +- bsp/gd32/arm/gd32307e-start/project.uvprojx | 24 +- bsp/gd32/arm/gd32307e-start/rtconfig.h | 10 +- bsp/gd32/arm/gd32407v-lckfb/.config | 24 +- bsp/gd32/arm/gd32407v-lckfb/board/Kconfig | 378 ++--- bsp/gd32/arm/gd32407v-lckfb/project.ewp | 132 +- bsp/gd32/arm/gd32407v-lckfb/project.uvoptx | 866 +--------- bsp/gd32/arm/gd32407v-lckfb/project.uvprojx | 1417 ++-------------- bsp/gd32/arm/gd32407v-lckfb/rtconfig.h | 10 +- bsp/gd32/arm/gd32407v-start/.config | 24 +- bsp/gd32/arm/gd32407v-start/board/Kconfig | 376 ++--- bsp/gd32/arm/gd32407v-start/project.ewp | 122 +- bsp/gd32/arm/gd32407v-start/project.uvoptx | 866 +--------- bsp/gd32/arm/gd32407v-start/project.uvprojx | 1481 +++-------------- bsp/gd32/arm/gd32407v-start/rtconfig.h | 10 +- bsp/gd32/arm/gd32450z-eval/.config | 28 +- bsp/gd32/arm/gd32450z-eval/board/Kconfig | 446 ++--- bsp/gd32/arm/gd32450z-eval/project.ewp | 136 +- bsp/gd32/arm/gd32450z-eval/project.uvprojx | 44 +- bsp/gd32/arm/gd32450z-eval/rtconfig.h | 12 +- bsp/gd32/arm/gd32470i-eval/.config | 26 +- bsp/gd32/arm/gd32470i-eval/board/Kconfig | 446 ++--- bsp/gd32/arm/gd32470i-eval/project.ewp | 146 +- bsp/gd32/arm/gd32470i-eval/project.uvoptx | 816 --------- bsp/gd32/arm/gd32470i-eval/project.uvprojx | 1303 ++------------- bsp/gd32/arm/gd32470i-eval/rtconfig.h | 10 +- bsp/gd32/arm/gd32470z-lckfb/.config | 26 +- bsp/gd32/arm/gd32470z-lckfb/board/Kconfig | 446 ++--- bsp/gd32/arm/gd32470z-lckfb/project.ewp | 124 +- bsp/gd32/arm/gd32470z-lckfb/project.uvprojx | 52 +- bsp/gd32/arm/gd32470z-lckfb/rtconfig.h | 10 +- bsp/gd32/arm/gd32527I-eval/.config | 26 +- bsp/gd32/arm/gd32527I-eval/board/Kconfig | 428 ++--- bsp/gd32/arm/gd32527I-eval/project.ewp | 115 +- bsp/gd32/arm/gd32527I-eval/project.uvprojx | 121 +- bsp/gd32/arm/gd32527I-eval/rtconfig.h | 10 +- bsp/gd32/arm/gd32e230-lckfb/.config | 24 +- bsp/gd32/arm/gd32e230-lckfb/board/Kconfig | 252 ++- bsp/gd32/arm/gd32e230-lckfb/project.uvoptx | 573 +++++++ bsp/gd32/arm/gd32e230-lckfb/project.uvprojx | 1148 +++++++++++++ bsp/gd32/arm/gd32e230-lckfb/rtconfig.h | 10 +- bsp/gd32/arm/gd32e230-lckfb/template.uvoptx | 573 +++++++ bsp/gd32/arm/gd32e230-lckfb/template.uvprojx | 562 +++++++ bsp/gd32/arm/gd32e503v-eval/.config | 28 +- bsp/gd32/arm/gd32e503v-eval/board/Kconfig | 257 ++- bsp/gd32/arm/gd32e503v-eval/project.ewp | 103 +- bsp/gd32/arm/gd32e503v-eval/project.uvoptx | 780 --------- bsp/gd32/arm/gd32e503v-eval/project.uvprojx | 1360 +++------------ bsp/gd32/arm/gd32e503v-eval/rtconfig.h | 13 +- bsp/gd32/arm/gd32h759i-eval/.config | 21 +- bsp/gd32/arm/gd32h759i-eval/board/Kconfig | 203 ++- bsp/gd32/arm/gd32h759i-eval/project.ewp | 124 +- bsp/gd32/arm/gd32h759i-eval/project.uvprojx | 116 +- bsp/gd32/arm/gd32h759i-eval/rtconfig.h | 10 +- bsp/gd32/arm/gd32h759i-start/.config | 21 +- bsp/gd32/arm/gd32h759i-start/board/Kconfig | 221 ++- bsp/gd32/arm/gd32h759i-start/project.ewp | 1480 ++++------------ bsp/gd32/arm/gd32h759i-start/project.uvoptx | 817 ++++++++- bsp/gd32/arm/gd32h759i-start/project.uvprojx | 202 ++- bsp/gd32/arm/gd32h759i-start/rtconfig.h | 10 +- bsp/gd32/arm/gd32h759i-start/template.ewp | 1344 +++------------ bsp/gd32/arm/gd32h759i-start/template.eww | 2 +- bsp/gd32/arm/gd32h759i-start/template.uvoptx | 817 ++++++++- bsp/gd32/arm/gd32h759i-start/template.uvprojx | 428 ++++- .../arm/libraries/gd32_drivers/drv_usart.c | 1 + 118 files changed, 13345 insertions(+), 27557 deletions(-) create mode 100644 bsp/gd32/arm/gd32e230-lckfb/project.uvoptx create mode 100644 bsp/gd32/arm/gd32e230-lckfb/project.uvprojx create mode 100644 bsp/gd32/arm/gd32e230-lckfb/template.uvoptx create mode 100644 bsp/gd32/arm/gd32e230-lckfb/template.uvprojx diff --git a/bsp/gd32/arm/gd32103c-eval/.config b/bsp/gd32/arm/gd32103c-eval/.config index 5c11ef98df8..683660ae4ab 100644 --- a/bsp/gd32/arm/gd32103c-eval/.config +++ b/bsp/gd32/arm/gd32103c-eval/.config @@ -347,8 +347,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Using USB legacy version # @@ -631,6 +629,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set # end of tools packages # @@ -725,6 +726,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -887,6 +889,12 @@ CONFIG_PKG_GD32_ARM_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/gd32/gd32- CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER_LATEST_VERSION=y CONFIG_PKG_GD32_ARM_SERIES_DRIVER_VER="latest" # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK # end of HAL & SDK Drivers # @@ -935,6 +943,7 @@ CONFIG_PKG_GD32_ARM_SERIES_DRIVER_VER="latest" # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -1406,7 +1415,7 @@ CONFIG_SOC_SERIES_GD32F10x=y # # Hardware Drivers Config # -CONFIG_SOC_GD32103V=y +CONFIG_SOC_GD32F103VC=y # # Onboard Peripheral Drivers @@ -1417,12 +1426,15 @@ CONFIG_SOC_GD32103V=y # CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_SERIAL_V1=y +# CONFIG_BSP_USING_SERIAL_V2 is not set # CONFIG_BSP_USING_UART0 is not set CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_UART1_RX_USING_DMA is not set +CONFIG_BSP_UART1_TX_PIN="PA2" +CONFIG_BSP_UART1_RX_PIN="PA3" +CONFIG_BSP_UART1_AFIO="AF7" # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set -# CONFIG_BSP_USING_UART4 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_TIM is not set diff --git a/bsp/gd32/arm/gd32103c-eval/board/Kconfig b/bsp/gd32/arm/gd32103c-eval/board/Kconfig index 2e98cae740f..46de28e3606 100644 --- a/bsp/gd32/arm/gd32103c-eval/board/Kconfig +++ b/bsp/gd32/arm/gd32103c-eval/board/Kconfig @@ -4,7 +4,7 @@ config SOC_SERIES_GD32F10x bool default y -config SOC_GD32103V +config SOC_GD32F103VC bool select SOC_SERIES_GD32F10x select RT_USING_COMPONENTS_INIT @@ -25,57 +25,199 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_UART bool "Enable UART" default y - select RT_USING_SERIAL if BSP_USING_UART - config BSP_USING_UART0 + choice + prompt "Select UART framework version" + default BSP_USING_SERIAL_V1 + + config BSP_USING_SERIAL_V1 + bool "Use Serial V1 framework" + select RT_USING_SERIAL + + config BSP_USING_SERIAL_V2 + bool "Use Serial V2 framework" + select RT_USING_SERIAL_V2 + endchoice + + menuconfig BSP_USING_UART0 bool "Enable UART0" default n + if BSP_USING_UART0 + config BSP_UART0_TX_PIN + string "UART0 TX name, such as PA8" + default "PA9" + + config BSP_UART0_RX_PIN + string "UART0 RX name, such as PA9" + default "PA10" + + config BSP_UART0_AFIO + string "UART0 alternate function, such as AF7" + default "AF1" + + if BSP_USING_SERIAL_V2 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART0_DMA_PING_BUFSIZE + int "Set UART0 RX DMA ping-pong buffer size" + range 16 65535 + depends on BSP_UART0_RX_USING_DMA + default 64 + + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + default 128 + + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + default 128 + endif + endif - config BSP_UART0_RX_USING_DMA - bool "Enable UART0 RX DMA" - depends on BSP_USING_UART0 - select RT_SERIAL_USING_DMA - default n - - config BSP_USING_UART1 + menuconfig BSP_USING_UART1 bool "Enable UART1" default y + if BSP_USING_UART1 + config BSP_UART1_TX_PIN + string "UART1 TX name, such as PA8" + default "PA2" + + config BSP_UART1_RX_PIN + string "UART1 RX name, such as PA9" + default "PA3" + + config BSP_UART1_AFIO + string "UART1 alternate function, such as AF7" + default "AF7" + + if BSP_USING_SERIAL_V2 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART1_DMA_PING_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 16 65535 + depends on BSP_UART1_RX_USING_DMA + default 64 + + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + default 128 + + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + default 128 + endif + endif - config BSP_UART1_RX_USING_DMA - bool "Enable UART1 RX DMA" - depends on BSP_USING_UART1 - select RT_SERIAL_USING_DMA - default n - - config BSP_USING_UART2 + menuconfig BSP_USING_UART2 bool "Enable UART2" default n + if BSP_USING_UART2 + config BSP_UART2_TX_PIN + string "UART2 TX name, such as PA8" + default "PA8" + + config BSP_UART2_RX_PIN + string "UART2 RX name, such as PA9" + default "PA9" + + config BSP_UART2_AFIO + string "UART2 alternate function, such as AF7" + default "AF7" + + if BSP_USING_SERIAL_V2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART2_DMA_PING_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 16 65535 + depends on BSP_UART2_RX_USING_DMA + default 64 + + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + default 128 + + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + default 128 + endif + endif - config BSP_UART2_RX_USING_DMA - bool "Enable UART2 RX DMA" - depends on BSP_USING_UART2 - select RT_SERIAL_USING_DMA - default n - - config BSP_USING_UART3 + menuconfig BSP_USING_UART3 bool "Enable UART3" default n - - config BSP_UART3_RX_USING_DMA - bool "Enable UART3 RX DMA" - depends on BSP_USING_UART3 - select RT_SERIAL_USING_DMA - default n - - config BSP_USING_UART4 - bool "Enable UART4" - default n - - config BSP_UART4_RX_USING_DMA - bool "Enable UART4 RX DMA" - depends on BSP_USING_UART4 - select RT_SERIAL_USING_DMA - default n + if BSP_USING_UART3 + config BSP_UART3_TX_PIN + string "UART3 TX name, such as PA8" + default "PA8" + + config BSP_UART3_RX_PIN + string "UART3 RX name, such as PA9" + default "PA9" + + config BSP_UART3_AFIO + string "UART3 alternate function, such as AF7" + default "AF7" + + if BSP_USING_SERIAL_V2 + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART3_DMA_PING_BUFSIZE + int "Set UART3 RX DMA ping-pong buffer size" + range 16 65535 + depends on BSP_UART3_RX_USING_DMA + default 64 + + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + default 128 + + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + default 128 + endif + endif endif menuconfig BSP_USING_SPI diff --git a/bsp/gd32/arm/gd32103c-eval/project.ewp b/bsp/gd32/arm/gd32103c-eval/project.ewp index 2218268e137..1167c385eb3 100644 --- a/bsp/gd32/arm/gd32103c-eval/project.ewp +++ b/bsp/gd32/arm/gd32103c-eval/project.ewp @@ -166,13 +166,13 @@ 1 @@ -303,27 +303,29 @@ @@ -1275,27 +1277,29 @@ @@ -303,26 +303,28 @@ @@ -1275,26 +1277,28 @@ @@ -1275,27 +1277,29 @@ @@ -1276,28 +1278,30 @@ @@ -1275,27 +1277,29 @@ @@ -1275,27 +1277,29 @@ @@ -303,27 +303,29 @@ @@ -1275,27 +1277,29 @@ @@ -303,26 +303,28 @@ @@ -1275,26 +1277,28 @@ @@ -303,27 +303,29 @@ @@ -1275,27 +1277,29 @@ @@ -303,27 +303,29 @@ @@ -1275,27 +1277,29 @@ @@ -1277,27 +1279,29 @@ @@ -303,27 +303,29 @@ @@ -1275,27 +1277,29 @@ @@ -306,28 +306,30 @@ @@ -1280,28 +1282,30 @@ @@ -306,29 +305,30 @@ @@ -1281,29 +1280,30 @@ @@ -306,28 +306,30 @@ @@ -1281,28 +1283,30 @@