diff --git "a/20251218 \346\267\273\345\212\240\344\272\206N32\344\270\252pwm \345\222\214\345\256\232\346\227\266\345\231\250\350\256\241\346\225\260\357\274\214\346\265\213\351\207\217\350\204\211\345\256\275\347\232\204\351\251\261\345\212\250\357\274\214\345\242\236\345\212\240\344\272\206V1\347\211\210\344\270\262\345\217\243Kconfig\351\205\215\347\275\256\357\274\214spi\351\251\261\345\212\250Kconfig\351\205\215\347\275\256.txt" "b/20251218 \346\267\273\345\212\240\344\272\206N32\344\270\252pwm \345\222\214\345\256\232\346\227\266\345\231\250\350\256\241\346\225\260\357\274\214\346\265\213\351\207\217\350\204\211\345\256\275\347\232\204\351\251\261\345\212\250\357\274\214\345\242\236\345\212\240\344\272\206V1\347\211\210\344\270\262\345\217\243Kconfig\351\205\215\347\275\256\357\274\214spi\351\251\261\345\212\250Kconfig\351\205\215\347\275\256.txt" new file mode 100644 index 00000000000..e69de29bb2d diff --git "a/bsp n32 - \345\277\253\346\215\267\346\226\271\345\274\217.lnk" "b/bsp n32 - \345\277\253\346\215\267\346\226\271\345\274\217.lnk" new file mode 100644 index 00000000000..d7c1feadee2 Binary files /dev/null and "b/bsp n32 - \345\277\253\346\215\267\346\226\271\345\274\217.lnk" differ diff --git a/bsp/hk32/hk32f030c8-mini/board/msp/hk32_msp.c.orig b/bsp/hk32/hk32f030c8-mini/board/msp/hk32_msp.c.orig deleted file mode 100644 index 8dde386561f..00000000000 --- a/bsp/hk32/hk32f030c8-mini/board/msp/hk32_msp.c.orig +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-14 Jonas first version - */ - -#include -#include -#include "hk32_msp.h" - -#ifdef BSP_USING_UART -void hk32_msp_usart_init(void *Instance) -{ - GPIO_InitTypeDef GPIO_InitStruct; - USART_TypeDef *USARTx = (USART_TypeDef *)Instance; - - GPIO_StructInit(&GPIO_InitStruct); - GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz; -#ifdef BSP_USING_UART1 - if(USART1 == USARTx) - { - #define USART1_REMAP - #ifndef USART1_REMAP - RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); - - GPIO_InitStruct.GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_9; - GPIO_Init(GPIOA, &GPIO_InitStruct); - - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStruct.GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_10; - GPIO_Init(GPIOA, &GPIO_InitStruct); - - GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_1); - GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_1); - - #else - RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE); - - GPIO_InitStruct.GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_6; - GPIO_Init(GPIOB, &GPIO_InitStruct); - - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStruct.GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_7; - GPIO_Init(GPIOB, &GPIO_InitStruct); - - GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_0); - GPIO_PinAFConfig(GPIOB, GPIO_PinSource7, GPIO_AF_0); - #endif - } -#endif -#ifdef BSP_USING_UART2 - if(USART2 == USARTx) - { - RCC_APB2PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); - - GPIO_InitStruct.GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_2; - GPIO_Init(GPIOA, &GPIO_InitStruct); - - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStruct.GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_3; - GPIO_Init(GPIOA, &GPIO_InitStruct); - - GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_1); - GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_1); - } -#endif - /* Add others */ -} -#endif /* BSP_USING_SERIAL */ -#ifdef BSP_USING_I2C -void hk32_msp_i2c_init(void *Instance) -{ - GPIO_InitTypeDef GPIO_InitStruct; - I2C_TypeDef *I2Cx = (I2C_TypeDef *)Instance; - - GPIO_StructInit(&GPIO_InitStruct); - GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz; -#ifdef BSP_USING_I2C1 - if(I2C1 == I2Cx) - { - #ifndef I2C1_REMAP - RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE); - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE); - - GPIO_InitStruct.GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_6; - GPIO_Init(GPIOB, &GPIO_InitStruct); - - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStruct.GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_6; - GPIO_Init(GPIOB, &GPIO_InitStruct); - - GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_1); - GPIO_PinAFConfig(GPIOB, GPIO_PinSource7, GPIO_AF_1); - #else - RCC_APB2PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE); - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE); - - GPIO_InitStruct.GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_8; - GPIO_Init(GPIOB, &GPIO_InitStruct); - - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStruct.GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_9; - GPIO_Init(GPIOB, &GPIO_InitStruct); - - GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_1); - GPIO_PinAFConfig(GPIOB, GPIO_PinSource9, GPIO_AF_1); - #endif - } -#endif - /* Add others */ -} -#endif /* BSP_USING_I2C */ - - -#ifdef BSP_USING_SPI -void hk32_msp_spi_init(void *Instance) -{ - GPIO_InitTypeDef GPIO_InitStruct; - SPI_TypeDef *SPIx = (SPI_TypeDef *)Instance; - - GPIO_StructInit(&GPIO_InitStruct); - GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz; -#ifdef BSP_USING_SPI1 - if(SPI1 == SPIx) - { - #ifndef SPI1_REMAP - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE); - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); - - GPIO_InitStruct.GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_4; - GPIO_Init(GPIOA, &GPIO_InitStruct); - - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStruct.GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7; - GPIO_Init(GPIOA, &GPIO_InitStruct); - - GPIO_PinAFConfig(GPIOA, GPIO_PinSource5, GPIO_AF_0); - GPIO_PinAFConfig(GPIOA, GPIO_PinSource6, GPIO_AF_0); - GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_0); - #else - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE); - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE); - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); - - GPIO_InitStruct.GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_15; - GPIO_Init(GPIOA, &GPIO_InitStruct); - - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStruct.GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5; - GPIO_Init(GPIOB, &GPIO_InitStruct); - - GPIO_PinAFConfig(GPIOB, GPIO_PinSource3, GPIO_AF_0); - GPIO_PinAFConfig(GPIOB, GPIO_PinSource4, GPIO_AF_0); - GPIO_PinAFConfig(GPIOB, GPIO_PinSource5, GPIO_AF_0); - #endif - } -#endif - /* Add others */ -} -#endif /* BSP_USING_I2C */ - - - diff --git a/bsp/microchip/samc21/bsp/CMSIS/Documentation/Core/html/index.html b/bsp/microchip/samc21/bsp/CMSIS/Documentation/Core/html/index.html deleted file mode 100644 index 24643bb625b..00000000000 --- a/bsp/microchip/samc21/bsp/CMSIS/Documentation/Core/html/index.html +++ /dev/null @@ -1,196 +0,0 @@ - - - - - -Overview -CMSIS-Core (Cortex-M): Overview - - - - - - - - - - - - - - -
-
- - - - - - - -
-
CMSIS-Core (Cortex-M) -  Version 5.1.2 -
-
CMSIS-Core support for Cortex-M processor-based devices
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-
- -
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    - -
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- - - -
-
- -
-
-
- -
- - - - -
- -
- -
-
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Overview
-
-
-

CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

-
    -
  • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
    • -
  • System exception names to interface to system exceptions without having compatibility issues.
    • -
  • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
    • -
  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
    • -
  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
    • -
  • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
    • -
-

The following sections provide details about the CMSIS-Core (Cortex-M):

- -
-

CMSIS-Core (Cortex-M) in ARM::CMSIS Pack

-

Files relevant to CMSIS-Core (Cortex-M) are present in the following ARM::CMSIS directories:

- - - - - - - - - - - -
File/Folder Content
CMSIS\Documentation\Core This documentation
CMSIS\Core\Include CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.)
Device Arm reference implementations of Cortex-M devices
Device\_Template_Vendor CMSIS-Core Device Templates for extension by silicon vendors
-
-

-Processor Support

-

CMSIS supports the complete range of Cortex-M processors (with exception of Cortex-M1) and the Armv8-M architecture including security extensions.

-

-Cortex-M Reference Manuals

-

The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:

- -

The Cortex-M23 and Cortex-M33 are described with Technical Reference Manuals that are available here:

- -

-Armv8-M Architecture

-

Armv8-M introduces two profiles baseline (for power and area constrained applications) and mainline (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles are supported by CMSIS.

-

The Armv8-M Architecture is described in the Armv8-M Architecture Reference Manual.

-
-

-Tested and Verified Toolchains

-

The CMSIS-Core Device Templates supplied by Arm have been tested and verified with the following toolchains:

-
    -
  • Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)
    • -
  • Arm: Arm Compiler 6.9
    • -
  • Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)
    • -
  • GNU: GNU Tools for Arm Embedded 6.3.1 20170620
    • -
  • IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
    • -
-
-
-
- - - - diff --git a/bsp/microchip/samd51-adafruit-metro-m4/bsp/CMSIS/Documentation/Core/html/index.html b/bsp/microchip/samd51-adafruit-metro-m4/bsp/CMSIS/Documentation/Core/html/index.html deleted file mode 100644 index 24643bb625b..00000000000 --- a/bsp/microchip/samd51-adafruit-metro-m4/bsp/CMSIS/Documentation/Core/html/index.html +++ /dev/null @@ -1,196 +0,0 @@ - - - - - -Overview -CMSIS-Core (Cortex-M): Overview - - - - - - - - - - - - - - -
-
- - - - - - - -
-
CMSIS-Core (Cortex-M) -  Version 5.1.2 -
-
CMSIS-Core support for Cortex-M processor-based devices
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-
- -
-
    - -
-
- - - -
-
- -
-
-
- -
- - - - -
- -
- -
-
-
Overview
-
-
-

CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

-
    -
  • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
    • -
  • System exception names to interface to system exceptions without having compatibility issues.
    • -
  • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
    • -
  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
    • -
  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
    • -
  • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
    • -
-

The following sections provide details about the CMSIS-Core (Cortex-M):

- -
-

CMSIS-Core (Cortex-M) in ARM::CMSIS Pack

-

Files relevant to CMSIS-Core (Cortex-M) are present in the following ARM::CMSIS directories:

- - - - - - - - - - - -
File/Folder Content
CMSIS\Documentation\Core This documentation
CMSIS\Core\Include CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.)
Device Arm reference implementations of Cortex-M devices
Device\_Template_Vendor CMSIS-Core Device Templates for extension by silicon vendors
-
-

-Processor Support

-

CMSIS supports the complete range of Cortex-M processors (with exception of Cortex-M1) and the Armv8-M architecture including security extensions.

-

-Cortex-M Reference Manuals

-

The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:

- -

The Cortex-M23 and Cortex-M33 are described with Technical Reference Manuals that are available here:

- -

-Armv8-M Architecture

-

Armv8-M introduces two profiles baseline (for power and area constrained applications) and mainline (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles are supported by CMSIS.

-

The Armv8-M Architecture is described in the Armv8-M Architecture Reference Manual.

-
-

-Tested and Verified Toolchains

-

The CMSIS-Core Device Templates supplied by Arm have been tested and verified with the following toolchains:

-
    -
  • Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)
    • -
  • Arm: Arm Compiler 6.9
    • -
  • Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)
    • -
  • GNU: GNU Tools for Arm Embedded 6.3.1 20170620
    • -
  • IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
    • -
-
-
-
- - - - diff --git a/bsp/microchip/samd51-seeed-wio-terminal/bsp/CMSIS/Documentation/Core/html/index.html b/bsp/microchip/samd51-seeed-wio-terminal/bsp/CMSIS/Documentation/Core/html/index.html deleted file mode 100644 index 24643bb625b..00000000000 --- a/bsp/microchip/samd51-seeed-wio-terminal/bsp/CMSIS/Documentation/Core/html/index.html +++ /dev/null @@ -1,196 +0,0 @@ - - - - - -Overview -CMSIS-Core (Cortex-M): Overview - - - - - - - - - - - - - - -
-
- - - - - - - -
-
CMSIS-Core (Cortex-M) -  Version 5.1.2 -
-
CMSIS-Core support for Cortex-M processor-based devices
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-
- -
-
    - -
-
- - - -
-
- -
-
-
- -
- - - - -
- -
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-
-
Overview
-
-
-

CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

-
    -
  • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
    • -
  • System exception names to interface to system exceptions without having compatibility issues.
    • -
  • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
    • -
  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
    • -
  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
    • -
  • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
    • -
-

The following sections provide details about the CMSIS-Core (Cortex-M):

- -
-

CMSIS-Core (Cortex-M) in ARM::CMSIS Pack

-

Files relevant to CMSIS-Core (Cortex-M) are present in the following ARM::CMSIS directories:

- - - - - - - - - - - -
File/Folder Content
CMSIS\Documentation\Core This documentation
CMSIS\Core\Include CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.)
Device Arm reference implementations of Cortex-M devices
Device\_Template_Vendor CMSIS-Core Device Templates for extension by silicon vendors
-
-

-Processor Support

-

CMSIS supports the complete range of Cortex-M processors (with exception of Cortex-M1) and the Armv8-M architecture including security extensions.

-

-Cortex-M Reference Manuals

-

The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:

- -

The Cortex-M23 and Cortex-M33 are described with Technical Reference Manuals that are available here:

- -

-Armv8-M Architecture

-

Armv8-M introduces two profiles baseline (for power and area constrained applications) and mainline (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles are supported by CMSIS.

-

The Armv8-M Architecture is described in the Armv8-M Architecture Reference Manual.

-
-

-Tested and Verified Toolchains

-

The CMSIS-Core Device Templates supplied by Arm have been tested and verified with the following toolchains:

-
    -
  • Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)
    • -
  • Arm: Arm Compiler 6.9
    • -
  • Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)
    • -
  • GNU: GNU Tools for Arm Embedded 6.3.1 20170620
    • -
  • IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
    • -
-
-
-
- - - - diff --git a/bsp/microchip/same54/bsp/CMSIS/Documentation/Core/html/index.html b/bsp/microchip/same54/bsp/CMSIS/Documentation/Core/html/index.html deleted file mode 100644 index 24643bb625b..00000000000 --- a/bsp/microchip/same54/bsp/CMSIS/Documentation/Core/html/index.html +++ /dev/null @@ -1,196 +0,0 @@ - - - - - -Overview -CMSIS-Core (Cortex-M): Overview - - - - - - - - - - - - - - -
-
- - - - - - - -
-
CMSIS-Core (Cortex-M) -  Version 5.1.2 -
-
CMSIS-Core support for Cortex-M processor-based devices
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-
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-
    - -
-
- - - -
-
- -
-
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- -
- - - - -
- -
- -
-
-
Overview
-
-
-

CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

-
    -
  • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
    • -
  • System exception names to interface to system exceptions without having compatibility issues.
    • -
  • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
    • -
  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
    • -
  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
    • -
  • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
    • -
-

The following sections provide details about the CMSIS-Core (Cortex-M):

- -
-

CMSIS-Core (Cortex-M) in ARM::CMSIS Pack

-

Files relevant to CMSIS-Core (Cortex-M) are present in the following ARM::CMSIS directories:

- - - - - - - - - - - -
File/Folder Content
CMSIS\Documentation\Core This documentation
CMSIS\Core\Include CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.)
Device Arm reference implementations of Cortex-M devices
Device\_Template_Vendor CMSIS-Core Device Templates for extension by silicon vendors
-
-

-Processor Support

-

CMSIS supports the complete range of Cortex-M processors (with exception of Cortex-M1) and the Armv8-M architecture including security extensions.

-

-Cortex-M Reference Manuals

-

The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:

- -

The Cortex-M23 and Cortex-M33 are described with Technical Reference Manuals that are available here:

- -

-Armv8-M Architecture

-

Armv8-M introduces two profiles baseline (for power and area constrained applications) and mainline (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles are supported by CMSIS.

-

The Armv8-M Architecture is described in the Armv8-M Architecture Reference Manual.

-
-

-Tested and Verified Toolchains

-

The CMSIS-Core Device Templates supplied by Arm have been tested and verified with the following toolchains:

-
    -
  • Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)
    • -
  • Arm: Arm Compiler 6.9
    • -
  • Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)
    • -
  • GNU: GNU Tools for Arm Embedded 6.3.1 20170620
    • -
  • IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
    • -
-
-
-
- - - - diff --git a/bsp/microchip/same70/bsp/CMSIS/Documentation/Core/html/index.html b/bsp/microchip/same70/bsp/CMSIS/Documentation/Core/html/index.html deleted file mode 100644 index 24643bb625b..00000000000 --- a/bsp/microchip/same70/bsp/CMSIS/Documentation/Core/html/index.html +++ /dev/null @@ -1,196 +0,0 @@ - - - - - -Overview -CMSIS-Core (Cortex-M): Overview - - - - - - - - - - - - - - -
-
- - - - - - - -
-
CMSIS-Core (Cortex-M) -  Version 5.1.2 -
-
CMSIS-Core support for Cortex-M processor-based devices
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-
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-
    - -
-
- - - -
-
- -
-
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Overview
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CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

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  • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
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  • System exception names to interface to system exceptions without having compatibility issues.
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  • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
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  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
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  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
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  • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
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The following sections provide details about the CMSIS-Core (Cortex-M):

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CMSIS-Core (Cortex-M) in ARM::CMSIS Pack

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Files relevant to CMSIS-Core (Cortex-M) are present in the following ARM::CMSIS directories:

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File/Folder Content
CMSIS\Documentation\Core This documentation
CMSIS\Core\Include CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.)
Device Arm reference implementations of Cortex-M devices
Device\_Template_Vendor CMSIS-Core Device Templates for extension by silicon vendors
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-Processor Support

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CMSIS supports the complete range of Cortex-M processors (with exception of Cortex-M1) and the Armv8-M architecture including security extensions.

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-Cortex-M Reference Manuals

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The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:

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The Cortex-M23 and Cortex-M33 are described with Technical Reference Manuals that are available here:

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-Armv8-M Architecture

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Armv8-M introduces two profiles baseline (for power and area constrained applications) and mainline (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles are supported by CMSIS.

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The Armv8-M Architecture is described in the Armv8-M Architecture Reference Manual.

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-Tested and Verified Toolchains

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The CMSIS-Core Device Templates supplied by Arm have been tested and verified with the following toolchains:

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  • Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)
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  • Arm: Arm Compiler 6.9
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  • Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)
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  • GNU: GNU Tools for Arm Embedded 6.3.1 20170620
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  • IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
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- - - - diff --git "a/bsp/n32 - \345\277\253\346\215\267\346\226\271\345\274\217.lnk" "b/bsp/n32 - \345\277\253\346\215\267\346\226\271\345\274\217.lnk" new file mode 100644 index 00000000000..d83532d3d65 Binary files /dev/null and "b/bsp/n32 - \345\277\253\346\215\267\346\226\271\345\274\217.lnk" differ diff --git a/bsp/n32/libraries/n32_drivers/SConscript b/bsp/n32/libraries/n32_drivers/SConscript index 107e4d1b333..c235d0d1c3b 100644 --- a/bsp/n32/libraries/n32_drivers/SConscript +++ b/bsp/n32/libraries/n32_drivers/SConscript @@ -7,6 +7,10 @@ cwd = GetCurrentDir() # add the general drivers. src = Split(""" """) +#common driver file gpio,rcc init +src += ['drv_base.c'] + +src += ['drv_base.c'] if GetDepend(['RT_USING_PIN']): src += ['drv_gpio.c'] @@ -20,6 +24,7 @@ if GetDepend(['RT_USING_SERIAL']): if GetDepend(['RT_USING_HWTIMER']): src += ['drv_hwtimer.c'] + if GetDepend(['RT_USING_PWM']): src += ['drv_pwm.c'] @@ -45,6 +50,18 @@ if GetDepend(['RT_USING_RTC']): if GetDepend(['RT_USING_WDT']): src += ['drv_wdt.c'] +if GetDepend(['BSP_USING_PWM']): + src += ['drv_pwm.c'] + +if GetDepend(['BSP_USING_TIM_ETR_CNT']): + src += ['tim_etr_cnt.c'] + +if GetDepend(['BSP_USING_TIM_EXT_COUNTER']): + src += ['drv_tim_external_counter.c'] + +if GetDepend(['BSP_USING_TIM_PULSE_WIDTH']): + src += ['drv_tim_pulse_width.c'] + path = [cwd] path += [cwd + '/config'] diff --git a/bsp/n32/libraries/n32_drivers/drv_base.c b/bsp/n32/libraries/n32_drivers/drv_base.c new file mode 100644 index 00000000000..7288690af62 --- /dev/null +++ b/bsp/n32/libraries/n32_drivers/drv_base.c @@ -0,0 +1,115 @@ +#include + + +#define DBG_TAG "PWM" +#define DBG_LEVEL DBG_LOG +#include +#include "board.h" +/** + * @brief 使能对应GPIO的时钟 + */ +void n32_gpio_rcc_enable(GPIO_Module *gpio_grp) +{ + assert_param(IS_GPIO_ALL_PERIPH(gpio_grp)); + if (GPIOA == gpio_grp) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); + LOG_D("enable gpio rcc GPIOA"); + } + else if (GPIOB == gpio_grp) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE); + LOG_D("enable gpio rcc GPIOB"); + } + else if (GPIOC == gpio_grp) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE); + LOG_D("enable gpio rcc GPIOC"); + } + else if (GPIOD == gpio_grp) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOD, ENABLE); + LOG_D("enable gpio rcc GPIOD"); + } +#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) + else if (GPIOE == gpio_grp) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOE, ENABLE); + } + else if (GPIOF == gpio_grp) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOF, ENABLE); + } + else if (GPIOG == gpio_grp) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOG, ENABLE); + } +#endif +} +/**定时器2的引脚涉及了SWD-JTAG的调试引脚，在复用时需要先设置jSWD-JTAG的复用 + * 复用功能 GPIO端口 + JTMS/SWDIO PA13-----------swd + JTCK/SWCLK A14------------swd + JTDI PA15 + JTDO PB3 + NJTRST PB4 + + * GPIO_ConfigPinRemap(GPIO_RMP_SW_JTAG_SW_ENABLE,ENABLE); +*/ +void gpio_remap_JTAGOFF_SWDON(GPIO_Module *gpio_grp, uint16_t pin) +{ +#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) + + if ((GPIOA == gpio_grp && GPIO_PIN_15) || + (GPIOB == gpio_grp && GPIO_PIN_3) || + (GPIOB == gpio_grp && GPIO_PIN_4)) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE); + GPIO_ConfigPinRemap(GPIO_RMP_SW_JTAG_SW_ENABLE, ENABLE); + } +#endif +} + +/** + * @brief 定时器的时钟使能配置 + */ +void n32_time_rcc_config(TIM_Module *htim) +{ + RT_ASSERT(TIM1 == htim || TIM2 == htim || TIM3 == htim || TIM4 == htim || TIM5 == htim || TIM8 == htim +#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) + ); +#else + || TIM9 == htim); +#endif + + if (TIM1 == htim) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_TIM1, ENABLE); + } + else if (TIM2 == htim) + { + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM2, ENABLE); + } + else if (TIM3 == htim) + { + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM3, ENABLE); + } + else if (TIM4 == htim) + { + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM4, ENABLE); + } + else if (TIM5 == htim) + { + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM5, ENABLE); + } + else if (TIM8 == htim) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_TIM8, ENABLE); + } +#if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) + else if (TIM9 == htim) + { + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM9, ENABLE); + } +#endif +} diff --git a/bsp/n32/libraries/n32_drivers/drv_base.h b/bsp/n32/libraries/n32_drivers/drv_base.h new file mode 100644 index 00000000000..de911b7e610 --- /dev/null +++ b/bsp/n32/libraries/n32_drivers/drv_base.h @@ -0,0 +1,25 @@ +#ifndef __DRV_BASE__ +#define __DRV_BASE__ +#include "board.h" +/** + * @brief 使能对应GPIO的时钟 + */ + void n32_gpio_rcc_enable(GPIO_Module *gpio_grp); + + /** + * @brief 定时器的时钟使能配置 + */ + void n32_time_rcc_config(TIM_Module *htim); + + /**定时器2的引脚涉及了SWD-JTAG的调试引脚，在复用时需要先设置jSWD-JTAG的复用 + * 复用功能 GPIO端口 + JTMS/SWDIO PA13-----------swd + JTCK/SWCLK A14------------swd + JTDI PA15 + JTDO PB3 + NJTRST PB4 + + * GPIO_ConfigPinRemap(GPIO_RMP_SW_JTAG_SW_ENABLE,ENABLE); +*/ +void gpio_remap_JTAGOFF_SWDON(GPIO_Module *gpio_grp, uint16_t pin); +#endif diff --git a/bsp/n32/libraries/n32_drivers/drv_pwm.c b/bsp/n32/libraries/n32_drivers/drv_pwm.c new file mode 100644 index 00000000000..6989be7eb0c --- /dev/null +++ b/bsp/n32/libraries/n32_drivers/drv_pwm.c @@ -0,0 +1,1070 @@ +/** + * @file drv_pwm.c + * @brief + * @author jiache (wanghuan3037@fiberhome.com) + * @version 1.0 + * @date 2025-12-02 + * + * @copyright Copyright (c) 2025 58 + * + * 2025-12-2 + * 1.PWM驱动的日志加入标签 + * 2.pwm驱动设置都是设置的周期时间单位ns，脉宽也是时间ns + * 3.pwm驱动使用Kconfig方式配置，将头文件的配置移动到c文件中；定时器1的4个复用通道测试OK + * 4.定时器2的remap=0，测试PA0-PA3输出pwm OK ；remap=3PA15 PB3 PB10 PB11测试OK + * 5.定时器3的remap=0，测试PA6,PA7,PB0,PB1输出pwm OK ；定时器3remap=3 PC6-PC9输出测试OK + * + *2025-12-06 + 1.N32L406的定时器2pwm PA15,PB3，PB10,PB11可用，添加了Kconfig配置 + 2.测试发现tim2 的PA0,PA1,输出pwm异常，PA2,PB11输出正常 + 3.测试发现tim2 的PA8,PA9,PA10,PA11,输出pwm出正常 + 4.测试发现tim3 的PA6,PA7,PB0,PB1,输出pwm出正常 + 5.测试发现tim3 的Pb4,pb5,pc8,pc9,输出pwm出正常 + 6.测试发现tim3 的pc6,pc7,输出pwm出正常 + +2025-12-18 + n32g52x的定时器tim1的pa-pa11的pwm配置加上了，未测试 + */ +#include +#ifdef BSP_USING_PWM + +#define DBG_TAG "PWM" +#include +#define PWM_LOG_E(...) LOG_E(__VA_ARGS__) +#define PWM_LOG_D(...) LOG_I(__VA_ARGS__) + +#include +#include +#include +#include +#include + +#define MAX_PERIOD 0xffff +#define MIN_PERIOD 1 +#define MIN_PULSE 1 + +struct n32_pwm_channel +{ + GPIO_Module *gpio_grp; // pwm 使用的gpio分组 + uint16_t pin; // pwm 使用的gpio pin + uint16_t pwm_mode; // pwm 使用的gpio pin +#if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) + uint32_t gpio_af; // 引脚复用功能 +#endif + char *info; +}; + +struct n32_pwm +{ + struct rt_device_pwm pwm_device; // 设备驱动框架的pwm对象 + TIM_Module *tim; // 定时器指针 + struct n32_pwm_channel ch[4]; // 定时器通道 + uint32_t prescaler; // 定时器预分频系数 +#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) + uint32_t gpio_af; // 引脚复用功能 +#endif + char *name; // pwm名字也是驱动的名字 +}; + +/** + * @brief 定义定时器对象 + * + */ +static struct n32_pwm n32_pwm_obj[] = + { +#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) +/* ================================================定时器1配置定义================================================*/ +#ifdef BSP_USING_TIM1_PWM + { + .tim = TIM1, + .name = "pwm1", + +/****************************通道定义*********************************** */ + +#ifdef TIM1_REMAP_0 + .gpio_af = 0, + +#ifdef BSP_USING_TIM1_PWM_CH1 + .ch[0].gpio_grp = GPIOA, + .ch[0].pin = GPIO_PIN_8, + .ch[0].pwm_mode = TIM_OCMODE_PWM1, + .ch[0].info = "TIM1 PWMCH1 PA8", +#endif /* BSP_USING_TIM1_PWM_CH1 */ +#ifdef BSP_USING_TIM1_PWM_CH2 + .ch[1].gpio_grp = GPIOA, + .ch[1].pin = GPIO_PIN_9, + .ch[1].pwm_mode = TIM_OCMODE_PWM1, + .ch[1].info = "TIM1 PWMCH2 PA9", +#endif /* BSP_USING_TIM1_PWM_CH2 */ +#ifdef BSP_USING_TIM1_PWM_CH3 + .ch[2].gpio_grp = GPIOA, + .ch[2].pin = GPIO_PIN_10, + .ch[2].pwm_mode = TIM_OCMODE_PWM1, + .ch[2].info = "TIM1 PWMCH3 PA10", +#endif /* BSP_USING_TIM1_PWM_CH3 */ +#ifdef BSP_USING_TIM1_PWM_CH4 + .ch[3].gpio_grp = GPIOA, + .ch[3].pin = GPIO_PIN_11, + .ch[3].pwm_mode = TIM_OCMODE_PWM1, + .ch[3].info = "TIM1 PWMCH4 PA11", +#endif /* BSP_USING_TIM1_PWM_CH4 */ +#endif /*TIM1_REMAP_0*/ + +#ifdef TIM1_REMAP_3 + .gpio_af = GPIO_ALL_RMP_TIM1, + +#ifdef BSP_USING_TIM1_PWM_CH1 + .ch[0].gpio_grp = GPIOE, + .ch[0].pin = GPIO_PIN_9, + .ch[0].pwm_mode = TIM_OCMODE_PWM1, + .ch[0].info = "TIM1 PWMCH1 PE9", +#endif /* TIM1_PWM_CFG_CH1 */ +#ifdef BSP_USING_TIM1_PWM_CH2 + .ch[1].gpio_grp = GPIOE, + .ch[1].pin = GPIO_PIN_11, + .ch[1].pwm_mode = TIM_OCMODE_PWM1, + .ch[1].info = "TIM1 PWMCH2 PE11", +#endif /* TIM1_PWM_CFG_CH2 */ +#ifdef BSP_USING_TIM1_PWM_CH3 + .ch[2].gpio_grp = GPIOE, + .ch[2].pin = GPIO_PIN_13, + .ch[2].pwm_mode = TIM_OCMODE_PWM1, + .ch[2].info = "TIM1 PWMCH3 PE13", +#endif /* TIM1_PWM_CFG_CH3 */ +#ifdef BSP_USING_TIM1_PWM_CH4 + .ch[3].gpio_grp = GPIOE, + .ch[3].pin = GPIO_PIN_14, + .ch[3].pwm_mode = TIM_OCMODE_PWM1, + .ch[3].info = "TIM1 PWMCH4 PE14", +#endif /* TIM1_PWM_CFG_CH4 */ +#endif /*TIM1_REMAP_3*/ + + /****************************通道定义*********************************** */ + }, +#endif /*BSP_USING_TIM1_PWM*/ + +/* ================================================定时器1配置定义================================================*/ + +/* ================================================定时器2配置定义================================================*/ +#ifdef BSP_USING_TIM2_PWM + { + .tim = TIM2, + .name = "pwm2", + +/****************************通道定义*********************************** */ + +#ifdef TIM2_REMAP_0 + .gpio_af = 0, +#endif +#ifdef TIM2_REMAP_1 + .gpio_af = GPIO_PartialRemap1_TIM2, +#endif +#ifdef TIM2_REMAP_2 + .gpio_af = GPIO_PART2_RMP_TIM2, +#endif +#ifdef TIM2_REMAP_3 + .gpio_af = GPIO_ALL_RMP_TIM2, +#endif + +#if defined(TIM2_REMAP_0) || defined(TIM2_REMAP_2) +#ifdef BSP_USING_TIM2_PWM_CH0 + .ch[0].gpio_grp = GPIOA, + .ch[0].pin = GPIO_PIN_0, + .ch[0].pwm_mode = TIM_OCMODE_PWM1, + .ch[0].info = "TIM2 PWMCH0 PA0", +#endif /*TIM2_PWM_CFG_CH1 */ + +#ifdef BSP_USING_TIM2_PWM_CH1 + .ch[1].gpio_grp = GPIOA, + .ch[1].pin = GPIO_PIN_1, + .ch[1].pwm_mode = TIM_OCMODE_PWM1, + .ch[1].info = "TIM2 PWMCH1 PA1", +#endif /*TIM2_PWM_CFG_CH2 */ +#endif /*TIM2_REMAP_1 TIM2_REMAP_3 */ + +#if defined(TIM2_REMAP_1) || defined(TIM2_REMAP_3) +#ifdef BSP_USING_TIM2_PWM_CH0 + .ch[0].gpio_grp = GPIOA, + .ch[0].pin = GPIO_PIN_15, + .ch[0].pwm_mode = TIM_OCMODE_PWM1, + .ch[0].info = "TIM2 PWMCH0 PA15", +#endif /*TIM2_PWM_CFG_CH1 */ + +#ifdef BSP_USING_TIM2_PWM_CH1 + .ch[1].gpio_grp = GPIOB, + .ch[1].pin = GPIO_PIN_3, + .ch[1].pwm_mode = TIM_OCMODE_PWM1, + .ch[1].info = "TIM2 PWMCH1 PB3", +#endif /*TIM2_PWM_CFG_CH2 */ +#endif /*defined(TIM2_REMAP_2) ||defined(TIM2_REMAP_4) */ + +#if defined(TIM2_REMAP_0) || defined(TIM2_REMAP_1) +#ifdef BSP_USING_TIM2_PWM_CH2 + .ch[2].gpio_grp = GPIOA, + .ch[2].pin = GPIO_PIN_2, + .ch[2].pwm_mode = TIM_OCMODE_PWM1, + .ch[2].info = "TIM2 PWMCH2 PA2", +#endif /*TIM2_PWM_CFG_CH2 */ +#ifdef BSP_USING_TIM2_PWM_CH3 + .ch[3].gpio_grp = GPIOA, + .ch[3].pin = GPIO_PIN_3, + .ch[3].pwm_mode = TIM_OCMODE_PWM1, + .ch[3].info = "TIM2 PWMCH3 PA3", +#endif /*TIM2_PWM_CFG_CH2 */ +#endif /*defined(TIM2_REMAP_0) ||defined(TIM2_REMAP_1)*/ + +#if defined(TIM2_REMAP_2) || defined(TIM2_REMAP_3) +#ifdef BSP_USING_TIM2_PWM_CH2 + .ch[2].gpio_grp = GPIOB, + .ch[2].pin = GPIO_PIN_10, + .ch[2].pwm_mode = TIM_OCMODE_PWM1, + .ch[2].info = "TIM2 PWMCH2 PB10", +#endif /*TIM2_PWM_CFG_CH2 */ +#ifdef BSP_USING_TIM2_PWM_CH3 + .ch[3].gpio_grp = GPIOB, + .ch[3].pin = GPIO_PIN_11, + .ch[3].pwm_mode = TIM_OCMODE_PWM1, + .ch[3].info = "TIM2 PWMCH3 PB11", +#endif /*TIM2_PWM_CFG_CH2 */ +#endif /*defined(TIM2_REMAP_2) ||defined(TIM2_REMAP_3)*/ + +#endif /*BSP_USING_TIM2_PWM*/ + }, + +/* ================================================定时器3配置定义================================================*/ +#ifdef BSP_USING_TIM3_PWM + { + .tim = TIM3, + .name = "pwm3", +#ifdef TIM3_REMAP_0 + .gpio_af = 0, +#endif +#ifdef TIM3_REMAP_2 + .gpio_af = GPIO_PART1_RMP_TIM3, +#endif +#ifdef TIM3_REMAP_3 + .gpio_af = GPIO_ALL_RMP_TIM3, +#endif +#if defined(TIM3_REMAP_0) +#ifdef BSP_USING_TIM3_PWM_CH0 + .ch[0].gpio_grp = GPIOA, + .ch[0].pin = GPIO_PIN_6, + .ch[0].pwm_mode = TIM_OCMODE_PWM1, + .ch[0].info = "TIM3 PWMCH0 PA6", +#endif /*TIM2_PWM_CFG_CH1 */ + +#ifdef BSP_USING_TIM3_PWM_CH1 + .ch[1].gpio_grp = GPIOA, + .ch[1].pin = GPIO_PIN_7, + .ch[1].pwm_mode = TIM_OCMODE_PWM1, + .ch[1].info = "TIM3 PWMCH1 PA7", +#endif /*TIM2_PWM_CFG_CH2 */ +#endif /*TIM2_REMAP_0 */ + +#if defined(TIM3_REMAP_2) +#ifdef BSP_USING_TIM3_PWM_CH0 + .ch[0].gpio_grp = GPIOB, + .ch[0].pin = GPIO_PIN_4, + .ch[0].pwm_mode = TIM_OCMODE_PWM1, + .ch[0].info = "TIM3 PWMCH0 PB4", +#endif /*TIM2_PWM_CFG_CH1 */ + +#ifdef BSP_USING_TIM3_PWM_CH1 + .ch[1].gpio_grp = GPIOB, + .ch[1].pin = GPIO_PIN_5, + .ch[1].pwm_mode = TIM_OCMODE_PWM1, + .ch[1].info = "TIM3 PWMCH1 PB5", +#endif /*TIM2_PWM_CFG_CH2 */ +#endif /*TIM2_REMAP_2 */ + +#if defined(TIM3_REMAP_0) || defined(TIM3_REMAP_2) +#ifdef BSP_USING_TIM3_PWM_CH2 + .ch[2].gpio_grp = GPIOB, + .ch[2].pin = GPIO_PIN_0, + .ch[2].pwm_mode = TIM_OCMODE_PWM1, + .ch[2].info = "TIM3 PWMCH2 PB0", +#endif /*BSP_USING_TIM3_PWM_CH2 */ +#ifdef BSP_USING_TIM3_PWM_CH3 + .ch[3].gpio_grp = GPIOB, + .ch[3].pin = GPIO_PIN_1, + .ch[3].pwm_mode = TIM_OCMODE_PWM1, + .ch[3].info = "TIM3 PWMCH3 PB1", +#endif /*BSP_USING_TIM3_PWM_CH3 */ +#endif /*defined(TIM3_REMAP_0) || defined(TIM3_REMAP_2)*/ + +#if defined(TIM3_REMAP_3) +#ifdef BSP_USING_TIM3_PWM_CH0 + .ch[0].gpio_grp = GPIOC, + .ch[0].pin = GPIO_PIN_6, + .ch[0].pwm_mode = TIM_OCMODE_PWM1, + .ch[0].info = "TIM3 PWMCH0 PC6", +#endif /*BSP_USING_TIM3_PWM_CH0 */ +#ifdef BSP_USING_TIM3_PWM_CH1 + .ch[1].gpio_grp = GPIOC, + .ch[1].pin = GPIO_PIN_7, + .ch[1].pwm_mode = TIM_OCMODE_PWM1, + .ch[1].info = "TIM3 PWMCH1 PC7", +#endif /*BSP_USING_TIM3_PWM_CH1 */ +#ifdef BSP_USING_TIM3_PWM_CH2 + .ch[2].gpio_grp = GPIOC, + .ch[2].pin = GPIO_PIN_8, + .ch[2].pwm_mode = TIM_OCMODE_PWM1, + .ch[2].info = "TIM3 PWMCH2 PC8", +#endif /*BSP_USING_TIM3_PWM_CH2 */ +#ifdef BSP_USING_TIM3_PWM_CH3 + .ch[3].gpio_grp = GPIOC, + .ch[3].pin = GPIO_PIN_9, + .ch[3].pwm_mode = TIM_OCMODE_PWM1, + .ch[3].info = "TIM3 PWMCH3 PC9", +#endif /*BSP_USING_TIM3_PWM_CH3 */ +#endif /*defined(TIM3_REMAP_3)*/ + }, +#endif /*BSP_USING_TIM3_PWM */ + +#else //=========================== defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)===================== + +#ifdef BSP_USING_TIM1_PWM //-------------------BSP_USING_TIM1_PWM-------------------------- +#define N32L406_CFG + { + .tim = TIM1, + .name = "pwm1", +#ifdef BSP_USING_TIM1_PWM_CH1 + .ch[0].gpio_grp = GPIOA, + .ch[0].pin = GPIO_PIN_8, + .ch[0].pwm_mode = TIM_OCMODE_PWM1, + .ch[0].info = "TIM1 PWMCH1 PA8", + .ch[0].gpio_af = GPIO_AF2_TIM1, +#endif /* TIM1_PWM_CFG_CH1 */ + +#ifdef BSP_USING_TIM1_PWM_CH2 + .ch[1].gpio_grp = GPIOA, + .ch[1].pin = GPIO_PIN_9, + .ch[1].pwm_mode = TIM_OCMODE_PWM1, + .ch[1].info = "TIM1 PWMCH2 PA9", + .ch[1].gpio_af = GPIO_AF2_TIM1, +#endif /* TIM1_PWM_CFG_CH2 */ +#ifdef BSP_USING_TIM1_PWM_CH3 + .ch[2].gpio_grp = GPIOA, + .ch[2].pin = GPIO_PIN_10, + .ch[2].pwm_mode = TIM_OCMODE_PWM1, + .ch[2].info = "TIM1 PWMCH3 PA10", + .ch[2].gpio_af = GPIO_AF2_TIM1, +#endif /* TIM1_PWM_CFG_CH3 */ +#ifdef BSP_USING_TIM1_PWM_CH4 + .ch[3].gpio_grp = GPIOA, + .ch[3].pin = GPIO_PIN_11, + .ch[3].pwm_mode = TIM_OCMODE_PWM1, + .ch[3].info = "TIM1 PWMCH4 PA11", + .ch[3].gpio_af = GPIO_AF2_TIM1, +#endif /* TIM1_PWM_CFG_CH4 */ + }, +#endif /*-------------------------------------BSP_USING_TIM1_PWM--------------11111------------*/ + +#ifdef BSP_USING_TIM2_PWM //-------------------BSP_USING_TIM2_PWM--------------222222------------ +#define N32L406_CFG_TIM2 + { + .tim = TIM2, + .name = "pwm2", +#ifdef BSP_USING_TIM2_PWM_CH1 +#ifdef TIM2_PWM_CH1_PA0 + .ch[0].gpio_grp = GPIOA, + .ch[0].pin = GPIO_PIN_0, + .ch[0].info = "TIM2 PWMCH1 PA0", + .ch[0].gpio_af = GPIO_AF2_TIM2, +#endif /* TIM2_PWM_CH1_PA0 */ +#ifdef TIM2_PWM_CH1_PA15 + .ch[0].gpio_grp = GPIOA, + .ch[0].pin = GPIO_PIN_15, + .ch[0].info = "TIM2 PWMCH1 PA15", + .ch[0].gpio_af = GPIO_AF5_TIM2, +#endif /* TIM2_PWM_CH1_PA15 */ + .ch[0].pwm_mode = TIM_OCMODE_PWM1, +#endif /* TIM2_PWM_CFG_CH1 */ + +#ifdef BSP_USING_TIM2_PWM_CH2 +#ifdef TIM2_PWM_CH2_PA1 + .ch[1].gpio_grp = GPIOA, + .ch[1].pin = GPIO_PIN_1, + .ch[1].info = "TIM2 PWMCH2 PA1", +#endif /* TIM2_PWM_CH2_PA1 */ +#ifdef TIM2_PWM_CH2_PB3 + .ch[1].gpio_grp = GPIOB, + .ch[1].pin = GPIO_PIN_3, + .ch[1].info = "TIM2 PWMCH2 PB3", +#endif /* TIM2_PWM_CH2_PB3 */ + .ch[1].gpio_af = GPIO_AF2_TIM2, + .ch[1].pwm_mode = TIM_OCMODE_PWM1, +#endif /* TIM2_PWM_CFG_CH2 */ +#ifdef BSP_USING_TIM2_PWM_CH3 +#ifdef TIM2_PWM_CH3_PA2 + .ch[2].gpio_grp = GPIOA, + .ch[2].pin = GPIO_PIN_2, + .ch[2].info = "TIM2 PWMCH3 PA2", +#endif /* TIM2_PWM_CH3_PA2 */ +#ifdef TIM2_PWM_CH3_PB10 + .ch[2].gpio_grp = GPIOB, + .ch[2].pin = GPIO_PIN_10, + .ch[2].info = "TIM2 PWMCH3 PB10", +#endif /* TIM2_PWM_CH3_PB10 */ + .ch[2].pwm_mode = TIM_OCMODE_PWM1, + .ch[2].gpio_af = GPIO_AF2_TIM2, +#endif /* TIM2_PWM_CFG_CH3 */ +#ifdef BSP_USING_TIM2_PWM_CH4 + .ch[3].gpio_grp = GPIOB, + .ch[3].pin = GPIO_PIN_11, + .ch[3].info = "TIM2 PWMCH4 PB11", + .ch[3].gpio_af = GPIO_AF2_TIM2, + .ch[3].pwm_mode = TIM_OCMODE_PWM1, +#endif /* TIM2_PWM_CFG_CH4 */ + }, +#endif /*-------------------------------------BSP_USING_TIM2_PWM-------------------222222-------*/ + +#ifdef BSP_USING_TIM3_PWM //-------------------BSP_USING_TIM3_PWM--------------33333333------------ +#define N32L406_CFG_TIM3 + { + .tim = TIM3, + .name = "pwm3", +#ifdef BSP_USING_TIM3_PWM_CH1 +#ifdef TIM3_PWM_CH1_PA6 + .ch[0].gpio_grp = GPIOA, + .ch[0].pin = GPIO_PIN_6, + .ch[0].info = "TIM3 PWMCH1 PA6", + +#endif /* TIM3_PWM_CH1_PA6 */ +#ifdef TIM3_PWM_CH1_PB4 + .ch[0].gpio_grp = GPIOB, + .ch[0].pin = GPIO_PIN_4, + .ch[0].info = "TIM3 PWMCH1 PB4", +#endif /* TIM3_PWM_CH1_PB4 */ +#ifdef TIM3_PWM_CH1_PC6 + .ch[0].gpio_grp = GPIOC, + .ch[0].pin = GPIO_PIN_6, + .ch[0].info = "TIM3 PWMCH1 PC6", +#endif /* TIM3_PWM_CH1_PC6 */ + .ch[0].gpio_af = GPIO_AF2_TIM3, + .ch[0].pwm_mode = TIM_OCMODE_PWM1, +#endif /* TIM3_PWM_CFG_CH1 */ + +#ifdef BSP_USING_TIM3_PWM_CH2 +#ifdef TIM3_PWM_CH2_PA7 + .ch[1].gpio_grp = GPIOA, + .ch[1].pin = GPIO_PIN_7, + .ch[1].info = "TIM3 PWMCH2 PA7", + .ch[1].gpio_af = GPIO_AF2_TIM3, +#endif /* TIM3_PWM_CH2_PA7 */ +#ifdef TIM3_PWM_CH2_PB5 + .ch[1].gpio_grp = GPIOB, + .ch[1].pin = GPIO_PIN_5, + .ch[1].info = "TIM3 PWMCH2 PB5", + .ch[1].gpio_af = GPIO_AF4_TIM3, +#endif /* TIM3_PWM_CH2_PB5 */ +#ifdef TIM3_PWM_CH2_PC7 + .ch[1].gpio_grp = GPIOC, + .ch[1].pin = GPIO_PIN_7, + .ch[1].info = "TIM3 PWMCH2 PC7", + .ch[1].gpio_af = GPIO_AF2_TIM3, +#endif /* TIM3_PWM_CH2_PC7 */ + .ch[1].pwm_mode = TIM_OCMODE_PWM1, +#endif /* TIM3_PWM_CFG_CH2 */ +#ifdef BSP_USING_TIM3_PWM_CH3 +#ifdef TIM3_PWM_CH3_PB0 + .ch[2].gpio_grp = GPIOB, + .ch[2].pin = GPIO_PIN_0, + .ch[2].info = "TIM3 PWMCH3 PB0", +#endif /* TIM3_PWM_CH3_PB0 */ +#ifdef TIM3_PWM_CH3_PC8 + .ch[2].gpio_grp = GPIOC, + .ch[2].pin = GPIO_PIN_8, + .ch[2].info = "TIM3 PWMCH3 PC8", +#endif /* TIM3_PWM_CH3_PC8 */ + .ch[2].pwm_mode = TIM_OCMODE_PWM1, + .ch[2].gpio_af = GPIO_AF2_TIM3, +#endif /* TIM3_PWM_CFG_CH3 */ +#ifdef BSP_USING_TIM3_PWM_CH4 +#ifdef TIM3_PWM_CH4_PB1 + .ch[3].gpio_grp = GPIOB, + .ch[3].pin = GPIO_PIN_1, + .ch[3].info = "TIM3 PWMCH4 PB1", +#endif /* TIM3_PWM_CH4_PB1 */ +#ifdef TIM3_PWM_CH4_PC9 + .ch[3].gpio_grp = GPIOC, + .ch[3].pin = GPIO_PIN_9, + .ch[3].info = "TIM3 PWMCH4 PC9", +#endif /* TIM3_PWM_CH4_PC9 */ + .ch[3].gpio_af = GPIO_AF2_TIM3, + .ch[3].pwm_mode = TIM_OCMODE_PWM1, +#endif /* TIM3_PWM_CFG_CH4 */ + }, +#endif /*-------------------------------------BSP_USING_TIM3_PWM-------------------3333333-------*/ + +#endif +}; + +// /** +// * @brief 通道配置加载，根据配置宏加载 +// * +// */ +// void n32_load_channel_cfg(void) +// { +// PWM_LOG_D("%s %d ", __FUNCTION__, __LINE__); +// /*******************************BSP_USING_TIM1_PWM********************************* */ +// #ifdef BSP_USING_TIM1_PWM +// rt_memset(n32_pwm_obj[TIM1_INDEX].ch, 0, 4 * sizeof(struct n32_pwm_channel)); +// #ifdef BSP_USING_TIM2_PWM_CH1 +// struct n32_pwm_channel t1h1 = TIM1_PWM_CFG_CH1; +// RT_ASSERT(t1h1.ch_num < 4); +// n32_pwm_obj[TIM1_INDEX].ch[t1h1.ch_num] = t1h1; +// #endif +// #ifdef BSP_USING_TIM1_PWM_CH4 +// struct n32_pwm_channel t1h4 = TIM1_PWM_CFG_CH4; +// RT_ASSERT(t1h4.ch_num < 4); +// n32_pwm_obj[TIM1_INDEX].ch[t1h4.ch_num] = t1h4; +// #endif +// #endif +// /*******************************BSP_USING_TIM2_PWM********************************* */ + +// #ifdef BSP_USING_TIM2_PWM // 定时器2 +// rt_memset(n32_pwm_obj[TIM2_INDEX].ch, 0, 4 * sizeof(struct n32_pwm_channel)); +// #ifdef BSP_USING_TIM2_PWM_CH1 // 通道一 +// struct n32_pwm_channel t2h1 = TIM2_PWM_CFG_CH1; +// RT_ASSERT(t2h1.ch_num < 4); +// n32_pwm_obj[TIM2_INDEX].ch[t2h1.ch_num] = t2h1; +// #endif +// #ifdef BSP_USING_TIM2_PWM_CH2 // 通道2 +// struct n32_pwm_channel t2h2 = TIM2_PWM_CFG_CH2; +// RT_ASSERT(t2h2.ch_num < 4); +// n32_pwm_obj[TIM2_INDEX].ch[t2h2.ch_num] = t2h2; +// #endif +// #endif +// } +/** + * 获取定时器时钟频率 + */ +static rt_uint32_t tim_clock_get(TIM_Module *htim) +{ + RCC_ClocksType RCC_Clocks; + RCC_GetClocksFreqValue(&RCC_Clocks); + if (htim == TIM1 || htim == TIM8) + { + return RCC_Clocks.Pclk2Freq * 2; + } + else + { + return RCC_Clocks.Pclk1Freq * 2; + } +} + +/** + * + * 通道pwm输出使能控制 + * + */ +static rt_err_t drv_pwm_enable(struct n32_pwm *pwm, const rt_uint32_t channel, rt_bool_t enable) +{ + TIM_Module *time = pwm->tim; + + uint16_t tim_ch; + switch (channel) + { + case 0: + tim_ch = TIM_CH_1; + break; + case 1: + tim_ch = TIM_CH_2; + break; + case 2: + tim_ch = TIM_CH_3; + break; + case 3: + tim_ch = TIM_CH_4; + + default: + break; + } + + TIM_EnableCapCmpCh(time, tim_ch, enable ? TIM_CAP_CMP_ENABLE : TIM_CAP_CMP_DISABLE); + + PWM_LOG_D("%s %d ch enable ch = %x ", __FUNCTION__, __LINE__, channel); + return RT_EOK; +} +/* +互补输出使能控制 +*/ +static rt_err_t drv_pwmn_enable(struct n32_pwm *pwm, const rt_uint16_t channel, rt_bool_t enable) +{ + /* Converts the channel number to the channel number of Hal library */ + uint16_t tim_ch; + switch (channel) + { + case 0: + tim_ch = TIM_CH_1; + break; + case 1: + tim_ch = TIM_CH_2; + break; + case 2: + tim_ch = TIM_CH_3; + break; + case 3: + tim_ch = TIM_CH_4; + + default: + break; + } + // 互补输出控制 + TIM_EnableCapCmpChN(pwm->tim, tim_ch, enable ? TIM_CAP_CMP_N_ENABLE : TIM_CAP_CMP_N_DISABLE); + + return RT_EOK; +} +/** + * @brief 获取定时器的工作周期和占空比ns + */ +static rt_err_t drv_pwm_get(struct n32_pwm *pwm, struct rt_pwm_configuration *configuration) +{ + TIM_Module *htim = pwm->tim; + + TIM_Module *tim = pwm->tim; + // 得到定时器的时钟频率 + rt_uint32_t tim_clock = tim_clock_get(tim); + /* 转换为纳秒Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */ + // 1.计算得到定时器的时钟频率，单位MHz + tim_clock /= 1000000UL; + // 计算得到周期，单位nS 重载值x分频值 + uint32_t period = TIM_GetAutoReload(tim) + 1; + uint32_t psc = tim->PSC + 1; + configuration->period = period * psc * 1000UL / tim_clock; + + // 计算得到脉宽，单位nS + uint32_t cmp = 0; + switch (configuration->channel) + { + case 0: + cmp = TIM_GetCap1(htim); + break; + case 1: + cmp = TIM_GetCap2(htim); + break; + case 2: + cmp = TIM_GetCap3(htim); + break; + case 3: + cmp = TIM_GetCap4(htim); + break; + default: + cmp = 0; + break; + } + + configuration->pulse = (cmp + 1) * (psc) * 1000UL / tim_clock; + PWM_LOG_D("period = %d pulse= %d ", __FUNCTION__, __LINE__, configuration->period, configuration->pulse); + + return RT_EOK; +} + +/** + * @brief 设置定时器的工作周期 + * + * @param pwm + * @param configuration + * @return rt_err_t + */ +static rt_err_t drv_pwm_set_period(struct n32_pwm *pwm, struct rt_pwm_configuration *configuration) +{ + + rt_uint32_t period; + rt_uint64_t tim_clock, psc; + + tim_clock = tim_clock_get(pwm->tim); + /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */ + tim_clock /= 1000000UL; + period = (rt_uint64_t)configuration->period * tim_clock / 1000ULL; + psc = period / MAX_PERIOD + 1; + period = period / psc; + // 1.设置分频 + TIM_ConfigPrescaler(pwm->tim, psc - 1, TIM_PSC_RELOAD_MODE_UPDATE); + + if (period < MIN_PERIOD) + { + period = MIN_PERIOD; + } + // 2.修改重载值，也就是周期 + TIM_SetAutoReload(pwm->tim, period - 1); + + PWM_LOG_D("%s %d psc=%d period %d ", __FUNCTION__, __LINE__, psc, period); + return RT_EOK; +} +/** + * @brief 设置定时器的占空比 + * + * @param pwm + * @param configuration + * @return rt_err_t + */ +static rt_err_t drv_pwm_set_pulse(struct n32_pwm *pwm, struct rt_pwm_configuration *configuration) +{ + + rt_uint32_t period, pulse; + rt_uint32_t tim_clock; + /* Converts the channel number to the channel number of Hal library */ + TIM_Module *tim = pwm->tim; + tim_clock = tim_clock_get(tim); + /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */ + // 1.计算得到定时器的时钟频率，单位MHz + tim_clock /= 1000000UL; + // 计算得到比较器的值 + period = (TIM_GetAutoReload(tim) + 1) * (TIM_GetPrescaler(tim) + 1) * 1000UL / tim_clock; + pulse = (rt_uint64_t)configuration->pulse * (TIM_GetAutoReload(tim) + 1) / period; + + if (pulse < MIN_PULSE) + { + pulse = MIN_PULSE; + } + /*To determine user input, output high level is required*/ + else if (pulse >= period) + { + pulse = period + 1; + } + PWM_LOG_D("pulse = %d", pulse); + // 设置比较值 + switch (configuration->channel) + { + case 0: + TIM_SetCmp1(tim, pulse); + break; + case 1: + TIM_SetCmp2(tim, pulse); + break; + case 2: + TIM_SetCmp3(tim, pulse); + break; + case 3: + TIM_SetCmp4(tim, pulse); + break; + default: + configuration->pulse = 0; + break; + } + + TIM_SetCnt(tim, 0); + TIM_GenerateEvent(tim, TIM_EVT_SRC_UPDATE); + + return RT_EOK; +} + +static rt_err_t drv_pwm_set(struct n32_pwm *pwm, struct rt_pwm_configuration *configuration) +{ + + rt_uint32_t period, pulse; + rt_uint32_t tim_clock, psc; + /* Converts the channel number to the channel number of Hal library */ + TIM_Module *tim = pwm->tim; + tim_clock = tim_clock_get(tim); + /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */ + // 1.计算得到定时器的时钟频率，单位MHz + tim_clock /= 1000000UL; + PWM_LOG_D("TIME CLK = %dMHz,PWM fre = %dHz", tim_clock, 1000 * 1000 * 1000 / configuration->period); + period = (rt_uint64_t)configuration->period * tim_clock / 1000ULL; + // 得到预分频值 + psc = period / MAX_PERIOD + 1; + // 得到重载值 + period = period / psc; + + // 1.设置分频 + TIM_ConfigPrescaler(tim, psc - 1, TIM_PSC_RELOAD_MODE_UPDATE); + + if (period < MIN_PERIOD) + { + period = MIN_PERIOD; + } + // 2.修改重载值，也就是周期 + TIM_SetAutoReload(tim, period - 1); + // PWM_LOG_D("TIME period %d", period); + // 计算得到比较器的值 + pulse = (rt_uint64_t)configuration->pulse * tim_clock / psc / 1000ULL; + if (pulse < MIN_PULSE) + { + pulse = MIN_PULSE; + } + /*To determine user input, output high level is required*/ + else if (pulse >= period) + { + pulse = period + 1; + } + PWM_LOG_D("TIME ch %d = pulse %d psc=%d period=%d", configuration->channel, pulse, psc, period); + + // 设置比较值 + switch (configuration->channel) + { + case 0: + TIM_SetCmp1(tim, pulse); + break; + case 1: + TIM_SetCmp2(tim, pulse); + break; + case 2: + TIM_SetCmp3(tim, pulse); + break; + case 3: + TIM_SetCmp4(tim, pulse); + break; + default: + configuration->pulse = 0; + break; + } + + TIM_SetCnt(tim, 0); + TIM_GenerateEvent(tim, TIM_EVT_SRC_UPDATE); + + return RT_EOK; +} + +static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + struct n32_pwm *pwm = (struct n32_pwm *)device->parent.user_data; + switch (cmd) + { + case PWM_CMD_ENABLE: + // 互补使能 + if (configuration->complementary) + { + drv_pwmn_enable(pwm, configuration->channel, RT_TRUE); + } + return drv_pwm_enable(pwm, configuration->channel, RT_TRUE); + + case PWM_CMD_DISABLE: + if (configuration->complementary) + { + drv_pwmn_enable(pwm, configuration->channel, RT_FALSE); + } + return drv_pwm_enable(pwm, configuration->channel, RT_FALSE); + case PWM_CMD_SET: + + return drv_pwm_set(pwm, configuration); + case PWM_CMD_SET_PERIOD: + return drv_pwm_set_period(pwm, configuration); + case PWM_CMD_SET_PULSE: + return drv_pwm_set_pulse(pwm, configuration); + case PWM_CMD_GET: + return drv_pwm_get(pwm, configuration); + default: + return -RT_EINVAL; + } +} + +/** + * @brief 配置pwm输出对应的gpio引脚 + */ +static void pwm_time_gpio_config(struct n32_pwm_channel *chanel) + +{ + PWM_LOG_D("%s %d config %s is ok", __FUNCTION__, __LINE__, chanel->info); + GPIO_InitType GPIO_InitStructure; + +#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) + + gpio_remap_JTAGOFF_SWDON(chanel->gpio_grp, chanel->pin); + + GPIO_InitStruct(&GPIO_InitStructure); + /* pwm mode gpio cofig*/ + GPIO_InitStructure.Pin = chanel->pin; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitPeripheral(chanel->gpio_grp, &GPIO_InitStructure); + +#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE); + GPIO_InitStruct(&GPIO_InitStructure); + GPIO_InitStructure.Pin = chanel->pin; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Current = GPIO_DC_4mA; + GPIO_InitStructure.GPIO_Alternate = chanel->gpio_af; + GPIO_InitPeripheral(chanel->gpio_grp, &GPIO_InitStructure); + + // GPIO_ConfigPinRemap(GPIOA_PORT_SOURCE, GPIO_PIN_SOURCE0, GPIO_AF2_TIM2); + // GPIO_ConfigPinRemap(GPIOA_PORT_SOURCE, GPIO_PIN_SOURCE1, GPIO_AF2_TIM2); + +#endif +} + +static void pwm_oc_init(const rt_uint16_t chanel, const rt_uint16_t mode, TIM_Module *tim) +{ + OCInitType TIM_OCInitStructure; + /*输出通道配置*/ + TIM_OCInitStructure.OcMode = mode; // pwm的工作模式 + TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE; + TIM_OCInitStructure.Pulse = 500; + TIM_OCInitStructure.OcPolarity = TIM_OC_POLARITY_HIGH; + + switch (chanel) + { + + case 0: + TIM_InitOc1(tim, &TIM_OCInitStructure); + TIM_ConfigOc1Preload(tim, TIM_OC_PRE_LOAD_ENABLE); + break; + case 1: + TIM_InitOc2(tim, &TIM_OCInitStructure); + TIM_ConfigOc2Preload(tim, TIM_OC_PRE_LOAD_ENABLE); + break; + case 2: + TIM_InitOc3(tim, &TIM_OCInitStructure); + TIM_ConfigOc3Preload(tim, TIM_OC_PRE_LOAD_ENABLE); + break; + case 3: + TIM_InitOc4(tim, &TIM_OCInitStructure); + TIM_ConfigOc4Preload(tim, TIM_OC_PRE_LOAD_ENABLE); + break; + default: + + break; + } +} + +static rt_err_t n32_hw_pwm_init(struct n32_pwm *device) +{ + rt_err_t result = RT_EOK; + TIM_TimeBaseInitType TIM_TimeBaseStructure; + + RT_ASSERT(device != RT_NULL); + // 使能时钟 + n32_time_rcc_config(device->tim); + + // 配置定时器 + TIM_TimeBaseStructure.Period = 1000; // + TIM_TimeBaseStructure.Prescaler = device->prescaler; + TIM_TimeBaseStructure.ClkDiv = 0; + TIM_TimeBaseStructure.CntMode = TIM_CNT_MODE_UP; + TIM_InitTimeBase(device->tim, &TIM_TimeBaseStructure); +#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) + + // 时钟使能 + if (device->gpio_af) + { + // 引脚重映射 + GPIO_ConfigPinRemap(device->gpio_af, ENABLE); + } +#endif + + /*输出通道配置*/ + for (int i = 0; i < 4; i++) + { + if (device->ch[i].gpio_grp) + { + /**gpio rcc */ + n32_gpio_rcc_enable(device->ch[i].gpio_grp); + // 配置gpio复用功能 + pwm_time_gpio_config(device->ch + i); + // pwm输出设置 + pwm_oc_init(i, device->ch[i].pwm_mode, device->tim); + // 关闭输出 + drv_pwm_enable(device, i, RT_FALSE); + } + } + + // 使能定时器 + TIM_ConfigArPreload(device->tim, ENABLE); + TIM_Enable(device->tim, ENABLE); + // 使能PWM输出通道 + if (device->tim == TIM1 || device->tim == TIM8) + { + TIM_EnableCtrlPwmOutputs(device->tim, ENABLE); + } + + return result; +} + +static struct rt_pwm_ops drv_ops = + { + .control = drv_pwm_control, +}; + +static int n32_pwm_init(void) +{ + int i = 0; + int result = RT_EOK; + // 加载通道配置 + // n32_load_channel_cfg(); + + for (i = 0; i < sizeof(n32_pwm_obj) / sizeof(n32_pwm_obj[0]); i++) + { + /* pwm init */ + if (n32_hw_pwm_init(&n32_pwm_obj[i]) != RT_EOK) + { + PWM_LOG_E("%s init failed", n32_pwm_obj[i].name); + result = -RT_ERROR; + goto __exit; + } + else + { + + /* register pwm device */ + if (rt_device_pwm_register(&n32_pwm_obj[i].pwm_device, n32_pwm_obj[i].name, &drv_ops, n32_pwm_obj + i) == RT_EOK) + { + // PWM_LOG_D("%s register success", n32_pwm_obj[i].name); + } + else + { + PWM_LOG_E("%s register failed", n32_pwm_obj[i].name); + result = -RT_ERROR; + } + } + } + +__exit: + return result; +} +INIT_DEVICE_EXPORT(n32_pwm_init); + +#if 0 // pem demo +#include +#include + +#define PWM_DEV_NAME "pwm1" /* PWM设备名称 */ +#define PWM_DEV_CHANNEL 0 /* PWM通道 */ + +struct rt_device_pwm *pwm; /* PWM设备句柄 */ + +static int pwm_led_sample(void) +{ + rt_uint32_t period, pulse; + + period = 1000000; /* 周期为0.5ms，单位为纳秒ns */ + pulse = period >> 1; /* PWM脉冲宽度值，单位为纳秒ns */ +// pulse=0.1f*period; + /* 查找设备 */ + pwm = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME); + if (pwm == RT_NULL) + { + LOG_D("pwm sample run ERROR! can't find %s device!\n", PWM_DEV_NAME); + return RT_ERROR; + } + + /* 设置PWM周期和脉冲宽度默认值 */ + // rt_pwm_set(pwm, 0, period, pulse); + // /* 使能设备 */ + // rt_pwm_enable(pwm, 0); + + // /* 设置PWM周期和脉冲宽度默认值 */ + // rt_pwm_set(pwm, 1, period, pulse); + // /* 使能设备 */ + // rt_pwm_enable(pwm, 1); + + // /* 设置PWM周期和脉冲宽度默认值 */ + // rt_pwm_set(pwm, 2, period, pulse); + // /* 使能设备 */ + // rt_pwm_enable(pwm, 2); + + /* 设置PWM周期和脉冲宽度默认值 */ + rt_pwm_set(pwm, 3, period, pulse); + /* 使能设备 */ + rt_pwm_enable(pwm, 3); + return 0; +} +/* 导出到 msh 命令列表中 */ +// MSH_CMD_EXPORT(pwm_led_sample, pwm sample); + +INIT_APP_EXPORT(pwm_led_sample); +#endif + +#endif /* BSP_USING_PWM */ diff --git a/bsp/n32/libraries/n32_drivers/drv_pwm.h b/bsp/n32/libraries/n32_drivers/drv_pwm.h new file mode 100644 index 00000000000..41b9fecc6b3 --- /dev/null +++ b/bsp/n32/libraries/n32_drivers/drv_pwm.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-19 Nations first version + */ + +#ifndef __DRV_PWM_H__ +#define __DRV_PWM_H__ + +#include +#include +#include "board.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_PWM_H__ */ diff --git a/bsp/n32/libraries/n32_drivers/drv_spi.c b/bsp/n32/libraries/n32_drivers/drv_spi.c index 5728b0d06c4..20d5ffe3728 100644 --- a/bsp/n32/libraries/n32_drivers/drv_spi.c +++ b/bsp/n32/libraries/n32_drivers/drv_spi.c @@ -6,37 +6,46 @@ * Change Logs: * Date Author Notes * 2022-10-19 Nations first version + * + * 202512-03 + * 1.spi 的驱动优化，在G457上spi2可行 + * 2.新增了Kconfig的配置文件，测试spi2的remap=3测试OK + * 2025-12-04 + * 1.增加了spi1和spi2的Kconfig配置选项，未测试 + * + * 2025-12-18 + * 1.添加了注释 信息 + * 2.目前代码支持N32G45x和N32L40x系列的 + * 3.在PGM-11项目测试了N32L40x的spi1，表示可行 */ +#include -#include "drv_spi.h" +#define DBG_TAG "SPI" +#define DBG_LVL LOG_LVL_INFO +#include +#include "drv_base.h" +#include "drv_spi.h" #if defined(RT_USING_SPI) && defined(RT_USING_PIN) #include #if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || \ defined(BSP_USING_SPI3) -/* #define DEBUG */ -#ifdef DEBUG -#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__) -#else -#define DEBUG_PRINTF(...) -#endif - /* private rt-thread spi ops function */ -static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration) +static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration) { SPI_InitType SPI_InitStructure; RCC_ClocksType RCC_ClockFreq; - SPI_Module* spi_periph; + SPI_Module *spi_periph; RT_ASSERT(device != RT_NULL); RT_ASSERT(configuration != RT_NULL); RCC_GetClocksFreqValue(&RCC_ClockFreq); - spi_periph = (SPI_Module*)device->bus->parent.user_data; + spi_periph = (SPI_Module *)device->bus->parent.user_data; #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) if (spi_periph != SPI1 && spi_periph != SPI2 && spi_periph != SPI3) @@ -69,9 +78,9 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat max_hz = configuration->max_hz; - DEBUG_PRINTF("sys freq: %d\n", RCC_ClockFreq.SysclkFreq); - DEBUG_PRINTF("CK_APB2 freq: %d\n", RCC_ClockFreq.Pclk2Freq); - DEBUG_PRINTF("max freq: %d\n", max_hz); + LOG_D("sys freq: %d\n", RCC_ClockFreq.SysclkFreq); + LOG_D("CK_APB2 freq: %d\n", RCC_ClockFreq.Pclk2Freq); + LOG_D("max freq: %d\n", max_hz); if (spi_periph == SPI1) { @@ -82,31 +91,31 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat spi_apb_clock = RCC_ClockFreq.Pclk1Freq; } - if (max_hz >= spi_apb_clock/2) + if (max_hz >= spi_apb_clock / 2) { SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_2; } - else if (max_hz >= spi_apb_clock/4) + else if (max_hz >= spi_apb_clock / 4) { SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_4; } - else if (max_hz >= spi_apb_clock/8) + else if (max_hz >= spi_apb_clock / 8) { SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_8; } - else if (max_hz >= spi_apb_clock/16) + else if (max_hz >= spi_apb_clock / 16) { SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_16; } - else if (max_hz >= spi_apb_clock/32) + else if (max_hz >= spi_apb_clock / 32) { SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_32; } - else if (max_hz >= spi_apb_clock/64) + else if (max_hz >= spi_apb_clock / 64) { SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_64; } - else if (max_hz >= spi_apb_clock/128) + else if (max_hz >= spi_apb_clock / 128) { SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_128; } @@ -119,22 +128,22 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat switch (configuration->mode & RT_SPI_MODE_3) { - case RT_SPI_MODE_0: - SPI_InitStructure.CLKPOL = SPI_CLKPOL_LOW; - SPI_InitStructure.CLKPHA = SPI_CLKPHA_FIRST_EDGE; - break; - case RT_SPI_MODE_1: - SPI_InitStructure.CLKPOL = SPI_CLKPOL_LOW; - SPI_InitStructure.CLKPHA = SPI_CLKPHA_SECOND_EDGE; - break; - case RT_SPI_MODE_2: - SPI_InitStructure.CLKPOL = SPI_CLKPOL_HIGH; - SPI_InitStructure.CLKPHA = SPI_CLKPHA_FIRST_EDGE; - break; - case RT_SPI_MODE_3: - SPI_InitStructure.CLKPOL = SPI_CLKPOL_HIGH; - SPI_InitStructure.CLKPHA = SPI_CLKPHA_SECOND_EDGE; - break; + case RT_SPI_MODE_0: + SPI_InitStructure.CLKPOL = SPI_CLKPOL_LOW; + SPI_InitStructure.CLKPHA = SPI_CLKPHA_FIRST_EDGE; + break; + case RT_SPI_MODE_1: + SPI_InitStructure.CLKPOL = SPI_CLKPOL_LOW; + SPI_InitStructure.CLKPHA = SPI_CLKPHA_SECOND_EDGE; + break; + case RT_SPI_MODE_2: + SPI_InitStructure.CLKPOL = SPI_CLKPOL_HIGH; + SPI_InitStructure.CLKPHA = SPI_CLKPHA_FIRST_EDGE; + break; + case RT_SPI_MODE_3: + SPI_InitStructure.CLKPOL = SPI_CLKPOL_HIGH; + SPI_InitStructure.CLKPHA = SPI_CLKPHA_SECOND_EDGE; + break; } /* MSB or LSB */ @@ -148,9 +157,9 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat } /* SPI configuration */ SPI_InitStructure.DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX; - SPI_InitStructure.SpiMode = SPI_MODE_MASTER; - SPI_InitStructure.NSS = SPI_NSS_SOFT; - SPI_InitStructure.CRCPoly = 7; + SPI_InitStructure.SpiMode = SPI_MODE_MASTER; + SPI_InitStructure.NSS = SPI_NSS_SOFT; + SPI_InitStructure.CRCPoly = 7; SPI_Init(spi_periph, &SPI_InitStructure); @@ -160,11 +169,11 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat return RT_EOK; } -static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message) +static rt_ssize_t xfer(struct rt_spi_device *device, struct rt_spi_message *message) { struct n32_spi_cs *cs_pin = device->parent.user_data; - SPI_Module* spi_periph = (SPI_Module*)device->bus->parent.user_data; - struct rt_spi_configuration * config = &device->config; + SPI_Module *spi_periph = (SPI_Module *)device->bus->parent.user_data; + struct rt_spi_configuration *config = &device->config; RT_ASSERT(device != NULL); RT_ASSERT(message != NULL); @@ -173,194 +182,398 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes if (message->cs_take) { rt_pin_write(cs_pin->GPIO_Pin, PIN_LOW); - DEBUG_PRINTF("spi take cs\n"); + LOG_D("spi take cs %d \n", cs_pin->GPIO_Pin); } - if (config->data_width <= 8) - { - const rt_uint8_t * send_ptr = message->send_buf; - rt_uint8_t * recv_ptr = message->recv_buf; - rt_uint32_t size = message->length; + if (config->data_width <= 8) + { + const rt_uint8_t *send_ptr = message->send_buf; + rt_uint8_t *recv_ptr = message->recv_buf; + rt_uint32_t size = message->length; - DEBUG_PRINTF("spi poll transfer start: %d\n", size); + LOG_D("spi poll transfer start: %d\n", size); - while (size--) - { - rt_uint8_t data = 0xA5; + while (size--) + { + rt_uint8_t data = 0xA5; - if (send_ptr != RT_NULL) - { - data = *send_ptr++; - } + if (send_ptr != RT_NULL) + { + data = *send_ptr++; + } - /* Loop while DAT register in not emplty */ - while (SPI_I2S_GetStatus(spi_periph, SPI_I2S_TE_FLAG) == RESET); + /* Loop while DAT register in not emplty */ + while (SPI_I2S_GetStatus(spi_periph, SPI_I2S_TE_FLAG) == RESET) + ; - /* Send the byte */ - SPI_I2S_TransmitData(spi_periph, data); + /* Send the byte */ + SPI_I2S_TransmitData(spi_periph, data); - /* Wait until a data is received */ - while (SPI_I2S_GetStatus(spi_periph, SPI_I2S_RNE_FLAG) == RESET); + /* Wait until a data is received */ + while (SPI_I2S_GetStatus(spi_periph, SPI_I2S_RNE_FLAG) == RESET) + ; - /* Get the received data */ - data = SPI_I2S_ReceiveData(spi_periph); + /* Get the received data */ + data = SPI_I2S_ReceiveData(spi_periph); - if (recv_ptr != RT_NULL) - { - *recv_ptr++ = data; - } + if (recv_ptr != RT_NULL) + { + *recv_ptr++ = data; } - DEBUG_PRINTF("spi poll transfer finsh\n"); } - else if (config->data_width <= 16) + LOG_D("spi poll transfer finsh\n"); + } + else if (config->data_width <= 16) + { + const rt_uint16_t *send_ptr = message->send_buf; + rt_uint16_t *recv_ptr = message->recv_buf; + rt_uint32_t size = message->length; + + while (size--) { - const rt_uint16_t * send_ptr = message->send_buf; - rt_uint16_t * recv_ptr = message->recv_buf; - rt_uint32_t size = message->length; + rt_uint16_t data = 0xFF; - while (size--) + if (send_ptr != RT_NULL) { - rt_uint16_t data = 0xFF; - - if (send_ptr != RT_NULL) - { - data = *send_ptr++; - } + data = *send_ptr++; + } - /* Loop while DAT register in not emplty */ - while (SPI_I2S_GetStatus(spi_periph, SPI_I2S_TE_FLAG) == RESET); + /* Loop while DAT register in not emplty */ + while (SPI_I2S_GetStatus(spi_periph, SPI_I2S_TE_FLAG) == RESET) + ; - /* Send the byte */ - SPI_I2S_TransmitData(spi_periph, data); + /* Send the byte */ + SPI_I2S_TransmitData(spi_periph, data); - /* Wait until a data is received */ - while (RESET == SPI_I2S_GetStatus(spi_periph, SPI_I2S_RNE_FLAG)); + /* Wait until a data is received */ + while (RESET == SPI_I2S_GetStatus(spi_periph, SPI_I2S_RNE_FLAG)) + ; - /* Get the received data */ - data = SPI_I2S_ReceiveData(spi_periph); + /* Get the received data */ + data = SPI_I2S_ReceiveData(spi_periph); - if (recv_ptr != RT_NULL) - { - *recv_ptr++ = data; - } + if (recv_ptr != RT_NULL) + { + *recv_ptr++ = data; } } + } /* release CS */ if (message->cs_release) { rt_pin_write(cs_pin->GPIO_Pin, PIN_HIGH); - DEBUG_PRINTF("spi release cs\n"); + LOG_D("spi release cs\n"); } return message->length; } static struct rt_spi_ops spi_ops = -{ - configure, - xfer + { + configure, + xfer, }; -int rt_hw_spi_init(void) +static void n32_spi_rcc_enable(const SPI_Module *spi) { - int result = 0; - GPIO_InitType GPIO_InitStructure; - -#ifdef BSP_USING_SPI1 - static struct rt_spi_bus spi_bus1; - spi_bus1.parent.user_data = (void *)SPI1; - - result = rt_spi_bus_register(&spi_bus1, "spi1", &spi_ops); + if (SPI1 == spi) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_SPI1, ENABLE); + } +#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) + else if (SPI2 == spi) + { + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_SPI2, ENABLE); + } + else if (SPI3 == spi) + { + RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_SPI3, ENABLE); + } +#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) + else if (SPI2 == spi) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_SPI2, ENABLE); + } +#endif +} #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) - RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA | RCC_APB2_PERIPH_SPI1, ENABLE); +typedef struct +{ + struct rt_spi_bus spi_bus; + SPI_Module *spi; + uint32_t spi_remap; + uint16_t pin_sclk; + uint16_t pin_mosi; + uint16_t pin_miso; + GPIO_Module *gpio_grp; + char *name; + char *info; +} n32_spi_hd_t; +#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) +typedef struct +{ + struct rt_spi_bus spi_bus; + SPI_Module *spi; + uint16_t pin_sclk; + uint16_t pin_mosi; + uint16_t pin_miso; + uint8_t pin_sclk_remap; + uint8_t pin_mosi_remap; + uint8_t pin_miso_remap; + GPIO_Module *gpio_grp; + char *name; + char *info; +} n32_spi_hd_t; +#endif +void n32_spi_gpio_init(const n32_spi_hd_t *spi_hd) +{ + GPIO_InitType GPIO_InitStructure; GPIO_InitStruct(&GPIO_InitStructure); + n32_gpio_rcc_enable(spi_hd->gpio_grp); - /* Confige SPI1_SCLK(PA5) and SPI1_MOSI(PA7) */ - GPIO_InitStructure.Pin = GPIO_PIN_5 | GPIO_PIN_7; +#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) + if (spi_hd->spi_remap) + { + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE); + GPIO_ConfigPinRemap(spi_hd->spi_remap, ENABLE); + } + /* Confige SPI1_SCLK and SPI1_MOSI */ + GPIO_InitStructure.Pin = spi_hd->pin_sclk | spi_hd->pin_mosi; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitPeripheral(spi_hd->gpio_grp, &GPIO_InitStructure); - /* Confige SPI1_MISO(PA6) */ - GPIO_InitStructure.Pin = GPIO_PIN_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure); + /* Confige SPI1_MISO */ + GPIO_InitStructure.Pin = spi_hd->pin_miso; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_InitPeripheral(spi_hd->gpio_grp, &GPIO_InitStructure); #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) - RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); - RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_SPI1 | RCC_APB2_PERIPH_AFIO, ENABLE); + // afio rcc + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE); GPIO_InitStruct(&GPIO_InitStructure); - /* Confige SPI1_SCLK(PA5) and SPI1_MISO(PA6) and SPI1_MOSI(PA7) */ - GPIO_InitStructure.Pin = GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStructure.GPIO_Alternate = GPIO_AF0_SPI1; - GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure); -#endif + /* Confige SPI1_SCLK */ + GPIO_InitStructure.Pin = spi_hd->pin_sclk; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Alternate = spi_hd->pin_sclk_remap; + GPIO_InitPeripheral(spi_hd->gpio_grp, &GPIO_InitStructure); + /*SPI1_MISO()*/ + GPIO_InitStructure.Pin = spi_hd->pin_mosi; + GPIO_InitStructure.GPIO_Alternate = spi_hd->pin_mosi_remap; + GPIO_InitPeripheral(spi_hd->gpio_grp, &GPIO_InitStructure); + /*SPI1_MISO()*/ + GPIO_InitStructure.Pin = spi_hd->pin_miso; + GPIO_InitStructure.GPIO_Alternate = spi_hd->pin_miso_remap; + GPIO_InitPeripheral(spi_hd->gpio_grp, &GPIO_InitStructure); #endif +} -#ifdef BSP_USING_SPI2 - static struct rt_spi_bus spi_bus2; - spi_bus2.parent.user_data = (void *)SPI2; - - result = rt_spi_bus_register(&spi_bus2, "spi2", &spi_ops); - +static void n32_spi_init(n32_spi_hd_t *spi_hd) +{ + n32_spi_rcc_enable(spi_hd->spi);//时钟初始化 + n32_spi_gpio_init(spi_hd);//gpio初始化 + spi_hd->spi_bus.parent.user_data = spi_hd->spi; + //注册spi总线设备 + if (RT_EOK == rt_spi_bus_register(&spi_hd->spi_bus, spi_hd->name, &spi_ops)) + { + LOG_D("register %s is ok,pin={%s}", spi_hd->name, spi_hd->info); + } + else + { + LOG_W("register %s is error,pin={%s}", spi_hd->name, spi_hd->info); + } +} +static n32_spi_hd_t n32_spi_hd[] = { #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) - RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE); - RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_SPI2, ENABLE); - - GPIO_InitStruct(&GPIO_InitStructure); +#define SOC_SOC_N32G45X_SPI_CFG_START +#ifdef BSP_USING_SPI1 + { - /* Confige SPI2_SCLK(PB13) and SPI2_MOSI(PB15) */ - GPIO_InitStructure.Pin = GPIO_PIN_13 | GPIO_PIN_15; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure); + .spi = SPI1, + .name = "spi1", +#ifdef BSP_SPI1_REMAP_0 + .spi_remap = 0, + .pin_sclk = GPIO_PIN_5, + .pin_miso = GPIO_PIN_6, + .pin_mosi = GPIO_PIN_7, + .gpio_grp = GPIOA, + .info = " PA5 PA6 PA7", +#endif /*BSP_SPI_REMAP_0*/ +#ifdef BSP_SPI1_REMAP_1 + .spi_remap = GPIO_RMP1_SPI1, + .pin_sclk = GPIO_PIN_3, + .pin_miso = GPIO_PIN_4, + .pin_mosi = GPIO_PIN_5, + .gpio_grp = GPIOB, + .info = " PB3 PB4 PB5 (JATG)", +#endif /*BSP_SPI_REMAP_1*/ +#ifdef BSP_SPI1_REMAP_3 + .spi_remap = GPIO_RMP3_SPI1, + .pin_sclk = GPIO_PIN_7, + .pin_miso = GPIO_PIN_8, + .pin_mosi = GPIO_PIN_9, + .gpio_grp = GPIOE, + .info = " PE7 PE8 PE9", +#endif /*BSP_SPI_REMAP_3*/ + }, +#endif /*BSP_USING_SPI1*/ - /* Confige SPI2_MISO(PB14) */ - GPIO_InitStructure.Pin = GPIO_PIN_14; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure); -#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) - RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE); - RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_SPI2 | RCC_APB2_PERIPH_AFIO, ENABLE); +#ifdef BSP_USING_SPI2 + { - GPIO_InitStruct(&GPIO_InitStructure); - /* Confige SPI2_SCLK(PB13) and SPI2_MISO(PB14) and SPI2_MOSI(PB15) */ - GPIO_InitStructure.Pin = GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStructure.GPIO_Alternate = GPIO_AF0_SPI2; - GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure); -#endif -#endif + .spi = SPI2, + .name = "spi2", +#ifdef BSP_SPI2_REMAP_0 + .spi_remap = 0, + .pin_sclk = GPIO_PIN_13, + .pin_miso = GPIO_PIN_14, + .pin_mosi = GPIO_PIN_15, + .gpio_grp = GPIOB, + .info = " PB13,PB14,PB15", +#endif /*BSP_SPI_REMAP_0*/ +#ifdef BSP_SPI2_REMAP_1 + .spi_remap = GPIO_RMP1_SPI2, + .pin_sclk = GPIO_PIN_7, + .pin_miso = GPIO_PIN_8, + .pin_mosi = GPIO_PIN_9, + .gpio_grp = GPIOC, + .info = " PC7 PC8 PC9", +#endif /*BSP_SPI_REMAP_1*/ +#ifdef BSP_SPI2_REMAP_3 + .spi_remap = GPIO_RMP2_SPI2, + .pin_sclk = GPIO_PIN_11, + .pin_miso = GPIO_PIN_12, + .pin_mosi = GPIO_PIN_13, + .gpio_grp = GPIOE, + .info = " PE11 PE12 PE13", +#endif /*BSP_SPI_REMAP_3*/ + }, +#endif /*BSP_USING_SPI2*/ #ifdef BSP_USING_SPI3 - static struct rt_spi_bus spi_bus3; - spi_bus3.parent.user_data = (void *)SPI3; + { - result = rt_spi_bus_register(&spi_bus3, "spi3", &spi_ops); + .spi = SPI3, + .name = "spi3", +#ifdef BSP_SPI3_REMAP_0 + .spi_remap = 0, + .pin_sclk = GPIO_PIN_3, + .pin_miso = GPIO_PIN_4, + .pin_mosi = GPIO_PIN_5, + .gpio_grp = GPIOB, + .info = "spi3 PB3 PB4 PB5", +#endif /*BSP_SPI3_REMAP_0*/ +#ifdef BSP_SPI3_REMAP_1 + .spi_remap = GPIO_RMP1_SPI3, + .pin_sclk = GPIO_PIN_10, + .pin_miso = GPIO_PIN_11, + .pin_mosi = GPIO_PIN_12, + .gpio_grp = GPIOC, + .info = "spi3 PC10 PC11 PC12", +#endif /*BSP_SPI3_REMAP_1*/ +#ifdef BSP_SPI3_REMAP2 + .spi_remap = GPIO_RMP2_SPI3, + .pin_sclk = GPIO_PIN_9, + .pin_miso = GPIO_PIN_10, + .pin_mosi = GPIO_PIN_11, + .gpio_grp = GPIOD, + .info = "spi2 PD9 PD11 PD12", +#endif /*BSP_SPI3_REMAP_3*/ + }, +#endif /*BSP_USING_SPI*/ +#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) +#define SOC_N32L43X_SPI_CFG_START //配置开始标记，无实际意义 +#ifdef BSP_USING_SPI1 + { - RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB | RCC_APB2_PERIPH_AFIO, ENABLE); - RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_SPI3, ENABLE); + .spi = SPI1, + .name = "spi1", +#ifdef BSP_SPI1_REMAP_0 + .pin_sclk = GPIO_PIN_5, + .pin_sclk_remap = GPIO_AF0_SPI1, + .pin_miso = GPIO_PIN_6, + .pin_miso_remap = GPIO_AF0_SPI1, + .pin_mosi = GPIO_PIN_7, + .pin_mosi_remap = GPIO_AF0_SPI1, + .gpio_grp = GPIOA, + .info = " PA5 PA6 PA7", +#endif /*BSP_SPI_REMAP_0*/ +#ifdef BSP_SPI1_REMAP_1 + .pin_sclk = GPIO_PIN_3, + .pin_sclk_remap = GPIO_AF1_SPI1, + .pin_miso = GPIO_PIN_4, + .pin_miso_remap = GPIO_AF1_SPI1, + .pin_mosi = GPIO_PIN_5, + .pin_mosi_remap = GPIO_AF0_SPI1, + .gpio_grp = GPIOB, + .info = " PB3 PB4 PB5", +#endif /*BSP_SPI_REMAP_1*/ +#ifdef BSP_SPI1_REMAP_2 + .pin_sclk = GPIO_PIN_4, + .pin_sclk_remap = GPIO_AF5_SPI1, + .pin_miso = GPIO_PIN_5, + .pin_miso_remap = GPIO_AF5_SPI1, + .pin_mosi = GPIO_PIN_6, + .pin_mosi_remap = GPIO_AF5_SPI1, + .gpio_grp = GPIOD, + .info = "PD4 PD5 PD6", +#endif /*BSP_SPI_REMAP_2*/ + }, +#endif /*BSP_USING_SPI1*/ - GPIO_ConfigPinRemap(GPIO_RMP_SW_JTAG_SW_ENABLE, ENABLE); +#ifdef BSP_USING_SPI2 + { - GPIO_InitStruct(&GPIO_InitStructure); + .spi = SPI2, + .name = "spi2", +#ifdef BSP_SPI2_REMAP_0 + .pin_sclk = GPIO_PIN_13, + .pin_sclk_remap = GPIO_AF0_SPI2, + .pin_miso = GPIO_PIN_14, + .pin_miso_remap = GPIO_AF0_SPI2, + .pin_mosi = GPIO_PIN_15, + .pin_mosi_remap = GPIO_AF0_SPI2, + .gpio_grp = GPIOB, + .info = " PB13 PB14 PB15", +#endif /*BSP_SPI_REMAP_0*/ +#ifdef BSP_SPI2_REMAP_1 + .pin_sclk = GPIO_PIN_7, + .pin_sclk_remap = GPIO_AF5_SPI2, + .pin_miso = GPIO_PIN_8, + .pin_miso_remap = GPIO_AF5_SPI2, + .pin_mosi = GPIO_PIN_9, + .pin_mosi_remap = GPIO_AF5_SPI2, + .gpio_grp = GPIOC, + .info = "PC7 PC8 PC9", +#endif /*BSP_SPI_REMAP_1*/ +#ifdef BSP_SPI2_REMAP_2 + .pin_sclk = GPIO_PIN_10, + .pin_sclk_remap = GPIO_AF5_SPI2, + .pin_miso = GPIO_PIN_11, + .pin_miso_remap = GPIO_AF0_SPI2, + .pin_mosi = GPIO_PIN_12, + .pin_mosi_remap = GPIO_AF0_SPI2, + .gpio_grp = GPIOA, + .info = "PA10 PA11 PA12", +#endif /*BSP_SPI_REMAP_2*/ + }, +#endif /*BSP_USING_SPI2*/ + +#endif /*defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)*/ +}; + +int rt_hw_spi_init(void) +{ + for (int i = 0; i < sizeof(n32_spi_hd) / sizeof(n32_spi_hd_t); i++) + { + n32_spi_init(n32_spi_hd + i); + } + return RT_EOK; - /* Confige SPI3_SCLK(PB3) and SPI3_MOSI(PB5) */ - GPIO_InitStructure.Pin = GPIO_PIN_3 | GPIO_PIN_5; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure); - /* Confige SPI3_MISO(PB4) */ - GPIO_InitStructure.Pin = GPIO_PIN_4; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure); -#endif - return result; } INIT_BOARD_EXPORT(rt_hw_spi_init); diff --git a/bsp/n32/libraries/n32_drivers/drv_tim_external_counter.c b/bsp/n32/libraries/n32_drivers/drv_tim_external_counter.c new file mode 100644 index 00000000000..bac8605205b --- /dev/null +++ b/bsp/n32/libraries/n32_drivers/drv_tim_external_counter.c @@ -0,0 +1,1102 @@ +/** + * @file drv_tim_external_counter.c + * @brief + * @author jiache (wanghuan3037@fiberhome.com) + * @version 1.0 + * @date 2025-11-28 + * 2025-11-28 + * 1.驱动的优化，并测试额所有的定时器均可实现外部时钟1方式计数 + name=eclktm1 ===》 TIM1 PA8 + name=eclktm2 ===》 TIM2 PA15 + name=eclktm3 ===》 TIM3 PA6 + name=eclktm4 ===》 TIM4 PB6 + name=eclktm5 ===》 TIM5 PA0 + name=eclktm8 ===》 TIM8 PC6 + 2.RT_USING_DEVICE_OPS操作方式的实现 + 3.日志标签的加入 +*2025-12-1 + 1.测试了每个定时器的通道1，通道的默认复用引脚，外部时钟1计数均OK + 2.外部计数的引脚复用全部采用Kconfig方式配置 + * 202512-2 + * 1.将定时器的时钟和gpio时钟统一放在drv_base.c中 + +2025-12-08 + 1.移植兼容N32L40X的兼容代码，修改了Kconfig添加了配置 + 2.测试了TIM1的PA8,测量1MHz的脉冲没有问题；测量10M也是OK的，示波器显示10.7MHz，实测10666668 + * 2025-12-12 + 1.添加了N32L406的TIM2,TIM3的外部计数配置添加 + *- + * @copyright Copyright (c) 2025 58 + * + */ +#include +#ifdef BSP_USING_TIM_EXT_COUNTER +#include "board.h" +#include + +#define DBG_TAG "TIM_CH_CNT" +#ifdef BSP_USING_TIM_ETR_CNT_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif +#include +#include "drv_base.h" +enum +{ +#ifdef BSP_USING_TIM1_EXT_COUNTER + EXT_CLK_TIM1, +#endif +#ifdef BSP_USING_TIM2_EXT_COUNTER + EXT_CLK_TIM2, +#endif +#ifdef BSP_USING_TIM3_EXT_COUNTER + EXT_CLK_TIM3, +#endif +#ifdef BSP_USING_TIM4_EXT_COUNTER + EXT_CLK_TIM4, +#endif +#ifdef BSP_USING_TIM5_EXT_COUNTER + EXT_CLK_TIM5, +#endif +#ifdef BSP_USING_TIM8_EXT_COUNTER + EXT_CLK_TIM8, +#endif + EXT_CLK_NUM +}; +struct n32_tim_ext_counter_config +{ + TIM_Module *timer_periph; /* 定时器外设 */ + GPIO_Module *gpio_periph; /* GPIO外设 */ + uint16_t gpio_pin; /* GPIO引脚 */ + uint32_t gpio_af; /* GPIO复用功能 */ + uint16_t tim_channel; /* 定时器通道 */ + uint16_t polarity; /* 极性配置 */ + uint16_t filter; /* 滤波配置 */ + IRQn_Type irqn; /* 中断号 */ + const char *info; /* 设备信息 */ +}; + +/* 外部计数器设备结构体 */ +struct n32_tim_ext_counter_device +{ + struct rt_device parent; + struct n32_tim_ext_counter_config *config; + rt_uint32_t count_value; + rt_uint32_t overflow_count; + void (*overflow_callback)(rt_device_t dev); /* 修正回调函数签名 */ + void *callback_args; +}; + +static rt_err_t n32_tim_ext_counter_register(struct n32_tim_ext_counter_device *device, + const char *name, + struct n32_tim_ext_counter_config *config); +/* TIM1外部计数器初始化 */ + +static struct n32_tim_ext_counter_config tim1_ext_counter_config[EXT_CLK_NUM] = + { +#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) +#define N32_EXT_CLK_CNT_G457 +#ifdef BSP_USING_TIM1_EXT_COUNTER /*CH1=PA8(0,1,2),PE9(3) ; CH2=PA9(0,1,2),PE11(3)*/ + + { + .timer_periph = TIM1, + .polarity = TIM_IC_POLARITY_RISING, + .filter = 0x0, + .irqn = TIM1_UP_IRQn, + +#ifdef TIM1_CH1_PA8 + .tim_channel = TIM_CH_1, + .gpio_periph = GPIOA, + .gpio_pin = GPIO_PIN_8, + .gpio_af = 0, + .info = "TIM1 PA8", +#endif /*TIM1_CH1_PA8*/ + +#ifdef TIM1_CH1_PE9 + .tim_channel = TIM_CH_1, + .gpio_periph = GPIOE, + .gpio_pin = GPIO_PIN_9, + .gpio_af = GPIO_ALL_RMP_TIM1, + .info = "TIM1 PE9", +#endif /*TIM1_CH1_PE9*/ + +#ifdef TIM1_CH2_PA9 + .tim_channel = TIM_CH_2, + .gpio_periph = GPIOA, + .gpio_pin = GPIO_PIN_9, + .gpio_af = 0, + .info = "TIM1 PA9", +#endif /*TIM1_CH2_PA9*/ + +#ifdef TIM1_CH2_PE11 + .tim_channel = TIM_CH_2, + .gpio_periph = GPIOE, + .gpio_pin = GPIO_PIN_11, + .gpio_af = GPIO_ALL_RMP_TIM1, + .info = "TIM1 PE11", +#endif /*TIM1_CH1_PA8*/ + }, +#endif /*BSP_USING_TIM1_EXT_COUNTER*/ + +#ifdef BSP_USING_TIM2_EXT_COUNTER /******CH1=PA0(0,2),PA15(1,3) ; CH2=PA1(0,2),PB3(1,3)******************************* */ + + { + .timer_periph = TIM2, + .polarity = TIM_IC_POLARITY_RISING, + .filter = 0x0, + .irqn = TIM2_IRQn, +#ifdef TIM2_CH1_PA0 + .tim_channel = TIM_CH_1, + .gpio_periph = GPIOA, + .gpio_pin = GPIO_PIN_0, + .gpio_af = 0, + .info = "TIM2 PA0", +#endif /*TIM2_CH1_PA0*/ + +#ifdef TIM2_CH1_PA15 + .tim_channel = TIM_CH_1, + .gpio_periph = GPIOA, + .gpio_pin = GPIO_PIN_15, + .gpio_af = GPIO_ALL_RMP_TIM2, + .info = "TIM2 PA15", +#endif /*TIM2_CH1_PA15*/ + +#ifdef TIM2_CH2_PA1 + .tim_channel = TIM_CH_2, + .gpio_periph = GPIOA, + .gpio_pin = GPIO_PIN_1, + .gpio_af = 0, + .info = "TIM2 PA1", +#endif /*TIM2_CH2_PA1*/ + +#ifdef TIM2_CH2_PB3 + .tim_channel = TIM_CH_2, + .gpio_periph = GPIOB, + .gpio_pin = GPIO_PIN_3, + .gpio_af = GPIO_ALL_RMP_TIM2, + .info = "TIM2 PB3", +#endif /*TIM2_CH2_PB3*/ + }, +#endif /*BSP_USING_TIM2_EXT_COUNTER*/ + +#ifdef BSP_USING_TIM3_EXT_COUNTER /******Select TIM2 CH1=PA6(0),PB4(2),PC6(3) ; CH2=PA7(0),PB5(2),PC7(3)******************************* */ + + { + .timer_periph = TIM3, + .polarity = TIM_IC_POLARITY_RISING, + .filter = 0x0, + .irqn = TIM3_IRQn, +#ifdef TIM3_CH1_PA6 + .tim_channel = TIM_CH_1, + .gpio_periph = GPIOA, + .gpio_pin = GPIO_PIN_6, + .gpio_af = 0, + .info = "TIM3 PA6", +#endif /*TIM3_CH1_PA6*/ + +#ifdef TIM3_CH1_PB4 + .tim_channel = TIM_CH_1, + .gpio_periph = GPIOB, + .gpio_pin = GPIO_PIN_4, + .gpio_af = GPIO_PART1_RMP_TIM3, + .info = "TIM3 PB4", +#endif /*TIM3_CH1_PB4*/ + +#ifdef TIM3_CH1_PC6 + .tim_channel = TIM_CH_1, + .gpio_periph = GPIOC, + .gpio_pin = GPIO_PIN_6, + .gpio_af = GPIO_ALL_RMP_TIM3, + .info = "TIM3 PC6", +#endif /*TIM3_CH1_PC6*/ + +#ifdef TIM3_CH2_PA7 + .tim_channel = TIM_CH_2, + .gpio_periph = GPIOA, + .gpio_pin = GPIO_PIN_7, + .gpio_af = 0, + .info = "TIM3 PA7", +#endif /*TIM3_CH2_PA7*/ + +#ifdef TIM3_CH2_PB5 + .tim_channel = TIM_CH_2, + .gpio_periph = GPIOB, + .gpio_pin = GPIO_PIN_5, + .gpio_af = GPIO_PART1_RMP_TIM3, + .info = "TIM3 PB5", +#endif /*TIM3_CH2_PB5*/ + +#ifdef TIM3_CH2_PC7 + .tim_channel = TIM_CH_2, + .gpio_periph = GPIOC, + .gpio_pin = GPIO_PIN_7, + .gpio_af = GPIO_ALL_RMP_TIM3, + .info = "TIM3 PC7", +#endif /*TIM3_CH2_PC7*/ + }, +#endif /*BSP_USING_TIM3_EXT_COUNTER*/ + +#ifdef BSP_USING_TIM4_EXT_COUNTER /******CH1=PA0(0,2),PA15(1,3) ; CH2=PA1(0,2),PB3(1,3)******************************* */ + + { + .timer_periph = TIM4, + .polarity = TIM_IC_POLARITY_RISING, + .filter = 0x0, + .irqn = TIM4_IRQn, +#ifdef TIM4_CH1_PB6 + .tim_channel = TIM_CH_1, + .gpio_periph = GPIOB, + .gpio_pin = GPIO_PIN_6, + .gpio_af = 0, + .info = "TIM4 PB6", +#endif /*TIM4_CH1_PB6*/ + +#ifdef TIM4_CH1_PD12 + .tim_channel = TIM_CH_1, + .gpio_periph = GPIOD, + .gpio_pin = GPIO_PIN_12, + .gpio_af = GPIO_RMP_TIM4, + .info = "TIM4 PD12", +#endif /*TIM4_CH1_PD12*/ + +#ifdef TIM4_CH2_PB7 + .tim_channel = TIM_CH_2, + .gpio_periph = GPIOB, + .gpio_pin = GPIO_PIN_7, + .gpio_af = 0, + .info = "TIM4 PB7", +#endif /*TIM4_CH2_PB7*/ + +#ifdef TIM4_CH2_PD13 + .tim_channel = TIM_CH_2, + .gpio_periph = GPIOD, + .gpio_pin = GPIO_PIN_13, + .gpio_af = GPIO_RMP_TIM4, + .info = "TIM4 PD13", +#endif /*TIM4_CH2_PD13*/ + }, +#endif /*BSP_USING_TIM4_EXT_COUNTER*/ + +#ifdef BSP_USING_TIM5_EXT_COUNTER /******Select TIM5 CH1=PA0; CH2=PA1******************************* */ + + { + .timer_periph = TIM5, + .polarity = TIM_IC_POLARITY_RISING, + .filter = 0x0, + .irqn = TIM5_IRQn, +#ifdef TIM5_CH1_PA0 + .tim_channel = TIM_CH_1, + .gpio_periph = GPIOA, + .gpio_pin = GPIO_PIN_0, + .gpio_af = 0, + .info = "TIM5 PA0", +#endif /*TIM5_CH1_PA0*/ + +#ifdef TIM5_CH1_PA1 + .tim_channel = TIM_CH_2, + .gpio_periph = GPIOA, + .gpio_pin = GPIO_PIN_1, + .gpio_af = 0, + .info = "TIM5 PA1", +#endif /*TIM5_CH1_PA1*/ + + }, +#endif /*BSP_USING_TIM5_EXT_COUNTER*/ + +#ifdef BSP_USING_TIM8_EXT_COUNTER /******Select TIM8 CH1=PC6(0,1),PD14(3) ; CH2=PC7(0,1),PD15(3)****************************** */ + + { + .timer_periph = TIM8, + .polarity = TIM_IC_POLARITY_RISING, + .filter = 0x0, + .irqn = TIM8_UP_IRQn, +#ifdef TIM8_CH1_PC6 + .tim_channel = TIM_CH_1, + .gpio_periph = GPIOC, + .gpio_pin = GPIO_PIN_6, + .gpio_af = 0, + .info = "TIM8 PC6", +#endif /*TIM8_CH1_PC6*/ + +#ifdef TIM8_CH1_PD14 + .tim_channel = TIM_CH_1, + .gpio_periph = GPIOD, + .gpio_pin = GPIO_PIN_14, + .gpio_af = GPIO_RMP3_TIM8, + .info = "TIM8 PD14", +#endif /*TIM8_CH1_PD14*/ + +#ifdef TIM8_CH2_PC7 + .tim_channel = TIM_CH_2, + .gpio_periph = GPIOC, + .gpio_pin = GPIO_PIN_7, + .gpio_af = 0, + .info = "TIM8 PC7", +#endif /*TIM8_CH2_PC7*/ + +#ifdef TIM8_CH2_PD15 + .tim_channel = TIM_CH_2, + .gpio_periph = GPIOD, + .gpio_pin = GPIO_PIN_15, + .gpio_af = GPIO_RMP3_TIM8, + .info = "TIM8 PD15", +#endif /*TIM8_CH2_PD15*/ + }, +#endif /*BSP_USING_TIM8_EXT_COUNTER*/ +#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) +#define N32_EXT_CLK_CNT_L406 +#ifdef BSP_USING_TIM1_EXT_COUNTER + { + + .timer_periph = TIM1, + .polarity = TIM_IC_POLARITY_RISING, + .filter = 0x0, + .irqn = TIM1_UP_IRQn, +#ifdef TIM1_CH1_PA8 + .tim_channel = TIM_CH_1, + .gpio_periph = GPIOA, + .gpio_pin = GPIO_PIN_8, + .gpio_af = GPIO_AF2_TIM1, + .info = "TIM1 PA8", +#endif /*TIM1_CH1_PA8*/ + }, +#endif /*BSP_USING_TIM1_EXT_COUNTER*/ + +#ifdef BSP_USING_TIM2_EXT_COUNTER + { + + .timer_periph = TIM2, + .polarity = TIM_IC_POLARITY_RISING, + .filter = 0x0, + .irqn = TIM1_UP_IRQn, +#ifdef TIM2_CH1_PA0 + .tim_channel = TIM_CH_1, + .gpio_periph = GPIOA, + .gpio_pin = GPIO_PIN_0, + .gpio_af = GPIO_AF2_TIM2, + .info = "TIM2 PA0", +#endif /*TIM2_CH1_PA0*/ +#ifdef TIM2_CH1_PA15 + .tim_channel = TIM_CH_1, + .gpio_periph = GPIOA, + .gpio_pin = GPIO_PIN_15, + .gpio_af = GPIO_AF5_TIM2, + .info = "TIM2 PA15", +#endif /*TIM2_CH1_PA15*/ +#ifdef TIM2_CH2_PA1 + .tim_channel = TIM_CH_2, + .gpio_periph = GPIOA, + .gpio_pin = GPIO_PIN_1, + .gpio_af = GPIO_AF2_TIM2, + .info = "TIM2 PA1", +#endif /*TIM2_CH2_PA1*/ +#ifdef TIM2_CH2_PB3 + .tim_channel = TIM_CH_2, + .gpio_periph = GPIOB, + .gpio_pin = GPIO_PIN_3, + .gpio_af = GPIO_AF2_TIM2, + .info = "TIM2 PB3", +#endif /*TIM2_CH2_PB3*/ + }, +#endif /*BSP_USING_TIM2_EXT_COUNTER*/ + + +#ifdef BSP_USING_TIM3_EXT_COUNTER + { + + .timer_periph = TIM3, + .polarity = TIM_IC_POLARITY_RISING, + .filter = 0x0, + .irqn = TIM1_UP_IRQn, +#ifdef TIM3_CH1_PA6 + .tim_channel = TIM_CH_1, + .gpio_periph = GPIOA, + .gpio_pin = GPIO_PIN_6, + .gpio_af = GPIO_AF2_TIM3, + .info = "TIM3 PA6", +#endif /*TIM3_CH1_PA6*/ +#ifdef TIM3_CH1_PB4 + .tim_channel = TIM_CH_1, + .gpio_periph = GPIOB, + .gpio_pin = GPIO_PIN_4, + .gpio_af = GPIO_AF5_TIM3, + .info = "TIM3 PB4", +#endif /*TIM3_CH1_PB4*/ +#ifdef TIM3_CH1_PC6 + .tim_channel = TIM_CH_1, + .gpio_periph = GPIOC, + .gpio_pin = GPIO_PIN_6, + .gpio_af = GPIO_AF5_TIM3, + .info = "TIM3 PC6", +#endif /*TIM3_CH1_PC6*/ +#ifdef TIM3_CH2_PA7 + .tim_channel = TIM_CH_2, + .gpio_periph = GPIOA, + .gpio_pin = GPIO_PIN_7, + .gpio_af = GPIO_AF2_TIM3, + .info = "TIM3 PA7", +#endif /*TIM3_CH2_PA7*/ +#ifdef TIM3_CH2_PB5 + .tim_channel = TIM_CH_2, + .gpio_periph = GPIOB, + .gpio_pin = GPIO_PIN_5, + .gpio_af = GPIO_AF2_TIM3, + .info = "TIM3 PB5", +#endif /*TIM3_CH2_PB5*/ +#ifdef TIM3_CH2_PC7 + .tim_channel = TIM_CH_2, + .gpio_periph = GPIOC, + .gpio_pin = GPIO_PIN_7, + .gpio_af = GPIO_AF2_TIM3, + .info = "TIM3 PC7", +#endif /*TIM3_CH2_PC7*/ + }, +#endif /*BSP_USING_TIM3_EXT_COUNTER*/ + + +#endif + +}; + +static struct n32_tim_ext_counter_device tim1_ext_counter_device[EXT_CLK_NUM]; +static int rt_hw_tim1_ext_counter_init(void) +{ + + char name[32]; + for (int i = 0; i < EXT_CLK_NUM; i++) + { + rt_memset(name, 0, 32); + rt_snprintf(name, 32, "eclktm%d", i); + n32_tim_ext_counter_register(tim1_ext_counter_device + i, + name, + tim1_ext_counter_config + i); + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_tim1_ext_counter_init); + +// /* TIM2外部计数器初始化 */ +// #ifdef BSP_USING_TIM2_EXT_COUNTER + +// static struct n32_tim_ext_counter_device tim2_ext_counter_device; +// static struct n32_tim_ext_counter_config tim2_ext_counter_config = +// { +// .timer_periph = TIM2, +// .gpio_periph = GPIOA, +// .gpio_pin = GPIO_PIN_15, /* PA15 - TIM2_CH1 */ +// .gpio_af = GPIO_ALL_RMP_TIM2, /* TIM2全重映射 */ +// .tim_channel = TIM_CH_1, +// .polarity = TIM_IC_POLARITY_RISING, +// .filter = 0x0, +// .irqn = TIM2_IRQn, +// .info = "TIM2 PA15"}; + +// static int rt_hw_tim2_ext_counter_init(void) +// { +// return n32_tim_ext_counter_register(&tim2_ext_counter_device, +// "eclktm2", +// &tim2_ext_counter_config); +// } +// INIT_DEVICE_EXPORT(rt_hw_tim2_ext_counter_init); +// #endif + +// /* TIM3外部计数器初始化 */ +// #ifdef BSP_USING_TIM3_EXT_COUNTER +// static struct n32_tim_ext_counter_device tim3_ext_counter_device; +// static struct n32_tim_ext_counter_config tim3_ext_counter_config = +// { +// .timer_periph = TIM3, +// .gpio_periph = GPIOA, +// .gpio_pin = GPIO_PIN_6, /* PA6 - TIM3_CH1 */ +// .gpio_af = 0, /* TIM3默认映射 */ +// .tim_channel = TIM_CH_1, +// .polarity = TIM_IC_POLARITY_RISING, +// .filter = 0x0, +// .irqn = TIM3_IRQn, +// .info = "TIM3 PA6"}; + +// static int rt_hw_tim3_ext_counter_init(void) +// { +// return n32_tim_ext_counter_register(&tim3_ext_counter_device, +// "eclktm3", +// &tim3_ext_counter_config); +// } +// INIT_DEVICE_EXPORT(rt_hw_tim3_ext_counter_init); +// #endif + +// /* TIM4外部计数器初始化 */ +// #ifdef BSP_USING_TIM4_EXT_COUNTER +// static struct n32_tim_ext_counter_device tim4_ext_counter_device; +// static struct n32_tim_ext_counter_config tim4_ext_counter_config = +// { +// .timer_periph = TIM4, +// .gpio_periph = GPIOB, +// .gpio_pin = GPIO_PIN_6, /* PB6 - TIM4_CH1 */ +// .gpio_af = 0, /* TIM4默认映射 */ +// .tim_channel = TIM_CH_1, +// .polarity = TIM_IC_POLARITY_RISING, +// .filter = 0x0, +// .irqn = TIM4_IRQn, +// .info = "TIM4 PB6"}; + +// static int rt_hw_tim4_ext_counter_init(void) +// { +// return n32_tim_ext_counter_register(&tim4_ext_counter_device, +// "eclktm4", +// &tim4_ext_counter_config); +// } +// INIT_DEVICE_EXPORT(rt_hw_tim4_ext_counter_init); +// #endif + +// /* TIM5外部计数器初始化 */ +// #ifdef BSP_USING_TIM5_EXT_COUNTER +// static struct n32_tim_ext_counter_device tim5_ext_counter_device; +// static struct n32_tim_ext_counter_config tim5_ext_counter_config = +// { +// .timer_periph = TIM5, +// .gpio_periph = GPIOA, +// .gpio_pin = GPIO_PIN_0, /* PA0 - TIM5_CH1 */ +// .gpio_af = 0, /* TIM5默认映射 */ +// .tim_channel = TIM_CH_1, +// .polarity = TIM_IC_POLARITY_RISING, +// .filter = 0x0, +// .irqn = TIM5_IRQn, +// .info = "TIM5 PA0"}; + +// static int rt_hw_tim5_ext_counter_init(void) +// { +// return n32_tim_ext_counter_register(&tim5_ext_counter_device, +// "eclktm5", +// &tim5_ext_counter_config); +// } +// INIT_DEVICE_EXPORT(rt_hw_tim5_ext_counter_init); +// #endif + +// /* TIM8外部计数器初始化 */ +// #ifdef BSP_USING_TIM8_EXT_COUNTER +// static struct n32_tim_ext_counter_device tim8_ext_counter_device; +// static struct n32_tim_ext_counter_config tim8_ext_counter_config = +// { +// .timer_periph = TIM8, +// .gpio_periph = GPIOC, +// .gpio_pin = GPIO_PIN_6, /* PC6 - TIM8_CH1 */ +// .gpio_af = 0, /* TIM8默认映射 */ +// .tim_channel = TIM_CH_1, +// .polarity = TIM_IC_POLARITY_RISING, +// .filter = 0x0, +// .irqn = TIM8_UP_IRQn, +// .info = "TIM8 PC6"}; + +// static int rt_hw_tim8_ext_counter_init(void) +// { +// return n32_tim_ext_counter_register(&tim8_ext_counter_device, +// "eclktm8", +// &tim8_ext_counter_config); +// } +// INIT_DEVICE_EXPORT(rt_hw_tim8_ext_counter_init); +// #endif + +// static void gpio_rcc_enable(GPIO_Module *GPIOx) +// { +// /* Check the parameters */ +// assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); +// /* Enable the GPIO Clock */ +// if (GPIOx == GPIOA) +// { +// RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE); +// } +// else if (GPIOx == GPIOB) +// { +// RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE); +// } +// else if (GPIOx == GPIOC) +// { +// RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE); +// } +// else if (GPIOx == GPIOD) +// { +// RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOD, ENABLE); +// } +// else if (GPIOx == GPIOE) +// { +// RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOE, ENABLE); +// } +// else if (GPIOx == GPIOF) +// { +// RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOF, ENABLE); +// } +// else if (GPIOx == GPIOG) +// { +// RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOG, ENABLE); +// } +// LOG_D("%s", __FUNCTION__); +// } + +// /* +// 定时器的时钟使能 +// time：定时器编号 +// */ +// void bsp_time_rcc_en(TIM_Module *time) +// { + +// if (TIM1 == time) +// { +// RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_TIM1, ENABLE); +// } +// else if (TIM8 == time) +// { +// RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_TIM8, ENABLE); +// } +// else if (TIM2 == time) +// { +// RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM2, ENABLE); +// } +// else if (TIM3 == time) +// { +// RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM3, ENABLE); +// } +// else if (TIM4 == time) +// { +// RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM4, ENABLE); +// } +// else if (TIM5 == time) +// { +// RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM5, ENABLE); +// } +// else if (TIM6 == time) +// { +// RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM6, ENABLE); +// } +// else if (TIM7_BASE == time) +// { +// RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM7, ENABLE); +// } +// LOG_D("%s", __FUNCTION__); +// } + +static rt_err_t n32_tim_ext_counter_init_hw(struct n32_tim_ext_counter_device *device) +{ + struct n32_tim_ext_counter_config *config = device->config; + GPIO_InitType GPIO_InitStructure; + TIM_TimeBaseInitType TIM_TimeBaseStructure; + + /* 使能时钟 */ + n32_gpio_rcc_enable(config->gpio_periph); + n32_time_rcc_config(config->timer_periph); +#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) + + /* 配置GPIO为输入模式 */ + GPIO_InitStructure.Pin = config->gpio_pin; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; /* 浮空输入 */ + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitPeripheral(config->gpio_periph, &GPIO_InitStructure); + + /* 配置GPIO复用功能 */ + if (config->gpio_af) + GPIO_ConfigPinRemap(config->gpio_af, ENABLE); + if (GPIOA == config->gpio_periph && GPIO_PIN_15 == config->gpio_pin) + { + GPIO_ConfigPinRemap(GPIO_RMP_SW_JTAG_SW_ENABLE, ENABLE); /*!< JTAG-DP Disabled and SW-DP Enabled */ + LOG_I("use pa15"); + } +#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE); + GPIO_InitStruct(&GPIO_InitStructure); + GPIO_InitStructure.Pin = config->gpio_pin; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Input; + GPIO_InitStructure.GPIO_Current = GPIO_DC_4mA; + GPIO_InitStructure.GPIO_Alternate = config->gpio_af; + GPIO_InitStructure.GPIO_Slew_Rate = GPIO_Slew_Rate_High; + GPIO_InitPeripheral(config->gpio_periph, &GPIO_InitStructure); +#endif + /* 复位定时器 */ + TIM_DeInit(config->timer_periph); + + /* 配置定时器基本参数 */ + TIM_InitTimBaseStruct(&TIM_TimeBaseStructure); + TIM_TimeBaseStructure.Period = 0xFFFF; /* 最大计数值 */ + TIM_TimeBaseStructure.Prescaler = 0; /* 不分频 */ + TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1; + TIM_TimeBaseStructure.CntMode = TIM_CNT_MODE_UP; + TIM_InitTimeBase(config->timer_periph, &TIM_TimeBaseStructure); + + /* 配置外部时钟模式1 - 按照手册步骤 */ + uint16_t ext_clk_src; + if (config->tim_channel == TIM_CH_1) + { + ext_clk_src = TIM_EXT_CLK_SRC_TI1; + LOG_D("Configuring TI1 as external clock source"); + } + else if (config->tim_channel == TIM_CH_2) + { + ext_clk_src = TIM_EXT_CLK_SRC_TI2; + LOG_D("Configuring TI2 as external clock source"); + } + else + { + LOG_E("Unsupported channel for external clock"); + return RT_ERROR; + } + + /* 使用库函数配置外部时钟 */ + TIM_ConfigExtTrigAsClk(config->timer_periph, ext_clk_src, config->polarity, config->filter); + + /* 验证配置 - 读取寄存器确认设置 */ + LOG_D("SMCTRL register: 0x%08X", config->timer_periph->SMCTRL); + LOG_D("CCMOD1 register: 0x%08X", config->timer_periph->CCMOD1); + LOG_D("CCEN register: 0x%08X", config->timer_periph->CCEN); + + /* 配置更新中断（溢出中断） */ + TIM_ConfigInt(config->timer_periph, TIM_INT_UPDATE, ENABLE); + TIM_ClearFlag(config->timer_periph, TIM_FLAG_UPDATE); // 中断标志清零 + + /* 清零计数器 */ + TIM_SetCnt(config->timer_periph, 0); + + /* 使能定时器 */ + TIM_Enable(config->timer_periph, ENABLE); + + LOG_I("External counter initialized: %s", config->info); + return RT_EOK; +} + +static rt_err_t n32_tim_ext_counter_open(rt_device_t dev, rt_uint16_t oflag) +{ + struct n32_tim_ext_counter_device *device = (struct n32_tim_ext_counter_device *)dev; + + /* 初始化硬件 */ + n32_tim_ext_counter_init_hw(device); + + /* 使能中断 */ + NVIC_SetPriority(device->config->irqn, 3); + NVIC_EnableIRQ(device->config->irqn); + + LOG_D("External counter %s opened", device->config->name); + return RT_EOK; +} + +static rt_err_t n32_tim_ext_counter_close(rt_device_t dev) +{ + struct n32_tim_ext_counter_device *device = (struct n32_tim_ext_counter_device *)dev; + + /* 禁用定时器 */ + TIM_Enable(device->config->timer_periph, DISABLE); + + /* 禁用中断 */ + NVIC_DisableIRQ(device->config->irqn); + + LOG_D("External counter %s closed", device->config->name); + return RT_EOK; +} +static rt_ssize_t n32_tim_ext_counter_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + struct n32_tim_ext_counter_device *device = (struct n32_tim_ext_counter_device *)dev; + rt_uint32_t *count_buf = (rt_uint32_t *)buffer; + + if (size < sizeof(rt_uint32_t)) + return 0; + + /* 读取当前计数值 */ + rt_uint16_t current_count = TIM_GetCnt(device->config->timer_periph); + device->count_value = (device->overflow_count << 16) + current_count; + + // 清零计数器 + TIM_SetCnt(device->config->timer_periph, 0); + device->overflow_count = 0; + + *count_buf = device->count_value; + return sizeof(rt_uint32_t); +} + +static rt_err_t n32_tim_ext_counter_control(rt_device_t dev, int cmd, void *args) +{ + struct n32_tim_ext_counter_device *device = (struct n32_tim_ext_counter_device *)dev; + + switch (cmd) + { + case RT_DEVICE_CTRL_RESUME: + /* 复位计数器 */ + TIM_SetCnt(device->config->timer_periph, 0); + device->overflow_count = 0; + device->count_value = 0; + break; + + case RT_DEVICE_CTRL_SET_INT: + /* 设置溢出回调函数 */ + if (args) + { + struct rt_device_notify *notify = (struct rt_device_notify *)args; + device->overflow_callback = notify->notify; + device->callback_args = notify->dev; /* 使用dev字段传递参数 */ + } + break; + + default: + return RT_EINVAL; + } + + return RT_EOK; +} + +/* 中断处理函数模板 */ +void n32_tim_ext_counter_irq_handler(struct n32_tim_ext_counter_device *device) +{ + rt_interrupt_enter(); // 进入中断 + if (TIM_GetIntStatus(device->config->timer_periph, TIM_INT_UPDATE) != RESET) + { + /* 清除中断标志 */ + TIM_ClrIntPendingBit(device->config->timer_periph, TIM_INT_UPDATE); + + /* 溢出计数 */ + device->overflow_count++; + + /* 调用回调函数 */ + if (device->overflow_callback) + { + device->overflow_callback((rt_device_t)device->callback_args); + } + } + rt_interrupt_leave(); // 离开中断 +} +#ifdef RT_USING_DEVICE_OPS +/**设备操作函数接口 */ +static const struct rt_device_ops ops = { + .init = RT_NULL, + .open = n32_tim_ext_counter_open, + .close = n32_tim_ext_counter_close, + .write = RT_NULL, + .control = n32_tim_ext_counter_control, + .read = n32_tim_ext_counter_read, + +}; +#endif +static rt_err_t n32_tim_ext_counter_register(struct n32_tim_ext_counter_device *device, + const char *name, + struct n32_tim_ext_counter_config *config) +{ + RT_ASSERT(device != RT_NULL); + RT_ASSERT(config != RT_NULL); + + device->config = config; + device->count_value = 0; + device->overflow_count = 0; + device->overflow_callback = RT_NULL; + device->callback_args = RT_NULL; + device->parent.type = RT_Device_Class_Miscellaneous; + device->parent.user_data = config; +#ifdef RT_USING_DEVICE_OPS + device->parent.ops = &ops; +#else + + device->parent.init = RT_NULL; + device->parent.open = n32_tim_ext_counter_open; + device->parent.close = n32_tim_ext_counter_close; + device->parent.read = n32_tim_ext_counter_read; + device->parent.write = RT_NULL; + device->parent.control = n32_tim_ext_counter_control; + +#endif + LOG_I("device name = %s infomations %s", name, config->info); + return rt_device_register(&device->parent, name, RT_DEVICE_FLAG_RDONLY); +} + +/* TIM1外部计数器中断处理 */ +#ifdef BSP_USING_TIM1_EXT_COUNTER +void TIM1_UP_IRQHandler(void) +{ + rt_interrupt_enter(); + n32_tim_ext_counter_irq_handler(tim1_ext_counter_device + EXT_CLK_TIM1); + rt_interrupt_leave(); +} +#endif + +/* TIM2外部计数器中断处理 */ +#ifdef BSP_USING_TIM2_EXT_COUNTER +void TIM2_IRQHandler(void) +{ + rt_interrupt_enter(); + n32_tim_ext_counter_irq_handler(tim1_ext_counter_device + EXT_CLK_TIM2); + rt_interrupt_leave(); +} +#endif + +/* TIM3外部计数器中断处理 */ +#ifdef BSP_USING_TIM3_EXT_COUNTER +void TIM3_IRQHandler(void) +{ + rt_interrupt_enter(); + n32_tim_ext_counter_irq_handler(tim1_ext_counter_device + EXT_CLK_TIM3); + rt_interrupt_leave(); +} +#endif + +/* TIM4外部计数器中断处理 */ +#ifdef BSP_USING_TIM4_EXT_COUNTER +void TIM4_IRQHandler(void) +{ + rt_interrupt_enter(); + n32_tim_ext_counter_irq_handler(tim1_ext_counter_device + EXT_CLK_TIM4); + rt_interrupt_leave(); +} +#endif + +/* TIM5外部计数器中断处理 */ +#ifdef BSP_USING_TIM5_EXT_COUNTER +void TIM5_IRQHandler(void) +{ + rt_interrupt_enter(); + n32_tim_ext_counter_irq_handler(tim1_ext_counter_device + EXT_CLK_TIM5); + rt_interrupt_leave(); +} +#endif + +/* TIM8外部计数器中断处理 */ +#ifdef BSP_USING_TIM8_EXT_COUNTER +void TIM8_UP_IRQHandler(void) +{ + rt_interrupt_enter(); + n32_tim_ext_counter_irq_handler(tim1_ext_counter_device + EXT_CLK_TIM8); + rt_interrupt_leave(); +} +#endif /**/ + +/*************************************shell 中断指令用于测试*************************************************************** */ +#ifdef RT_USING_FINSH +#include +#include +#include + +enum pwm_list_parameters +{ + ETR_LIST_PROBE = 1, + ETR_LIST_GET, +}; + +CMD_OPTIONS_STATEMENT(eclk_cnt_list) + +static int eclk_cnt_list(int argc, char **argv) +{ + rt_err_t result = -RT_ERROR; + char *result_str; + static rt_device_t device = RT_NULL; + int arg2 = 0; + uint32_t count = 0; + if (argc > 1) + { + if (MSH_OPT_ID_GET(eclk_cnt_list) == ETR_LIST_PROBE) + { + if (argc == 3) + { + device = rt_device_find(argv[2]); + if (device) + { + rt_device_open(device, 0); + } + result_str = (device == RT_NULL) ? "failure" : "success"; + rt_kprintf("probe %s %s\n", argv[2], result_str); + return (device == RT_NULL) ? -RT_ERROR : RT_EOK; + } + else + { + rt_kprintf("eclk_cnt probe - probe eclk_cnt by name\n"); + return -RT_EINVAL; + } + } + else if (device == RT_NULL) + { + rt_kprintf("Please using 'eclk_cnt probe ' first.\n"); + return -RT_ERROR; + } + + switch (MSH_OPT_ID_GET(eclk_cnt_list)) + { + + case ETR_LIST_GET: + // arg2 = atoi(argv[2]); + rt_device_read(device, 0, &count, sizeof(count)); + // count = bsp_timer_count_etr_get_count(device); + rt_kprintf("Info of device count= [%d]:\n", count); + return RT_EOK; + + break; + + default: + goto _usage; + } + } + else + { + goto _usage; + } + return result; + +_usage: + rt_kprintf("Usage: \n"); + rt_kprintf("eclk_cnt probe - probe eclk_cnt by name\n"); + rt_kprintf("eclk_cnt get - get eclk_cnt cnt info\n"); + + result = -RT_ERROR; + return result; +} +CMD_OPTIONS_NODE_START(eclk_cnt_list) +CMD_OPTIONS_NODE(ETR_LIST_PROBE, probe, probe eclk_cnt name) +CMD_OPTIONS_NODE(ETR_LIST_GET, get, get eclk_cnt count) +CMD_OPTIONS_NODE_END +MSH_CMD_EXPORT_ALIAS(eclk_cnt_list, eclk_cnt, control eclk_cnt device, optenable); + +#endif /* RT_USING_FINSH */ +/*************************************shell 中断指令用于测试*************************************************************** */ + +#ifdef BSP_USING_EXT_COUNTER_DEMO + +#define ETR_DEV_NAME "eclktm1" + +static rt_mailbox_t mb_etr; +static void timout_etr(void *parameter) +{ + uint32_t count = 0; + rt_device_t etr_dev = (rt_device_t)parameter; + rt_device_read(etr_dev, 0, &count, sizeof(count)); + rt_mb_send_wait(mb_etr, count, 0); +} +static void thd_entry_etr(void *parameter) +{ + uint32_t value = 0; + while (1) + { + if (RT_EOK == rt_mb_recv(mb_etr, &value, RT_WAITING_FOREVER)) + { + LOG_I("ETR CNT %d", value); + } + } +} +static int extr_app_demo(void) +{ + static rt_device_t etr_dev = RT_NULL; + etr_dev = rt_device_find(ETR_DEV_NAME); + if (etr_dev) + { + rt_device_open(etr_dev, 0); + } + else + { + LOG_W("ETR device not find"); + } + mb_etr = rt_mb_create(ETR_DEV_NAME, 5, RT_IPC_FLAG_FIFO); + RT_ASSERT(mb_etr); + rt_thread_t thd_etr = rt_thread_create(ETR_DEV_NAME, thd_entry_etr, etr_dev, 512, 20, 5); + RT_ASSERT(thd_etr); + rt_thread_startup(thd_etr); + rt_timer_t timer = rt_timer_create(ETR_DEV_NAME, timout_etr, etr_dev, 1000, RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_HARD_TIMER); + RT_ASSERT(timer); + rt_timer_start(timer); + return RT_EOK; +} +INIT_APP_EXPORT(extr_app_demo); +#endif /* BSP_USING_EXT_COUNTER_DEMO */ + +#endif /*BSP_USING_TIM_EXT_COUNTER*/ +/*************************************************************************************************** */ + diff --git a/bsp/n32/libraries/n32_drivers/drv_tim_external_counter.h b/bsp/n32/libraries/n32_drivers/drv_tim_external_counter.h new file mode 100644 index 00000000000..09498e1c26f --- /dev/null +++ b/bsp/n32/libraries/n32_drivers/drv_tim_external_counter.h @@ -0,0 +1,8 @@ +#ifndef __DRV_TIM_EXTERNAL_COUNTER_H__ +#define __DRV_TIM_EXTERNAL_COUNTER_H__ + +#include + +#endif /* __DRV_TIM_EXTERNAL_COUNTER_H__ */ + + diff --git a/bsp/n32/libraries/n32_drivers/drv_tim_pulse_width.c b/bsp/n32/libraries/n32_drivers/drv_tim_pulse_width.c new file mode 100644 index 00000000000..cfed37b1962 --- /dev/null +++ b/bsp/n32/libraries/n32_drivers/drv_tim_pulse_width.c @@ -0,0 +1,687 @@ + +/** + * @file drv_tim_pulse_width.c + * @brief + * @author jiache (wanghuan3037@fiberhome.com) + * @version 1.0 + * @date 2025-12-02 + * 1.添加注释，加入日志宏的定义 + * 2.处理头文件，将不必要的直接放入c文件 + * 3.处理了代码警告问题 + * 4.修改了pwm输入模式的滤波，将3改为0 + * 5. 基于N32g457 TIM8 测量：输入pwm的最大宽度测量范围 455100ns(Reload=0xfffc),最小的脉宽可以测量到28ns（COMP=0x02）,经测试1MHz的方波，输出比较器必须大于2时，测量测对准确 + * > pwm set 1 455100 28 455100ns=2197Hz，测量的频率不可以低于这个，否测测量的周期不准哦 + * 6回调函数的为空判定的bug修复 + * 7.在dam中断中需要+一个对象偏移，用于宏配置，于是添加了一个枚举，用于定义tim测量设备 + * 8.这个驱动使用了一个2000字节的dma缓存区，用户定时器的dma数据传输，以降低CPU的使用率；缓存越小，占用越小 + * 9.驱动使用了dma的传输过半中断，可以防止dma传输完成导致的数据覆盖问题。 + * 10.经过测试测量1MHz的方波的，脉宽 大于28ns情况，脉冲数据误差±1个脉冲；同时测量2MHz，将缓存放大到4096，mcu直接忙的打印都不输出了 + * 11.将定时器的时钟和gpio时钟统一放在drv_base.c中 + * 12.这个驱动必须注册一个回调函数，用于每一个脉宽数据的处理，回调函数执行与高优先级线程中 + * 13.该驱动支持高级定时器和通用定时器 + * 14.目前驱动仅仅支持通道1输入测量，理论上通道2也是可以的。 + * @copyright Copyright (c) 2025 58 + * + */ +#include + +#ifdef BSP_USING_TIM_PULSE_WIDTH + +#define DBG_TAG "PWT_7NS" +#define DBG_LVL DBG_INFO + +#include + +#include +#include "board.h" +#include "drv_tim_pulse_width.h" +#include "drv_base.h" + +/* 脉宽测量设备控制命令 */ +#define RT_DEVICE_CTRL_PULSE_WIDTH_TEST_TIMEOUT (RT_DEVICE_CTRL_BASE(Miscellaneous) + 0x10) // 间隔XX时间，开始统计采集的脉冲数量 +#define RT_DEVICE_CTRL_PULSE_WIDTH_SET_CALLBACK (RT_DEVICE_CTRL_BASE(Miscellaneous) + 0x11) // 设置回调函数 + +#define DMA_BUFFER_SIZE 4096 // 2KB DMA缓冲区 + +/* GPIO配置结构 */ +struct n32_tim_pulse_width_gpio +{ + GPIO_Module *gpio_port; /* GPIO端口 */ + rt_uint16_t gpio_pin; /* GPIO引脚 */ + rt_uint8_t gpio_af; /* 复用功能 */ +}; +/**dam配置结构体 */ +typedef struct +{ + uint32_t rcc_dma; // dma的时钟 + DMA_Module *dma; // dma外设 + DMA_ChannelType *dma_ch; // dam通道 + uint32_t dma_remap; // dma通道映射 + uint32_t dma_irq; // dma的中断号 + uint32_t dma_it_tx; // dma传输完成标记 + uint32_t dma_it_hx; // dma传输过半标记 +} dma_config_t; + +/* 脉宽测量配置结构 */ +struct n32_tim_pulse_width_config +{ + + TIM_Module *timer_periph; /* 定时器外设 */ + rt_uint16_t tim_channel; /* 定时器通道 */ + rt_uint16_t prescaler; /* 预分频器 */ + struct n32_tim_pulse_width_gpio gpio_config; /* GPIO配置 */ + dma_config_t dma_cfg; /**dma配置结构 */ + char *name; /**脉宽采集设备名称 */ + char *info; /*附加信息*/ +}; + +/* 脉宽测量设备结构 */ +struct n32_tim_pulse_width_device +{ + struct rt_device parent; + struct n32_tim_pulse_width_config *config; + // 每一次dma传输完成产生一次中断 + fun_pulse_callback pulse_callback; + rt_uint32_t dma_buffer[DMA_BUFFER_SIZE]; /* DMA缓冲区指针 */ + rt_thread_t thread; // 线程 + rt_mailbox_t box; // 接收dma传输完成的信号 + // DMA_ChannelType *dma_channel; /* DMA通道 */ +}; + +// 前向声明 +static void n32_tim_pulse_width_dma_config(struct n32_tim_pulse_width_device *device); +static void n32_tim_pulse_width_dma_start(struct n32_tim_pulse_width_device *device); +/* 重新启动DMA传输 */ +// void n32_tim_pulse_width_dma_restart(struct n32_tim_pulse_width_device *device); + +// dma事件 +enum EV +{ + TX_OK = 0X0FFF0000, + HX_OK, + OTHERS +}; + +enum PULSE_TEST_DEV +{ +#ifdef BSP_USING_TIM1_PULSE_WIDTH + PWTD_TIM1, +#endif +#ifdef BSP_USING_TIM4_PULSE_WIDTH + PWTD_TIM4, +#endif + +#ifdef BSP_USING_TIM8_PULSE_WIDTH + PWTD_TIM8, +#endif + + + PWTD_NUM /*设备数量*/ +}; + +/** + * @brief 脉宽采集对象 + * + */ +static struct n32_tim_pulse_width_device tim_pulse_width_device[PWTD_NUM]; + +/* TIM1脉宽测量配置 - PA8 */ + +static struct n32_tim_pulse_width_config tim_pulse_width_config[PWTD_NUM] = + { +#ifdef BSP_USING_TIM1_PULSE_WIDTH + { + .timer_periph = TIM1, + .tim_channel = TIM_CH_1, + .prescaler = 0, /* 1MHz计数频率 */ + .name = "pulse1", + .info = "TIM1 PA8", + .gpio_config = { + .gpio_port = GPIOA, + .gpio_pin = GPIO_PIN_8, + .gpio_af = 0, + }, + .dma_cfg = { + .rcc_dma = RCC_AHB_PERIPH_DMA1, + .dma = DMA1, + .dma_ch = DMA1_CH2, + .dma_remap = DMA1_REMAP_TIM1_CH1, + .dma_irq = DMA1_Channel2_IRQn, + .dma_it_tx = DMA1_INT_TXC2, + .dma_it_hx = DMA1_INT_HTX2, + }, + }, +#endif/*BSP_USING_TIM1_PULSE_WIDTH*/ + +#ifdef BSP_USING_TIM4_PULSE_WIDTH + {.timer_periph = TIM4, .tim_channel = TIM_CH_1, .prescaler = 0, /* 1MHz计数频率 */ + .name = "pulse4", + .info = "TIM4 PB6", + .gpio_config = { + .gpio_port = GPIOB, + .gpio_pin = GPIO_PIN_6, + .gpio_af = 0, + }, + .dma_cfg = { + .rcc_dma = RCC_AHB_PERIPH_DMA1, + .dma = DMA1, + .dma_ch = DMA1_CH1, + .dma_remap = DMA1_REMAP_TIM4_CH1, + .dma_irq = DMA1_Channel1_IRQn, + .dma_it_tx = DMA1_INT_TXC1, + .dma_it_hx = DMA1_INT_HTX1, + }} +#endif/*BSP_USING_TIM4_PULSE_WIDTH*/ + +#ifdef BSP_USING_TIM8_PULSE_WIDTH + {.timer_periph = TIM8, .tim_channel = TIM_CH_1, .prescaler = 0, /* 1MHz计数频率 */ + .name = "pulse8", + .info = "TIM8 PC6", + .gpio_config = { + .gpio_port = GPIOC, + .gpio_pin = GPIO_PIN_6, + .gpio_af = 0, + }, + .dma_cfg = { + .rcc_dma = RCC_AHB_PERIPH_DMA2, + .dma = DMA2, + .dma_ch = DMA2_CH3, + .dma_remap = DMA2_REMAP_TIM8_CH1, + .dma_irq = DMA2_Channel3_IRQn, + .dma_it_tx = DMA2_INT_TXC3, + .dma_it_hx = DMA2_INT_HTX3, + }} +#endif/*BSP_USING_TIM8_PULSE_WIDTH*/ + +}; + +/* DMA传输完成中断处理函数 */ +static void n32_tim_pulse_width_dma_irq_handler(struct n32_tim_pulse_width_device *device) +{ + // uint32_t int_flag = 0; + static volatile rt_uint32_t cnt = 0; + const dma_config_t *config = &(device->config->dma_cfg); + + if (DMA_GetIntStatus(config->dma_it_tx, config->dma) != RESET) + { + /* 清除DMA传输完成中断标志 */ + DMA_ClrIntPendingBit(config->dma_it_tx, config->dma); + // 传递传输完成信号 + rt_mb_send_wait(device->box, TX_OK, 0); + } + else if (DMA_GetIntStatus(config->dma_it_hx, config->dma) != RESET) + { + /* 清除DMA传输过半中断标志 */ + DMA_ClrIntPendingBit(config->dma_it_hx, config->dma); + + // 传递传输完成信号 + rt_mb_send_wait(device->box, HX_OK, 0); + } + + // else if (DMA_GetIntStatus(DMA1_INT_ERR2, DMA1) != RESET) + // { + // /* 清除DMA传输错误中断标志 */ + // DMA_ClrIntPendingBit(DMA1_INT_ERR2, DMA1); + // } +} +/* +线程 用于处理dam传输的数据，集中处理，降低CPU利用率 +*/ +static void thread_entry_pulse(void *parameter) +{ + rt_ubase_t val = 0; + rt_uint32_t len = 0; + rt_uint32_t data_size = 0; + rt_uint32_t data_start = 0; + + struct n32_tim_pulse_width_device *device = (struct n32_tim_pulse_width_device *)parameter; + while (1) + { + if (RT_EOK == rt_mb_recv(device->box, &val, RT_WAITING_FOREVER) && device->pulse_callback) + { + if (TX_OK == val) // 完成 + { + data_size = (DMA_BUFFER_SIZE >> 1); + data_start = (DMA_BUFFER_SIZE >> 1); + } + else if (HX_OK == val) // 过半 + { + data_start = 0; + data_size = (DMA_BUFFER_SIZE >> 1); + } + else // 用户手动停止时的处理 + { + /** + * 这里可能重复处理，上半段的数据，但是数据被清零了，不影响结果 + * + */ + data_start = 0; + data_size = DMA_BUFFER_SIZE - val; + } + + len = data_start + data_size; + for (int i = data_start; i < len; i += 2) + { + // 这里处理数据区分脉宽测量,dataptr[i]低电平的宽度，dataptr[i+1]高电平的宽度；只有非零才是有效的数 + if (device->dma_buffer[i + 1] && device->dma_buffer[i] && device->pulse_callback) + { + device->pulse_callback(&device->parent, device->dma_buffer[i + 1], device->dma_buffer[i], 0); + } + } + } + // 表示测量测试结束 + if (val != TX_OK && val != HX_OK) + { + device->pulse_callback(&device->parent, 0, 0, 1); + } + // 数据置零--很重要 + rt_memset(device->dma_buffer + data_start, 0, sizeof(rt_uint32_t) * data_size); + } +} +/** + * @brief gpio的配重 + * + * @param device + */ +static void n32_tim_pulse_width_gpio_init(struct n32_tim_pulse_width_device *device) +{ + struct n32_tim_pulse_width_config *config = device->config; + GPIO_InitType gpio_init; + /* 使能GPIO时钟 */ + n32_gpio_rcc_enable(config->gpio_config.gpio_port); + /* 配置GPIO引脚 */ + gpio_init.Pin = config->gpio_config.gpio_pin; + gpio_init.GPIO_Mode = GPIO_Mode_IPU; + gpio_init.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitPeripheral(config->gpio_config.gpio_port, &gpio_init); + + /* 配置AFIO重映射（如果需要） */ + if (config->gpio_config.gpio_af) + { + GPIO_ConfigPinRemap(config->gpio_config.gpio_af, ENABLE); + } +} +/** + * @brief 定时器的基本参数配置 + * + * @param device + */ +static void n32_tim_pulse_width_timebase_init(struct n32_tim_pulse_width_device *device) +{ + struct n32_tim_pulse_width_config *config = device->config; + TIM_TimeBaseInitType tim_base_init; + + /* 使能AFIO时钟 */ + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE); + + /* 使能定时器时钟 */ + n32_time_rcc_config(config->timer_periph); + + /* 配置定时器基本参数 */ + TIM_InitTimBaseStruct(&tim_base_init); + tim_base_init.Period = 0xFFFF; /* 最大计数值 */ + tim_base_init.Prescaler = config->prescaler; + tim_base_init.ClkDiv = TIM_CLK_DIV1; + tim_base_init.CntMode = TIM_CNT_MODE_UP; + TIM_InitTimeBase(config->timer_periph, &tim_base_init); +} +/** + * @brief pwm输入模式配置 + * + * @param device + */ +static void n32_tim_pulse_width_pwm_init(struct n32_tim_pulse_width_device *device) +{ + struct n32_tim_pulse_width_config *config = device->config; + TIM_ICInitType tim_ic_init; + /* 配置PWM输入模式 */ + TIM_InitIcStruct(&tim_ic_init); + tim_ic_init.Channel = config->tim_channel; /* 使用通道1和通道2 */ + tim_ic_init.IcPolarity = TIM_IC_POLARITY_RISING; /* CC1上升沿捕获周期 */ + tim_ic_init.IcSelection = TIM_IC_SELECTION_DIRECTTI; /* CC1直接映射到TI1 */ + tim_ic_init.IcPrescaler = TIM_IC_PSC_DIV1; + tim_ic_init.IcFilter = 0; + TIM_ConfigPwmIc(config->timer_periph, &tim_ic_init); +} + +// /* 重新启动DMA传输 */ +// void n32_tim_pulse_width_dma_restart(struct n32_tim_pulse_width_device *device) +// { +// const dma_config_t *config = &(device->config->dma_cfg); + +// // // 启动定时器 +// // TIM_Enable(device->config->timer_periph, DISABLE); +// // // 禁用DMA通道 +// // DMA_EnableChannel(device->dma_channel, DISABLE); + +// rt_uint32_t curcnt = DMA_GetCurrDataCounter(config->dma_ch); +// // 传递传输完成信号 +// rt_mb_send_wait(device->box, curcnt, 0); +// // 重新配置DMA缓冲区大小 +// // DMA_SetCurrDataCounter(device->dma_channel, DMA_BUFFER_SIZE); + +// // // 重新启用DMA通道 +// // DMA_EnableChannel(device->dma_channel, ENABLE); +// // // 启动定时器 +// // TIM_Enable(device->config->timer_periph, ENABLE); +// } + +// DMA配置函数 +static void n32_tim_pulse_width_dma_config(struct n32_tim_pulse_width_device *device) +{ + TIM_Module *tim = device->config->timer_periph; + const dma_config_t *config = &(device->config->dma_cfg); + DMA_InitType dma_init; + + rt_memset(device->dma_buffer, 0, sizeof(rt_uint32_t) * (DMA_BUFFER_SIZE)); + // 初始化DMA + RCC_EnableAHBPeriphClk(config->rcc_dma, ENABLE); + + // 配置DMA通道 + dma_init.PeriphAddr = (uint32_t)&tim->DADDR; // 捕获/比较寄存器1地址 + dma_init.MemAddr = (uint32_t)device->dma_buffer; + dma_init.Direction = DMA_DIR_PERIPH_SRC; + dma_init.BufSize = DMA_BUFFER_SIZE; + dma_init.PeriphInc = DMA_PERIPH_INC_DISABLE; + dma_init.DMA_MemoryInc = DMA_MEM_INC_ENABLE; + dma_init.PeriphDataSize = DMA_PERIPH_DATA_SIZE_WORD; + dma_init.MemDataSize = DMA_MemoryDataSize_Word; + dma_init.CircularMode = DMA_MODE_CIRCULAR; + dma_init.Priority = DMA_PRIORITY_HIGH; + dma_init.Mem2Mem = DMA_M2M_DISABLE; + + DMA_Init(config->dma_ch, &dma_init); + + DMA_RequestRemap(config->dma_remap, config->dma, config->dma_ch, ENABLE); + + // 配置DMA传输完成中断 + DMA_ConfigInt(config->dma_ch, DMA_INT_TXC, ENABLE); + DMA_ConfigInt(config->dma_ch, DMA_INT_HTX, ENABLE); + + // 配置NVIC + NVIC_InitType nvic_init; + nvic_init.NVIC_IRQChannel = config->dma_irq; + nvic_init.NVIC_IRQChannelPreemptionPriority = 2; + nvic_init.NVIC_IRQChannelSubPriority = 1; + nvic_init.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&nvic_init); + + // 使能定时器的DMA请求 + TIM_ConfigDma(tim, TIM_DMABASE_CAPCMPDAT1, TIM_DMABURST_LENGTH_2TRANSFERS); // 配置dam传输的开始地址CAPCMPDAT1和传输数量2TRANSFERS， + TIM_EnableDma(tim, TIM_DMA_CC1, ENABLE); +} + +// DMA启动函数 +static void n32_tim_pulse_width_dma_start(struct n32_tim_pulse_width_device *device) +{ + // 启动DMA传输 + DMA_EnableChannel(device->config->dma_cfg.dma_ch, ENABLE); +} + +/* 设备初始化 */ +static rt_err_t n32_tim_pulse_width_open(rt_device_t dev) +{ + struct n32_tim_pulse_width_device *device = (struct n32_tim_pulse_width_device *)dev; + struct n32_tim_pulse_width_config *config = device->config; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(config != RT_NULL); + + // 接收dma的传输结束信号 + device->box = rt_mb_create(config->name, 10, RT_IPC_FLAG_FIFO); + RT_ASSERT(device->box != RT_NULL); + /* 创建线程 1，名称是 thread1，入口是 thread1_entry*/ + device->thread = rt_thread_create(config->name, + thread_entry_pulse, device, + 512, + 5, 20); + /* 如果获得线程控制块，启动这个线程 */ + if (device->thread != RT_NULL) + rt_thread_startup(device->thread); + + // gpio + n32_tim_pulse_width_gpio_init(device); + // timbase + n32_tim_pulse_width_timebase_init(device); + // pwm + n32_tim_pulse_width_pwm_init(device); + + /* 配置从模式：复位模式，TI1FP1作为触发源 */ + TIM_SelectInputTrig(config->timer_periph, TIM_TRIG_SEL_TI1FP1); /* 选择TI1FP1作为触发源 */ + TIM_SelectSlaveMode(config->timer_periph, TIM_SLAVE_MODE_RESET); /* 复位模式 */ + + // 配置DMA + n32_tim_pulse_width_dma_config(device); + // 启动DMA + n32_tim_pulse_width_dma_start(device); + + // 启动定时器 + TIM_Enable(config->timer_periph, ENABLE); + + LOG_I("TIM PWM input open ok %s info =%s", config->name, config->info); + + return RT_EOK; +} +/** + * @brief 驱动的接口contrl函数 + * + * @param dev + * @param cmd + * @param args + * @return rt_err_t + */ +static rt_err_t n32_tim_pulse_width_control(rt_device_t dev, int cmd, void *args) +{ + struct n32_tim_pulse_width_device *device = (struct n32_tim_pulse_width_device *)dev; + const dma_config_t *config = &(device->config->dma_cfg); + rt_uint32_t curcnt = 0; + switch (cmd) + { + case RT_DEVICE_CTRL_PULSE_WIDTH_TEST_TIMEOUT: // 超时开始统计这个时间段的脉宽测量数据 + curcnt = DMA_GetCurrDataCounter(config->dma_ch); + // 传递传输完成信号 + rt_mb_send_wait(device->box, curcnt, 0); + break; + case RT_DEVICE_CTRL_PULSE_WIDTH_SET_CALLBACK: // 注册回调函数 + device->pulse_callback = (fun_pulse_callback)args; + break; + default: + break; + } + return RT_EOK; +} + +#ifdef RT_USING_DEVICE_OPS +/**设备操作函数接口 */ +const struct rt_device_ops ops = { + .init = RT_NULL, + .open = n32_tim_pulse_width_open, + .close = RT_NULL, + .write = RT_NULL, + .control = n32_tim_pulse_width_control, + .read = RT_NULL, +}; +#endif +/* 注册脉宽测量设备 */ +static rt_err_t n32_tim_pulse_width_register(struct n32_tim_pulse_width_device *device, + struct n32_tim_pulse_width_config *config) +{ + RT_ASSERT(device != RT_NULL); + RT_ASSERT(config != RT_NULL); + rt_memset(device, 0, sizeof(struct n32_tim_pulse_width_device)); + + device->config = config; + device->parent.type = RT_Device_Class_Miscellaneous; + device->parent.user_data = config; +#ifdef RT_USING_DEVICE_OPS + device->parent.ops = &ops; +#else + + device->parent.init = RT_NULL; + device->parent.open = n32_tim_pulse_width_open; + device->parent.control = n32_tim_pulse_width_control; + device->parent.write = RT_NULL; + device->parent.read = RT_NULL; + device->parent.close = RT_NULL; +#endif + return rt_device_register(&device->parent, config->name, RT_DEVICE_FLAG_RDONLY); +} + +#ifdef BSP_USING_TIM1_PULSE_WIDTH +// TIM1 DMA中断处理函数 +void DMA1_Channel2_IRQHandler(void) +{ + rt_interrupt_enter(); + n32_tim_pulse_width_dma_irq_handler(tim_pulse_width_device + PWTD_TIM1); + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIM4_PULSE_WIDTH +// TIM1 DMA中断处理函数 +void DMA1_Channel1_IRQHandler(void) +{ + rt_interrupt_enter(); + n32_tim_pulse_width_dma_irq_handler(tim_pulse_width_device + PWTD_TIM4); + rt_interrupt_leave(); +} +#endif + + +#ifdef BSP_USING_TIM8_PULSE_WIDTH +// TIM8 DMA中断处理函数 +void DMA2_Channel3_IRQHandler(void) +{ + rt_interrupt_enter(); + n32_tim_pulse_width_dma_irq_handler(tim_pulse_width_device + PWTD_TIM8); + rt_interrupt_leave(); +} +#endif + +static int rt_hw_tim1_pulse_width_init(void) +{ + + for (int i = 0; i < PWTD_NUM; i++) + { + n32_tim_pulse_width_register(tim_pulse_width_device + i, + tim_pulse_width_config + i); + LOG_I("register pwm width test %s info :%s", tim_pulse_width_config[i].name,tim_pulse_width_config[i].info); + } + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_tim1_pulse_width_init); + +#ifdef BSP_USING_PULSE_WIDTH_DEMO +/** + * @file drv_tim_pulse_width.c + * @brief + * @author jiache (wanghuan3037@fiberhome.com) + * @version 1.0 + * @date 2025-12-02 + * + * 输入pwm的最大宽度测量范围 455100ns(0xfffc),最小的脉宽可以测量到28ns（0x02）， + *这个驱动必须注册一个回调函数，用于每一个脉宽数据的处理，回调函数执行与高优先级线程中 + * @copyright Copyright (c) 2025 58 + * + */ +#include +#include +#include "drv_tim_pulse_width.h" +#include +#define DEV_NAME "pulse4" + +static rt_device_t pwm_input_dev = RT_NULL; +static rt_uint32_t total_pulse_count = 0, period_ns; +static rt_uint32_t cnt = 0; +rt_thread_t thread; // 线程 +rt_mailbox_t box; // 接收dma传输完成的信号 +static void pulse_callback(rt_device_t dev, rt_uint32_t pulse_width_us, rt_uint32_t period_us, rt_uint32_t status) +{ + if (status) + { + rt_mb_send_wait(box, cnt, 0); + cnt = 0; + } + else + { + cnt++; + total_pulse_count = pulse_width_us; + period_ns = period_us; + } +} + +void timeout_1S(void *parameter) +{ + + rt_device_t pwm_dev = (rt_device_t)parameter; + rt_device_control(pwm_input_dev, RT_DEVICE_CTRL_PULSE_WIDTH_TEST_TIMEOUT, 0); +} + +/* 线程 1 的入口函数 */ +static void thread_entry_data(void *parameter) +{ + rt_base_t val = 0; + rt_uint32_t len = 0; + rt_uint32_t data_size = 0; + rt_uint32_t data_start = 0; + struct n32_tim_pulse_width_device *device = (struct n32_tim_pulse_width_device *)parameter; + while (1) + { + if (RT_EOK == rt_mb_recv(box, &val, RT_WAITING_FOREVER)) + { + + LOG_I("CNT %d width %d period_ns %d(%04x)", val, total_pulse_count, period_ns, period_ns); + } + } +} + +/* PWM输入测试命令 */ +static int pwm_input_test(void) +{ + + /* 查找设备 */ + pwm_input_dev = rt_device_find(DEV_NAME); + + if (pwm_input_dev == RT_NULL) + { + LOG_W("Device %s not found!", DEV_NAME); + return -1; + } + + /* 设置回调函数 */ + // rt_device_set_rx_indicate(pwm_input_dev,pulse_callback); + rt_device_control(pwm_input_dev, RT_DEVICE_CTRL_PULSE_WIDTH_SET_CALLBACK, pulse_callback); + + /* 打开设备 */ + if (rt_device_open(pwm_input_dev, RT_DEVICE_OFLAG_RDONLY) != RT_EOK) + { + LOG_W("Failed to open device %s", DEV_NAME); + return -1; + } + + LOG_I("PWM input test started on %s", DEV_NAME); + + rt_timer_t timer = rt_timer_create("pulse", timeout_1S, pwm_input_dev, 1000, RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_HARD_TIMER); + + rt_timer_start(timer); + + // 接收dma的传输结束信号 + box = rt_mb_create("pulse", 10, RT_IPC_FLAG_FIFO); + RT_ASSERT(box != RT_NULL); + /* 创建线程 1，名称是 thread1，入口是 thread1_entry*/ + thread = rt_thread_create("pulseapp", + thread_entry_data, NULL, + 512, + 25, 20); + /* 如果获得线程控制块，启动这个线程 */ + if (thread != RT_NULL) + rt_thread_startup(thread); + + return 0; +} +INIT_APP_EXPORT(pwm_input_test); +// MSH_CMD_EXPORT(pwm_input_test, PWM input mode test); + +#endif/*BSP_USING_PULSE_WIDTH_DEMO*/ + +#endif /*BSP_USING_TIM_PULSE_WIDTH*/ diff --git a/bsp/n32/libraries/n32_drivers/drv_tim_pulse_width.h b/bsp/n32/libraries/n32_drivers/drv_tim_pulse_width.h new file mode 100644 index 00000000000..cca51f6e313 --- /dev/null +++ b/bsp/n32/libraries/n32_drivers/drv_tim_pulse_width.h @@ -0,0 +1,13 @@ +#ifndef __DRV_TIM_PULSE_WIDTH_H__ +#define __DRV_TIM_PULSE_WIDTH_H__ + + +#include +#include + +typedef void (*fun_pulse_callback)(rt_device_t dev, rt_uint32_t pulse_width_us, rt_uint32_t period_us,rt_uint32_t status); + + +#endif /* __DRV_TIM_PULSE_WIDTH_H__ */ + + diff --git a/bsp/n32/libraries/n32_drivers/drv_usart.c b/bsp/n32/libraries/n32_drivers/drv_usart.c index c14de578ad6..eabbbfc0c00 100644 --- a/bsp/n32/libraries/n32_drivers/drv_usart.c +++ b/bsp/n32/libraries/n32_drivers/drv_usart.c @@ -6,6 +6,15 @@ * Change Logs: * Date Author Notes * 2022-10-19 Nations first version + * + * * + * 2025-12-12 + 1.在N32L40x的平台添加了串口1-串口5的Kconfig串口配置 + + + * 2025-12-18 + 1.在N32G457的平台添加了串口1-串口7的Kconfig串口配置 + */ #include @@ -27,6 +36,7 @@ struct n32_uart USART_Module* uart_periph; //Todo: 3bits IRQn_Type irqn; //Todo: 7bits uint32_t per_clk; //Todo: 5bits + uint32_t remap; //N32G45X设备gpio的映射 uint32_t tx_gpio_clk; //Todo: 5bits uint32_t rx_gpio_clk; //Todo: 5bits GPIO_Module* tx_port; //Todo: 4bits @@ -174,15 +184,39 @@ void UART7_IRQHandler(void) static const struct n32_uart uarts[] = { #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) +#define UART_SOC_N32G45X_CFG_START #ifdef BSP_USING_USART1 { USART1, // uart peripheral index USART1_IRQn, // uart iqrn - RCC_APB2_PERIPH_USART1, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOA, // periph clock, tx gpio clock, rt gpio clock - GPIOA, GPIO_Mode_AF_PP, GPIO_PIN_9, // tx port, tx alternate, tx pin - GPIOA, GPIO_Mode_IN_FLOATING, GPIO_PIN_10, // rx port, rx alternate, rx pin + RCC_APB2_PERIPH_USART1, + #ifdef UART1_PA9_PA10 + 0, + RCC_APB2_PERIPH_GPIOA, + RCC_APB2_PERIPH_GPIOA, // periph clock, tx gpio clock, rt gpio clock + GPIOA, + GPIO_Mode_AF_PP, + GPIO_PIN_9, // tx port, tx alternate, tx pin + GPIOA, + GPIO_Mode_IN_FLOATING, + GPIO_PIN_10, // rx port, rx alternate, rx pin + &serial1, + "usart1", + #endif /*UART1_PA9_PA10*/ + + #ifdef UART1_PB6_PB7 + GPIO_RMP_USART1,/*io映射配置*/ + RCC_APB2_PERIPH_GPIOB, + RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock + GPIOB, + GPIO_Mode_AF_PP, + GPIO_PIN_6, // tx port, tx alternate, tx pin + GPIOB, + GPIO_Mode_IN_FLOATING, + GPIO_PIN_7, // rx port, rx alternate, rx pin &serial1, "usart1", + #endif /*UART1_PB6_PB7*/ }, #endif @@ -190,11 +224,62 @@ static const struct n32_uart uarts[] = { { USART2, // uart peripheral index USART2_IRQn, // uart iqrn - RCC_APB1_PERIPH_USART2, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOA, // periph clock, tx gpio clock, rt gpio clock - GPIOA, GPIO_Mode_AF_PP, GPIO_PIN_2, // tx port, tx alternate, tx pin - GPIOA, GPIO_Mode_IN_FLOATING, GPIO_PIN_3, // rx port, rx alternate, rx pin + RCC_APB1_PERIPH_USART2, + #ifdef UART2_PA2_PA3 + 0, + RCC_APB2_PERIPH_GPIOA, + RCC_APB2_PERIPH_GPIOA, // periph clock, tx gpio clock, rt gpio clock + GPIOA, + GPIO_Mode_AF_PP, + GPIO_PIN_2, // tx port, tx alternate, tx pin + GPIOA, + GPIO_Mode_IN_FLOATING, + GPIO_PIN_3, // rx port, rx alternate, rx pin + &serial2, + "usart2", + #endif /*UART2_PA2_PA3*/ + + #ifdef UART2_PD5_PD6 + GPIO_RMP1_USART2, + RCC_APB2_PERIPH_GPIOD, + RCC_APB2_PERIPH_GPIOD, // periph clock, tx gpio clock, rt gpio clock + GPIOD, + GPIO_Mode_AF_PP, + GPIO_PIN_5, // tx port, tx alternate, tx pin + GPIOD, + GPIO_Mode_IN_FLOATING, + GPIO_PIN_6, // rx port, rx alternate, rx pin &serial2, "usart2", + #endif /*UART2_PD5_PD6*/ + + #ifdef UART2_PC8_PC9 + GPIO_RMP2_USART2, + RCC_APB2_PERIPH_GPIOC, + RCC_APB2_PERIPH_GPIOC, // periph clock, tx gpio clock, rt gpio clock + GPIOC, + GPIO_Mode_AF_PP, + GPIO_PIN_8, // tx port, tx alternate, tx pin + GPIOC, + GPIO_Mode_IN_FLOATING, + GPIO_PIN_9, // rx port, rx alternate, rx pin + &serial2, + "usart2", + #endif /*UART2_PC8_PC9*/ + + #ifdef UART2_PB4_PB5 + GPIO_RMP3_USART2, + RCC_APB2_PERIPH_GPIOB, + RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock + GPIOB, + GPIO_Mode_AF_PP, + GPIO_PIN_4, // tx port, tx alternate, tx pin + GPIOB, + GPIO_Mode_IN_FLOATING, + GPIO_PIN_5, // rx port, rx alternate, rx pin + &serial2, + "usart2", + #endif /*UART2_PB4_PB5*/ }, #endif @@ -202,23 +287,79 @@ static const struct n32_uart uarts[] = { { USART3, // uart peripheral index USART3_IRQn, // uart iqrn - RCC_APB1_PERIPH_USART3, RCC_APB2_PERIPH_GPIOB, RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock + RCC_APB1_PERIPH_USART3, + #ifdef UART3_PB10_PB11 + 0, + RCC_APB2_PERIPH_GPIOB, + RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock GPIOB, GPIO_Mode_AF_PP, GPIO_PIN_10, // tx port, tx alternate, tx pin GPIOB, GPIO_Mode_IN_FLOATING, GPIO_PIN_11, // rx port, rx alternate, rx pin &serial3, "usart3", + #endif /*UART3_PB10_PB11*/ + + #ifdef UART3_PC10_PC11 + GPIO_PART_RMP_USART3, + RCC_APB2_PERIPH_GPIOC, + RCC_APB2_PERIPH_GPIOC, // periph clock, tx gpio clock, rt gpio clock + GPIOC, GPIO_Mode_AF_PP, GPIO_PIN_10, // tx port, tx alternate, tx pin + GPIOC, GPIO_Mode_IN_FLOATING, GPIO_PIN_11, // rx port, rx alternate, rx pin + &serial3, + "usart3", + #endif /*UART3_PC10_PC11*/ + + #ifdef UART3_PD8_PD9 + GPIO_ALL_RMP_USART3, + RCC_APB2_PERIPH_GPIOD, + RCC_APB2_PERIPH_GPIOD, // periph clock, tx gpio clock, rt gpio clock + GPIOD, GPIO_Mode_AF_PP, GPIO_PIN_8, // tx port, tx alternate, tx pin + GPIOD, GPIO_Mode_IN_FLOATING, GPIO_PIN_9, // rx port, rx alternate, rx pin + &serial3, + "usart3", + #endif /*UART3_PD8_PD9*/ }, #endif #ifdef BSP_USING_UART4 { - UART4, // uart peripheral index + UART4, // uart peripheral index UART4_IRQn, // uart iqrn - RCC_APB1_PERIPH_UART4, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOA, // periph clock, tx gpio clock, rt gpio clock + RCC_APB1_PERIPH_UART4, + #ifdef UART4_PC10_PC11 + 0, + RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOC, // periph clock, tx gpio clock, rt gpio clock + GPIOC, GPIO_Mode_AF_PP, GPIO_PIN_10, // tx port, tx alternate, tx pin + GPIOC, GPIO_Mode_IN_FLOATING, GPIO_PIN_11, // rx port, rx alternate, rx pin + &serial4, + "uart4", + #endif /*UART4_PC10_PC11*/ + + #ifdef UART4_PB2_PE7 + GPIO_RMP1_UART4, + RCC_APB2_PERIPH_GPIOB, RCC_APB2_PERIPH_GPIOE, // periph clock, tx gpio clock, rt gpio clock + GPIOB, GPIO_Mode_AF_PP, GPIO_PIN_2, // tx port, tx alternate, tx pin + GPIOE, GPIO_Mode_IN_FLOATING, GPIO_PIN_7, // rx port, rx alternate, rx pin + &serial4, + "uart4", + #endif /*UART4_PB2_PE7*/ + + #ifdef UART4_PA13_PA14 + GPIO_RMP2_UART4, + RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOA, // periph clock, tx gpio clock, rt gpio clock GPIOA, GPIO_Mode_AF_PP, GPIO_PIN_13, // tx port, tx alternate, tx pin GPIOA, GPIO_Mode_IN_FLOATING, GPIO_PIN_14, // rx port, rx alternate, rx pin &serial4, "uart4", + #endif /*UART4_PA13_PA14*/ + + #ifdef UART4_PD0_PD1 + GPIO_RMP2_UART4, + RCC_APB2_PERIPH_GPIOD, RCC_APB2_PERIPH_GPIOD, // periph clock, tx gpio clock, rt gpio clock + GPIOD, GPIO_Mode_AF_PP, GPIO_PIN_0, // tx port, tx alternate, tx pin + GPIOD, GPIO_Mode_IN_FLOATING, GPIO_PIN_1, // rx port, rx alternate, rx pin + &serial4, + "uart4", + #endif /*UART4_PD0_PD1*/ }, #endif @@ -226,11 +367,43 @@ static const struct n32_uart uarts[] = { { UART5, // uart peripheral index UART5_IRQn, // uart iqrn - RCC_APB1_PERIPH_UART5, RCC_APB2_PERIPH_GPIOB, RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock + RCC_APB1_PERIPH_UART5, + #ifdef UART5_PC12_PD2 + 0, + RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOD, // periph clock, tx gpio clock, rt gpio clock + GPIOC, GPIO_Mode_AF_PP, GPIO_PIN_12, // tx port, tx alternate, tx pin + GPIOD, GPIO_Mode_IN_FLOATING, GPIO_PIN_2, // rx port, rx alternate, rx pin + &serial5, + "uart5", + #endif /*UART5_PC12_PD2*/ + + #ifdef UART5_PB13_PB14 + GPIO_RMP1_UART5, + RCC_APB2_PERIPH_GPIOB, RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock GPIOB, GPIO_Mode_AF_PP, GPIO_PIN_13, // tx port, tx alternate, tx pin GPIOB, GPIO_Mode_IN_FLOATING, GPIO_PIN_14, // rx port, rx alternate, rx pin &serial5, "uart5", + #endif /*UART5_PB13_PB14*/ + + #ifdef UART5_PE8_PE9 + GPIO_RMP2_UART5, + RCC_APB2_PERIPH_GPIOE, RCC_APB2_PERIPH_GPIOE, // periph clock, tx gpio clock, rt gpio clock + GPIOE, GPIO_Mode_AF_PP, GPIO_PIN_8, // tx port, tx alternate, tx pin + GPIOE, GPIO_Mode_IN_FLOATING, GPIO_PIN_9, // rx port, rx alternate, rx pin + &serial5, + "uart5", + #endif /*UART5_PE8_PE9*/ + + #ifdef UART5_PB8_PB9 + GPIO_RMP3_UART5, + RCC_APB2_PERIPH_GPIOB, RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock + GPIOB, GPIO_Mode_AF_PP, GPIO_PIN_8, // tx port, tx alternate, tx pin + GPIOB, GPIO_Mode_IN_FLOATING, GPIO_PIN_9, // rx port, rx alternate, rx pin + &serial5, + "uart5", + #endif /*UART5_PB8_PB9*/ + }, #endif @@ -238,11 +411,33 @@ static const struct n32_uart uarts[] = { { UART6, // uart peripheral index UART6_IRQn, // uart iqrn - RCC_APB2_PERIPH_UART6, RCC_APB2_PERIPH_GPIOB, RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock + RCC_APB2_PERIPH_UART6, + #ifdef UART6_PB0_PB1 + GPIO_RMP3_UART6, + RCC_APB2_PERIPH_GPIOB, RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock GPIOB, GPIO_Mode_AF_PP, GPIO_PIN_0, // tx port, tx alternate, tx pin GPIOB, GPIO_Mode_IN_FLOATING, GPIO_PIN_1, // rx port, rx alternate, rx pin &serial6, "uart6", + #endif /*UART6_PB0_PB1*/ + + #ifdef UART6_PC0_PC1 + GPIO_RMP2_UART6, + RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOC, // periph clock, tx gpio clock, rt gpio clock + GPIOC, GPIO_Mode_AF_PP, GPIO_PIN_0, // tx port, tx alternate, tx pin + GPIOC, GPIO_Mode_IN_FLOATING, GPIO_PIN_1, // rx port, rx alternate, rx pin + &serial6, + "uart6", + #endif /*UART6_PC0_PC1*/ + + #ifdef UART6_PE2_PE3 + 0, + RCC_APB2_PERIPH_GPIOE, RCC_APB2_PERIPH_GPIOE, // periph clock, tx gpio clock, rt gpio clock + GPIOE, GPIO_Mode_AF_PP, GPIO_PIN_1, // tx port, tx alternate, tx pin + GPIOE, GPIO_Mode_IN_FLOATING, GPIO_PIN_1, // rx port, rx alternate, rx pin + &serial6, + "uart6", + #endif /*UART6_PE2_PE3*/ }, #endif @@ -250,76 +445,248 @@ static const struct n32_uart uarts[] = { { UART7, // uart peripheral index UART7_IRQn, // uart iqrn - RCC_APB2_PERIPH_UART7, RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOC, // periph clock, tx gpio clock, rt gpio clock + RCC_APB2_PERIPH_UART7, + #ifdef UART7_PC4_PC5 + 0, + RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOC, // periph clock, tx gpio clock, rt gpio clock + GPIOC, GPIO_Mode_AF_PP, GPIO_PIN_4, // tx port, tx alternate, tx pin + GPIOC, GPIO_Mode_IN_FLOATING, GPIO_PIN_5, // rx port, rx alternate, rx pin + &serial7, + "uart7", + #endif /*UART7_PC4_PC5*/ + + #ifdef UART7_PC2_PC3 + GPIO_RMP1_UART7, + RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOC, // periph clock, tx gpio clock, rt gpio clock GPIOC, GPIO_Mode_AF_PP, GPIO_PIN_2, // tx port, tx alternate, tx pin GPIOC, GPIO_Mode_IN_FLOATING, GPIO_PIN_3, // rx port, rx alternate, rx pin &serial7, "uart7", + #endif /*UART7_PC2_PC3*/ + + #ifdef UART7_PG0_PG1 + GPIO_RMP3_UART7, + RCC_APB2_PERIPH_GPIOG, RCC_APB2_PERIPH_GPIOG, // periph clock, tx gpio clock, rt gpio clock + GPIOG, GPIO_Mode_AF_PP, GPIO_PIN_0, // tx port, tx alternate, tx pin + GPIOG, GPIO_Mode_IN_FLOATING, GPIO_PIN_1, // rx port, rx alternate, rx pin + &serial7, + "uart7", + #endif /*UART7_PG0_PG1*/ }, #endif #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) - +#define UART_SOC_N32L43X_CFG_START #ifdef BSP_USING_USART1 { - USART1, // uart peripheral index - USART1_IRQn, // uart iqrn - RCC_APB2_PERIPH_USART1, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOA, // periph clock, tx gpio clock, rt gpio clock - GPIOA, GPIO_AF4_USART1, GPIO_PIN_9, // tx port, tx alternate, tx pin - GPIOA, GPIO_AF4_USART1, GPIO_PIN_10, // rx port, rx alternate, rx pin + USART1, // uart peripheral index + USART1_IRQn, // uart iqrn + RCC_APB2_PERIPH_USART1, +#ifdef UART1_TX_PA4_PA5 + RCC_APB2_PERIPH_GPIOA, + RCC_APB2_PERIPH_GPIOA, // periph clock, tx gpio clock, rt gpio clock + GPIOA, + GPIO_AF1_USART1, + GPIO_PIN_4, // tx port, tx alternate, tx pin + GPIOA, + GPIO_AF4_USART1, + GPIO_PIN_5, // rx port, rx alternate, rx pin &serial1, "usart1", +#endif +#ifdef UART1_PA9_PA10 + RCC_APB2_PERIPH_GPIOA, + RCC_APB2_PERIPH_GPIOA, // periph clock, tx gpio clock, rt gpio clock + GPIOA, + GPIO_AF4_USART1, + GPIO_PIN_9, // tx port, tx alternate, tx pin + GPIOA, + GPIO_AF4_USART1, + GPIO_PIN_10, // rx port, rx alternate, rx pin + &serial1, + "usart1", +#endif +#ifdef UART1_PB6_PB7 + RCC_APB2_PERIPH_GPIOB, + RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock + GPIOB, + GPIO_AF0_USART1, + GPIO_PIN_6, // tx port, tx alternate, tx pin + GPIOB, + GPIO_AF0_USART1, + GPIO_PIN_7, // rx port, rx alternate, rx pin + &serial1, + "usart1", +#endif + }, #endif #ifdef BSP_USING_USART2 { - USART2, // uart peripheral index - USART2_IRQn, // uart iqrn - RCC_APB1_PERIPH_USART2, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOA, // periph clock, tx gpio clock, rt gpio clock - GPIOA, GPIO_AF4_USART2, GPIO_PIN_2, // tx port, tx alternate, tx pin - GPIOA, GPIO_AF4_USART2, GPIO_PIN_3, // rx port, rx alternate, rx pin + USART2, // uart peripheral index + USART2_IRQn, // uart iqrn + RCC_APB1_PERIPH_USART2, +#ifdef UART2_TX_PA2_RX_PA3 + RCC_APB2_PERIPH_GPIOA, + RCC_APB2_PERIPH_GPIOA, // periph clock, tx gpio clock, rt gpio clock + GPIOA, + GPIO_AF4_USART2, + GPIO_PIN_2, // tx port, tx alternate, tx pin + GPIOA, + GPIO_AF4_USART2, + GPIO_PIN_3, // rx port, rx alternate, rx pin + &serial2, + "usart2", +#endif /*UART2_TX_PA2_RX_PA3*/ +#ifdef UART2_TX_PB4_RX_PB5 + RCC_APB2_PERIPH_GPIOB, + RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock + GPIOB, + GPIO_AF4_USART2, + GPIO_PIN_4, // tx port, tx alternate, tx pin + GPIOB, + GPIO_AF6_USART2, + GPIO_PIN_5, // rx port, rx alternate, rx pin &serial2, "usart2", +#endif /*UART2_TX_PB4_RX_PB5*/ }, #endif #ifdef BSP_USING_USART3 { - USART3, // uart peripheral index - USART3_IRQn, // uart iqrn - RCC_APB1_PERIPH_USART3, RCC_APB2_PERIPH_GPIOB, RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock - GPIOB, GPIO_AF0_USART3, GPIO_PIN_10, // tx port, tx alternate, tx pin - GPIOB, GPIO_AF5_USART3, GPIO_PIN_11, // rx port, rx alternate, rx pin + USART3, // uart peripheral index + USART3_IRQn, // uart iqrn + RCC_APB1_PERIPH_USART3, +#ifdef UART3_TX_PB10_RX_B11 + RCC_APB2_PERIPH_GPIOB, + RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock + GPIOB, + GPIO_AF0_USART3, + GPIO_PIN_10, // tx port, tx alternate, tx pin + GPIOB, + GPIO_AF5_USART3, + GPIO_PIN_11, // rx port, rx alternate, rx pin + &serial3, + "usart3", +#endif /*UART3_TX_PB10_RX_B11*/ +#ifdef UART3_TX_PC10_RX_PC11 + RCC_APB2_PERIPH_GPIOC, + RCC_APB2_PERIPH_GPIOC, // periph clock, tx gpio clock, rt gpio clock + GPIOC, + GPIO_AF5_USART3, + GPIO_PIN_10, // tx port, tx alternate, tx pin + GPIOC, + GPIO_AF5_USART3, + GPIO_PIN_11, // rx port, rx alternate, rx pin &serial3, "usart3", +#endif /*UART3_TX_PC10_RX_PC11*/ }, #endif #ifdef BSP_USING_UART4 { - UART4, // uart peripheral index - UART4_IRQn, // uart iqrn - RCC_APB2_PERIPH_UART4, RCC_APB2_PERIPH_GPIOB, RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock - GPIOB, GPIO_AF6_UART4, GPIO_PIN_0, // tx port, tx alternate, tx pin - GPIOB, GPIO_AF6_UART4, GPIO_PIN_1, // rx port, rx alternate, rx pin + UART4, // uart peripheral index + UART4_IRQn, // uart iqrn + RCC_APB2_PERIPH_UART4, +#ifdef UART4_TX_PB0_RX_PB1 + RCC_APB2_PERIPH_GPIOB, + RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock + GPIOB, + GPIO_AF6_UART4, + GPIO_PIN_0, // tx port, tx alternate, tx pin + GPIOB, + GPIO_AF6_UART4, + GPIO_PIN_1, // rx port, rx alternate, rx pin &serial4, "uart4", +#endif /*UART4_TX_PB0_RX_PB1*/ +#ifdef UART4_TX_PB14_RX_PB15 + RCC_APB2_PERIPH_GPIOB, + RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock + GPIOB, + GPIO_AF6_UART4, + GPIO_PIN_14, // tx port, tx alternate, tx pin + GPIOB, + GPIO_AF6_UART4, + GPIO_PIN_15, // rx port, rx alternate, rx pin + &serial4, + "uart4", +#endif /*UART4_TX_PB14_RX_PB15*/ +#ifdef UART4_TX_PC10_RX_PC11 + RCC_APB2_PERIPH_GPIOC, + RCC_APB2_PERIPH_GPIOC, // periph clock, tx gpio clock, rt gpio clock + GPIOC, + GPIO_AF6_UART4, + GPIO_PIN_10, // tx port, tx alternate, tx pin + GPIOC, + GPIO_AF6_UART4, + GPIO_PIN_11, // rx port, rx alternate, rx pin + &serial4, + "uart4", +#endif /*UART4_TX_PC10_RX_PC11*/ +#ifdef UART4_TX_PD13_RX_PD12 + RCC_APB2_PERIPH_GPIOD, + RCC_APB2_PERIPH_GPIOD, // periph clock, tx gpio clock, rt gpio clock + GPIOD, + GPIO_AF6_UART4, + GPIO_PIN_13, // tx port, tx alternate, tx pin + GPIOD, + GPIO_AF6_UART4, + GPIO_PIN_12, // rx port, rx alternate, rx pin + &serial4, + "uart4", +#endif /*UART4_TX_PD13_RX_PD12*/ }, #endif #ifdef BSP_USING_UART5 { - UART5, // uart peripheral index - UART5_IRQn, // uart iqrn - RCC_APB2_PERIPH_UART5, RCC_APB2_PERIPH_GPIOB, RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock - GPIOB, GPIO_AF6_UART5, GPIO_PIN_8, // tx port, tx alternate, tx pin - GPIOB, GPIO_AF6_UART5, GPIO_PIN_9, // rx port, rx alternate, rx pin + UART5, // uart peripheral index + UART5_IRQn, // uart iqrn + RCC_APB2_PERIPH_UART5, +#ifdef UART5_TX_PB4_RX_PB5 + RCC_APB2_PERIPH_GPIOB, + RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock + GPIOB, + GPIO_AF6_UART5, + GPIO_PIN_4, // tx port, tx alternate, tx pin + GPIOB, + GPIO_AF6_UART5, + GPIO_PIN_5, // rx port, rx alternate, rx pin + &serial5, + "uart5", +#endif /*UART5_TX_PB4_RX_PB5*/ +#ifdef UART5_TX_PB8_RX_PB9 + RCC_APB2_PERIPH_GPIOB, + RCC_APB2_PERIPH_GPIOB, // periph clock, tx gpio clock, rt gpio clock + GPIOB, + GPIO_AF6_UART5, + GPIO_PIN_8, // tx port, tx alternate, tx pin + GPIOB, + GPIO_AF6_UART5, + GPIO_PIN_9, // rx port, rx alternate, rx pin + &serial5, + "uart5", +#endif /*UART5_TX_PB8_RX_PB9*/ +#ifdef UART5_TX_PC12_RX_PD2 + RCC_APB2_PERIPH_GPIOC, + RCC_APB2_PERIPH_GPIOD, // periph clock, tx gpio clock, rt gpio clock + GPIOC, + GPIO_AF6_UART5, + GPIO_PIN_12, // tx port, tx alternate, tx pin + GPIOD, + GPIO_AF6_UART5, + GPIO_PIN_2, // rx port, rx alternate, rx pin &serial5, "uart5", +#endif /*UART5_TX_PC12_RX_PD2*/ }, #endif #endif + }; /** @@ -347,23 +714,11 @@ void n32_uart_gpio_init(struct n32_uart *uart, struct serial_configure *cfg) { RCC_EnableAPB1PeriphClk(uart->per_clk, ENABLE); } - -#ifdef BSP_USING_UART4 - GPIO_ConfigPinRemap(GPIO_RMP_SW_JTAG_DISABLE, ENABLE); - GPIO_ConfigPinRemap(GPIO_RMP2_UART4, ENABLE); -#endif /* BSP_USING_UART4 */ - -#ifdef BSP_USING_UART5 - GPIO_ConfigPinRemap(GPIO_RMP1_UART5, ENABLE); -#endif /* BSP_USING_UART5 */ - -#ifdef BSP_USING_UART6 - GPIO_ConfigPinRemap(GPIO_RMP3_UART6, ENABLE); -#endif /* BSP_USING_UART6 */ - -#ifdef BSP_USING_UART7 - GPIO_ConfigPinRemap(GPIO_RMP1_UART7, ENABLE); -#endif /* BSP_USING_UART7 */ + //io 映射 + if(uart->remap) + { + GPIO_ConfigPinRemap(uart->remap, ENABLE); + } GPIO_InitStruct(&GPIO_InitStructure); diff --git a/bsp/n32/libraries/n32_drivers/tim_etr_cnt.c b/bsp/n32/libraries/n32_drivers/tim_etr_cnt.c new file mode 100644 index 00000000000..3fb2522c410 --- /dev/null +++ b/bsp/n32/libraries/n32_drivers/tim_etr_cnt.c @@ -0,0 +1,629 @@ +/** + * @file tim_etr_cnt.c + * @brief + * @author jiache (wanghuan3037@fiberhome.com) + * @version 1.0 + * @date 2025-11-28 + * 2025-11-28 + * 1.引脚重映射; + * 2.支持了RT_USING_DEVICE_OPS的定义, + * 3.增加了N457支持的所有定时器外部ETR计数驱动 + * 4.日志输出的标签设置 + * 5.Kconfig添加了引脚选择 + * 6.这里添加了依赖RT_USING_HWTIMER + * 7.测试了默认和复用引脚均计数OK + * 202512-2 + * 1.将定时器的时钟和gpio时钟统一放在drv_base.c中 + * 2025-11-28 + * + * 2025-12-02 + * RT_USING_DEVICE_OPS 宏的ops没有添加ops条件编译 + 2025-12-06 + 1.修改了在N32L406的兼容驱动代码 + 2.经测试TIM1的ETR PA12脉冲采样正常.经过测试100K可以采集到，1M方法采集不了 + 3.经过测试TIM2 PA0用于外部ETR计数，正常，测试OK，100K的脉冲测量不可行，10K可行，20K正常，25K可以 + 4.使用TIM_ConfigExtClkMode1和TIM_ConfigExtClkMode2就可以实现外部时钟的计数配置 + 5.测试错误：：使用外部计数TIM2,ETR PA0测试发现25K,20K，16K，12K在N32L406计数采集OK，50K严重丢数，测试不对，PA0我的看法板连接了按键，按键有一个滤波电容产生了计数的影响。 + 5.在N32L406计数采集，使用外部计数TIM1,ETR PA12测试发现100K,1MHz，2MHz，10MOK，还是高级定时器牛逼 + 6.使用外部计数TIM2,ETR PA15测试,100K，1M（测试OK误差2个计数），10M(可以测，但是，多了666K)在N32L406计数采集OK + 7.使用外部计数TIM9,ETR PB测试,100Kok + 8.经过测试TIM_ConfigExtClkMode2的滤波设置为1时m,在测试10M时，没有计数 + * @copyright Copyright (c) 2025 58 + * + */ +#include "tim_etr_cnt.h" +#ifdef BSP_USING_TIM_ETR_CNT + +#include "board.h" +#include +#include + +#define DBG_TAG "ETR" +#ifdef BSP_USING_TIM_ETR_CNT_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif +#include +#include "drv_base.h" +typedef struct +{ + struct rt_device parent; + GPIO_Module *gpio_grp; // gpio分组 + uint16_t pin; // gpio pin + TIM_Module *time; // 定时器 + uint32_t irq_up; // 定时器溢出中断 + // uint32_t gpio_rcc; // gpio时钟 + volatile uint32_t over; // 溢出次数 + uint32_t ioremap; // gpio重映射 + char name[RT_NAME_MAX]; + char *info_str; +} time_counter_etr_t; + +static time_counter_etr_t s_times_count_etr[] = { + +#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) +#define N32G45X_CONFIG +#ifdef BSP_USING_TIM1_ETR_CNT +#ifdef TIM1_ETR_PIN_PA12 + { + .gpio_grp = GPIOA, + .pin = GPIO_PIN_12, + .ioremap = 0, /* [PA12=(0,1,2) PE7=(3)]*/ + .time = TIM1, + // .gpio_rcc = RCC_APB2_PERIPH_GPIOA, + .irq_up = TIM1_UP_IRQn, + .info_str = "TIM1 PA12", + }, +#endif +#ifdef TIM1_ETR_PIN_PE7 + { + .gpio_grp = GPIOE, + .pin = GPIO_PIN_7, + .ioremap = GPIO_ALL_RMP_TIM1, /* [PA12=(0,1,2) PE7=(3)]*/ + .time = TIM1, + // .gpio_rcc = RCC_APB2_PERIPH_GPIOE, + .irq_up = TIM1_UP_IRQn, + .info_str = "TIM1 PE7", + + }, +#endif +#endif + +#ifdef BSP_USING_TIM2_ETR_CNT +#ifdef TIM2_ETR_PIN_PA0 + { + .gpio_grp = GPIOA, + .pin = GPIO_PIN_0, + .ioremap = 0, /*[PA0=0;PA15=(1,3);PA0=2;]*/ + .time = TIM2, + // .gpio_rcc = RCC_APB2_PERIPH_GPIOA, + .irq_up = TIM2_IRQn, + .info_str = "TIM2 PA0", + }, +#endif /*TIM2_ETR_PIN_PA0*/ +#ifdef TIM2_ETR_PIN_PA15 + { + .gpio_grp = GPIOA, + .pin = GPIO_PIN_15, + .ioremap = GPIO_PartialRemap1_TIM2, /*[PA0=0;PA15=(1,3);PA0=2;]*/ + .time = TIM2, + // .gpio_rcc = RCC_APB2_PERIPH_GPIOA, + .irq_up = TIM2_IRQn, + .info_str = "TIM2 PA15", + }, +#endif /*TIM2_ETR_PIN_PA15*/ +#endif /*BSP_USING_TIM2_ETR_CNT*/ + +#ifdef BSP_USING_TIM3_ETR_CNT + { + .gpio_grp = GPIOD, + .pin = GPIO_PIN_2, + .ioremap = 0, /*olny PD2*/ + .time = TIM3, + // .gpio_rcc = RCC_APB2_PERIPH_GPIOD, + .irq_up = TIM3_IRQn, + .info_str = "TIM3 PD2", + }, +#endif + +#ifdef BSP_USING_TIM4_ETR_CNT + { + .gpio_grp = GPIOE, + .pin = GPIO_PIN_0, + .ioremap = 0, /*olny PE0*/ + .time = TIM4, + // .gpio_rcc = RCC_APB2_PERIPH_GPIOE, + .irq_up = TIM4_IRQn, + .info_str = "TIM4 PE0", + }, +#endif + +#ifdef BSP_USING_TIM8_ETR_CNT +#ifdef TIM8_ETR_PIN_PA0 + { + .gpio_grp = GPIOA, + .pin = GPIO_PIN_0, + .ioremap = 0, /*[PA0=0,PB4=1,3]*/ + .time = TIM8, + // .gpio_rcc = RCC_APB2_PERIPH_GPIOA, + .irq_up = TIM8_UP_IRQn, + .info_str = "TIM8 PA0", + }, +#endif +#ifdef TIM8_ETR_PIN_PB4 + { + .gpio_grp = GPIOB, + .pin = GPIO_PIN_4, + .ioremap = GPIO_RMP1_TIM8, /*[PA0=0,PB4=1,3]*/ + .time = TIM8, + // .gpio_rcc = RCC_APB2_PERIPH_GPIOB, + .irq_up = TIM8_UP_IRQn, + .info_str = "TIM8 PB4", + }, +#endif +#endif +#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) +#define N32L40X_CONFIG +#ifdef BSP_USING_TIM1_ETR_CNT + { + .gpio_grp = GPIOA, + .pin = GPIO_PIN_12, + .ioremap = GPIO_AF2_TIM1, + .time = TIM1, + .irq_up = TIM1_UP_IRQn, + .info_str = "TIM1 PA12", + }, +#endif /*TIM1_ETR_PIN_PA0*/ +#ifdef BSP_USING_TIM2_ETR_CNT +#ifdef TIM2_ETR_PIN_PA0 + { + .gpio_grp = GPIOA, + .pin = GPIO_PIN_0, + .ioremap = GPIO_AF5_TIM2, + .time = TIM2, + .irq_up = TIM2_IRQn, + .info_str = "TIM2 PA0", + }, +#endif /*TIM2_ETR_PIN_PA0*/ +#ifdef TIM1_ETR_PIN_PA15 + { + .gpio_grp = GPIOA, + .pin = GPIO_PIN_15, + .ioremap = GPIO_AF2_TIM2, + .time = TIM2, + .irq_up = TIM2_IRQn, + .info_str = "TIM2 PA15", + }, +#endif /*TIM2_ETR_PIN_PA15*/ +#endif /*BSP_USING_TIM2_ETR_CNT*/ +#ifdef BSP_USING_TIM3_ETR_CNT + { + .gpio_grp = GPIOD, + .pin = GPIO_PIN_2, + .ioremap = GPIO_AF2_TIM3, + .time = TIM3, + .irq_up = TIM3_IRQn, + .info_str = "TIM3 PD2", + }, +#endif /*BSP_USING_TIM3_ETR_CNT*/ +#ifdef BSP_USING_TIM9_ETR_CNT + { + .gpio_grp = GPIOB, + .pin = GPIO_PIN_2, + .ioremap = GPIO_AF1_TIM9, + .time = TIM9, + .irq_up = TIM9_IRQn, + .info_str = "TIM9 PB2", + }, +#endif /*BSP_USING_TIM9_ETR_CNT*/ + + +#endif /*SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X*/ +}; + +// /* +// 定时器的时钟使能 +// time：定时器编号 +// */ +// void bsp_time_etr_cnt_rcc_en(TIM_Module *time) +// { + +// if (TIM1 == time) +// { +// RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_TIM1, ENABLE); +// } +// else if (TIM8 == time) +// { +// RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_TIM8, ENABLE); +// } +// else if (TIM2 == time) +// { +// RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM2, ENABLE); +// } +// else if (TIM3 == time) +// { +// RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM3, ENABLE); +// } +// else if (TIM4 == time) +// { +// RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM4, ENABLE); +// } +// else if (TIM5 == time) +// { +// RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM5, ENABLE); +// } +// else if (TIM6 == time) +// { +// RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM6, ENABLE); +// } +// LOG_D("%s", __FUNCTION__); +// } + +/** + * 中断相关初始化. + */ +static void bsp_time_count_nvic_etr_config(TIM_Module *time, uint32_t irq) +{ + NVIC_InitType NVIC_InitStructure; + + /* Enable the TIM1 global Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = irq; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + TIM_ClrIntPendingBit(time, TIM_INT_UPDATE); // 清除中断标志 + TIM_ConfigInt(time, TIM_INT_UPDATE, ENABLE); // 使能中断 + LOG_D("%s", __FUNCTION__); +} + +/** + * @brief 外部计数ETR计数配置 + * + * @param etr + */ +void bsp_time_etr_cnt_config(time_counter_etr_t *etr) +{ + // 使能 GPIOA 和 TIM1 时钟 + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA | RCC_APB2_PERIPH_TIM1, ENABLE); + // 时钟 + // RCC_EnableAPB2PeriphClk(etr->gpio_rcc, ENABLE); + n32_gpio_rcc_enable(etr->gpio_grp); + n32_time_rcc_config(etr->time); + uint32_t gpio_af; // 引脚复用功能 + GPIO_InitType GPIO_InitStructure; +#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) + + // 配置 gpio 为浮空输入，用作外部触发输入 + GPIO_InitStruct(&GPIO_InitStructure); + GPIO_InitStructure.Pin = etr->pin; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; // 配置为浮空输入GPIO_Mode_IN_FLOATING + GPIO_InitPeripheral(etr->gpio_grp, &GPIO_InitStructure); + // 引脚重映射 + if (etr->ioremap) + { + GPIO_ConfigPinRemap(etr->ioremap, ENABLE); + } + if (GPIOA == etr->gpio_grp && GPIO_PIN_15 == etr->pin) + { + GPIO_ConfigPinRemap(GPIO_RMP_SW_JTAG_SW_ENABLE, ENABLE); /*!< JTAG-DP Disabled and SW-DP Enabled */ + } +#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) + RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE); + GPIO_InitStruct(&GPIO_InitStructure); + GPIO_InitStructure.Pin = etr->pin; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Input; + GPIO_InitStructure.GPIO_Current = GPIO_DC_4mA; + GPIO_InitStructure.GPIO_Alternate = etr->ioremap; + GPIO_InitStructure.GPIO_Slew_Rate = GPIO_Slew_Rate_High; + GPIO_InitPeripheral(etr->gpio_grp, &GPIO_InitStructure); +#endif + + // 配置 TIM1 为外部触发模式，使用 PA12 作为触发源 + TIM_TimeBaseInitType TIM_TimeBaseStructure; + TIM_InitTimBaseStruct(&TIM_TimeBaseStructure); + + TIM_TimeBaseStructure.Prescaler = 0; // 不分频 + TIM_TimeBaseStructure.Period = 0xFFFF; // 最大计数值 + TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1; // 无分频 + TIM_TimeBaseStructure.CntMode = TIM_CNT_MODE_UP; // 向上计数 + TIM_InitTimeBase(etr->time, &TIM_TimeBaseStructure); + + + TIM_ConfigExtClkMode2(etr->time, TIM_EXT_TRG_PSC_OFF, TIM_EXT_TRIG_POLARITY_INVERTED, 1); + + // 配置外部触发模式，使用 ETR (PA12) 作为外部时钟源 + // TIM_ConfigExtClkMode1(etr->time, TIM_EXT_TRG_PSC_OFF, TIM_EXT_TRIG_POLARITY_NONINVERTED, 0); + + // 中断使能 + bsp_time_count_nvic_etr_config(etr->time, etr->irq_up); + + // 启动 TIM + TIM_Enable(etr->time, ENABLE); + LOG_D("%s", __FUNCTION__); +} + +/* + 获取定时器计数值 + +*/ +uint32_t bsp_timer_count_etr_get_count(time_counter_etr_t *ptime) +{ + uint32_t count; + RT_ASSERT(ptime); + + // time_counter_etr_t *ptime = s_times_count_etr + id; + count = ptime->over << 16 | TIM_GetCnt(ptime->time); // 溢出统计 + TIM_SetCnt(ptime->time, 0); // 清零 + ptime->over = 0; // 清零 + + return count; +} + +// 定时器中断集中处理函数 +static void bsp_time_count_etr_irq(time_counter_etr_t *ptime) +{ + rt_interrupt_enter(); // 进入中断 + if (TIM_GetIntStatus(ptime->time, TIM_INT_UPDATE) != RESET) + { + TIM_ClrIntPendingBit(ptime->time, TIM_INT_UPDATE); + ptime->over++; + } + rt_interrupt_leave(); // 离开中断 +} + +#ifdef BSP_USING_TIM1_ETR_CNT +void TIM1_UP_IRQHandler(void) +{ + bsp_time_count_etr_irq(s_times_count_etr + TIME1_ETR); +} +#endif + +#ifdef BSP_USING_TIM2_ETR_CNT +void TIM2_IRQHandler(void) +{ + bsp_time_count_etr_irq(s_times_count_etr + TIME2_ETR); +} +#endif + +#ifdef BSP_USING_TIM3_ETR_CNT +void TIM3_IRQHandler(void) +{ + bsp_time_count_etr_irq(s_times_count_etr + TIME3_ETR); +} +#endif + +#ifdef BSP_USING_TIM4_ETR_CNT +void TIM4_IRQHandler(void) +{ + bsp_time_count_etr_irq(s_times_count_etr + TIME4_ETR); +} +#endif + +#ifdef BSP_USING_TIM8_ETR_CNT +void TIM8_UP_IRQHandler(void) +{ + bsp_time_count_etr_irq(s_times_count_etr + TIME8_ETR); +} +#endif + #ifdef BSP_USING_TIM9_ETR_CNT +void TIM9_IRQHandler(void) +{ + bsp_time_count_etr_irq(s_times_count_etr + TIME9_ETR); +} +#endif +/**设备打开函数 */ +static rt_err_t n32_tim_etr_cnt_open(rt_device_t dev, rt_uint16_t oflag) +{ + time_counter_etr_t *device = (time_counter_etr_t *)dev; + bsp_time_etr_cnt_config(device); + LOG_I("INIT ETR %s", device->info_str); + return RT_EOK; +} +/** + * @brief 外部计数ETR计数读，同时加入了溢出统计和读取后清除计数 + * + * @param dev + * @param pos + * @param buffer + * @param size + * @return rt_ssize_t + */ +static rt_ssize_t n32_tim_etr_cnt_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + time_counter_etr_t *device = (time_counter_etr_t *)dev; + rt_uint32_t *count_buf = (rt_uint32_t *)buffer; + + *count_buf = bsp_timer_count_etr_get_count(device); + return sizeof(rt_uint32_t); +} +#ifdef RT_USING_DEVICE_OPS +/**设备操作函数接口 */ +const struct rt_device_ops ops = { + .init = RT_NULL, + .open = n32_tim_etr_cnt_open, + .close = RT_NULL, + .write = RT_NULL, + .control = RT_NULL, + .read = n32_tim_etr_cnt_read, +}; +#endif +static rt_err_t n32_tim_ert_cnt_register(time_counter_etr_t *device, + const char *name) +{ + RT_ASSERT(device != RT_NULL); + device->parent.type = RT_Device_Class_Miscellaneous; // 杂项设备 +#ifdef RT_USING_DEVICE_OPS + device->parent.ops = &ops; +#else + device->parent.init = RT_NULL; + device->parent.open = n32_tim_etr_cnt_open; + device->parent.close = RT_NULL; + device->parent.read = n32_tim_etr_cnt_read; + device->parent.write = RT_NULL; + device->parent.control = RT_NULL; + device->parent.user_data = device; +#endif + + return rt_device_register(&device->parent, name, RT_DEVICE_FLAG_RDONLY); +} + +// 一键初始化所有定时器 +int bsp_timer_count_etr_all_init(void) +{ + int num = sizeof(s_times_count_etr) / sizeof(time_counter_etr_t); + for (int i = 0; i < num; i++) + { + rt_memset(s_times_count_etr[i].name, 0, RT_NAME_MAX); + rt_snprintf(s_times_count_etr[i].name, RT_NAME_MAX, "etr%d", i); + if (RT_EOK == n32_tim_ert_cnt_register(s_times_count_etr + i, s_times_count_etr[i].name)) + { + LOG_I("regiter ETR cnt name = %s is ok time= %s", s_times_count_etr[i].name, s_times_count_etr[i].info_str); + } + else + { + LOG_W("regiter ETR cnt %s is fail time= %s ", s_times_count_etr[i].name, s_times_count_etr[i].info_str); + } + } + return 0; +} + +INIT_DEVICE_EXPORT(bsp_timer_count_etr_all_init); + +/*************************************shell 中断指令用于测试*************************************************************** */ +#ifdef RT_USING_FINSH +#include +#include +#include + +enum pwm_list_parameters +{ + ETR_LIST_PROBE = 1, + ETR_LIST_GET, +}; + +CMD_OPTIONS_STATEMENT(etr_list) + +static int etr_list(int argc, char **argv) +{ + rt_err_t result = -RT_ERROR; + char *result_str; + static rt_device_t device= RT_NULL; + int arg2 = 0; + uint32_t count = 0; + if (argc > 1) + { + if (MSH_OPT_ID_GET(etr_list) == ETR_LIST_PROBE) + { + if (argc == 3) + { + device = rt_device_find(argv[2]); + if (device) + { + rt_device_open(device, 0); + } + result_str = (device == RT_NULL) ? "failure" : "success"; + rt_kprintf("probe %s %s\n", argv[2], result_str); + return (device == RT_NULL) ? -RT_ERROR : RT_EOK; + } + else + { + rt_kprintf("etr probe - probe etr by name\n"); + return -RT_EINVAL; + } + } + else if (device == RT_NULL) + { + rt_kprintf("Please using 'etr probe ' first.\n"); + return -RT_ERROR; + } + + switch (MSH_OPT_ID_GET(etr_list)) + { + + case ETR_LIST_GET: + // arg2 = atoi(argv[2]); + rt_device_read(device, 0, &count, sizeof(count)); + // count = bsp_timer_count_etr_get_count(device); + rt_kprintf("Info of device count= [%d]:\n", count); + return RT_EOK; + + break; + + default: + goto _usage; + } + } + else + { + goto _usage; + } + return result; + +_usage: + rt_kprintf("Usage: \n"); + rt_kprintf("etr probe - probe etr by name\n"); + rt_kprintf("etr get - get etr cnt info\n"); + + result = -RT_ERROR; + return result; +} +CMD_OPTIONS_NODE_START(etr_list) +CMD_OPTIONS_NODE(ETR_LIST_PROBE, probe, probe etr name) +CMD_OPTIONS_NODE(ETR_LIST_GET, get, get etr count) +CMD_OPTIONS_NODE_END +MSH_CMD_EXPORT_ALIAS(etr_list, etr, control etr device, optenable); + +#endif /* RT_USING_FINSH */ + +#ifdef BSP_USING_TIM_ETR_CNT_DEMO // demo +#define ETR_DEV_NAME "etr2" + +static rt_mailbox_t mb_etr; +static void timout_etr(void *parameter) +{ + uint32_t count = 0; + rt_device_t etr_dev = (rt_device_t)parameter; + rt_device_read(etr_dev, 0, &count, sizeof(count)); + rt_mb_send_wait(mb_etr,count,0); +} +static void thd_entry_etr(void *parameter) +{ + uint32_t value = 0; + while (1) + { + if (RT_EOK == rt_mb_recv(mb_etr, &value, RT_WAITING_FOREVER)) + { + LOG_I("ETR CNT %d", value); + } + } +} +static int extr_app_demo(void) +{ + static rt_device_t etr_dev = RT_NULL; + etr_dev = rt_device_find(ETR_DEV_NAME); + if (etr_dev) + { + rt_device_open(etr_dev, 0); + } + else + { + LOG_W("ETR device not find"); + } + mb_etr = rt_mb_create(ETR_DEV_NAME, 5, RT_IPC_FLAG_FIFO); + RT_ASSERT(mb_etr); + rt_thread_t thd_etr = rt_thread_create(ETR_DEV_NAME, thd_entry_etr, etr_dev, 512, 20, 5); + RT_ASSERT(thd_etr); + rt_thread_startup(thd_etr); + rt_timer_t timer = rt_timer_create(ETR_DEV_NAME, timout_etr, etr_dev, 1000, RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_HARD_TIMER); + RT_ASSERT(timer); + rt_timer_start(timer); + return RT_EOK; +} +INIT_APP_EXPORT(extr_app_demo); +#endif /* BSP_USING_TIM_ETR_CNT_DEMO */ +/*************************************shell 中断指令用于测试*************************************************************** */ + +#endif /**BSP_USING_TIM_ETR_CNT */ diff --git a/bsp/n32/libraries/n32_drivers/tim_etr_cnt.h b/bsp/n32/libraries/n32_drivers/tim_etr_cnt.h new file mode 100644 index 00000000000..2fb0833e76c --- /dev/null +++ b/bsp/n32/libraries/n32_drivers/tim_etr_cnt.h @@ -0,0 +1,40 @@ +#ifndef __N32_BSP_TIME_COUNT__ETR_H__ +#define __N32_BSP_TIME_COUNT__ETR_H__ + +/* + 文件功能 +*/ +/*****************枚举定义 开始*******************/ +#include + + +typedef enum +{ +#ifdef BSP_USING_TIM1_ETR_CNT + TIME1_ETR, +#endif +#ifdef BSP_USING_TIM2_ETR_CNT + TIME2_ETR, +#endif +#ifdef BSP_USING_TIM3_ETR_CNT + TIME3_ETR, +#endif +#ifdef BSP_USING_TIM4_ETR_CNT + TIME4_ETR, +#endif + +#ifdef BSP_USING_TIM8_ETR_CNT + TIME8_ETR, +#endif +#ifdef BSP_USING_TIM9_ETR_CNT + TIME9_ETR, +#endif + + TIME_COUNT_ETR_NUM, +} em_tim_count_etr; + +/*****************枚举定义 结束*******************/ + +/*****************函数声明 结束*******************/ + +#endif diff --git a/bsp/n32/n32g457qel-stb/.config b/bsp/n32/n32g457qel-stb/.config index b8eb0410fff..ae7c843c989 100644 --- a/bsp/n32/n32g457qel-stb/.config +++ b/bsp/n32/n32g457qel-stb/.config @@ -180,7 +180,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="usart1" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -263,7 +263,7 @@ CONFIG_RT_USING_DAC=y # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set # CONFIG_RT_USING_RANDOM is not set -# CONFIG_RT_USING_PWM is not set +CONFIG_RT_USING_PWM=y # CONFIG_RT_USING_PULSE_ENCODER is not set # CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set @@ -274,6 +274,7 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y # CONFIG_RT_USING_SOFT_SPI is not set # CONFIG_RT_USING_QSPI is not set # CONFIG_RT_USING_SPI_MSD is not set @@ -368,8 +369,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Using USB legacy version # @@ -378,6 +377,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -747,6 +747,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -903,6 +904,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK # end of HAL & SDK Drivers # @@ -1433,6 +1440,8 @@ CONFIG_SOC_N32G45X=y CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_USART1=y +CONFIG_UART1_PA9_PA10=y +# CONFIG_UART1_PB6_PB7 is not set # CONFIG_BSP_USING_USART2 is not set # CONFIG_BSP_USING_USART3 is not set # CONFIG_BSP_USING_UART4 is not set @@ -1447,6 +1456,17 @@ CONFIG_BSP_USING_USART1=y # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_DAC is not set # CONFIG_BSP_USING_CAN is not set +CONFIG_BSP_USING_PWM=y +# CONFIG_BSP_USING_TIM1_PWM is not set +# CONFIG_BSP_USING_TIM2_PWM is not set +# CONFIG_BSP_USING_TIM3_PWM is not set +# CONFIG_BSP_USING_TIM_ETR_CNT is not set +# CONFIG_BSP_USING_TIM_EXT_COUNTER is not set +CONFIG_BSP_USING_TIM_PULSE_WIDTH=y +CONFIG_BSP_USING_PULSE_WIDTH_DEMO=y +CONFIG_BSP_USING_TIM1_PULSE_WIDTH=y +# CONFIG_BSP_USING_TIM4_PULSE_WIDTH is not set +# CONFIG_BSP_USING_TIM8_PULSE_WIDTH is not set # end of On-chip Peripheral Drivers # diff --git a/bsp/n32/n32g457qel-stb/board/Kconfig b/bsp/n32/n32g457qel-stb/board/Kconfig index 2e186f1a749..407eed97e68 100644 --- a/bsp/n32/n32g457qel-stb/board/Kconfig +++ b/bsp/n32/n32g457qel-stb/board/Kconfig @@ -30,32 +30,120 @@ menu "On-chip Peripheral Drivers" config BSP_USING_USART1 bool "Enable USART1" default y + if BSP_USING_USART1 + choice + prompt "Select UART Pin" + default UART1_PA9_PA10 + config UART1_PA9_PA10 + bool "REMAP0 PA9 PA10" + config UART1_PB6_PB7 + bool "REMAP1 PB6 PB7" + endchoice + endif config BSP_USING_USART2 bool "Enable USART2" default n + if BSP_USING_USART2 + choice + prompt "Select UART Pin" + default UART2_PA2_PA3 + config UART2_PA2_PA3 + bool "REMAP0 PA2 PA3" + config UART2_PD5_PD6 + bool "REMAP1 PD5 PD6" + config UART2_PC8_PC9 + bool "REMAP2 PC8 PC9" + config UART2_PB4_PB5 + bool "REMAP3 PB4 PB5" + endchoice + endif config BSP_USING_USART3 bool "Enable USART3" default n + if BSP_USING_USART3 + choice + prompt "Select UART Pin" + default UART3_PB10_PB11 + config UART3_PB10_PB11 + bool "REMAP0 PB10_PB11" + config UART3_PC10_PC11 + bool "REMAP1 PC10_PC11" + config UART3_PD8_PD9 + bool "REMAP3 PD8_PD9" + endchoice + endif config BSP_USING_UART4 bool "Enable UART4" default n + if BSP_USING_UART4 + choice + prompt "Select UART Pin" + default UART4_PC10_PC11 + config UART4_PC10_PC11 + bool "REMAP0 PC10_PC11" + config UART4_PB2_PE7 + bool "REMAP1 PB2_PE7" + config UART4_PA13_PA14 + bool "REMAP2 PA13_PA14" + config UART4_PD0_PD1 + bool "REMAP3 PD0_PD1" + endchoice + endif config BSP_USING_UART5 bool "Enable UART5" default n + if BSP_USING_UART5 + choice + prompt "Select UART Pin" + default UART5_PC12_PD2 + config UART5_PC12_PD2 + bool "REMAP0 PC12_PD2" + config UART5_PB13_PB14 + bool "REMAP1 PB13_PB14" + config UART5_PE8_PE9 + bool "REMAP2 PE8_PE9" + config UART5_PB8_PB9 + bool "REMAP3 PB8_PB9" + endchoice + endif config BSP_USING_UART6 bool "Enable UART6" default n + if BSP_USING_UART6 + choice + prompt "Select UART Pin" + default UART6_PE2_PE3 + config UART6_PE2_PE3 + bool "REMAP0 PE2_PE3" + config UART6_PC0_PC1 + bool "REMAP2 PC0_PC1" + config UART6_PB0_PB1 + bool "REMAP3 PB0_PB1" + endchoice + endif config BSP_USING_UART7 bool "Enable UART7" default n + if BSP_USING_UART7 + choice + prompt "Select UART Pin" + default UART7_PC4_PC5 + config UART7_PC4_PC5 + bool "REMAP0 PC4_PC5" + config UART7_PC2_PC3 + bool "REMAP1 PC2_PC3" + config UART7_PG0_PG1 + bool "REMAP3 PG0_PG1" + endchoice + endif endif - + #--------BSP_USING_SPI------------------- menuconfig BSP_USING_SPI bool "Enable SPI BUS" default n @@ -64,16 +152,55 @@ menu "On-chip Peripheral Drivers" config BSP_USING_SPI1 bool "Enable SPI1 BUS" default n + if BSP_USING_SPI1 + choice + prompt "Select SPI2 PIN" + default BSP_SPI1_REMAP_0 + config BSP_SPI1_REMAP_0 + bool "PA5 PA6 PA7" + config BSP_SPI1_REMAP_1 + bool "PB3 PB4 PB5" + config BSP_SPI1_REMAP_3 + bool "PE7 PE 8 PE9" + endchoice + endif config BSP_USING_SPI2 bool "Enable SPI2 BUS" default n + if BSP_USING_SPI2 + choice + prompt "Select SPI2 PIN" + default BSP_SPI2_REMAP_0 + config BSP_SPI2_REMAP_0 + bool "PB13 PB14 PB15" + config BSP_SPI2_REMAP_1 + bool "PC7 PC8 PC9" + config BSP_SPI2_REMAP_3 + bool "PE11 PE12 PE13" + endchoice + endif config BSP_USING_SPI3 bool "Enable SPI3 BUS" default n + if BSP_USING_SPI3 + choice + prompt "Select SPI3 PIN" + default BSP_SPI3_REMAP_0 + + config BSP_SPI3_REMAP_0 + bool "PB3 PB4 PB5" - endif + config BSP_SPI3_REMAP_1 + bool "PC10 PC11 PC12" + + config BSP_SPI3_REMAP_3 + bool "PD9 PD11 PD12" + endchoice + endif + + endif #--------BSP_USING_SPI------------------- menuconfig BSP_USING_I2C1 bool "Enable I2C1 BUS (software simulation)" @@ -189,6 +316,338 @@ menu "On-chip Peripheral Drivers" bool "using can2" default n endif + + #-----------------------------PWM---------------------------------- + menuconfig BSP_USING_PWM + bool "Enable N32G45x PWM" + default n + select RT_USING_PWM + select RT_USING_HWTIMER + if BSP_USING_PWM + menuconfig BSP_USING_TIM1_PWM + bool "Enable TIM1 output PWM" + default n + # --------------selcet remap----------------- + if BSP_USING_TIM1_PWM + choice + prompt "Select Pin" + default TIM1_REMAP_0 + config TIM1_REMAP_0 + bool "PA8 PA9 PA10 PA11" + config TIM1_REMAP_3 + bool "PE9 PE11 PE13 PE14" + endchoice + # -----------tim chanle enable----------------- + config BSP_USING_TIM1_PWM_CH1 + bool "Enable TIM1 CH1" + default n + config BSP_USING_TIM1_PWM_CH2 + bool "Enable TIM1 CH2" + default n + config BSP_USING_TIM1_PWM_CH3 + bool "Enable TIM1 CH3" + default n + config BSP_USING_TIM1_PWM_CH4 + bool "Enable TIM1 CH4" + default n + endif + + + menuconfig BSP_USING_TIM2_PWM + bool "Enable TIM2 output PWM" + default n + if BSP_USING_TIM2_PWM + choice + prompt "Select Pin" + default TIM2_REMAP_0 + config TIM2_REMAP_0 + bool "PA0 PA1 PA2 PA3" + config TIM2_REMAP_1 + bool "PA15 PB3 PA2 PA3" + config TIM2_REMAP_2 + bool "PA0 PA1 PB10 PB11" + config TIM2_REMAP_3 + bool "PA15 PB3 PB10 PB11" + endchoice + + config BSP_USING_TIM2_PWM_CH0 + bool "Enable TIM2 CH1" + default n + config BSP_USING_TIM2_PWM_CH1 + bool "Enable TIM2 CH2" + default n + config BSP_USING_TIM2_PWM_CH2 + bool "Enable TIM2 CH3" + default n + config BSP_USING_TIM2_PWM_CH3 + bool "Enable TIM2 CH4" + default n + endif + + menuconfig BSP_USING_TIM3_PWM + bool "Enable TIM3 output PWM" + default n + if BSP_USING_TIM3_PWM + choice + prompt "Select Pin" + default TIM3_REMAP_0 + config TIM3_REMAP_0 + bool "PA6 PA7 PB0 PB1" + config TIM3_REMAP_2 + bool "PB4 PB5 PB0 PB1" + config TIM3_REMAP_3 + bool "PC6 PC7 PC8 PC9" + endchoice + + config BSP_USING_TIM3_PWM_CH0 + bool "Enable TIM3 CH1" + default n + config BSP_USING_TIM3_PWM_CH1 + bool "Enable TIM3 CH2" + default n + config BSP_USING_TIM3_PWM_CH2 + bool "Enable TIM3 CH3" + default n + config BSP_USING_TIM3_PWM_CH3 + bool "Enable TIM3 CH3" + default n + endif#BSP_USING_TIM3_PWM + + endif#BSP_USING_PWM + + #-------------------- TIM ETR CLOCK2 -------------------- + menuconfig BSP_USING_TIM_ETR_CNT + bool "Enable timer ETR" + select RT_USING_HWTIMER + default n + if BSP_USING_TIM_ETR_CNT + config BSP_USING_TIM_ETR_CNT_DEBUG + bool "Enable TIM ETR debug message output" + default n + config BSP_USING_TIM_ETR_CNT_DEMO + bool "Enable demo" + default n + + config BSP_USING_TIM1_ETR_CNT + bool "Enable TIM1 ETR" + default n + choice + prompt "Select TIM2 ETR" + default TIM1_ETR_PIN_PA12 + + config TIM1_ETR_PIN_PA12 + bool "PA12 REMAP VAL = 0,1,2" + + config TIM1_ETR_PIN_PE7 + bool "PE7 REMAP VAL = 3" + endchoice + + config BSP_USING_TIM2_ETR_CNT + bool "Enable TIM2 ETR" + default n + choice + prompt "Select TIM2 ETR" + default TIM2_ETR_PIN_PA0 + + config TIM2_ETR_PIN_PA0 + bool "PA0 REMAP VAL = 0,2" + + config TIM2_ETR_PIN_PA15 + bool "PA15 REMAP VAL = 1,3" + endchoice + + config BSP_USING_TIM3_ETR_CNT + bool "Enable TIM3 ETR PD2" + default n + + config BSP_USING_TIM4_ETR_CNT + bool "Enable TIM4 ETR PE0" + default n + + config BSP_USING_TIM8_ETR_CNT + bool "Enable TIM8 ETR PA0" + default n + choice + prompt "Select tim ETR" + default TIM8_ETR_PIN_PA0 + + config TIM8_ETR_PIN_PA0 + bool "PA0 REMAP VAL = 0" + + config TIM8_ETR_PIN_PB4 + bool "PB4 REMAP VAL = 1,3" + endchoice + + endif + #-------------------- TIM ETR CLOCK2 -------------------- + #-----------------------------EXT_COUNTER---------------------------------- + menuconfig BSP_USING_TIM_EXT_COUNTER + bool "Enable TIM External Counter" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM_EXT_COUNTER + config BSP_USING_EXT_COUNTER_DEMO + bool "Enable External Counter Demo" + default n + config BSP_USING_TIM1_EXT_COUNTER + bool "Enable TIM1 External Counter" + default n + choice + prompt "Select TIM1 Pin" + default TIM1_CH1_PA8 + + config TIM1_CH1_PA8 + bool "PA8" + + config TIM1_CH1_PE9 + bool "PE9" + + config TIM1_CH2_PA9 + bool "PA9" + + config TIM1_CH2_PE11 + bool "PE11 " + + endchoice + + config BSP_USING_TIM2_EXT_COUNTER + bool "Enable TIM2 External Counter" + default n + choice + prompt "Select TIM2 Pin" + default TIM2_CH1_PA0 + + config TIM2_CH1_PA0 + bool "PA0" + + config TIM2_CH1_PA15 + bool "PA15" + + config TIM2_CH2_PA1 + bool "PA1" + + config TIM2_CH2_PB3 + bool "PB3" + + endchoice + + config BSP_USING_TIM3_EXT_COUNTER + bool "Enable TIM3 External Counter" + default n + choice + prompt "Select TIM2 Pin" + default TIM3_CH1_PA6 + + config TIM3_CH1_PA6 + bool "PA6" + + config TIM3_CH1_PB4 + bool "PB4" + + config TIM3_CH1_PC6 + bool "PC6" + + config TIM3_CH2_PA7 + bool "PA7" + + config TIM3_CH2_PB5 + bool "PB5" + + config TIM3_CH2_PC7 + bool "PC7" + + endchoice + + config BSP_USING_TIM4_EXT_COUNTER + bool "Enable TIM4 External Counter" + default n + choice + prompt "Select TIM4 Pin" + default TIM4_CH1_PB6 + + config TIM4_CH1_PB6 + bool "PB6" + + config TIM4_CH1_PD12 + bool "PD12" + + config TIM4_CH2_PB7 + bool "PB7" + + config TIM4_CH2_PD13 + bool "PD13" + + endchoice + + config BSP_USING_TIM5_EXT_COUNTER + bool "Enable TIM5 External Counter" + default n + choice + prompt "Select TIM5 Pin" + default TIM5_CH1_PA0 + + config TIM5_CH1_PA0 + bool "PA0" + + config TIM5_CH1_PA1 + bool "PA1" + + endchoice + + config BSP_USING_TIM8_EXT_COUNTER + bool "Enable TIM8 External Counter" + default n + choice + prompt "Select TIM8 Pin" + default TIM8_CH1_PC6 + + config TIM8_CH1_PC6 + bool "PC6" + + config TIM8_CH1_PD14 + bool "PD14" + + config TIM8_CH2_PC7 + bool "PC7" + + config TIM8_CH2_PD15 + bool "PD15" + + endchoice + endif #EXT_COUNTER + + + #-----------------------------PULSE_WIDTH---------------------------------- + menuconfig BSP_USING_TIM_PULSE_WIDTH + bool "Hardware Timer Pulse Width Measurement" + default n + if BSP_USING_TIM_PULSE_WIDTH + config BSP_USING_PULSE_WIDTH_DEMO + bool "Enable app demo" + default n + + config BSP_USING_TIM1_PULSE_WIDTH + bool "Enable TIM1 PA8" + default n + help + Enable TIM1_CH1 for pulse width measurement using input capture and reset mode + GPIO: PA8 (TIM1_CH1) + + config BSP_USING_TIM4_PULSE_WIDTH + bool "Enable TIM4 PB6" + default n + help + Enable TIM4_CH4 for pulse width measurement using input capture and reset mode + GPIO: PB6 (TIM4_CH1) + + + config BSP_USING_TIM8_PULSE_WIDTH + bool "Enable TIM8 PC6" + default n + help + Enable TIM8_CH1 for pulse width measurement using input capture and reset mode + GPIO: PC6 (TIM2_CH1_REMAP) + endif #--------PULSE_WIDTH---------------- rsource "../../libraries/n32_drivers/Kconfig" diff --git a/bsp/n32/n32g457qel-stb/project.uvprojx b/bsp/n32/n32g457qel-stb/project.uvprojx index b994bc1107a..3b80eff5d50 100644 --- a/bsp/n32/n32g457qel-stb/project.uvprojx +++ b/bsp/n32/n32g457qel-stb/project.uvprojx @@ -334,9 +334,9 @@ 0 - USE_STDPERIPH_DRIVER, RT_USING_LIBC, __RTTHREAD__, __STDC_LIMIT_MACROS, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_ARMLIBC, N32G45X + N32G45X, RT_USING_LIBC, __RTTHREAD__, USE_STDPERIPH_DRIVER, RT_USING_ARMLIBC, __CLK_TCK=RT_TICK_PER_SECOND, __STDC_LIMIT_MACROS - ..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\smp_call;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\libraries\n32_drivers\config;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\posix\io\poll;..\libraries\n32_drivers;..\..\..\components\libc\posix\ipc;..\..\..\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\inc;..\..\..\components\drivers\phy;.;..\..\..\components\drivers\include;..\libraries\N32G45x_Firmware_Library\CMSIS\core;..\..\..\components\libc\posix\io\epoll;..\..\..\libcpu\arm\cortex-m4;..\..\..\libcpu\arm\common;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\include;..\..\..\components\drivers\include;applications;..\..\..\components\drivers\include;..\libraries\N32G45x_Firmware_Library\CMSIS\device;..\..\..\components\finsh + ..\libraries\N32G45x_Firmware_Library\CMSIS\core;..\..\..\components\drivers\include;..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\inc;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\libcpu\arm\common;..\..\..\components\drivers\smp_call;..\libraries\N32G45x_Firmware_Library\CMSIS\device;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;.;..\..\..\components\drivers\spi;..\libraries\n32_drivers\config;..\..\..\components\drivers\phy;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\posix\io\epoll;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\net\utest;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\libc\posix\ipc;..\..\..\components\finsh;applications;..\..\..\libcpu\arm\cortex-m4;..\libraries\n32_drivers;..\..\..\components\drivers\include @@ -388,61 +388,40 @@ - Compiler + CPU - syscall_mem.c - 1 - ..\..\..\components\libc\compilers\armlibc\syscall_mem.c - - - - - syscalls.c - 1 - ..\..\..\components\libc\compilers\armlibc\syscalls.c - - - - - cctype.c - 1 - ..\..\..\components\libc\compilers\common\cctype.c - - - - - cstdlib.c + atomic_arm.c 1 - ..\..\..\components\libc\compilers\common\cstdlib.c + ..\..\..\libcpu\arm\common\atomic_arm.c - cstring.c + div0.c 1 - ..\..\..\components\libc\compilers\common\cstring.c + ..\..\..\libcpu\arm\common\div0.c - ctime.c + showmem.c 1 - ..\..\..\components\libc\compilers\common\ctime.c + ..\..\..\libcpu\arm\common\showmem.c - cunistd.c - 1 - ..\..\..\components\libc\compilers\common\cunistd.c + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S - cwchar.c + cpuport.c 1 - ..\..\..\components\libc\compilers\common\cwchar.c + ..\..\..\libcpu\arm\cortex-m4\cpuport.c @@ -771,6 +750,25 @@ + + + rt_drv_pwm.c + 1 + ..\..\..\components\drivers\misc\rt_drv_pwm.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dev_pin.c @@ -909,6 +907,13 @@ ..\libraries\n32_drivers\drv_adc.c + + + drv_base.c + 1 + ..\libraries\n32_drivers\drv_base.c + + drv_can.c @@ -937,6 +942,13 @@ ..\libraries\n32_drivers\drv_hwtimer.c + + + drv_pwm.c + 1 + ..\libraries\n32_drivers\drv_pwm.c + + drv_rtc.c @@ -951,6 +963,13 @@ ..\libraries\n32_drivers\drv_spi.c + + + drv_tim_pulse_width.c + 1 + ..\libraries\n32_drivers\drv_tim_pulse_width.c + + drv_usart.c @@ -970,30 +989,30 @@ Finsh - cmd.c + msh_parse.c 1 - ..\..\..\components\finsh\cmd.c + ..\..\..\components\finsh\msh_parse.c - msh.c + shell.c 1 - ..\..\..\components\finsh\msh.c + ..\..\..\components\finsh\shell.c - msh_parse.c + cmd.c 1 - ..\..\..\components\finsh\msh_parse.c + ..\..\..\components\finsh\cmd.c - shell.c + msh.c 1 - ..\..\..\components\finsh\shell.c + ..\..\..\components\finsh\msh.c @@ -1305,78 +1324,96 @@ - klibc + Libc - kerrno.c + syscall_mem.c 1 - ..\..\..\src\klibc\kerrno.c + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c - rt_vsnprintf_tiny.c + syscalls.c 1 - ..\..\..\src\klibc\rt_vsnprintf_tiny.c + ..\..\..\components\libc\compilers\armlibc\syscalls.c - kstdio.c + cctype.c 1 - ..\..\..\src\klibc\kstdio.c + ..\..\..\components\libc\compilers\common\cctype.c - kstring.c + cstdlib.c 1 - ..\..\..\src\klibc\kstring.c + ..\..\..\components\libc\compilers\common\cstdlib.c - rt_vsscanf.c + cstring.c 1 - ..\..\..\src\klibc\rt_vsscanf.c + ..\..\..\components\libc\compilers\common\cstring.c - - - libcpu - atomic_arm.c + ctime.c 1 - ..\..\..\libcpu\arm\common\atomic_arm.c + ..\..\..\components\libc\compilers\common\ctime.c - div0.c + cunistd.c 1 - ..\..\..\libcpu\arm\common\div0.c + ..\..\..\components\libc\compilers\common\cunistd.c - showmem.c + cwchar.c 1 - ..\..\..\libcpu\arm\common\showmem.c + ..\..\..\components\libc\compilers\common\cwchar.c - context_rvds.S - 2 - ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + kerrno.c + 1 + ..\..\..\src\klibc\kerrno.c - cpuport.c + kstdio.c 1 - ..\..\..\libcpu\arm\cortex-m4\cpuport.c + ..\..\..\src\klibc\kstdio.c + + + + + kstring.c + 1 + ..\..\..\src\klibc\kstring.c + + + + + rt_vsnprintf_tiny.c + 1 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + + + rt_vsscanf.c + 1 + ..\..\..\src\klibc\rt_vsscanf.c @@ -1384,58 +1421,58 @@ Libraries - n32g45x_wwdg.c + n32g45x_usart.c 1 - ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_wwdg.c + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_usart.c - misc.c + n32g45x_wwdg.c 1 - ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\misc.c + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_wwdg.c - n32g45x_rcc.c + n32g45x_gpio.c 1 - ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rcc.c + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_gpio.c - n32g45x_can.c + system_n32g45x.c 1 - ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_can.c + ..\libraries\N32G45x_Firmware_Library\CMSIS\device\system_n32g45x.c - system_n32g45x.c + n32g45x_tim.c 1 - ..\libraries\N32G45x_Firmware_Library\CMSIS\device\system_n32g45x.c + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_tim.c - n32g45x_spi.c + n32g45x_exti.c 1 - ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_spi.c + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_exti.c - n32g45x_usart.c + n32g45x_i2c.c 1 - ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_usart.c + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_i2c.c - n32g45x_pwr.c + n32g45x_spi.c 1 - ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_pwr.c + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_spi.c @@ -1447,58 +1484,58 @@ - n32g45x_i2c.c + n32g45x_dma.c 1 - ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_i2c.c + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dma.c - n32g45x_iwdg.c + n32g45x_dac.c 1 - ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_iwdg.c + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dac.c - n32g45x_adc.c + misc.c 1 - ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_adc.c + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\misc.c - n32g45x_gpio.c + n32g45x_rcc.c 1 - ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_gpio.c + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rcc.c - n32g45x_exti.c + n32g45x_pwr.c 1 - ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_exti.c + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_pwr.c - n32g45x_tim.c + n32g45x_iwdg.c 1 - ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_tim.c + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_iwdg.c - n32g45x_dac.c + n32g45x_adc.c 1 - ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dac.c + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_adc.c - n32g45x_dma.c + n32g45x_can.c 1 - ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dma.c + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_can.c diff --git a/bsp/n32/n32g457qel-stb/rtconfig.h b/bsp/n32/n32g457qel-stb/rtconfig.h index e2e0b578710..8f7aaae3e9c 100644 --- a/bsp/n32/n32g457qel-stb/rtconfig.h +++ b/bsp/n32/n32g457qel-stb/rtconfig.h @@ -104,7 +104,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "usart1" -#define RT_VER_NUM 0x50201 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC @@ -158,8 +158,10 @@ #define RT_USING_I2C_BITOPS #define RT_USING_ADC #define RT_USING_DAC +#define RT_USING_PWM #define RT_USING_RTC #define RT_USING_SPI +#define RT_USING_SPI_ISR #define RT_USING_WDT #define RT_USING_PIN #define RT_USING_HWTIMER @@ -332,6 +334,10 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -425,6 +431,11 @@ #define BSP_USING_GPIO #define BSP_USING_UART #define BSP_USING_USART1 +#define UART1_PA9_PA10 +#define BSP_USING_PWM +#define BSP_USING_TIM_PULSE_WIDTH +#define BSP_USING_PULSE_WIDTH_DEMO +#define BSP_USING_TIM1_PULSE_WIDTH /* end of On-chip Peripheral Drivers */ /* Board extended module Drivers */ diff --git a/bsp/n32/n32l40xcl-stb/.config b/bsp/n32/n32l40xcl-stb/.config index f9070b0e8e2..0664f5016fe 100644 --- a/bsp/n32/n32l40xcl-stb/.config +++ b/bsp/n32/n32l40xcl-stb/.config @@ -179,7 +179,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="usart1" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -256,7 +256,7 @@ CONFIG_RT_USING_DAC=y # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set # CONFIG_RT_USING_RANDOM is not set -# CONFIG_RT_USING_PWM is not set +CONFIG_RT_USING_PWM=y # CONFIG_RT_USING_PULSE_ENCODER is not set # CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set @@ -267,6 +267,7 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y # CONFIG_RT_USING_SOFT_SPI is not set # CONFIG_RT_USING_QSPI is not set # CONFIG_RT_USING_SPI_MSD is not set @@ -361,8 +362,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Using USB legacy version # @@ -371,6 +370,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -738,6 +738,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -894,6 +895,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK # end of HAL & SDK Drivers # @@ -1420,6 +1427,9 @@ CONFIG_SOC_N32L40X=y CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_USART1=y +# CONFIG_UART1_TX_PA4_PA5 is not set +CONFIG_UART1_PA9_PA10=y +# CONFIG_UART1_PB6_PB7 is not set # CONFIG_BSP_USING_USART2 is not set # CONFIG_BSP_USING_USART3 is not set # CONFIG_BSP_USING_UART4 is not set @@ -1432,6 +1442,25 @@ CONFIG_BSP_USING_USART1=y # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_DAC is not set # CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_PWM is not set +CONFIG_TIM2_CH1_PA0=y +# CONFIG_TIM2_CH1_PA15 is not set +# CONFIG_TIM2_CH2_PA1 is not set +# CONFIG_TIM2_CH2_PB3 is not set +CONFIG_TIM3_CH1_PA6=y +# CONFIG_TIM3_CH1_PB4 is not set +# CONFIG_TIM3_CH1_PC6 is not set +# CONFIG_TIM3_CH2_PA7 is not set +# CONFIG_TIM3_CH2_PB5 is not set +# CONFIG_TIM3_CH2_PC7 is not set +# CONFIG_BSP_USING_TIM_ETR_CNT is not set +CONFIG_BSP_USING_TIM_EXT_COUNTER=y +CONFIG_BSP_USING_TIM1_EXT_COUNTER=y +CONFIG_TIM1_CH1_PA8=y +# CONFIG_TIM1_CH2_PA9 is not set +CONFIG_BSP_USING_EXT_COUNTER_DEMO=y +# CONFIG_BSP_USING_TIM2_EXT_COUNTER is not set +# CONFIG_BSP_USING_TIM3_EXT_COUNTER is not set # end of On-chip Peripheral Drivers # diff --git a/bsp/n32/n32l40xcl-stb/RTE/_rt-thread/RTE_Components.h b/bsp/n32/n32l40xcl-stb/RTE/_rt-thread/RTE_Components.h new file mode 100644 index 00000000000..79d5313d7b8 --- /dev/null +++ b/bsp/n32/n32l40xcl-stb/RTE/_rt-thread/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'project' + * Target: 'rt-thread' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "n32l40x.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/bsp/n32/n32l40xcl-stb/board/Kconfig b/bsp/n32/n32l40xcl-stb/board/Kconfig index 4303b8e4ad1..8e00065d9d8 100644 --- a/bsp/n32/n32l40xcl-stb/board/Kconfig +++ b/bsp/n32/n32l40xcl-stb/board/Kconfig @@ -22,6 +22,7 @@ menu "On-chip Peripheral Drivers" select RT_USING_PIN default y + #---------------N32L40x UART-------------------- menuconfig BSP_USING_UART bool "Enable UART" default y @@ -30,39 +31,121 @@ menu "On-chip Peripheral Drivers" config BSP_USING_USART1 bool "Enable USART1" default y + if BSP_USING_USART1 + choice + prompt "Select UART Pin" + default UART1_PA9_PA10 + config UART1_TX_PA4_PA5 + bool "PA4 AF1 PA5 AF4" + config UART1_PA9_PA10 + bool "PA9 AF4 PA10 AF4" + config UART1_PB6_PB7 + bool "PB6 AF0 PB7 AF0" + endchoice + endif config BSP_USING_USART2 bool "Enable USART2" default n + if BSP_USING_USART2 + choice + prompt "Select UART Pin" + default UART2_TX_PA2_RX_PA3 + config UART2_TX_PA2_RX_PA3 + bool "PA2 PA3 AF2" + config UART2_TX_PB4_RX_PB5 + bool "PB4 AF4 PB5 AF6" + endchoice + endif config BSP_USING_USART3 bool "Enable USART3" default n + if BSP_USING_USART3 + choice + prompt "Select UART Pin" + default UART3_TX_PB10_RX_B11 + config UART3_TX_PB10_RX_B11 + bool "PB10 AF0 PB11 AF5" + config UART3_TX_PC10_RX_PC11 + bool "PC10 AF5 PC11 AF5" + endchoice + endif config BSP_USING_UART4 bool "Enable UART4" default n + if BSP_USING_UART4 + choice + prompt "Select UART Pin" + default UART4_TX_PB0_RX_PB1 + config UART4_TX_PB0_RX_PB1 + bool "PB0 AF6 PB1 AF6" + config UART4_TX_PB14_RX_PB15 + bool "PB14 AF6 PB15 AF6" + config UART4_TX_PC10_RX_PC11 + bool "PC10 AF6 PC11 AF6" + config UART4_TX_PD13_RX_PD12 + bool "PD13 AF6 PD12 AF6" + endchoice + endif config BSP_USING_UART5 bool "Enable UART5" default n + if BSP_USING_UART5 + choice + prompt "Select UART Pin" + default UART5_TX_PB8_RX_PB9 + config UART5_TX_PB4_RX_PB5 + bool "PB4 AF6 PB5 AF6" + config UART5_TX_PB8_RX_PB9 + bool "PB8 AF6 PB9 AF6" + config UART5_TX_PC12_RX_PD2 + bool "PC12 AF6 PD2 AF6" + endchoice + endif endif - + #---------------N32L40x UART-------------------- + menuconfig BSP_USING_SPI bool "Enable SPI BUS" default n select RT_USING_SPI if BSP_USING_SPI - config BSP_USING_SPI1 + config BSP_USING_SPI1 bool "Enable SPI1 BUS" default n + if BSP_USING_SPI1 + choice + prompt "Select SPI1 PIN" + default BSP_SPI1_REMAP_0 + config BSP_SPI1_REMAP_0 + bool "PA5 PA6 PA7" + config BSP_SPI1_REMAP_1 + bool "PB3 PB4 PB5" + config BSP_SPI1_REMAP_2 + bool "PD4 PD5 PD6" + endchoice + endif config BSP_USING_SPI2 bool "Enable SPI2 BUS" default n - - endif + if BSP_USING_SPI2 + choice + prompt "Select SPI2 PIN" + default BSP_SPI2_REMAP_0 + config BSP_SPI2_REMAP_0 + bool "PB13 PB14 PB15" + config BSP_SPI2_REMAP_1 + bool "PC7 PC8 PC9" + config BSP_SPI2_REMAP_3 + bool "PA10 PA11 PA12" + endchoice + endif + endif #BSP_USING_SPI menuconfig BSP_USING_I2C1 bool "Enable I2C1 BUS (software simulation)" @@ -164,6 +247,240 @@ menu "On-chip Peripheral Drivers" select RT_USING_CAN default n + #-----------------------------PWM---------------------------------- + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + select RT_USING_PWM + select RT_USING_HWTIMER + if BSP_USING_PWM + menuconfig BSP_USING_TIM1_PWM + bool "Enable TIM1 output PWM" + default n + # --------------selcet remap----------------- + if BSP_USING_TIM1_PWM + config BSP_USING_TIM1_PWM_CH1 + bool "Enable TIM1 channel1 PA8 AF2" + default n + config BSP_USING_TIM1_PWM_CH2 + bool "Enable TIM1 channel2 PA9 AF2" + default n + config BSP_USING_TIM1_PWM_CH3 + bool "Enable TIM1 channel3 PA10 AF2" + default n + config BSP_USING_TIM1_PWM_CH4 + bool "Enable TIM1 channel4 PA11 AF2" + default n + endif#BSP_USING_TIM1_PWM + + + menuconfig BSP_USING_TIM2_PWM + bool "Enable TIM2 output PWM" + default n + if BSP_USING_TIM2_PWM + config BSP_USING_TIM2_PWM_CH1 + bool "Enable TIM2 channel1" + default n + if BSP_USING_TIM2_PWM_CH1 + choice + prompt "Select Pin" + default TIM2_PWM_CH1_PA0 + config TIM2_PWM_CH1_PA0 + bool "PA0 AF2" + config TIM2_PWM_CH1_PA15 + bool "PA15 AF5" + endchoice + endif + config BSP_USING_TIM2_PWM_CH2 + bool "Enable TIM2 channel2" + default n + if BSP_USING_TIM2_PWM_CH2 + choice + prompt "Select Pin" + default TIM2_PWM_CH2_PA1 + config TIM2_PWM_CH2_PA1 + bool "PA1 AF2" + config TIM2_PWM_CH2_PB3 + bool "PB3 AF2" + endchoice + endif + config BSP_USING_TIM2_PWM_CH3 + bool "Enable TIM2 channel3" + default n + if BSP_USING_TIM2_PWM_CH3 + choice + prompt "Select Pin" + default TIM2_PWM_CH3_PA2 + config TIM2_PWM_CH3_PA2 + bool "PA2 AF2" + config TIM2_PWM_CH3_PB10 + bool "PB10 AF2" + endchoice + endif + config BSP_USING_TIM2_PWM_CH4 + bool "Enable TIM2 channel3 AF2 PB11" + default n + endif#BSP_USING_TIM2_PWM + + menuconfig BSP_USING_TIM3_PWM + bool "Enable TIM3 output PWM" + default n + if BSP_USING_TIM3_PWM + config BSP_USING_TIM3_PWM_CH1 + bool "Enable TIM3 channel1" + default n + if BSP_USING_TIM3_PWM_CH1 + choice + prompt "Select Pin" + default TIM3_PWM_CH1_PA6 + config TIM3_PWM_CH1_PA6 + bool "PA6 AF2" + config TIM3_PWM_CH1_PB4 + bool "PB4 AF2" + config TIM3_PWM_CH1_PC6 + bool "PC6 AF5" + endchoice + endif + config BSP_USING_TIM3_PWM_CH2 + bool "Enable TIM3 channel2" + default n + if BSP_USING_TIM3_PWM_CH2 + choice + prompt "Select Pin" + default TIM3_PWM_CH2_PA7 + config TIM3_PWM_CH2_PA7 + bool "PA7 AF2" + config TIM3_PWM_CH2_PB5 + bool "PB5 AF2" + config TIM3_PWM_CH2_PC7 + bool "PC7 AF2" + endchoice + endif + config BSP_USING_TIM3_PWM_CH3 + bool "Enable TIM3 channel3" + default n + if BSP_USING_TIM3_PWM_CH3 + choice + prompt "Select Pin" + default TIM3_PWM_CH3_PB0 + config TIM3_PWM_CH3_PB0 + bool "PB0 AF2" + config TIM3_PWM_CH3_PC8 + bool "PC8 AF2" + endchoice + endif + config BSP_USING_TIM3_PWM_CH4 + bool "Enable TIM3 channel3 AF2 PB11" + default n + if BSP_USING_TIM3_PWM_CH4 + choice + prompt "Select Pin" + default TIM3_PWM_CH4_PB1 + config TIM3_PWM_CH4_PB1 + bool "PB1 AF2" + config TIM3_PWM_CH4_PC9 + bool "PC89 AF2" + endchoice + endif + endif #BSP_USING_TIM3_PWM + endif#BSP_USING_PWM + + #------------TIM ETR CLOCK2-------------- + menuconfig BSP_USING_TIM_ETR_CNT + bool "Enable timer ETR MAX=10M" + select RT_USING_HWTIMER + default n + if BSP_USING_TIM_ETR_CNT + config BSP_USING_TIM_ETR_CNT_DEBUG + bool "Enable TIM ETR debug message output" + default n + config BSP_USING_TIM_ETR_CNT_DEMO + bool "Enable demo" + default n + + config BSP_USING_TIM1_ETR_CNT + bool "Enable TIM1 ETR PA12 AF2" + default n + + config BSP_USING_TIM2_ETR_CNT + bool "Enable TIM1 ETR" + default n + choice + prompt "Select TIM2 ETR PIN" + default TIM2_ETR_PIN_PA0 + config TIM2_ETR_PIN_PA0 + bool "PA0 AF5" + config TIM1_ETR_PIN_PA15 + bool "PA15 AF2" + endchoice # + config BSP_USING_TIM3_ETR_CNT + bool "Enable TIM3 ETR PD2 AF2" + default n + config BSP_USING_TIM9_ETR_CNT + bool "Enable TIM9 ETR PB2 AF1" + default n + endif#BSP_USING_TIM_ETR_CNT + #------------TIM ETR CLOCK2-------------- + + + #-----------------------------EXT_COUNTER---------------------------------- + menuconfig BSP_USING_TIM_EXT_COUNTER + bool "Enable TIM External Counter" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM_EXT_COUNTER + config BSP_USING_EXT_COUNTER_DEMO + bool "Enable External Counter Demo" + default n + + config BSP_USING_TIM1_EXT_COUNTER + bool "Enable TIM1 External Counter" + default n + choice + prompt "Select TIM1 Pin" + default TIM1_CH1_PA8 + config TIM1_CH1_PA8 + bool "PA8 AF2" + config TIM1_CH2_PA9 + bool "PA9 AF2" + endchoice + + config BSP_USING_TIM2_EXT_COUNTER + bool "Enable TIM2 External Counter" + default n + choice + prompt "Select TIM2 Pin" + default TIM2_CH1_PA0 + config TIM2_CH1_PA0 + bool "PA0 AF2" + config TIM2_CH1_PA15 + bool "PA15 AF5" + config TIM2_CH2_PA1 + bool "PA1 AF2" + config TIM2_CH2_PB3 + bool "PB3 AF2" + endchoice + + config BSP_USING_TIM3_EXT_COUNTER + bool "Enable TIM3 External Counter" + default n + choice + prompt "Select TIM3 Pin" + default TIM3_CH1_PA6 + config TIM3_CH1_PA6 + bool "PA6 AF2" + config TIM3_CH1_PB4 + bool "PB4 AF2" + config TIM3_CH1_PC6 + bool "PC6 AF2" + config TIM3_CH2_PA7 + bool "PA7 AF2" + config TIM3_CH2_PB5 + bool "PB5 AF2" + config TIM3_CH2_PC7 + bool "PC7 AF2" + endchoice + endif#---------BSP_USING_TIM_EXT_COUNTER------------ rsource "../../libraries/n32_drivers/Kconfig" endmenu diff --git a/bsp/n32/n32l40xcl-stb/project.uvprojx b/bsp/n32/n32l40xcl-stb/project.uvprojx index 82add6e608d..4c2e2d8c3c9 100644 --- a/bsp/n32/n32l40xcl-stb/project.uvprojx +++ b/bsp/n32/n32l40xcl-stb/project.uvprojx @@ -334,9 +334,9 @@ 0 - RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, USE_STDPERIPH_DRIVER, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, N32L40X + N32L40X, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, RT_USING_ARMLIBC, RT_USING_LIBC, USE_STDPERIPH_DRIVER, __STDC_LIMIT_MACROS - ..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\epoll;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\drivers\include;..\libraries\n32_drivers;..\libraries\n32_drivers\config;..\..\..\components\libc\posix\io\eventfd;..\libraries\N32L40x_Firmware_Library\CMSIS\core;..\..\..\components\drivers\include;..\..\..\components\drivers\include;.;applications;board;..\..\..\libcpu\arm\common;..\..\..\components\drivers\spi;..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\inc;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\include;..\..\..\libcpu\arm\cortex-m4;..\libraries\N32L40x_Firmware_Library\CMSIS\device;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\drivers\smp_call;..\..\..\components\drivers\phy;..\..\..\components\libc\posix\ipc;..\..\..\components\drivers\include + ..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\libraries\n32_drivers\config;..\..\..\components\libc\posix\io\epoll;..\..\..\components\drivers\include;..\libraries\n32_drivers;..\..\..\components\drivers\smp_call;applications;..\..\..\libcpu\arm\cortex-m4;..\..\..\libcpu\arm\common;..\..\..\components\libc\posix\ipc;..\libraries\N32L40x_Firmware_Library\CMSIS\core;..\..\..\include;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\drivers\spi;..\..\..\components\libc\compilers\common\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\drivers\phy;..\..\..\components\libc\posix\io\poll;..\..\..\components\net\utest;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\inc;..\..\..\components\drivers\include;..\..\..\components\drivers\include;.;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\libraries\N32L40x_Firmware_Library\CMSIS\device;board;..\..\..\components\libc\compilers\common\extension\fcntl\octal @@ -388,61 +388,33 @@ - Compiler + CPU - syscall_mem.c - 1 - ..\..\..\components\libc\compilers\armlibc\syscall_mem.c - - - - - syscalls.c - 1 - ..\..\..\components\libc\compilers\armlibc\syscalls.c - - - - - cctype.c - 1 - ..\..\..\components\libc\compilers\common\cctype.c - - - - - cstdlib.c - 1 - ..\..\..\components\libc\compilers\common\cstdlib.c - - - - - cstring.c + div0.c 1 - ..\..\..\components\libc\compilers\common\cstring.c + ..\..\..\libcpu\arm\common\div0.c - ctime.c + showmem.c 1 - ..\..\..\components\libc\compilers\common\ctime.c + ..\..\..\libcpu\arm\common\showmem.c - cunistd.c - 1 - ..\..\..\components\libc\compilers\common\cunistd.c + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S - cwchar.c + cpuport.c 1 - ..\..\..\components\libc\compilers\common\cwchar.c + ..\..\..\libcpu\arm\cortex-m4\cpuport.c @@ -771,6 +743,25 @@ + + + rt_drv_pwm.c + 1 + ..\..\..\components\drivers\misc\rt_drv_pwm.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dev_pin.c @@ -909,6 +900,13 @@ ..\libraries\n32_drivers\drv_adc.c + + + drv_base.c + 1 + ..\libraries\n32_drivers\drv_base.c + + drv_can.c @@ -937,6 +935,13 @@ ..\libraries\n32_drivers\drv_hwtimer.c + + + drv_pwm.c + 1 + ..\libraries\n32_drivers\drv_pwm.c + + drv_rtc.c @@ -951,6 +956,13 @@ ..\libraries\n32_drivers\drv_spi.c + + + drv_tim_external_counter.c + 1 + ..\libraries\n32_drivers\drv_tim_external_counter.c + + drv_usart.c @@ -977,23 +989,23 @@ - msh_parse.c + shell.c 1 - ..\..\..\components\finsh\msh_parse.c + ..\..\..\components\finsh\shell.c - shell.c + msh.c 1 - ..\..\..\components\finsh\shell.c + ..\..\..\components\finsh\msh.c - msh.c + msh_parse.c 1 - ..\..\..\components\finsh\msh.c + ..\..\..\components\finsh\msh_parse.c @@ -1305,71 +1317,96 @@ - klibc + Libc - kerrno.c + syscall_mem.c 1 - ..\..\..\src\klibc\kerrno.c + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c - kstring.c + syscalls.c 1 - ..\..\..\src\klibc\kstring.c + ..\..\..\components\libc\compilers\armlibc\syscalls.c - rt_vsnprintf_tiny.c + cctype.c 1 - ..\..\..\src\klibc\rt_vsnprintf_tiny.c + ..\..\..\components\libc\compilers\common\cctype.c - rt_vsscanf.c + cstdlib.c 1 - ..\..\..\src\klibc\rt_vsscanf.c + ..\..\..\components\libc\compilers\common\cstdlib.c - kstdio.c + cstring.c 1 - ..\..\..\src\klibc\kstdio.c + ..\..\..\components\libc\compilers\common\cstring.c - - - libcpu - div0.c + ctime.c 1 - ..\..\..\libcpu\arm\common\div0.c + ..\..\..\components\libc\compilers\common\ctime.c - showmem.c + cunistd.c 1 - ..\..\..\libcpu\arm\common\showmem.c + ..\..\..\components\libc\compilers\common\cunistd.c - context_rvds.S - 2 - ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + cwchar.c + 1 + ..\..\..\components\libc\compilers\common\cwchar.c - cpuport.c + kerrno.c 1 - ..\..\..\libcpu\arm\cortex-m4\cpuport.c + ..\..\..\src\klibc\kerrno.c + + + + + kstdio.c + 1 + ..\..\..\src\klibc\kstdio.c + + + + + kstring.c + 1 + ..\..\..\src\klibc\kstring.c + + + + + rt_vsnprintf_tiny.c + 1 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + + + rt_vsscanf.c + 1 + ..\..\..\src\klibc\rt_vsscanf.c @@ -1377,9 +1414,9 @@ Libraries - misc.c + n32l40x_exti.c 1 - ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\misc.c + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_exti.c @@ -1391,107 +1428,107 @@ - n32l40x_gpio.c + n32l40x_spi.c 1 - ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_gpio.c + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_spi.c - n32l40x_spi.c + n32l40x_flash.c 1 - ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_spi.c + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_flash.c - n32l40x_can.c + n32l40x_rcc.c 1 - ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_can.c + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_rcc.c - n32l40x_flash.c + n32l40x_gpio.c 1 - ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_flash.c + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_gpio.c - n32l40x_wwdg.c + n32l40x_i2c.c 1 - ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_wwdg.c + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_i2c.c - n32l40x_exti.c + n32l40x_dac.c 1 - ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_exti.c + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_dac.c - system_n32l40x.c + n32l40x_iwdg.c 1 - ..\libraries\N32L40x_Firmware_Library\CMSIS\device\system_n32l40x.c + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_iwdg.c - n32l40x_iwdg.c + n32l40x_tim.c 1 - ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_iwdg.c + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_tim.c - n32l40x_dac.c + n32l40x_wwdg.c 1 - ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_dac.c + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_wwdg.c - n32l40x_adc.c + n32l40x_rtc.c 1 - ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_adc.c + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_rtc.c - n32l40x_usart.c + misc.c 1 - ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_usart.c + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\misc.c - n32l40x_i2c.c + n32l40x_usart.c 1 - ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_i2c.c + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_usart.c - n32l40x_rtc.c + n32l40x_can.c 1 - ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_rtc.c + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_can.c - n32l40x_rcc.c + n32l40x_adc.c 1 - ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_rcc.c + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_adc.c - n32l40x_tim.c + system_n32l40x.c 1 - ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_tim.c + ..\libraries\N32L40x_Firmware_Library\CMSIS\device\system_n32l40x.c diff --git a/bsp/n32/n32l40xcl-stb/rtconfig.h b/bsp/n32/n32l40xcl-stb/rtconfig.h index 236a2cdae79..f8092c73576 100644 --- a/bsp/n32/n32l40xcl-stb/rtconfig.h +++ b/bsp/n32/n32l40xcl-stb/rtconfig.h @@ -104,7 +104,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "usart1" -#define RT_VER_NUM 0x50201 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ @@ -153,8 +153,10 @@ #define RT_USING_I2C_BITOPS #define RT_USING_ADC #define RT_USING_DAC +#define RT_USING_PWM #define RT_USING_RTC #define RT_USING_SPI +#define RT_USING_SPI_ISR #define RT_USING_WDT #define RT_USING_PIN #define RT_USING_HWTIMER @@ -327,6 +329,10 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -419,6 +425,13 @@ #define BSP_USING_GPIO #define BSP_USING_UART #define BSP_USING_USART1 +#define UART1_PA9_PA10 +#define TIM2_CH1_PA0 +#define TIM3_CH1_PA6 +#define BSP_USING_TIM_EXT_COUNTER +#define BSP_USING_TIM1_EXT_COUNTER +#define TIM1_CH1_PA8 +#define BSP_USING_EXT_COUNTER_DEMO /* end of On-chip Peripheral Drivers */ /* Board extended module Drivers */ diff --git a/bsp/renesas/ra4m2-eco/JLinkLog.txt b/bsp/renesas/ra4m2-eco/JLinkLog.txt deleted file mode 100644 index 5ca076c18bc..00000000000 --- a/bsp/renesas/ra4m2-eco/JLinkLog.txt +++ /dev/null @@ -1,170 +0,0 @@ -T4F84 000:185.922 SEGGER J-Link V8.60 Log File -T4F84 000:186.079 DLL Compiled: Aug 13 2025 12:04:02 -T4F84 000:186.097 Logging started @ 2025-08-19 05:48 -T4F84 000:186.115 Process: D:\software\MDK5.38\UV4\UV4.exe -T4F84 000:186.140 - 186.132ms -T4F84 000:186.167 JLINK_SetWarnOutHandler(...) -T4F84 000:186.189 - 0.023ms -T4F84 000:186.206 JLINK_OpenEx(...) -T4F84 000:194.532 Firmware: J-Link OB-S124 compiled Apr 1 2025 10:13:40 -T4F84 000:196.122 Firmware: J-Link OB-S124 compiled Apr 1 2025 10:13:40 -T4F84 000:236.470 Hardware: V1.00 -T4F84 000:236.564 S/N: 831189195 -T4F84 000:236.617 OEM: SEGGER -T4F84 000:236.670 Feature(s): None -T4F84 000:238.010 Bootloader: 2017 Feb 06 -T4F84 000:249.973 USB speed mode: Full speed (12 MBit/s) -T4F84 000:250.922 TELNET listener socket opened on port 19021 -T4F84 000:251.035 WEBSRV WEBSRV_Init(): Starting webserver thread(s) -T4F84 000:251.114 WEBSRV Failed to put socket into listener state (port 19080) -T4F84 000:251.140 WEBSRV Failed to put socket into listener state (port 19081) -T4F84 000:251.292 WEBSRV Webserver running on local port 19082 -T4F84 000:251.427 Looking for J-Link GUI Server exe at: D:\software\MDK5.38\ARM\Segger\JLinkGUIServer.exe -T4F84 000:251.529 Looking for J-Link GUI Server exe at: D:\software\SEGGER\JLink_V860\JLinkGUIServer.exe -T4F84 000:251.551 Forking J-Link GUI Server: D:\software\SEGGER\JLink_V860\JLinkGUIServer.exe -T4F84 000:253.912 J-Link GUI Server info: "J-Link GUI server V8.60 " -T4F84 000:254.286 - 68.074ms returns "O.K." -T4F84 000:254.350 JLINK_GetEmuCaps() -T4F84 000:254.366 - 0.015ms returns 0xB8EA5A33 -T4F84 000:254.385 JLINK_TIF_GetAvailable(...) -T4F84 000:255.430 - 1.043ms -T4F84 000:255.554 JLINK_SetErrorOutHandler(...) -T4F84 000:255.583 - 0.029ms -T4F84 000:255.630 JLINK_ExecCommand("ProjectFile = "E:\workspace\rt-thread\bsp\renesas\ra4m2-eco\JLinkSettings.ini"", ...). -T4F84 000:269.484 Ref file found at: D:\software\MDK5.38\ARM\Segger\JLinkDevices.ref -T4F84 000:269.600 REF file references invalid XML file: D:\software\SEGGER\JLink_V860\JLinkDevices.xml -T4F84 000:271.566 - 15.937ms returns 0x00 -T4F84 000:271.638 JLINK_ExecCommand("Device = R7FA4M2AD", ...). -T4F84 000:272.257 Flash bank @ 0x0100A100: SFL: Parsing sectorization info from ELF file -T4F84 000:272.305 FlashDevice.SectorInfo[0]: .SectorSize = 0x00000010, .SectorStartAddr = 0x00000000 -T4F84 000:272.328 FlashBank @0x0100A100: Sectorization info from SFL ELF file ignored because sectorization override from DLL / XML file is active. -T4F84 000:273.580 Flash bank @ 0x60000000: SFL: Parsing sectorization info from ELF file -T4F84 000:273.629 FlashDevice.SectorInfo[0]: .SectorSize = 0x00010000, .SectorStartAddr = 0x00000000 -T4F84 000:277.643 Device "R7FA4M2AD" selected. -T4F84 000:278.149 - 6.488ms returns 0x00 -T4F84 000:278.172 JLINK_ExecCommand("DisableConnectionTimeout", ...). -T4F84 000:278.192 ERROR: Unknown command -T4F84 000:278.211 - 0.023ms returns 0x01 -T4F84 000:278.225 JLINK_GetHardwareVersion() -T4F84 000:278.240 - 0.013ms returns 10000 -T4F84 000:278.253 JLINK_GetDLLVersion() -T4F84 000:278.266 - 0.012ms returns 86000 -T4F84 000:278.280 JLINK_GetOEMString(...) -T4F84 000:278.295 JLINK_GetFirmwareString(...) -T4F84 000:278.308 - 0.013ms -T4F84 000:278.323 JLINK_GetDLLVersion() -T4F84 000:278.336 - 0.012ms returns 86000 -T4F84 000:278.350 JLINK_GetCompileDateTime() -T4F84 000:278.363 - 0.012ms -T4F84 000:278.377 JLINK_GetFirmwareString(...) -T4F84 000:278.390 - 0.013ms -T4F84 000:278.404 JLINK_GetHardwareVersion() -T4F84 000:278.416 - 0.012ms returns 10000 -T4F84 000:278.430 JLINK_GetSN() -T4F84 000:278.443 - 0.012ms returns 831189195 -T4F84 000:278.457 JLINK_GetOEMString(...) -T4F84 001:591.260 JLINK_TIF_Select(JLINKARM_TIF_JTAG) -T4F84 001:591.814 - ***** Error: -T4F84 001:591.849 Debugger tries to select target interface JTAG. -This interface is not supported by the connected emulator. -Selection will be ignored by the DLL. -T4F84 001:591.872 - 0.617ms returns 0x01 -T4F84 001:591.925 JLINK_HasError() -T4F84 001:592.034 JLINK_SetSpeed(5000) -T4F84 001:592.052 - 0.019ms -T4F84 001:592.944 JLINK_HasError() -T4F84 001:592.975 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) -T4F84 001:592.991 - 0.015ms returns JLINKARM_RESET_TYPE_NORMAL -T4F84 001:593.006 JLINK_Reset() -T4F84 001:599.594 ConfigTargetSettings() start -T4F84 001:599.630 J-Link Script File: Executing ConfigTargetSettings() -T4F84 001:599.651 ConfigTargetSettings() end - Took 19us -T4F84 001:600.716 InitTarget() start -T4F84 001:600.741 J-Link Script File: Executing InitTarget() -T4F84 001:600.758 SWD selected. Executing JTAG -> SWD switching sequence. -T4F84 001:607.626 DAP initialized successfully. -T4F84 001:607.669 Determining TrustZone configuration... -T4F84 001:611.130 Secure Debug: Disabled (NSECSD) -T4F84 001:611.197 Instruction set simulation: Disabled -T4F84 001:611.242 Determining currently configured transfer type by reading the AHB-AP CSW register. -T4F84 001:613.761 Transfer type does not match DLM state. Changing transfer type accordingly. -T4F84 001:615.496 InitTarget() end - Took 14.7ms -T4F84 001:617.936 Found SW-DP with ID 0x5BA02477 -T4F84 001:626.098 DPIDR: 0x5BA02477 -T4F84 001:626.138 CoreSight SoC-400 or earlier -T4F84 001:626.159 Scanning AP map to find all available APs -T4F84 001:629.933 AP[2]: Stopped AP scan as end of AP map has been reached -T4F84 001:629.989 AP[0]: AHB-AP (IDR: 0x24770011, ADDR: 0x00000000) -T4F84 001:630.029 AP[1]: APB-AP (IDR: 0x44770002, ADDR: 0x01000000) -T4F84 001:630.069 Iterating through AP map to find AHB-AP to use -T4F84 001:634.015 AP[0]: Core found -T4F84 001:634.041 AP[0]: AHB-AP ROM base: 0xE00FF000 -T4F84 001:636.068 CPUID register: 0x410FC241. Implementer code: 0x41 (ARM) -T4F84 001:636.151 Found Cortex-M4 r0p1, Little endian. -T4F84 001:636.226 - ***** Warning: -T4F84 001:636.278 Identified core does not match configuration. (Found: Cortex-M4, Configured: Cortex-M33) -T4F84 001:637.135 -- Max. mem block: 0x000014E8 -T4F84 001:639.043 CPU_ReadMem(4 bytes @ 0xE000EDF0) -T4F84 001:641.077 CPU_ReadMem(4 bytes @ 0xE0002000) -T4F84 001:643.098 FPUnit: 6 code (BP) slots and 2 literal slots -T4F84 001:643.132 CPU_ReadMem(4 bytes @ 0xE000EDFC) -T4F84 001:645.110 CPU_ReadMem(4 bytes @ 0xE0001000) -T4F84 001:647.240 CPU_WriteMem(4 bytes @ 0xE0001000) -T4F84 001:649.591 CPU_ReadMem(4 bytes @ 0xE000ED88) -T4F84 001:651.701 CPU_WriteMem(4 bytes @ 0xE000ED88) -T4F84 001:653.795 CPU_ReadMem(4 bytes @ 0xE000ED88) -T4F84 001:656.071 CPU_WriteMem(4 bytes @ 0xE000ED88) -T4F84 001:658.139 CoreSight components: -T4F84 001:658.180 ROMTbl[0] @ E00FF000 -T4F84 001:658.205 CPU_ReadMem(64 bytes @ 0xE00FF000) -T4F84 001:664.432 CPU_ReadMem(32 bytes @ 0xE000EFE0) -T4F84 001:668.700 [0][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7 -T4F84 001:668.758 CPU_ReadMem(32 bytes @ 0xE0001FE0) -T4F84 001:672.935 [0][1]: E0001000 CID B105E00D PID 003BB002 DWT -T4F84 001:672.974 CPU_ReadMem(32 bytes @ 0xE0002FE0) -T4F84 001:677.021 [0][2]: E0002000 CID B105E00D PID 002BB003 FPB -T4F84 001:677.098 CPU_ReadMem(32 bytes @ 0xE0000FE0) -T4F84 001:681.268 [0][3]: E0000000 CID B105E00D PID 003BB001 ITM -T4F84 001:681.328 CPU_ReadMem(32 bytes @ 0xE0040FE0) -T4F84 001:685.511 [0][4]: E0040000 CID B105900D PID 000BB9A1 TPIU -T4F84 001:685.598 CPU_ReadMem(32 bytes @ 0xE0041FE0) -T4F84 001:689.784 [0][5]: E0041000 CID B105900D PID 000BB925 ETM -T4F84 001:689.833 CPU_ReadMem(32 bytes @ 0xE0042FE0) -T4F84 001:693.998 [0][6]: E0042000 CID B105900D PID 002BB908 CSTF -T4F84 001:694.074 CPU_ReadMem(32 bytes @ 0xE0043FE0) -T4F84 001:698.284 [0][7]: E0043000 CID B105900D PID 001BB961 TMC -T4F84 001:698.363 CPU_ReadMem(32 bytes @ 0xE0044FE0) -T4F84 001:702.487 [0][8]: E0044000 CID B105F00D PID 001BB101 TSG -T4F84 001:702.838 ResetTarget() start -T4F84 001:702.896 J-Link Script File: Executing ResetTarget() -T4F84 001:702.932 CPU_ReadMem(4 bytes @ 0xE000ED44) -T4F84 001:705.135 Reset: Halt core after reset via DEMCR.VC_CORERESET. -T4F84 001:705.189 CPU is running -T4F84 001:705.210 CPU_WriteMem(4 bytes @ 0xE000EDF0) -T4F84 001:707.307 CPU is running -T4F84 001:707.366 CPU_WriteMem(4 bytes @ 0xE000EDFC) -T4F84 001:710.222 Reset: Reset device via AIRCR.SYSRESETREQ. -T4F84 001:710.329 CPU is running -T4F84 001:710.390 CPU_WriteMem(4 bytes @ 0xE000ED0C) -T4F84 001:764.578 CPU_ReadMem(4 bytes @ 0xE000EDF0) -T4F84 001:766.822 CPU_ReadMem(4 bytes @ 0xE000EDF0) -T4F84 001:769.301 CPU is running -T4F84 001:769.328 CPU_WriteMem(4 bytes @ 0xE000EDFC) -T4F84 001:771.430 ResetTarget() end - Took 68.5ms -T4F84 001:771.455 Device specific reset executed. -T4F84 001:801.778 CPU_WriteMem(4 bytes @ 0xE0002000) -T4F84 001:804.065 CPU_ReadMem(4 bytes @ 0xE000EDFC) -T4F84 001:806.072 CPU_ReadMem(4 bytes @ 0xE0001000) -T4F84 001:808.178 - 215.171ms -T4F84 001:808.236 JLINK_GetId() -T4F84 001:809.053 - 0.816ms returns 0x5BA02477 -T4F84 001:818.094 JLINK_GetFirmwareString(...) -T4F84 001:818.132 - 0.038ms -T4F84 223:929.760 JLINK_Close() -T4F84 223:930.528 CPU_ReadMem(4 bytes @ 0xE0001000) -T4F84 223:931.472 CPU_WriteMem(4 bytes @ 0xE0001004) -T4F84 223:937.792 - 8.030ms -T4F84 223:937.840 -T4F84 223:937.872 Closed diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Release_Notes.html b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Release_Notes.html deleted file mode 100644 index 97c793085b1..00000000000 --- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Release_Notes.html +++ /dev/null @@ -1,292 +0,0 @@ - - - - - - - Release Notes for STM32L1xx CMSIS - - - - - -
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Release Notes for STM32L1xx CMSIS

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Copyright © 2009-2018 ARM Limited - STMicroelectronics
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Purpose

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This driver provides the CMSIS device for the stm32l1xx products. This covers:

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  • STM32L100xx devices
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  • STM32L151xx devices
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  • STM32L152xx devices
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  • STM32L162xx devices
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This driver is composed of the descriptions of the registers under “Include” directory.

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Various template file are provided to easily build an application. They can be adapted to fit applications requirements.

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  • Templates/system_stm32l1xx.c contains the initialization code referred as SystemInit.
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  • Startup files are provided as example for IAR©, KEIL© and SW4STM32©.
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  • Linker files are provided as example for IAR©, KEIL© and SW4STM32©.
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Update History

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Main Changes

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Maintenance release

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Contents

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  • Improve GCC startup files robustness.
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  • Add LSI maximum startup time datasheet value: LSI_STARTUP_TIME.
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  • Add atomic register access macros.
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  • Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS.
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  • Remove bit definition related to PF and PG ports from unsupported devices (L1xxxB devices).
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  • Fix SYSCFG_EXTICR1_EXTI3_PF and SYSCFG_EXTICR1_EXTI3_PG defines values.
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  • Update the hal_flash.h file to correctly support the FLASH_SIZE of cat.2 devices.
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Main Changes

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Maintenance release

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Contents

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  • All header files -
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    • Remove NVIC CMSIS bits definitions to avoid duplication with CMSIS Core V5.x
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    • Remove GPIOx BRR register from GPIO structure and bit definitions when not supported
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    • Add ADC VREFINT/TEMPSENSOR addresses definitions in line with products datasheets: -
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      • VREFINT_CAL_ADDR_CMSIS
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      • TEMPSENSOR_CAL1_ADDR_CMSIS
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      • TEMPSENSOR_CAL2_ADDR_CMSIS
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    • Remove unused IS_TIM_SYNCHRO_INSTANCE() assert macro
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    • Update IS_TIM_MASTER_INSTANCE with all supported instances.
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  • system_stm32l1xx.c file -
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    • Update SystemInit() API to don’t reset RCC registers to its reset values
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Main Changes

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Maintenance release

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Contents

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  • stm32l0xx.h -
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    • Align ErrorStatus typedef to common error handling
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  • startup_stm32l1xxxxx.s -
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    • Update header of startup files to remove build error with ARM compiler.
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  • Updated Update CMSIS Devices compliancy with MISRA C 2012 rules -
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    • Rule-10.6: Use ‘UL’ postfix for _Msk definitions and memory/peripheral base addresses
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  • Update CMSIS device description files according to latest version of HAL/LL drivers -
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    • Correct definitions for USB_COUNT3_TX_0 and USB_COUNT3_TX_1 registers
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    • Add IS_PCD_ALL_INSTANCE definition
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    • Add IS_TIM_SYNCHRO_INSTANCE macro definition
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    • Update macros definition for TIM instances
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Main Changes

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Patch release

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Contents

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  • Corrected devices supporting RI_HYSCR3, RI_HYSCR4, RI_ASMRx, RI_CMRx, RI_CICRx registers in CMSIS files.
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Main Changes

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Maintenance release

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Contents

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  • Removed DATE and VERSION fields from header files.
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Main Changes

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Maintenance release

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Contents

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  • Update CMSIS Devices compliancy with MISRA C 2004 rules: -
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    • MISRA C 2004 rule 10.6 (‘U’ suffix applied to all constants of ‘unsigned’ type)
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    • Update system_stm32l1xx.h/.c files.
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  • Align Bit definitions for SCB_CFSR register to be compliant with CMSIS Core V4.x and V5.x.
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  • Rename RTC_CR_BCK bits in RTC_CR register to RTC_CR_BKP, to be aligned with others series.
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  • Rename GPIO_AFRL_AFRLx and GPIO_AFRL_AFRHx bit definitions (from GPIO_AFRL/AFRH registers) to GPIO_AFRL_AFSELx.
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Main Changes

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Maintenance release

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Contents

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  • Add macros _Pos and _Msk for each constants. -
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    • For instance: -
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      • #define ADC_LTR_LT ((uint32_t)0x00000FFFU)
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    • Is now provided as: -
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      • #define ADC_LTR_LT_Pos (0U)
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      • #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos)
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      • #define ADC_LTR_LT ADC_LTR_LT_Msk
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  • IS_I2S_ALL_INSTANCE is now SPI2 and SPI3 instead of SPI1 and SPI2.
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  • Update the TIM_ARR_ARR and TIM_CNT_CNT as they support the 32 bit counter feature.
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  • Add macro IS_TIM_ETR_INSTANCE.
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  • Add RI_ASCR2_GR6_x with x = 1,2,3,4 if applicable.
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  • Add macro IS_SMBUS_ALL_INSTANCE.
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  • Set default value for SystemCoreClock to 2097000 instead of 32000000.
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  • Correct the presence of TIM9 for some devices inside various TIMER macros.
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Main Changes

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Maintenance release

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Contents

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  • Add HardFault_IRQn.
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  • Add BKP5R to BKP19R for RTC_TypeDef for stm32l151xba.
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  • Align bits naming on all stm32 families (ex: WWDG_CFR_WDGTB0 -> WWDG_CFR_WDGTB_0).
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  • Rename RCC_CFGR_MCO_DIVx to RCC_CFGR_MCOPRE_DIVx
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  • Align Bits naming on all stm32 families (ex: EXTI_IMR_MR0 –> EXTI_IMR_IM0)
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  • Update .icf file to correct empty linker ROM Start/End menu, under IAR, for stm32l151xdx, stm32l152xdx and stm32l162xdx.
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  • Rename RCC_CFGR_MCO_x to RCC_CFGR_MCOSEL_x to be aligned with Reference Manual.
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  • Update CMSIS drivers to apply MISRA C 2004 rule 10.6. (Use U postfix)
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  • Add defines FLASHSIZE_BASE and UID_BASE
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  • ADC common instance standardization (new define ADC1_COMMON)
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  • Remove bit GPIO_BRR_BR_x from Cat1 to Cat2 devices
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  • Literals “ADC_SMPR1_SMP27, ADC_SMPR1_SMP28, ADC_SMPR1_SMP29” are available on Cat4, Cat5 only.
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  • Add DMA_CNDTR_NDT, DMA_CPAR_PA and DMA_CMAR_MA definitions present on other stm32 families.
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  • Add defines to trig feature inside source code based on CMSIS content: -
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    • RTC_TAMPER1_SUPPORT
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    • RTC_TAMPER2_SUPPORT
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    • RTC_TAMPER3_SUPPORT
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    • RTC_BACKUP_SUPPORT
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    • RTC_WAKEUP_SUPPORT
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    • RTC_SMOOTHCALIB_SUPPORT
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    • RTC_SUBSECOND_SUPPORT.
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    • PWR_PVD_SUPPORT
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  • Set CMSIS variables PLLMulTable, AHBPrescTable and APBPrescTable as external in system_stm32l1xx.h.
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  • Bit 23 of all EXTI registers (IMR, EMR, …) is not supported on Cat 1 & 2.
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  • Correct a wrong values for RI_ASCR1_CH_27 to RI_ASCR1_CH_30
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  • Add defines for LCD capacitance
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  • Suppress SPI1 from I2S_ALL_INSTANCE
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Main Changes

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Maintenance release

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Contents

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  • Removing the __IO attribute for PLLMulTable and AHBPrescTable. This was leading to issue during C++ initialisation.
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  • IDR field of CRC_TypeDef changed from uint32_t to uint8_t to comply with register structure.
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  • Added TIM10 and TIM11 to IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE).
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  • Renaming USB_CNTR_LP_MODE to USB_CNTR_LPMODE for naming consistancy with other bits.
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  • Renaming USB_ISTR_PMAOVRM to USB_ISTR_PMAOVR to use the name of the bit in this register.
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Main Changes

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Maintenance release

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Contents

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  • Ensure compliancy w/ C++
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  • Minor update on Timer assert.
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  • Adding IS_AES_ALL_INSTANCE macro for product with AES.
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Main Changes

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Maintenance release

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Contents

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  • Add CMSIS files for new STM32L1 eXtended Devices : STM32L151xDX, STM32L152xDX and STM32L162xDX
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Main Changes

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Maintenance release

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Contents

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  • Update based on STM32Cube specification
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Other compatibilities

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  • This version has to be used only with STM32CubeL1 based development
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- - - diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Release_Notes.html b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Release_Notes.html deleted file mode 100644 index ff7924e26aa..00000000000 --- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Release_Notes.html +++ /dev/null @@ -1,1147 +0,0 @@ - - - - - - - Release Notes for STM32L1xx HAL Drivers - - - - - -
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Release Notes for STM32L1xx HAL Drivers

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Copyright © 2017 STMicroelectronics
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License

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Licensed by ST under BSD 3-Clause license (the "License"). You may not use this package except in compliance with the License. You may obtain a copy of the License at:

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https://opensource.org/licenses/BSD-3-Clause

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Purpose

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The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.

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The portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.

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The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provides a basic set of optimized and one shot services. The Low layer drivers, contrary to the HAL ones are not fully portable across the STM32 families; the availability of some functions depends on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:

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  • New set of inline functions for direct and atomic register access
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  • One-shot operations that can be used by the HAL drivers or from application level
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  • Full independence from HAL and standalone usage (without HAL drivers)
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  • Full features coverage of all the supported peripherals
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Update History

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Main Changes

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Maintenance release

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  • Patch release to to fix known defects and enhancements implementation.
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Contents

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  • HAL Generic update -
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    • Update HAL TimeBase TIM template for more robustness -
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      • Update Hal_Init_Tick() API to propoerty store the priority when using the non-default time base.
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  • HAL/LL TIM update -
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    • Previous release note corrected by removing reference to ChannelNState.
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    • Made TIM_DMADelayPulseCplt callback as a private function.
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    • Update HAL_TIMEx_OnePulseN_Start and HAL_TIMEx_OnePulseN_Stop (pooling and IT mode) to take into consideration all OutputChannel parameters.
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    • Update input capture measurement in DMA mode to avoid zero return values at high frequencies.
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    • Update LL_TIM_GetCounterMode() API to return the correct counter mode.
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    • Correct reversed description of TIM_LL_EC_ONEPULSEMODE One Pulse Mode.
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  • HAL/LL SPI update -
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    • Update LL_SPI_TransmitData8() API to avoid casting the result to 8 bits.
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    • Update to fix MISRA-C 2012 Rule-13.2.
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  • HAL/LL USART update -
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    • Remove useless check on maximum BRR value by removing IS_LL_USART_BRR_MAX() macro.
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  • HAL UART update -
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    • Correction on UART ReceptionType management in case of ReceptionToIdle API are called from RxEvent callback. Update UART polling and interruption processes to fix issues related to access out of user’s specified buffer. Fix wrong comment related to RX pin configuration within the description section. Enhance reception for idle services (ReceptionToIdle): -
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      • Add a new field (HAL_UART_RxTypeTypeDef) to the UART_HandleTypeDef structure to identify the type of ongoing reception.
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      • Add UART Reception Event Callback registration.
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      • Add reception specific APIs specific to reception for Idle transfer in different modes:
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      • HAL_UARTEx_ReceiveToIdle(): Receive an amount of data in blocking mode until either the expected number of data is received or an IDLE event occurs.
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      • HAL_UARTEx_ReceiveToIdle_IT(): Receive an amount of data in interrupt mode until either the expected number of data is received or an IDLE event occurs.
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      • HAL_UARTEx_ReceiveToIdle_DMA(): Receive an amount of data in DMA mode until either the expected number of data is received or an IDLE event occurs.
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      • Update HAL_UART_Receive(), HAL_UART_Receive_IT() and HAL_UART_Receive_DMA() APIs to support the new enhancement of ReceptionToIdle.
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  • HAL SMARTCARD update -
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    • Fix typos in the SMARTCARD State definition description.
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  • HAL IRDA update -
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    • Fix typos in the IRDA State definition description.
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  • HAL RTC update -
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    • New APIs to subtract or add one hour to the calendar in one single operation without going through the initialization procedure (Daylight Saving): -
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      • HAL_RTC_DST_Add1Hour()
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      • HAL_RTC_DST_Sub1Hour()
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      • HAL_RTC_DST_SetStoreOperation()
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      • HAL_RTC_DST_ClearStoreOperation()
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      • HAL_RTC_DST_ReadStoreOperation()
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      • DayLightSaving and StoreOperation interfaces from RTC_TimeTypeDef type and HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H() and HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H() macros are now deprecated.
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      • -
    • Fix the wait for the RSF bit to be cleared in the LL_RTC_WaitForSynchro function.
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    • Correct month management in IS_LL_RTC_MONTH() macro.
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    • Update __HAL_RTC_…(__HANDLE__, …) macros to access registers through (__HANDLE__)->Instance pointer and avoid “unused variable” warnings.
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  • LL FMC_LL update -
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    • Fix compilation warning with gcc -Wpedantic compiler option
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  • HAL SDMMC update -
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    • Update the definition of SDMMC_DATATIMEOUT constant in order to allow the user to redefine it in his proper application.
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    • SD_FindSCR() updated to resolve an issue with FIFO blocking when reading.
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    • Update the definition of SDMMC_DATATIMEOUT constant in order to allow the user to redefine it in his proper application.
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    • Add the block size settings in the initialization functions and remove it from read/write transactions to avoid repeated and inefficient reconfiguration.
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    • Update read/write functions in DMA mode in order to force the DMA direction.
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    • Deploy new functions MMC_ReadExtCSD() and SDMMC_CmdSendEXTCSD () that read and check the sectors number of the device in order to resolve the issue of wrongly reading big memory size.
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  • HAL FLASH update -
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    • Update FLASH_SetErrorCode() to correctly handle the SIZERR flag.
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  • HAL USB_FS update -
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    • HAL PCD: add fix transfer complete for IN Interrupt transaction in single buffer mode.
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  • HAL OPAMP update -
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    • Fix CodeSonar error.
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    • Update HAL_OPAMP_SelfCalibrate() API to avoid wrong configuration of trimming value “n” and “p”.
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  • HAL I2C update -
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    • Update to avoid I2C interrupt in endless loop: -
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      • Update HAL_I2C_Master_Transmit_IT(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA() and HAL_I2C_Master_Receive_DMA() APIs to unlock the I2C peripheral before generating the start.
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    • Update the management of (hi2c->hdmatx!=NULL) & (hi2c->hdmarx!=NULL) check.
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    • Update to prevent several calls of Start bit: -
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      • Update I2C_MemoryTransmit_TXE_BTF() API to increment EventCount.
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    • Update to use the right macro to clear I2C ADDR flag inside I2C_Slave_ADDR() API as it’s indicated in the reference manual.
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    • Update HAL_I2C_EV_IRQHandler() and I2C_MasterTransmit_BTF() APIs to fix an issue where the transfer of the first few bytes to an I2C memory fails.
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  • HAL/LL ADC update -
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    • Update HAL_ADC_Stop_DMA() API to check if DMA state is Busy before calling HAL_DMA_Abort() API to avoid DMA internal error.
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    • Update HAL ADC driver to add include of the LL ADC driver.
      • -
    • Update timeout mechanism to avoid false timeout detection in case of preemption.
      • -
    • Update LL_ADC_REG_Init() API to avoid enabling continuous mode and discontinuous mode simultaneously.
      • -
    • -
  • HAL WWDG update -
      -
    • Update HAL driver description.
      • -
    • -
  • HAL IWDG update -
      -
    • Update HAL_IWDG_Init() API in order to fix HAL_GetTick() timeout vulnerability issue.
      • -
    • Add LSI startup time in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT).
      • -
    • -
  • HAL EXTI update -
      -
    • Update macros using LINE as a macro parameter to use EXTI_LINE instead to resolve parameter conflicts with standard C usage.
      • -
    • Update HAL_EXTI_GetConfigLine() API to set default configuration value of Trigger and GPIOSel before checking each corresponding registers.
      • -
    • -
-
-
-
- -
-

Main Changes

-

Maintenance release

-
    -
  • General updates to fix known defect.
    • -
-

Contents

-
    -
  • HAL/LL I2C driver -
      -
    • Update to fix hardfault issue with HAL_I2C_Mem_Write_DMA() API: -
        -
      • Abort the right ongoing DMA transfer when memory write access request operation failed: fix typo “hdmarx” replaced by “hdmatx”
        • -
      • -
    • -
-
-
-
- -
-

Main Changes

-

Maintenance release

-
    -
  • Patch release to fix issue in I2C HAL driver
    • -
-

Contents

-
    -
  • HAL I2C driver -
      -
    • Update I2C_MasterReceiveRXNE() static API to avoid set the STOP bit again after the bit clearing by Hardware during the masking operation. -
        -
      • Add new API I2C_WaitOnSTOPRequestThroughIT() to wait for stop bit.
        • -
      • -
    • -
-
-
-
- -
-

Main Changes

-

Maintenance release

-
    -
  • Add new HAL EXTI driver
    • -
  • General updates to fix known defects and enhancements implementation
    • -
-

Contents

-
    -
  • HAL driver -
      -
    • Enhance HAL_SetTickFreq() API robustness -
        -
      • Restore previous tick frequency when a wrong tick initialization occurs.
        • -
      • -
    • -
  • LL ADC driver -
      -
    • Fix ADC TEMPSENSOR/VREFINT calibration addresses
      • -
    • -
  • HAL/LL GPIO driver -
      -
    • Update HAL_GPIO_TogglePin() API to allow the toggling of many pins
      • -
    • Update GPIO initialization sequence to avoid unwanted pulse on GPIO Pin’s
      • -
    • -
  • HAL EXTI driver -
      -
    • Add new HAL_EXTI driver.
      • -
    • -
  • HAL FLASH driver -
      -
    • Fix assert compilation error with HAL_FLASHEx_DATAEEPROM_Erase() API.
      • -
    • -
  • HAL/LL I2C driver -
      -
    • Update HAL_I2C_ER_IRQHandler() API to fix acknowledge failure issue with I2C memory IT processes -
        -
      • Add stop condition generation when NACK occurs.
        • -
      • -
    • Update I2C_DMAXferCplt(), I2C_DMAError() and I2C_DMAAbort() APIs to fix hardfault issue when hdmatx and hdmarx parameters in i2c handle aren’t initialized (NULL pointer).
      • -
    • Update HAL_I2C_Init() API to force software reset before setting new I2C configuration
      • -
    • Update HAL I2C processes to report ErrorCode when wrong I2C start condition occurs -
        -
      • Add new ErrorCode define: HAL_I2C_WRONG_START
        • -
      • Set ErrorCode parameter in I2C handle to HAL_I2C_WRONG_START
        • -
      • -
    • Update sequential APIs to avoid requesting a START when a STOP condition is not fully treated -
        -
      • Wait the end of STOP treatment by polling (with a timeout) the STOP bit on Control register CR1
        • -
      • -
    • -
  • HAL/LL I2S driver -
      -
    • Update HAL_I2S_DMAStop() API to be more safe -
        -
      • Add a check on BSY, TXE and RXNE flags before disabling the I2S
        • -
      • -
    • Update HAL_I2S_DMAStop() API to fix multi-call transfer issue(to avoid re-initializing the I2S for the next transfer). -
        -
      • Add __HAL_I2SEXT_FLUSH_RX_DR() and __HAL_I2S_FLUSH_RX_DR() macros to flush the remaining data inside DR registers.
        • -
      • Add new ErrorCode define: HAL_I2S_ERROR_BUSY_LINE_RX
        • -
      • -
    • -
  • HAL IRDA driver -
      -
    • Update IRDA interruption handler to manage correctly the overrun interrupt -
        -
      • Add in the HAL_IRDA_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.
        • -
      • -
    • -
  • HAL SMARTCARD driver -
      -
    • Update SMARTCARD interruption handler to manage correctly the overrun interrupt -
        -
      • Add in the HAL_SMARTCARD_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.
        • -
      • -
    • Update SMARTCARD transmission and reception API to handle memory corruption -
        -
      • HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Receive()
        • -
      • SMARTCARD_Transmit_IT(), SMARTCARD_Receive_IT()
        • -
      • -
    • -
  • HAL/LL SPI driver -
      -
    • Update to implement Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode.
      • -
    • Update SPI_DMAReceiveCplt() API to handle efficiently the repeated transfers. -
        -
      • To avoid setting the BaudRatePrescaler in case of Slave Motorola Mode
        • -
      • Use the bit-mask for SPI configuration
        • -
      • -
    • Update Transmit/Receive processes in half-duplex mode -
        -
      • Disable the SPI instance before setting BDIOE bit
        • -
      • -
    • Fix wrong timeout management -
        -
      • Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled
        • -
      • -
    • -
  • HAL/LL TIM driver -
      -
    • Align HAL/LL TIM driver with latest updates and enhancements
      • -
    • Add new macros to enable and disable the fast mode when using the one pulse mode to output a waveform with a minimum delay -
        -
      • __HAL_TIM_ENABLE_OCxFAST() and __HAL_TIM_DISABLE_OCxFAST().
        • -
      • -
    • Update Encoder interface mode to keep TIM_CCER_CCxNP bits low -
        -
      • Add TIM_ENCODERINPUTPOLARITY_RISING and TIM_ENCODERINPUTPOLARITY_FALLING definitions to determine encoder input polarity.
        • -
      • Add IS_TIM_ENCODERINPUT_POLARITY() macro to check the encoder input polarity.
        • -
      • Update HAL_TIM_Encoder_Init() API
        • -
      • Replace IS_TIM_IC_POLARITY() macro by IS_TIM_ENCODERINPUT_POLARITY() macro.
        • -
      • -
    • Fix bug when using multiple DMA request to different channels of same timer -
        -
      • Introduce DMA burst state management mechanism -
          -
        • Add a new structure for DMA Burst States definition : HAL_TIM_DMABurstStateTypeDef
          • -
        • Update __HAL_TIM_RESET_HANDLE_STATE to support DMABurstState
          • -
        • Add a new API HAL_TIM_DMABurstState() to get the actual state of a DMA burst operation
          • -
        • Add DMABurstState, the DMA burst operation state, in the TIM_HandleTypeDef structure
          • -
        • Add new API TIM_DMAErrorCCxN() for TIM DMA error callback (complementary channel)
          • -
        • Add new API TIM_DMADelayPulseNCplt() for TIM DMA Delay Pulse complete callback (complementary channel)
          • -
        • -
      • -
    • Implement TIM channel state management mechanism -
        -
      • Add new macro -
          -
        • TIM_CHANNEL_STATE_SET_ALL
          • -
        • TIM_CHANNEL_STATE_SET
          • -
        • TIM_CHANNEL_STATE_GET
          • -
        • -
      • Add new API HAL_TIM_GetActiveChannel()
        • -
      • Add new API HAL_TIM_GetChannelState() to get actual state of the TIM channel
        • -
      • Add a new structure for TIM channel States definition : HAL_TIM_ChannelStateTypeDef
        • -
      • Update __HAL_TIM_RESET_HANDLE_STATE to support ChannelState
        • -
      • Add a new element in the TIM_HandleTypeDef structure : ChannelState to manage TIM channel operation state
        • -
      • -
    • Update HAL_TIMEx_MasterConfigSynchronization() API to avoid functional errors and assert fails when using some TIM instances as input trigger. -
        -
      • Replace IS_TIM_SYNCHRO_INSTANCE() macro by IS_TIM_MASTER_INSTANCE() macro.
        • -
      • Add IS_TIM_SLAVE_INSTANCE() macro to check on TIM_SMCR_MSM bit.
        • -
      • -
    • Remove ‘register’ storage class specifier from LL TIM driver.
      • -
    • Add new API HAL_TIM_DMABurst_MultiWriteStart() allowing to configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
      • -
    • Add new API HAL_TIM_DMABurst_MultiReadStart() allowing to configure the DMA Burst to transfer Data from the TIM peripheral to the memory
      • -
    • -
  • HAL RCC driver -
      -
    • Fix extra parentheses compilation warnings with clang compiler
      • -
    • Update HAL_RCC_GetSysClockFreq() API to avoid the risk of rounding overflow.
      • -
    • -
  • HAL/LL UART driver -
      -
    • Update UART polling processes to handle efficiently the Lock mechanism -
        -
      • Move the process unlock at the top of the HAL_UART_Receive() and HAL_UART_Transmit() API.
        • -
      • -
    • Update UART interruption handler to manage correctly the overrun interrupt -
        -
      • Add in the HAL_UART_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.
        • -
      • -
    • Update UART BRR calculation for ROM size gain
      • -
    • -
  • HAL/LL USART driver -
      -
    • Update some API description -
        -
      • HAL_USART_Transmit() / HAL_USART_Transmit_IT() -
          -
        • HAL_USART_Receive() / HAL_USART_Receive_IT()
          • -
        • HAL_USART_TransmitReceive() / HAL_USART_TransmitReceive_IT()
          • -
        • HAL_USART_Transmit_DMA() / HAL_USART_Receive_DMA() / HAL_USART_TransmitReceive_DMA()
          • -
        • -
      • -
    • Update USART interruption handler to manage correctly the overrun interrupt -
        -
      • Add in the HAL_USART_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.
        • -
      • -
    • -
  • HAL/LL USB driver -
      -
    • Bug fix: USB_ReadPMA() and USB_WritePMA() by ensuring 16-bits access to USB PMA memory
      • -
    • Bug fix: correct USB RX count calculation
      • -
    • Fix USB Bulk transfer double buffer mode
      • -
    • Remove register keyword from USB defined macros as no more supported by C++ compiler
      • -
    • Minor rework on USBD_Start() and USBD_Stop() APIs: stopping device will be handled by HAL_PCD_DeInit() API.
      • -
    • -
  • LL UTILS driver -
      -
    • Add new LL API LL_SetFlashLatency() to set Flash latency.
      • -
    • -
-
-
-
- -
-

Main Changes

-

Maintenance release

-
    -
  • Add support of HAL callback registration feature
    • -
  • Add several enhancements implementation
    • -
  • Fix known defects to be aligned with others STM32 series
    • -
-

Contents

-
    -
  • HAL/LL generic -
      -

    • Add support of HAL callback registration feature

      • -

    • The feature disabled by default is available for the following HAL drivers:

      -
        -
      • ADC, COMP, DAC, I2C, I2S, IRDA, LPTIM, PCD, RNG, RTC, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART and WWDG
        • -
      • -

    • The feature may be enabled individually per HAL PPP driver by setting the corresponding definition USE_HAL_PPP_REGISTER_CALLBACKS to 1U in stm32l1xx_hal_conf.h project configuration file (template file stm32l1xx_hal_conf_template.h available from Drivers/STM32L1xx_HAL_Driver/Inc)

      • -

    • Once enabled, the user application may resort to HAL_PPP_RegisterCallback() to register specific callback function(s) and unregister it(them) with HAL_PPP_UnRegisterCallback().

      • -

    • Update HAL/LL Driver compliancy with MISRA C 2012 rules

      • -

    • stm32l1xx_hal_def.h

      -
        -
      • Update file to avoid compiler warnings from __packed definitions
        • -
      • Update UNUSED() macro to fix compilation warning with g++ compiler
        • -
      • Replace include stdio.h by stddef.h
        • -
      • Update __RAM_FUNC define to not impose function type
        • -
      • -
    • -
  • HAL driver -
      -
    • Add HAL_GetUIDw0(), HAL_GetUIDw1() and HAL_GetUIDw2() for 96-bit UID
      • -
    • Modify default HAL_Delay implementation to guarantee minimum delay
      • -
    • Update Doxygen tags in macros description to have generate correct CHM format
      • -
    • Update implementation of HAL_SetTickFreq() function
      • -
    • -
  • HAL ADC driver -
      -
    • Add callback registration feature -
        -
      • Add HAL_ADC_RegisterCallback() and HAL_ADC_UnRegisterCallback() APIs
        • -
      • Add callback identifiers in HAL_ADC_CallbackIDTypeDef enumerated typedef
        • -
      • -
    • Remove unused code in HAL_ADC_Stop_DMA() function.
      • -
    • -
  • HAL/LL COMP driver -
      -
    • Add callback registration feature -
        -
      • Add HAL_COMP_RegisterCallback() and HAL_COMP_UnRegisterCallback() APIs
        • -
      • Add callback identifiers in HAL_COMP_CallbackIDTypeDef enumerated typedef
        • -
      • -
    • Update define for COMP_NONINVERTINGINPUT_PA6
      • -
    • Update define for LL_COMP_INPUT_PLUS_IO11
      • -
    • Correct issue with input plus COMP1 in windowmode
      • -
    • Add missing LL function for COMP_CSR->VREFOUTEN bit
      • -
    • -
  • HAL CRC driver -
      -
    • Align HAL/LL CRC driver with latest updates and enhancements
      • -
    • Update CRC driver to remove not applicable InputDataFormat
      • -
    • -
  • HAL DAC driver -
      -
    • Align HAL/LL DAC driver with latest updates and enhancements
      • -
    • Add callback registration feature -
        -
      • Add HAL_DAC_RegisterCallback() and HAL_DAC_UnRegisterCallback() APIs
        • -
      • Add callback identifiers in HAL_DAC_CallbackIDTypeDef enumerated typedef
        • -
      • -
    • -
  • HAL/LL DMA driver -
      -
    • Align HAL/LL DMA drivers with latest updates and enhancements
      • -
    • Add missing APIs to register/unregister DMA callbacks
      • -
    • -
  • HAL FLASH driver -
      -
    • Update HAL_FLASH_Unlock() and HAL_FLASH_OB_Unlock() in order the functions do not return an error when already unlocked
      • -
    • Update HAL_FLASHEx_ProgramParallelHalfPage(), HAL_FLASHEx_HalfPageProgram(), HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(), HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord() so that the functions should not be restricted to privilege mode
      • -
    • Update FLASH_OB_GetRDP() function to return the correct RDP level
      • -
    • Update FLASH_OB_GetUser() and FLASH_OB_UserConfig() to use the combination of specific masks FLASH_OBR_IWDG_SW, FLASH_OBR_nRST_STOP and FLASH_OBR_nRST_STDBY
      • -
    • -
  • HAL GPIO driver -
      -
    • Update HAL_GPIO_DeInit() function to perform EXTI configuration reset before GPIO configuration
      • -
    • Improve robustness of HAL_GPIO_TogglePin() function
      • -
    • Update definition of IS_GPIO_PIN to remove compilation warning with IAR tool chain
      • -
    • Update usage description for HAL_GPIO_LockPin() to justify an unused read of a register
      • -
    • -
  • HAL/LL I2C driver -
      -
    • Align HAL/LL I2C driver with latest updates and enhancements
      • -
    • Add callback registration feature -
        -
      • Add HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), HAL_I2C_RegisterAddrCallback() and HAL_I2C_UnRegisterAddrCallback() APIs
        • -
      • Add callback identifiers in HAL_I2C_CallbackIDTypeDef enumerated typedef
        • -
      • -
    • Add I2C_FIRST_AND_NEXT_FRAME for I2C Sequential transfer options: allow to manage a sequence with start condition, address and data to transfer without a final stop condition, an then permit a call to the same master sequential interface several times.
      • -
    • Add reset on slave LISTEN_TX state in case of direction change
      • -
    • Remove unused variable in HAL_I2C_Slave_Transmit_IT/DMA() and HAL_I2C_Slave_Receive_IT/DMA() functions to avoid warning compilation with linux tool chain
      • -
    • Add I2C slave enhancement with the functions: HAL_I2C_Master_Sequential_Transmit_DMA(), HAL_I2C_Master_Sequential_Receive_DMA(), HAL_I2C_Slave_Sequential_Transmit_DMA(), HAL_I2C_Slave_Sequential_Receive_DMA() functions
      • -
    • Update HAL_I2C_Master_Seq_Transmit_IT(DMA), HAL_I2C_Master_Seq_Receive_IT(DMA) functions. -
        -
      • Update comments about Device Address parameter (DevAddress) description in I2C functions header
        • -
      • Add restart condition for each call of HAL_I2C_Master_Seq_xxxx_IT
        • -
      • Fix MISRAC2012 issue -
          -
        • Renamed HAL_I2C_Master_Sequential_Transmit_IT(DMA) to HAL_I2C_Master_Seq_Transmit_IT(DMA)
          • -
        • Renamed HAL_I2C_Master_Sequential_Receive_IT(DMA) to HAL_I2C_Master_Seq_Receive_IT(DMA)
          • -
        • Renamed HAL_I2C_Slave_Sequential_Transmit_IT(DMA) to HAL_I2C_Slave_Seq_Transmit_IT(DMA)
          • -
        • Renamed HAL_I2C_Slave_Sequential_Receive_IT(DMA) to HAL_I2C_Slave_Seq_Receive_IT(DMA)
          • -
        • -
      • -
    • Update ErrorCode to correct wrong returned value after waiting until BUSY flag is reset
      • -
    • -
  • HAL I2S driver -
      -
    • Align HAL I2S driver with latest updates and enhancements
      • -
    • Add callback registration feature -
        -
      • Add HAL_I2S_RegisterCallback() and HAL_I2S_UnRegisterCallback() APIs
        • -
      • Add callback identifiers in HAL_I2S_CallbackIDTypeDef enumerated typedef
        • -
      • -
    • -
  • HAL IRDA driver -
      -
    • Align HAL IRDA driver with latest updates and enhancements
      • -
    • Add callback registration feature -
        -
      • Add HAL_IRDA_RegisterCallback() and HAL_IRDA_UnRegisterCallback() APIs
        • -
      • Add callback identifiers in HAL_IRDA_CallbackIDTypeDef enumerated typedef
        • -
      • -
    • Review IRDA state machine to avoid cases where IRDA state is overwritten by IRDA IRQ
      • -
    • Implement new APIs for HAL IRDA Abort management: -
        -
      • HAL_IRDA_Abort(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortReceive(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_AbortReceive_IT()
        • -
      • -
    • Optimize WaitOnFlag management in IRDA_Transmit() function
      • -
    • Optimize all HAL IRQ Handler routines
      • -
    • Optimize HAL IRDA to avoid using macros as argument of function calls
      • -
    • -
  • HAL OPAMP driver -
      -
    • Align HAL OPAMP driver with latest updates and enhancements
      • -
    • Add callback registration feature -
        -
      • Add HAL_OPAMP_RegisterCallback() and HAL_OPAMP_UnRegisterCallback() APIs
        • -
      • Add callback identifiers in HAL_OPAMP_CallbackIDTypeDef enumerated typedef
        • -
      • -
    • -
  • HAL/LL RCC driver -
      -
    • Replace __HAL_RCC_CRYP_CLK_ENABLE by __HAL_RCC_AES_CLK_ENABLE
      • -
    • Change HAL_RCC_DeInit() to HAL_StatusTypeDef
      • -
    • Update HAL_RCC_DeInit() and LL_RCC_DeInit() to also clear interrupts and reset flags
      • -
    • Update HAL_RCC_DeInit() and LL_RCC_DeInit() to add check on PLLRDY before clearing PLLCFGR register
      • -
    • Update HAL_RCC_DeInit() to insure that default MSI range is set prior to enable MSI and use it as SYSCLK source
      • -
    • Update LL_RCC_DeInit() to add the key word volatile and avoid compilation issue with gcc -O3
      • -
    • Remove LSI_VALUE definition from stm32l1xx_hal_rcc_ex.h to have it declared in HAL Generic stm32l1xx_hal_conf_template.h/stm32l1xx_hal_conf.h as other families STM32 HAL drivers
      • -
    • Correct LSI_VALUE LL definition in stm32l1xx_ll_rcc.h
      • -
    • Update HAL_RCC_OscConfig() to avoid MCU hangs after some stop/wakeup cycles
      • -
    • Replace all calls to HAL_InitTick(TICK_INT_PRIORITY) with HAL_InitTick(uwTickPrio) to avoid Tick priority overwrite
      • -
    • Add new LL_RCC_PLL_SetMainSource macro to set the PLL source without enabling any PLL
      • -
    • -
  • HAL/LL RTC driver -
      -
    • Align HAL/LL RTC driver with latest updates and enhancements
      • -
    • Remove unused value in HAL_RTC_SetTime() function
      • -
    • Update implementation of LL_RTC_DATE_Get() function
      • -
    • Correct issue in the argument of LL_RTC_ALMB_SetDay() function
      • -
    • Add callback registration feature -
        -
      • Add HAL_RTC_RegisterCallback() and HAL_RTC_UnRegisterCallback() APIs
        • -
      • Add callback identifiers in HAL_RTC_CallbackIDTypeDef enumerated typedef
        • -
      • -
    • -
  • HAL SDMMC driver -
      -
    • Align HAL SDMMC driver with latest updates and enhancements
      • -
    • Due to limitation SDIO hardware flow control indicated in Errata Sheet : -
        -
      • In 4-bits bus wide mode, do not use the HAL_SD_WriteBlocks_IT() or HAL_SD_WriteBlocks() APIs otherwise underrun will occur and there is not possibility to activate the flow control
        • -
      • Use DMA mode when using 4-bits bus wide mode or decrease the frequency
        • -
      • -
    • Add callback registration feature -
        -
      • Add HAL_SD_RegisterCallback(),HAL_SD_UnRegisterCallback(), HAL_SD_RegisterTransceiverCallback() and HAL_SD_UnRegisterTransceiverCallback APIs
        • -
      • Add callback identifiers in HAL_SD_CallbackIDTypeDef enumerated typedef
        • -
      • -
    • -
  • HAL SMARTCARD driver -
      -
    • Align HAL SMARTCARD driver with latest updates and enhancements
      • -
    • Add callback registration feature -
        -
      • Add HAL_SMARTCARD_RegisterCallback() and HAL_SMARTCARD_UnRegisterCallback() APIs
        • -
      • Add callback identifiers in HAL_SMARTCARD_CallbackIDTypeDef enumerated typedef
        • -
      • -
    • Review SMARTCARD state machine to avoid cases where SMARTCARD state is overwritten by SMARTCARD IRQ
      • -
    • Implement new APIs for HAL SMARTCARD Abort management: -
        -
      • HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_AbortReceive_IT()
        • -
      • -
    • Optimize WaitOnFlag management in SMARTCARD_Transmit() function
      • -
    • Optimize all HAL IRQ Handler routines
      • -
    • Optimize HAL SMARTCARD to avoid using macros as argument of function calls
      • -
    • -
  • HAL/LL SPI driver -
      -
    • Align HAL/LL SPI driver with latest updates and enhancements
      • -
    • Backward compatibility: -
        -
      • Remove stm32l1xx_hal_spi_ex.c/.h files and move the functions/definitions to stm32l1xx_hal_spi.c/.h
        • -
      • The user projects must be updated to remove stm32l1xx_hal_spi_ex.c/.h from files list
        • -
      • -
    • Fix issue in HAL_SPI_Transmit() and HAL_SPI_TransmitReceive() functions
      • -
    • Update HAL/LL SPI driver to manage TI mode not supported by all STM32L1xx devices
      • -
    • Add callback registration feature -
        -
      • Add HAL_SPI_RegisterCallback() and HAL_SPI_UnRegisterCallback() APIs
        • -
      • Add callback identifiers in HAL_SPI_CallbackIDTypeDef enumerated typedef
        • -
      • -
    • -
  • HAL/LL TIM driver -
      -
    • Align HAL/LL TIM driver with latest updates and enhancements
      • -
    • Add support of preload control in HAL TIM API
      • -
    • Remove TIM_CHANNEL_4 argument from description of HAL_TIMEx_OCN_xxx() and HAL_TIMEx_PWMN_xxxx() functions
      • -
    • Update comments in HAL/LL functions to describe how to switch from Center Aligned counter mode to Edge Aligned Down mode
      • -
    • Remove OCIdleState from TIM_OC_InitTypeDef and TIM_OnePulse_InitTypeDef
      • -
    • Update behavior of LL_TIM_EnableUpdateEvent() and LL_TIM_DisableUpdateEvent() functions
      • -
    • Add callback registration feature + Add HAL_TIM_RegisterCallback() and HAL_TIM_UnRegisterCallback() APIs + Add callback identifiers in HAL_TIM_CallbackIDTypeDef enumerated typedef
      • -
    • -
  • HAL UART/USART driver -
      -
    • Align HAL UART/USART driver with latest updates and enhancements
      • -
    • Add callback registration feature -
        -
      • Add HAL_UART/USART_RegisterCallback() and HAL_UART/USART_UnRegisterCallback() APIs
        • -
      • Add callback identifiers in HAL_UART/USART_CallbackIDTypeDef enumerated typedef
        • -
      • -
    • Add missing __IO in UART/USART_HandleTypeDef definition (for TxXferCount and RxXferCount)
      • -
    • Review UART/USART state machine to avoid cases where UART/USART state is overwritten by UART/USART IRQ
      • -
    • Implement new APIs for HAL UART/USART Abort management: -
        -
      • HAL_UART/USART_Abort(), HAL_UART/USART_AbortTransmit(), HAL_UART/USART_AbortReceive(), HAL_UART/USART_Abort_IT(), HAL_UART/USART_AbortTransmit_IT(), HAL_UART/USART_AbortReceive_IT()
        • -
      • -
    • Optimize WaitOnFlag management in UART/USART_Transmit() function
      • -
    • Optimize all HAL IRQ Handler routines
      • -
    • Align __HAL_UART_GET_IT and __HAL_UART_GET_IT_SOURCE with other series
      • -
    • Optimize HAL UART/USART to avoid using macros as argument of function calls
      • -
    • Update USART BRR calculation
      • -
    • -
  • HAL USB driver -
      -
    • Align HAL USB driver with latest updates and enhancements
      • -
    • Upgrade to USB Device Library v2.5.2
      • -
    • Fix issue with Buffer Overflow in PCD_ReadPMA() function
      • -
    • Add callback registration feature -
        -
      • Add HAL_PCD_RegisterCallback(),HAL_PCD_UnRegisterCallback(), HAL_PCD_RegisterDataOutStageCallback(), HAL_PCD_UnRegisterDataOutStageCallback(), HAL_PCD_RegisterDataInStageCallback(), HAL_PCD_UnRegisterDataInStageCallback(), HAL_PCD_RegisterIsoOutIncpltCallback(), HAL_PCD_UnRegisterIsoOutIncpltCallback(), HAL_PCD_RegisterIsoInIncpltCallback(), HAL_PCD_UnRegisterIsoInIncpltCallback(), HAL_PCD_RegisterBcdCallback(), HAL_PCD_UnRegisterBcdCallback(), HAL_PCD_RegisterLpmCallback() and HAL_PCD_UnRegisterLpmCallback() APIs
        • -
      • Add callback identifiers in HAL_PCD_CallbackIDTypeDef enumerated typedef
        • -
      • -
    • -
  • LL UTILS driver -
      -
    • Correct LL_GetUID_Word2 function to fix error in UID flash location
      • -
    • Fix mismatch return type in LL_GetPackageType(void)
      • -
    • -
  • HAL WWDG driver -
      -
    • Align HAL WWDG driver with latest updates and enhancements
      • -
    • Add callback registration feature -
        -
      • Add HAL_WWDG_RegisterCallback() and HAL_WWDG_UnRegisterCallback() APIs
        • -
      • Add callback identifiers in HAL_WWDG_CallbackIDTypeDef enumerated typedef
        • -
      • -
    • -
-
-
-
- -
-

Main Changes

-

Patch release

-

Contents

-
    -
  • HAL/LL generic -
      -
    • Remove DATE and VERSION fields from header files
      • -
    • Update CHM User Manual for Drivers/STM32L1xx_HAL_Driver
      • -
    • -
-
-
-
- -
-

Main Changes

-

Maintenance release

-

Contents

-
    -
  • HAL/LL generic -
      -
    • Enhanced HAL delay and time base implementation: -
        -
      • Added new templates stm32l1xx_hal_timebase_tim_template.c which can be used to override the native HAL time base functions (defined as weak) and to use Timer as time base tick source.
        • -
      • For more details about the usage of these drivers, please refer to HAL_TimeBase_TIM examples and FreeRTOS-based applications.
        • -
      • -
    • Updated HAL Driver compliancy with MISRA C 2004 rules: -
        -
      • MISRA C 2004 rule 10.3 (illegal explicit conversion from type “unsigned int” to "uint16_t *)
        • -
      • MISRA C 2004 rule 10.5 (if the bitwise operators ~ and << are applied to an operand of underlying type ‘unsigned char’ or ‘unsigned short’, the result shall be immediately cast to the underlying type of the operand)
        • -
      • MISRA C 2004 rule 11.4 (cast should not be performed between a pointer to object type and a different pointer to object type)
        • -
      • MISRA C 2004 rule 12.6 (logical operators should not be confused with bitwise operators)
        • -
      • MISRA C 2004 rule 12.7 (bitwise operations not performed on signed integer types)
        • -
      • MISRA C 2004 rule 14.3 (a null statement shall only occur on a line by itself)
        • -
      • -
    • Removed (uint32_t) cast when “U” is used in order to avoid double definitions.
      • -
    • Replaced hard coded POSITION definition in HAL/LL drivers by the associated PPP_xxx_pos CMSIS define.
      • -
    • -
  • HAL CORTEX -
      -
    • Updated HAL_MPU_Disable function to clear whole CR register.
      • -
    • -
  • LL DMA -
      -
    • Improved CPAR and CMAR registers access in LL_DMA_ConfigAddresses function.
      • -
    • -
  • HAL FLASH -
      -
    • Updated HAL_FLASHEx_Erase_IT() function to check the FLASH is ready before starting Erase by IT.
      • -
    • -
  • HAL/LL GPIO -
      -
    • Renamed GPIO_AFRL_AFRLx and GPIO_AFRL_AFRHx bit to GPIO_AFRL_AFSELx.
      • -
    • -
  • HAL/LL I2C -
      -
    • Added LL_I2C_DisableReset() function to allow the disable of SWRST.
      • -
    • -
  • HAL PCD -
      -
    • Corrected double buffer implementation in PCD_SET_EP_DBUF1_CNT() macro.
      • -
    • Added missing USB_CNTR_SOFM in the setting of wInterrupt_Mask global variable used in HAL_PCD_Init.
      • -
    • Removed lock/unlock from receive and transmit endpoints.
      • -
    • -
  • HAL/LL PWR -
      -
    • Replaced HAL_PWREx_GetVoltageRange() function by direct register access to remove dependency with HAL PWR.
      • -
    • Renamed the LL_PWR_IsActiveFlag_VOSF() API to LL_PWR_IsActiveFlag_VOS() in order to remove reference to PWR flag name and to refer to the Power feature.
      • -
    • -
  • HAL/LL RTC -
      -
    • Renamed RTC_CR_BCK bits in RTC_CR register to RTC_CR_BKP, to be aligned with others series.
      • -
    • -
  • HAL/LL SPI -
      -
    • Removed LL_SPI_SR_UDR define which is available only for I2S feature.
      • -
    • Updated LL_SPI_TransmitData16() et LL_SPI_TransmitData8 functions.
      • -
    • -
  • HAL/LL TIM -
      -
    • Corrected error in LL_TIM_EnableUpdateEvent() and LL_TIM_DisableUpdateEvent() functions.
      • -
    • -
-
-
-
- -
-

Main Changes

-

Maintenance release

-
    -
  • First official release supporting the Low Level drivers for the STM32L1xx family: -
      -
    • Low Layer drivers APIs provide register level programming: they require deep knowledge of peripherals described in STM32L1xx Reference Manual.
      • -
    • Low Layer drivers are available for: ADC, COMP, CORTEX, CRC, DAC, DMA, EXTI, GPIO, I2C, IWDG, OPAMP, PWR, RCC, RTC, SPI, TIM, USART, WWDG peripherals and additional Low Level Bus, System and Utilities APIs.
      • -
    • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32l1xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32l1xx_ll_ppp.h file must be included in user code.
      • -
    • -
-

Contents

-
    -
  • Generic updates -
      -
    • Update HAL drivers to apply MISRA C 2004 rule 10.6.
      • -
    • uwTick must be global and not static to allow overwrite of HAL_IncTick()
      • -
    • -
  • ADC -
      -
    • Clear the bit OVR (overrun) in addition to EOC (end of conversion) inside HAL_ADC_Start, HAL_ADC_Start_IT and HAL_ADC_Start_DMA.
      • -
    • -
  • CRC -
      -
    • HAL_CRC_DeInit() resets CRC_IDR register to reset value.
      • -
    • -
  • DMA -
      -
    • Add function HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma).
      • -
    • This function aborts the DMA Transfer in Interrupt mode.
      • -
    • Add macro __HAL_DMA_GET_COUNTER
      • -
    • This macro permits to get the number of remaining data units in the current DMAy Channelx transfer.
      • -
    • Global driver code optimization to reduce memory footprint
      • -
    • -
  • FLASH -
      -
    • Correct MISRA 10.3 Error[Pm069]: if identifiers are given for any of the parameters, then the identifiers used in the declaration and definition shall be identical (MISRA C 2004 rule 16.4).
      • -
    • -
  • GPIO -
      -
    • IS_GPIO_PIN is more robust.
      • -
    • -
  • I2C -
      -
    • WaitOnFlag is optimized to effectively last until the expected timeout of a transfer.
      • -
    • Optimisation of the IRQHandler.
      • -
    • Rework DMA end process and I2C error management during DMA transfer.
      • -
    • HAL_I2C_Master_Transmit_DMA now returns an error in case of communication error.
      • -
    • Add support for repeated start feature.
      • -
    • -
  • IWDG -
      -
    • New simplified HAL IWDG driver: remove HAL_IWDG_Start(), HAL_IWDG_MspInit() and HAL_IWDG_GetState() APIs
      • -
    • API functions are:
      • -
    • HAL_IWDG_Init(): this function insures the configuration and the start of the IWDG counter
      • -
    • HAL_IWDG_Refresh(): this function insures the reload of the IWDG counter
      • -
    • Refer to the following example to identify the changes: IWDG_Example
      • -
    • -
  • PWR -
      -
    • Add new interface HAL_FLASHEx_GetError.
      • -
    • Add constant FLASH_SIZE.
      • -
    • Use suffix U for all the defines.
      • -
    • HAL_PWREx_DisableLowPowerRunMode now returns HAL_StatusTypeDef instead of void.
      • -
    • SB and ADDR are now managed in interrupt mode, not in polling.
      • -
    • Add DMA abort treatment
      • -
    • -
  • RCC -
      -
    • Rework the correction from V1.1.3: -
        -
      • Backup domain are no more reseted when RTC clock source is changed from reset value.
        • -
      • -
    • -
  • RTC -
      -
    • Updated HAL_RTCEx_SetWakeUpTimer_IT() function by adding clear of Wake-Up flag before enabling the interrupt.
      • -
    • -
  • SPI -
      -
    • Correct MISRA 5.2 “tmpreg” variable shall not be used inside MACRO.
      • -
    • In the SPI_HandleTypeDef structure, RxXferCount and TxXferCount are now __IO.
      • -
    • Clear the OVR flag before a new transfer.
      • -
    • -
  • TIMER -
      -
    • Correct the description of the function HAL_TIM_PWM_Start_IT. -
        -
      • The parameter Channel mentions the channel to be enabled and not the one to be disabled.
        • -
      • -
    • -
  • WWDG -
      -
    • New simplified HAL WWDG driver: remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() and HAL_WWDG_GetState() APIs -
        -
      • Update HAL_WWDG_Refresh() API to remove counter parameter
        • -
      • New field EWIMode in WWDG_InitTypeDef to specify need for Early Wakeup Interrupt
        • -
      • API functions are: HAL_WWDG_Init(), HAL_WWDG_MspInit(), HAL_WWDG_Refresh(), HAL_WWDG_IRQHandler() and HAL_WWDG_EarlyWakeupCallback()
        • -
      • -
    • -
-
-
-
- -
-

Main Changes

-

Maintenance release

-

Contents

-
    -
  • Generic update -
      -
    • Update HAL weak empty callbacks to prevent unused argument compilation warnings with some compilers.
      • -
    • Improve the update of the SystemCoreClock variable within the HAL Driver.
      • -
    • Split aAPBAHBPrescTable into aAHBPrescTable and aAPBPrescTable.
      • -
    • Reduce HSE_STARTUP_TIMEOUT from 5s to 100ms.
      • -
    • Reduce MSI_TIMEOUT_VALUE from 100ms to 2ms.
      • -
    • Reduce HSI_TIMEOUT_VALUE from 100ms to 2ms.
      • -
    • Reduce LSI_TIMEOUT_VALUE from 100ms to 2ms.
      • -
    • Reduce PLL_TIMEOUT_VALUE from 100ms to 2ms.
      • -
    • -
  • CORTEX -
      -
    • __HAL_CORTEX_SYSTICKCLK_CONFIG is now deprecated. Prefer using HAL_SYSTICK_CLKSourceConfig function.
      • -
    • -
  • FLASH -
      -
    • Correct issue preventing Cat.1 devices to write data in EEPROM.
      • -
    • -
  • I2C -
      -
    • Add NACK management during wait on flag treatment.
      • -
    • Update the state machine.
      • -
    • It is now possible to use the I2C transmission with a data size of 0.
      • -
    • -
  • RCC -
      -
    • Optimize HAL_RCC_ClockConfig.
      • -
    • LSEON is reset only if required inside HAL_RCC_OscConfig.
      • -
    • RCC HSE pre-scaler reconfiguration for LCD/RTC peripherical is now possible.
      • -
    • Backup domain are no more reseted when RTC clock source is changed from reset value.
      • -
    • -
  • SMARTCARD -
      -
    • Update description of GuardTime and Prescaler fields in SMARTCARD_InitTypeDef structure.
      • -
    • -
  • UART -
      -
    • HAL_LIN_SendBreak() now use IS_UART_LIN_INSTANCE instead of IS_UART_INSTANCE.
      • -
    • Correct the UART_BRR_SAMPLING8 macro in the case of cary handling.
      • -
    • -
-
-
-
- -
-

Main Changes

-

Maintenance release

-

Contents

-
    -
  • ADC -
      -
    • The ADC internal macro “IS_ADC_RANGE” is modified to take into account the ADC resolution.
      • -
    • The function HAL_ADC_PollForEvent, in case of timeout, returns HAL_TIMEOUT instead of HAL_ERROR.
      • -
    • HAL_ADC_Init set the ADC handle in state HAL_ADC_ERROR_INTERNAL if the user try to initialize the ADC in DiscontinuousConvMode and ContinuousConvMode simultaneously, which is not possible.
      • -
    • Enhance the check for ScanConvMode in HAL_ADC_Init.
      • -
    • -
  • Cortex -
      -
    • Corrected Misra error (MISRA C 2004 rule 10.5).
      • -
    • -
  • CRC -
      -
    • Corrected the macro __HAL_CRC_SET_IDR.
      • -
    • -
  • GPIO -
      -
    • Corrected the macro GPIO_GET_INDEX.
      • -
    • To insure the same naming accross all STM32 families (F4, F2, F0, F1, L1 etc): -
        -
      • Replacing GPIO_SPEED_VERY_LOW by GPIO_SPEED_FREQ_LOW.
        • -
      • Replacing GPIO_SPEED_LOW by GPIO_SPEED_FREQ_MEDIUM.
        • -
      • Replacing GPIO_SPEED_MEDIUM by GPIO_SPEED_FREQ_HIGH.
        • -
      • Replacing GPIO_SPEED_HIGH by GPIO_SPEED_FREQ_VERY_HIGH.
        • -
      • -
    • -
  • IRDA -
      -
    • Corrected the HAL_IRDA_IRQHandler which was preventing to handle 2 simultaneous errors.
      • -
    • -
  • I2C -
      -
    • Corrected an issue where the STOP bit was not cleared after reading data depending on APB/I2C frequency.
      • -
    • -
  • I2S -
      -
    • HAL_I2S_Transmit() is updated to keep the check on busy flag only for the slave.
      • -
    • -
  • PCD -
      -
    • Corrected issue when using USB Device double-buffering mode for IN endpoints.
      • -
    • do{ … } while(0) is used for multi statement macros.
      • -
    • -
  • PWR -
      -
    • Corrected Misra error (MISRA C 2004 rule 14.3).
      • -
    • -
  • RCC -
      -
    • In HAL_RCCEx_PeriphCLKConfig, the reset of the backup domain occurs only if the RTC clock source has been changed.
      • -
    • __HAL_RCC_HSE_CONFIG is updated to remove the transition from RCC_HSE_ON to RCC_HSE_BYPASS.
      • -
    • Adding the macro __HAL_RCC_MCO1_CONFIG to configure the MCO clock.
      • -
    • Adding the macros and function to handle LSE CSS interrupt.
      • -
    • Corrected an error in HAL_RCC_GetSysClockFreq when the PLL is used as system clock. An incorrect sysclockfreq was returned.
      • -
    • -
  • RTC -
      -
    • RTC_TimeTypeDef.SecondFraction field is added to specifies the range or granularity of Sub Second register content.This field will be used only by HAL_RTC_GetTime function.
      • -
    • HAL_RTC_GetTime is updated to take into account the new field RTC_TimeTypeDef.SecondFraction.
      • -
    • Corrected error in __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG macro.
      • -
    • Add additionnal checks on WUTWF flag in HAL_RTCEx_SetWakeUpTimer_IT.
      • -
    • do{ … } while(0) is used for multi statement macros.
      • -
    • -
  • USART -
      -
    • Corrected the HAL_USART_IRQHandler which was preventing to handle 2 simultaneous errors.
      • -
    • -
  • UART -
      -
    • Removed the activation of ERR IT from HAL_UART_Transmit_IT() which was leading to HAL_UART_IRQ_Handler wrong behavior.
      • -
    • Corrected the HAL_UART_IRQHandler which was preventing to handle 2 simultaneous errors.
      • -
    • -
  • SMARTCARD -
      -
    • Corrected the HAL_SMARTCARD_IRQHandler which was preventing to handle 2 simultaneous errors.
      • -
    • -
-
-
-
- -
-

Main Changes

-

Maintenance release

-
    -
  • Include path changes for compilation under Unix environment
    • -
  • Update drivers to be C++ compliant
    • -
-

Contents

-
    -
  • CORTEX -
      -
    • Added interface to access MPU features (refer to stm32l1xx_hal_cortex.h)
      • -
    • -
  • CRYP -
      -
    • Added Instance field in CRYP_HandleTypeDef. -
        -
      • HAL CRYP driver updated to support multi instance, so user must ensure that the new parameter Instance is initialized in his application (CRYPHandle.Instance = CRYP)
        • -
      • -
    • -
  • FLASH -
      -
    • Changing field name of NOR_CFITypeDef (CFI1X changed to CFI1_X)
      • -
    • -
  • PCD -
      -
    • HAL_PCD_ActiveRemoteWakeup renamed HAL_PCD_ActivateRemoteWakeup
      • -
    • HAL_PCD_DeActiveRemoteWakeup renamed to HAL_PCD_DeActivateRemoteWakeup
      • -
    • -
  • PWR -
      -
    • HAL_PWR_PVDConfig renamed HAL_PWR_ConfigPVD
      • -
    • Added new interfaces: -
        -
      • void HAL_PWR_EnableSleepOnExit(void);
        • -
      • void HAL_PWR_DisableSleepOnExit(void);
        • -
      • void HAL_PWR_EnableSEVOnPend(void);
        • -
      • void HAL_PWR_DisableSEVOnPend(void);
        • -
      • void HAL_PWR_EnableSleepOnExit(void);
        • -
      • uint32_t HAL_PWREx_GetVoltageRange(void);
        • -
      • -
    • -
  • RCC -
      -
    • HAL_RCC_CCSCallback renamed to HAL_RCC_CSSCallback
      • -
    • Adding HAL_RCCEx_GetPeriphCLKFreq interface.
      • -
    • -
  • SMARTCARD -
      -
    • Removal of HAL_SMARTCARD_ReInit interface.
      • -
    • -
  • SPI -
      -
    • HAL_SPI_GetError now returns a uint32_t instead of HAL_SPI_ErrorTypeDef.
      • -
    • -
  • TIMER -
      -
    • Adding interface HAL_TIM_SlaveConfigSynchronization_IT
      • -
    • -
  • UART -
      -
    • The field ErrorCode of UART_HandleTypeDef is changed from HAL_UART_ErrorTypeDef to uint32_t.
      • -
    • -
  • USART -
      -
    • The field ErrorCode of UART_HandleTypeDef is changed from HAL_UART_ErrorTypeDef to uint32_t.
      • -
    • -
-
-
-
- -
-

Main Changes

-

Maintenance release

-
    -
  • Add support of new STM32L1 eXtended devices - STM32l151xDX, STM32l152xDX & STM32l62xDX
    • -
-

Contents

-
    -
  • HAL generic -
      -
    • Add eXtended Devices switchs when needed -
        -
      • STM32L151xDX has same features than STM32L151xE
        • -
      • STM32L152xDX has same features than STM32L152xE
        • -
      • STM32L162xDX has same features than STM32L162xE
        • -
      • -
    • -
  • HAL FLASH -
      -
    • Add support of new STM32L1 Devices (same as other HAL)
      • -
    • stm32l1xx_hal_flash_ex.c : Specific treatment done in HAL_FLASHEx_Erase and HAL_FLASHEx_Erase_IT as memory is not continuous between 2 banks, user should perform pages erase by bank only
      • -
    • -
-
-
-
- -

Main Changes

-

First official release

-
-
-
- - - diff --git a/bsp/stm32/stm32h563-st-nucleo/context_rvds.lst b/bsp/stm32/stm32h563-st-nucleo/context_rvds.lst deleted file mode 100644 index 9a85aa2ef1f..00000000000 --- a/bsp/stm32/stm32h563-st-nucleo/context_rvds.lst +++ /dev/null @@ -1,779 +0,0 @@ - - - -ARM Macro Assembler Page 1 - - - 1 00000000 ;/* - 2 00000000 ;* Copyright (c) 2006-2018, RT-Thread Development Team - 3 00000000 ;* - 4 00000000 ;* SPDX-License-Identifier: Apache-2.0 - 5 00000000 ;* - 6 00000000 ; * Change Logs: - 7 00000000 ; * Date Author Notes - 8 00000000 ; * 2009-01-17 Bernard first version. - 9 00000000 ; * 2012-01-01 aozima support context switch l - oad/store FPU register. - 10 00000000 ; * 2013-06-18 aozima add restore MSP feature. - - 11 00000000 ; * 2013-06-23 aozima support lazy stack optim - ized. - 12 00000000 ; * 2018-07-24 aozima enhancement hard fault e - xception handler. - 13 00000000 ; */ - 14 00000000 - 15 00000000 ;/** - 16 00000000 ; * @addtogroup cortex-m33 - 17 00000000 ; */ - 18 00000000 ;/*@{*/ - 19 00000000 - 20 00000000 E000ED08 - SCB_VTOR - EQU 0xE000ED08 ; Vector Table Offs - et Register - 21 00000000 E000ED04 - NVIC_INT_CTRL - EQU 0xE000ED04 ; interrupt control - state register - 22 00000000 E000ED20 - NVIC_SYSPRI2 - EQU 0xE000ED20 ; system priority r - egister (2) - 23 00000000 FFFF0000 - NVIC_PENDSV_PRI - EQU 0xFFFF0000 ; PendSV and SysTic - k priority value (l - owest) - 24 00000000 10000000 - NVIC_PENDSVSET - EQU 0x10000000 ; value to trigger - PendSV exception - 25 00000000 - 26 00000000 AREA |.text|, CODE, READONLY, ALIGN= -2 - 27 00000000 THUMB - 28 00000000 REQUIRE8 - 29 00000000 PRESERVE8 - 30 00000000 - 31 00000000 IMPORT rt_thread_switch_interrupt_flag - 32 00000000 IMPORT rt_interrupt_from_thread - 33 00000000 IMPORT rt_interrupt_to_thread - 34 00000000 IMPORT rt_trustzone_current_context - 35 00000000 IMPORT rt_trustzone_context_load - 36 00000000 IMPORT rt_trustzone_context_store - 37 00000000 - 38 00000000 ;/* - - - -ARM Macro Assembler Page 2 - - - 39 00000000 ; * rt_base_t rt_hw_interrupt_disable(); - 40 00000000 ; */ - 41 00000000 rt_hw_interrupt_disable - PROC - 42 00000000 EXPORT rt_hw_interrupt_disable - 43 00000000 F3EF 8010 MRS r0, PRIMASK - 44 00000004 B672 CPSID I - 45 00000006 4770 BX LR - 46 00000008 ENDP - 47 00000008 - 48 00000008 ;/* - 49 00000008 ; * void rt_hw_interrupt_enable(rt_base_t level); - 50 00000008 ; */ - 51 00000008 rt_hw_interrupt_enable - PROC - 52 00000008 EXPORT rt_hw_interrupt_enable - 53 00000008 F380 8810 MSR PRIMASK, r0 - 54 0000000C 4770 BX LR - 55 0000000E ENDP - 56 0000000E - 57 0000000E ;/* - 58 0000000E ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 - to); - 59 0000000E ; * r0 --> from - 60 0000000E ; * r1 --> to - 61 0000000E ; */ - 62 0000000E rt_hw_context_switch_interrupt - 63 0000000E EXPORT rt_hw_context_switch_interrupt - 64 0000000E rt_hw_context_switch - PROC - 65 0000000E EXPORT rt_hw_context_switch - 66 0000000E - 67 0000000E ; set rt_thread_switch_interrupt_flag to 1 - 68 0000000E 4A5D LDR r2, =rt_thread_switch_interrupt -_flag - 69 00000010 6813 LDR r3, [r2] - 70 00000012 2B01 CMP r3, #1 - 71 00000014 D004 BEQ _reswitch - 72 00000016 F04F 0301 MOV r3, #1 - 73 0000001A 6013 STR r3, [r2] - 74 0000001C - 75 0000001C 4A5A LDR r2, =rt_interrupt_from_thread ; - set rt_interrupt_f - rom_thread - 76 0000001E 6010 STR r0, [r2] - 77 00000020 - 78 00000020 _reswitch - 79 00000020 4A5A LDR r2, =rt_interrupt_to_thread ; s - et rt_interrupt_to_ - thread - 80 00000022 6011 STR r1, [r2] - 81 00000024 - 82 00000024 485A LDR r0, =NVIC_INT_CTRL ; trigger th - e PendSV exception - (causes context swi - tch) - 83 00000026 F04F 5180 LDR r1, =NVIC_PENDSVSET - 84 0000002A 6001 STR r1, [r0] - 85 0000002C 4770 BX LR - - - -ARM Macro Assembler Page 3 - - - 86 0000002E ENDP - 87 0000002E - 88 0000002E ; r0 --> switch from thread stack - 89 0000002E ; r1 --> switch to thread stack - 90 0000002E ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from - ] stack - 91 0000002E PendSV_Handler - PROC - 92 0000002E EXPORT PendSV_Handler - 93 0000002E - 94 0000002E ; disable interrupt to protect context switch - 95 0000002E F3EF 8210 MRS r2, PRIMASK ; R2 = PRIMASK - 96 00000032 B672 CPSID I ; disable all inter - rupt - 97 00000034 - 98 00000034 ; get rt_thread_switch_interrupt_flag - 99 00000034 4853 LDR r0, =rt_thread_switch_interrupt -_flag - ; r0 = &rt_thread_s - witch_interrupt_fla - g - 100 00000036 6801 LDR r1, [r0] ; r1 = *r1 - 101 00000038 2900 CMP r1, #0x00 ; compare r1 == 0x0 - 0 - 102 0000003A D102 BNE schedule - 103 0000003C F382 8810 MSR PRIMASK, r2 ; if r1 == 0x00, do - msr PRIMASK, r2 - 104 00000040 4770 BX lr ; if r1 == 0x00, do - bx lr - 105 00000042 - 106 00000042 schedule - 107 00000042 B404 PUSH {r2} ; store interrupt s - tate - 108 00000044 - 109 00000044 ; clear rt_thread_switch_interrupt_flag to 0 - 110 00000044 F04F 0100 MOV r1, #0x00 ; r1 = 0x00 - 111 00000048 6001 STR r1, [r0] ; *r0 = r1 - 112 0000004A - 113 0000004A ; skip register save at the first time - 114 0000004A 484F LDR r0, =rt_interrupt_from_thread ; - r0 = &rt_interrupt - _from_thread - 115 0000004C 6801 LDR r1, [r0] ; r1 = *r0 - 116 0000004E B359 CBZ r1, switch_to_thread ; if r1 == - 0, goto switch_to_ - thread - 117 00000050 - 118 00000050 ; Whether TrustZone thread stack exists - 119 00000050 4950 LDR r1, =rt_trustzone_current_cont -ext - ; r1 = &rt_secure_c - urrent_context - 120 00000052 6809 LDR r1, [r1] ; r1 = *r1 - 121 00000054 B1A1 CBZ r1, contex_ns_store ; if r1 == - 0, goto contex_ns_s - tore - 122 00000056 - 123 00000056 ;call TrustZone fun, Save TrustZone stack - 124 00000056 B503 STMFD sp!, {r0-r1, lr} - - - -ARM Macro Assembler Page 4 - - - ; push register - 125 00000058 4608 MOV r0, r1 ; r0 = rt_secure_cu - rrent_context - 126 0000005A F7FF FFFE BL rt_trustzone_context_store ; ca - ll TrustZone store - fun - 127 0000005E E8BD 4003 LDMFD sp!, {r0-r1, lr} ; pop register - - 128 00000062 - 129 00000062 ; check break from TrustZone - 130 00000062 4672 MOV r2, lr ; r2 = lr - 131 00000064 F012 0F40 TST r2, #0x40 ; if EXC_RETURN[6] - is 1, TrustZone sta - ck was used - 132 00000068 D00A BEQ contex_ns_store ; if r2 & 0x40 - == 0, goto contex_n - s_store - 133 0000006A - 134 0000006A ; push PSPLIM CONTROL PSP LR current_context to stack - 135 0000006A F3EF 830B MRS r3, psplim ; r3 = psplim - 136 0000006E F3EF 8414 MRS r4, control ; r4 = control - 137 00000072 F3EF 8509 MRS r5, psp ; r5 = psp - 138 00000076 E925 001E STMFD r5!, {r1-r4} ; push to thread s - tack - 139 0000007A - 140 0000007A ; update from thread stack pointer - 141 0000007A 6800 LDR r0, [r0] ; r0 = rt_thread_sw - itch_interrupt_flag - - 142 0000007C 6005 STR r5, [r0] ; *r0 = r5 - 143 0000007E E013 b switch_to_thread ; goto switch_ - to_thread - 144 00000080 - 145 00000080 contex_ns_store - 146 00000080 - 147 00000080 F3EF 8109 MRS r1, psp ; get from thread s - tack pointer - 148 00000084 - 149 00000084 IF {FPU} != "SoftVFP" - 150 00000084 F01E 0F10 TST lr, #0x10 ; if(!EXC_RETURN[4] - ) - 151 00000088 BF08 ED21 - 8B10 VSTMFDEQ r1!, {d8 - d15} ; push FPU regi - ster s16~s31 - 152 0000008E ENDIF - 153 0000008E - 154 0000008E E921 0FF0 STMFD r1!, {r4 - r11} ; push r4 - r11 - register - 155 00000092 - 156 00000092 4A40 LDR r2, =rt_trustzone_current_cont -ext - ; r2 = &rt_secure_c - urrent_context - 157 00000094 6812 LDR r2, [r2] ; r2 = *r2 - 158 00000096 4673 MOV r3, lr ; r3 = lr - 159 00000098 F3EF 840B MRS r4, psplim ; r4 = psplim - 160 0000009C F3EF 8514 MRS r5, control ; r5 = control - 161 000000A0 E921 003C STMFD r1!, {r2-r5} ; push to thread s - tack - - - -ARM Macro Assembler Page 5 - - - 162 000000A4 - 163 000000A4 6800 LDR r0, [r0] - 164 000000A6 6001 STR r1, [r0] ; update from threa - d stack pointer - 165 000000A8 - 166 000000A8 switch_to_thread - 167 000000A8 4938 LDR r1, =rt_interrupt_to_thread - 168 000000AA 6809 LDR r1, [r1] - 169 000000AC 6809 LDR r1, [r1] ; load thread stack - pointer - 170 000000AE - 171 000000AE ; update current TrustZone context - 172 000000AE C93C LDMFD r1!, {r2-r5} ; pop thread stack - - 173 000000B0 F384 880B MSR psplim, r4 ; psplim = r4 - 174 000000B4 F385 8814 MSR control, r5 ; control = r5 - 175 000000B8 469E MOV lr, r3 ; lr = r3 - 176 000000BA 4E36 LDR r6, =rt_trustzone_current_cont -ext - ; r6 = &rt_secure_c - urrent_context - 177 000000BC 6032 STR r2, [r6] ; *r6 = r2 - 178 000000BE 4610 MOV r0, r2 ; r0 = r2 - 179 000000C0 - 180 000000C0 ; Whether TrustZone thread stack exists - 181 000000C0 B140 CBZ r0, contex_ns_load ; if r0 == 0 - , goto contex_ns_lo - ad - 182 000000C2 B40A PUSH {r1, r3} ; push lr, thread_s - tack - 183 000000C4 F7FF FFFE BL rt_trustzone_context_load ; cal - l TrustZone load fu - n - 184 000000C8 BC0A POP {r1, r3} ; pop lr, thread_st - ack - 185 000000CA 469E MOV lr, r3 ; lr = r1 - 186 000000CC F013 0F40 TST r3, #0x40 ; if EXC_RETURN[6] - is 1, TrustZone sta - ck was used - 187 000000D0 D000 BEQ contex_ns_load ; if r1 & 0x40 = - = 0, goto contex_ns - _load - 188 000000D2 E006 B pendsv_exit - 189 000000D4 - 190 000000D4 contex_ns_load - 191 000000D4 E8B1 0FF0 LDMFD r1!, {r4 - r11} ; pop r4 - r11 - register - 192 000000D8 - 193 000000D8 IF {FPU} != "SoftVFP" - 194 000000D8 F01E 0F10 TST lr, #0x10 ; if(!EXC_RETURN[4] - ) - 195 000000DC BF08 ECB1 - 8B10 VLDMFDEQ r1!, {d8 - d15} ; pop FPU regis - ter s16~s31 - 196 000000E2 ENDIF - 197 000000E2 - 198 000000E2 pendsv_exit - 199 000000E2 F381 8809 MSR psp, r1 ; update stack poin - ter - - - -ARM Macro Assembler Page 6 - - - 200 000000E6 ; restore interrupt - 201 000000E6 BC04 POP {r2} - 202 000000E8 F382 8810 MSR PRIMASK, r2 - 203 000000EC - 204 000000EC 4770 BX lr - 205 000000EE ENDP - 206 000000EE - 207 000000EE ;/* - 208 000000EE ; * void rt_hw_context_switch_to(rt_uint32 to); - 209 000000EE ; * r0 --> to - 210 000000EE ; * this fucntion is used to perform the first thread sw - itch - 211 000000EE ; */ - 212 000000EE rt_hw_context_switch_to - PROC - 213 000000EE EXPORT rt_hw_context_switch_to - 214 000000EE ; set to thread - 215 000000EE 4927 LDR r1, =rt_interrupt_to_thread - 216 000000F0 6008 STR r0, [r1] - 217 000000F2 - 218 000000F2 IF {FPU} != "SoftVFP" - 219 000000F2 ; CLEAR CONTROL.FPCA - 220 000000F2 F3EF 8214 MRS r2, CONTROL ; read - 221 000000F6 F022 0204 BIC r2, #0x04 ; modify - 222 000000FA F382 8814 MSR CONTROL, r2 ; write-back - 223 000000FE ENDIF - 224 000000FE - 225 000000FE ; set from thread to 0 - 226 000000FE 4922 LDR r1, =rt_interrupt_from_thread - 227 00000100 F04F 0000 MOV r0, #0x0 - 228 00000104 6008 STR r0, [r1] - 229 00000106 - 230 00000106 ; set interrupt flag to 1 - 231 00000106 491F LDR r1, =rt_thread_switch_interrupt -_flag - 232 00000108 F04F 0001 MOV r0, #1 - 233 0000010C 6008 STR r0, [r1] - 234 0000010E - 235 0000010E ; set the PendSV and SysTick exception priority - 236 0000010E 4822 LDR r0, =NVIC_SYSPRI2 - 237 00000110 4922 LDR r1, =NVIC_PENDSV_PRI - 238 00000112 F8D0 2000 LDR.W r2, [r0,#0x00] ; read - 239 00000116 EA41 0102 ORR r1,r1,r2 ; modify - 240 0000011A 6001 STR r1, [r0] ; write-back - 241 0000011C - 242 0000011C ; trigger the PendSV exception (causes context switch) - 243 0000011C 481C LDR r0, =NVIC_INT_CTRL - 244 0000011E F04F 5180 LDR r1, =NVIC_PENDSVSET - 245 00000122 6001 STR r1, [r0] - 246 00000124 - 247 00000124 ; restore MSP - 248 00000124 481E LDR r0, =SCB_VTOR - 249 00000126 6800 LDR r0, [r0] - 250 00000128 6800 LDR r0, [r0] - 251 0000012A F380 8808 MSR msp, r0 - 252 0000012E - 253 0000012E ; enable interrupts at processor level - 254 0000012E B661 CPSIE F - 255 00000130 B662 CPSIE I - - - -ARM Macro Assembler Page 7 - - - 256 00000132 - 257 00000132 ; ensure PendSV exception taken place before subsequent - operation - 258 00000132 F3BF 8F4F DSB - 259 00000136 F3BF 8F6F ISB - 260 0000013A - 261 0000013A ; never reach here! - 262 0000013A ENDP - 263 0000013A - 264 0000013A ; compatible with old version - 265 0000013A rt_hw_interrupt_thread_switch - PROC - 266 0000013A EXPORT rt_hw_interrupt_thread_switch - 267 0000013A 4770 BX lr - 268 0000013C ENDP - 269 0000013C - 270 0000013C IMPORT rt_hw_hard_fault_exception - 271 0000013C EXPORT HardFault_Handler - 272 0000013C HardFault_Handler - PROC - 273 0000013C - 274 0000013C ; get current context - 275 0000013C F3EF 8008 MRS r0, msp ;get fault context - from handler - 276 00000140 F01E 0F04 TST lr, #0x04 ;if(!EXC_RETURN[2]) - - 277 00000144 D001 BEQ get_sp_done - 278 00000146 F3EF 8009 MRS r0, psp ;get fault context - from thread - 279 0000014A get_sp_done - 280 0000014A - 281 0000014A E920 0FF0 STMFD r0!, {r4 - r11} ; push r4 - r11 - register - 282 0000014E - 283 0000014E 4A11 LDR r2, =rt_trustzone_current_cont -ext - ; r2 = &rt_secure_c - urrent_context - 284 00000150 6812 LDR r2, [r2] ; r2 = *r2 - 285 00000152 4673 MOV r3, lr ; r3 = lr - 286 00000154 F3EF 840B MRS r4, psplim ; r4 = psplim - 287 00000158 F3EF 8514 MRS r5, control ; r5 = control - 288 0000015C E920 003C STMFD r0!, {r2-r5} ; push to thread s - tack - 289 00000160 - 290 00000160 F840 ED04 STMFD r0!, {lr} ; push exec_return - register - 291 00000164 - 292 00000164 F01E 0F04 TST lr, #0x04 ; if(!EXC_RETURN[2] - ) - 293 00000168 D002 BEQ update_msp - 294 0000016A F380 8809 MSR psp, r0 ; update stack poin - ter to PSP - 295 0000016E E001 B update_done - 296 00000170 update_msp - 297 00000170 F380 8808 MSR msp, r0 ; update stack poin - ter to MSP - 298 00000174 update_done - 299 00000174 - - - -ARM Macro Assembler Page 8 - - - 300 00000174 B500 PUSH {lr} - 301 00000176 F7FF FFFE BL rt_hw_hard_fault_exception - 302 0000017A F85D EB04 POP {lr} - 303 0000017E - 304 0000017E F04E 0E04 ORR lr, lr, #0x04 - 305 00000182 4770 BX lr - 306 00000184 ENDP - 307 00000184 - 308 00000184 ALIGN 4 - 309 00000184 - 310 00000184 END - 00000000 - 00000000 - 00000000 - E000ED04 - 00000000 - E000ED20 - FFFF0000 - E000ED08 -Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M33 --fpu=FPv5-S -P --depend=.\build\keil\obj\context_rvds.d -o.\build\keil\obj\context_rvds.o -I -D:\1_tool_prog\2_MDK\pack\Keil\STM32H5xx_DFP\1.1.0\Drivers\CMSIS\Device\ST\STM3 -2H5xx\Include --predefine="__UVISION_VERSION SETA 536" --predefine="STM32H563xx - SETA 1" --list=context_rvds.lst ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -.text 00000000 - -Symbol: .text - Definitions - At line 26 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - None -Comment: .text unused -HardFault_Handler 0000013C - -Symbol: HardFault_Handler - Definitions - At line 272 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 271 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S -Comment: HardFault_Handler used once -PendSV_Handler 0000002E - -Symbol: PendSV_Handler - Definitions - At line 91 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 92 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S -Comment: PendSV_Handler used once -_reswitch 00000020 - -Symbol: _reswitch - Definitions - At line 78 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 71 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S -Comment: _reswitch used once -contex_ns_load 000000D4 - -Symbol: contex_ns_load - Definitions - At line 190 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 181 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - At line 187 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - -contex_ns_store 00000080 - -Symbol: contex_ns_store - Definitions - At line 145 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 121 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - At line 132 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - -get_sp_done 0000014A - -Symbol: get_sp_done - Definitions - At line 279 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 277 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S -Comment: get_sp_done used once -pendsv_exit 000000E2 - - - -ARM Macro Assembler Page 2 Alphabetic symbol ordering -Relocatable symbols - - -Symbol: pendsv_exit - Definitions - At line 198 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 188 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S -Comment: pendsv_exit used once -rt_hw_context_switch 0000000E - -Symbol: rt_hw_context_switch - Definitions - At line 64 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 65 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S -Comment: rt_hw_context_switch used once -rt_hw_context_switch_interrupt 0000000E - -Symbol: rt_hw_context_switch_interrupt - Definitions - At line 62 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 63 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S -Comment: rt_hw_context_switch_interrupt used once -rt_hw_context_switch_to 000000EE - -Symbol: rt_hw_context_switch_to - Definitions - At line 212 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 213 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S -Comment: rt_hw_context_switch_to used once -rt_hw_interrupt_disable 00000000 - -Symbol: rt_hw_interrupt_disable - Definitions - At line 41 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 42 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S -Comment: rt_hw_interrupt_disable used once -rt_hw_interrupt_enable 00000008 - -Symbol: rt_hw_interrupt_enable - Definitions - At line 51 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 52 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S -Comment: rt_hw_interrupt_enable used once -rt_hw_interrupt_thread_switch 0000013A - -Symbol: rt_hw_interrupt_thread_switch - Definitions - At line 265 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 266 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S -Comment: rt_hw_interrupt_thread_switch used once -schedule 00000042 - -Symbol: schedule - Definitions - - - -ARM Macro Assembler Page 3 Alphabetic symbol ordering -Relocatable symbols - - At line 106 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 102 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S -Comment: schedule used once -switch_to_thread 000000A8 - -Symbol: switch_to_thread - Definitions - At line 166 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 116 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - At line 143 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - -update_done 00000174 - -Symbol: update_done - Definitions - At line 298 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 295 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S -Comment: update_done used once -update_msp 00000170 - -Symbol: update_msp - Definitions - At line 296 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 293 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S -Comment: update_msp used once -18 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Absolute symbols - -NVIC_INT_CTRL E000ED04 - -Symbol: NVIC_INT_CTRL - Definitions - At line 21 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 82 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - At line 243 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - -NVIC_PENDSVSET 10000000 - -Symbol: NVIC_PENDSVSET - Definitions - At line 24 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 83 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - At line 244 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - -NVIC_PENDSV_PRI FFFF0000 - -Symbol: NVIC_PENDSV_PRI - Definitions - At line 23 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 237 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S -Comment: NVIC_PENDSV_PRI used once -NVIC_SYSPRI2 E000ED20 - -Symbol: NVIC_SYSPRI2 - Definitions - At line 22 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 236 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S -Comment: NVIC_SYSPRI2 used once -SCB_VTOR E000ED08 - -Symbol: SCB_VTOR - Definitions - At line 20 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 248 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S -Comment: SCB_VTOR used once -5 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -External symbols - -rt_hw_hard_fault_exception 00000000 - -Symbol: rt_hw_hard_fault_exception - Definitions - At line 270 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 301 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S -Comment: rt_hw_hard_fault_exception used once -rt_interrupt_from_thread 00000000 - -Symbol: rt_interrupt_from_thread - Definitions - At line 32 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 75 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - At line 114 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - At line 226 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - -rt_interrupt_to_thread 00000000 - -Symbol: rt_interrupt_to_thread - Definitions - At line 33 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 79 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - At line 167 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - At line 215 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - -rt_thread_switch_interrupt_flag 00000000 - -Symbol: rt_thread_switch_interrupt_flag - Definitions - At line 31 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 68 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - At line 99 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - At line 231 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - -rt_trustzone_context_load 00000000 - -Symbol: rt_trustzone_context_load - Definitions - At line 35 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 183 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S -Comment: rt_trustzone_context_load used once -rt_trustzone_context_store 00000000 - -Symbol: rt_trustzone_context_store - Definitions - At line 36 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - Uses - At line 126 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S -Comment: rt_trustzone_context_store used once -rt_trustzone_current_context 00000000 - -Symbol: rt_trustzone_current_context - Definitions - At line 34 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - - - -ARM Macro Assembler Page 2 Alphabetic symbol ordering -External symbols - - Uses - At line 119 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - At line 156 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - At line 176 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - At line 283 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - -7 symbols -365 symbols in table diff --git a/bsp/stm32/stm32h563-st-nucleo/startup_stm32h563xx.lst b/bsp/stm32/stm32h563-st-nucleo/startup_stm32h563xx.lst deleted file mode 100644 index 234860dd5ab..00000000000 --- a/bsp/stm32/stm32h563-st-nucleo/startup_stm32h563xx.lst +++ /dev/null @@ -1,3069 +0,0 @@ - - - -ARM Macro Assembler Page 1 - - - 1 00000000 ;******************************************************* - ************************ - 2 00000000 ;* File Name : startup_stm32h563xx.s - 3 00000000 ;* Author : MCD Application Team - 4 00000000 ;* Description : STM32H563xx Non Crypto devices v - ector table for MDK-ARM toolchain. - 5 00000000 ;* This module performs: - 6 00000000 ;* - Set the initial SP - 7 00000000 ;* - Set the initial PC == Reset_Ha - ndler - 8 00000000 ;* - Set the vector table entries w - ith the exceptions ISR address - 9 00000000 ;* - Branches to __main in the C li - brary (which eventually - 10 00000000 ;* calls main()). - 11 00000000 ;* After Reset the Cortex-M33 proce - ssor is in Thread mode, - 12 00000000 ;* priority is Privileged, and the - Stack is set to Main. - 13 00000000 ;******************************************************* - ************************ - 14 00000000 ;* @attention - 15 00000000 ;* - 16 00000000 ;* Copyright (c) 2023 STMicroelectronics. - 17 00000000 ;* All rights reserved. - 18 00000000 ;* - 19 00000000 ;* This software is licensed under terms that can be fou - nd in the LICENSE file - 20 00000000 ;* in the root directory of this software component. - 21 00000000 ;* If no LICENSE file comes with this software, it is pr - ovided AS-IS. - 22 00000000 ;* - 23 00000000 ;******************************************************* - ************************ - 24 00000000 ;* <<< Use Configuration Wizard in Context Menu >>> - 25 00000000 ; - 26 00000000 ; Amount of memory (in bytes) allocated for Stack - 27 00000000 ; Tailor this value to your application needs - 28 00000000 ; Stack Configuration - 29 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - 30 00000000 ; - 31 00000000 - 32 00000000 00000400 - Stack_Size - EQU 0x00000400 - 33 00000000 - 34 00000000 AREA STACK, NOINIT, READWRITE, ALIGN -=3 - 35 00000000 Stack_Mem - SPACE Stack_Size - 36 00000400 __initial_sp - 37 00000400 - 38 00000400 - 39 00000400 ; Heap Configuration - 40 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - 41 00000400 ; - 42 00000400 - 43 00000400 00000200 - Heap_Size - - - -ARM Macro Assembler Page 2 - - - EQU 0x00000200 - 44 00000400 - 45 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN= -3 - 46 00000000 __heap_base - 47 00000000 Heap_Mem - SPACE Heap_Size - 48 00000200 __heap_limit - 49 00000200 - 50 00000200 PRESERVE8 - 51 00000200 THUMB - 52 00000200 - 53 00000200 - 54 00000200 ; Vector Table Mapped to Address 0 at Reset - 55 00000200 AREA RESET, DATA, READONLY - 56 00000000 EXPORT __Vectors - 57 00000000 EXPORT __Vectors_End - 58 00000000 EXPORT __Vectors_Size - 59 00000000 - 60 00000000 00000000 - __Vectors - DCD __initial_sp ; Top of Stack - 61 00000004 00000000 DCD Reset_Handler ; Reset Handler - 62 00000008 00000000 DCD NMI_Handler ; NMI Handler - 63 0000000C 00000000 DCD HardFault_Handler ; Hard Fault - Handler - 64 00000010 00000000 DCD MemManage_Handler - ; MPU Fault Handler - - 65 00000014 00000000 DCD BusFault_Handler - ; Bus Fault Handler - - 66 00000018 00000000 DCD UsageFault_Handler ; Usage Faul - t Handler - 67 0000001C 00000000 DCD SecureFault_Handler ; Secure Fa - ult Handler - 68 00000020 00000000 DCD 0 ; Reserved - 69 00000024 00000000 DCD 0 ; Reserved - 70 00000028 00000000 DCD 0 ; Reserved - 71 0000002C 00000000 DCD SVC_Handler ; SVCall Handler - 72 00000030 00000000 DCD DebugMon_Handler ; Debug Monito - r Handler - 73 00000034 00000000 DCD 0 ; Reserved - 74 00000038 00000000 DCD PendSV_Handler ; PendSV Handler - - 75 0000003C 00000000 DCD SysTick_Handler - ; SysTick Handler - 76 00000040 ; External Interrupts - 77 00000040 00000000 DCD WWDG_IRQHandler - ; Window WatchDog - 78 00000044 00000000 DCD PVD_AVD_IRQHandler ; PVD/AVD th - rough EXTI Line det - ection Interrupt - 79 00000048 00000000 DCD RTC_IRQHandler ; RTC non-secure - interrupt - 80 0000004C 00000000 DCD RTC_S_IRQHandler ; RTC secure i - nterrupt - 81 00000050 00000000 DCD TAMP_IRQHandler ; Tamper non-se - cure interrupt - - - -ARM Macro Assembler Page 3 - - - 82 00000054 00000000 DCD RAMCFG_IRQHandler - ; RAMCFG global - 83 00000058 00000000 DCD FLASH_IRQHandler ; FLASH non-se - cure global interru - pt - 84 0000005C 00000000 DCD FLASH_S_IRQHandler ; FLASH secu - re global interrupt - - 85 00000060 00000000 DCD GTZC_IRQHandler ; Global TrustZ - one Controller inte - rrupt - 86 00000064 00000000 DCD RCC_IRQHandler ; RCC non-secure - global interrupt - 87 00000068 00000000 DCD RCC_S_IRQHandler ; RCC secure g - lobal interrupt - 88 0000006C 00000000 DCD EXTI0_IRQHandler ; EXTI Line0 i - nterrupt - 89 00000070 00000000 DCD EXTI1_IRQHandler ; EXTI Line1 i - nterrupt - 90 00000074 00000000 DCD EXTI2_IRQHandler ; EXTI Line2 i - nterrupt - 91 00000078 00000000 DCD EXTI3_IRQHandler ; EXTI Line3 i - nterrupt - 92 0000007C 00000000 DCD EXTI4_IRQHandler ; EXTI Line4 i - nterrupt - 93 00000080 00000000 DCD EXTI5_IRQHandler ; EXTI Line5 i - nterrupt - 94 00000084 00000000 DCD EXTI6_IRQHandler ; EXTI Line6 i - nterrupt - 95 00000088 00000000 DCD EXTI7_IRQHandler ; EXTI Line7 i - nterrupt - 96 0000008C 00000000 DCD EXTI8_IRQHandler ; EXTI Line8 i - nterrupt - 97 00000090 00000000 DCD EXTI9_IRQHandler ; EXTI Line9 i - nterrupt - 98 00000094 00000000 DCD EXTI10_IRQHandler ; EXTI Line10 - interrupt - 99 00000098 00000000 DCD EXTI11_IRQHandler ; EXTI Line11 - interrupt - 100 0000009C 00000000 DCD EXTI12_IRQHandler ; EXTI Line12 - interrupt - 101 000000A0 00000000 DCD EXTI13_IRQHandler ; EXTI Line13 - interrupt - 102 000000A4 00000000 DCD EXTI14_IRQHandler ; EXTI Line14 - interrupt - 103 000000A8 00000000 DCD EXTI15_IRQHandler ; EXTI Line15 - interrupt - 104 000000AC 00000000 DCD GPDMA1_Channel0_IRQHandler ; GP - DMA1 Channel 0 glob - al interrupt - 105 000000B0 00000000 DCD GPDMA1_Channel1_IRQHandler ; GP - DMA1 Channel 1 glob - al interrupt - 106 000000B4 00000000 DCD GPDMA1_Channel2_IRQHandler ; GP - DMA1 Channel 2 glob - al interrupt - 107 000000B8 00000000 DCD GPDMA1_Channel3_IRQHandler ; GP - DMA1 Channel 3 glob - al interrupt - - - -ARM Macro Assembler Page 4 - - - 108 000000BC 00000000 DCD GPDMA1_Channel4_IRQHandler ; GP - DMA1 Channel 4 glob - al interrupt - 109 000000C0 00000000 DCD GPDMA1_Channel5_IRQHandler ; GP - DMA1 Channel 5 glob - al interrupt - 110 000000C4 00000000 DCD GPDMA1_Channel6_IRQHandler ; GP - DMA1 Channel 6 glob - al interrupt - 111 000000C8 00000000 DCD GPDMA1_Channel7_IRQHandler ; GP - DMA1 Channel 7 glob - al interrupt - 112 000000CC 00000000 DCD IWDG_IRQHandler ; IWDG global i - nterrupt - 113 000000D0 00000000 DCD 0 ; Reserved - 114 000000D4 00000000 DCD ADC1_IRQHandler ; ADC1 global i - nterrupt - 115 000000D8 00000000 DCD DAC1_IRQHandler ; DAC1 global i - nterrupt - 116 000000DC 00000000 DCD FDCAN1_IT0_IRQHandler ; FDCAN1 - interrupt 0 - 117 000000E0 00000000 DCD FDCAN1_IT1_IRQHandler ; FDCAN1 - interrupt 1 - 118 000000E4 00000000 DCD TIM1_BRK_IRQHandler ; TIM1 Brea - k interrupt - 119 000000E8 00000000 DCD TIM1_UP_IRQHandler ; TIM1 Updat - e interrupt - 120 000000EC 00000000 DCD TIM1_TRG_COM_IRQHandler ; TIM1 - Trigger and Commuta - tion interrupt - 121 000000F0 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu - re Compare interrup - t - 122 000000F4 00000000 DCD TIM2_IRQHandler ; TIM2 global i - nterrupt - 123 000000F8 00000000 DCD TIM3_IRQHandler ; TIM3 global i - nterrupt - 124 000000FC 00000000 DCD TIM4_IRQHandler ; TIM4 global i - nterrupt - 125 00000100 00000000 DCD TIM5_IRQHandler ; TIM5 global i - nterrupt - 126 00000104 00000000 DCD TIM6_IRQHandler ; TIM6 global i - nterrupt - 127 00000108 00000000 DCD TIM7_IRQHandler ; TIM7 global i - nterrupt - 128 0000010C 00000000 DCD I2C1_EV_IRQHandler ; I2C1 Event - interrupt - 129 00000110 00000000 DCD I2C1_ER_IRQHandler ; I2C1 Error - interrupt - 130 00000114 00000000 DCD I2C2_EV_IRQHandler ; I2C2 Event - interrupt - 131 00000118 00000000 DCD I2C2_ER_IRQHandler ; I2C2 Error - interrupt - 132 0000011C 00000000 DCD SPI1_IRQHandler ; SPI1 global i - nterrupt - 133 00000120 00000000 DCD SPI2_IRQHandler ; SPI2 global i - nterrupt - 134 00000124 00000000 DCD SPI3_IRQHandler ; SPI3 global i - nterrupt - - - -ARM Macro Assembler Page 5 - - - 135 00000128 00000000 DCD USART1_IRQHandler ; USART1 glob - al interrupt - 136 0000012C 00000000 DCD USART2_IRQHandler ; USART2 glob - al interrupt - 137 00000130 00000000 DCD USART3_IRQHandler ; USART3 glob - al interrupt - 138 00000134 00000000 DCD UART4_IRQHandler ; UART4 global - interrupt - 139 00000138 00000000 DCD UART5_IRQHandler ; UART5 global - interrupt - 140 0000013C 00000000 DCD LPUART1_IRQHandler ; LPUART1 gl - obal interrupt - 141 00000140 00000000 DCD LPTIM1_IRQHandler ; LPTIM1 glob - al interrupt - 142 00000144 00000000 DCD TIM8_BRK_IRQHandler ; TIM8 Brea - k interrupt - 143 00000148 00000000 DCD TIM8_UP_IRQHandler ; TIM8 Updat - e interrupt - 144 0000014C 00000000 DCD TIM8_TRG_COM_IRQHandler ; TIM8 - Trigger and Commuta - tion interrupt - 145 00000150 00000000 DCD TIM8_CC_IRQHandler ; TIM8 Captu - re Compare interrup - t - 146 00000154 00000000 DCD ADC2_IRQHandler ; ADC2 global i - nterrupt - 147 00000158 00000000 DCD LPTIM2_IRQHandler ; LPTIM2 glob - al interrupt - 148 0000015C 00000000 DCD TIM15_IRQHandler ; TIM15 global - interrupt - 149 00000160 00000000 DCD TIM16_IRQHandler ; TIM16 global - interrupt - 150 00000164 00000000 DCD TIM17_IRQHandler ; TIM17 global - interrupt - 151 00000168 00000000 DCD USB_DRD_FS_IRQHandler ; USB DRD - FS global interrup - t - 152 0000016C 00000000 DCD CRS_IRQHandler ; CRS global int - errupt - 153 00000170 00000000 DCD UCPD1_IRQHandler ; UCPD1 global - interrupt - 154 00000174 00000000 DCD FMC_IRQHandler ; FMC global int - errupt - 155 00000178 00000000 DCD OCTOSPI1_IRQHandler ; OctoSPI1 - global interrupt - 156 0000017C 00000000 DCD SDMMC1_IRQHandler ; SDMMC1 glob - al interrupt - 157 00000180 00000000 DCD I2C3_EV_IRQHandler ; I2C2 Event - interrupt - 158 00000184 00000000 DCD I2C3_ER_IRQHandler ; I2C2 Error - interrupt - 159 00000188 00000000 DCD SPI4_IRQHandler ; SPI4 global i - nterrupt - 160 0000018C 00000000 DCD SPI5_IRQHandler ; SPI5 global i - nterrupt - 161 00000190 00000000 DCD SPI6_IRQHandler ; SPI6 global i - nterrupt - 162 00000194 00000000 DCD USART6_IRQHandler ; USART6 glob - al interrupt - - - -ARM Macro Assembler Page 6 - - - 163 00000198 00000000 DCD USART10_IRQHandler ; USART10 gl - obal interrupt - 164 0000019C 00000000 DCD USART11_IRQHandler ; USART11 gl - obal interrupt - 165 000001A0 00000000 DCD SAI1_IRQHandler ; Serial Audio - Interface 1 global - interrupt - 166 000001A4 00000000 DCD SAI2_IRQHandler ; Serial Audio - Interface 2 global - interrupt - 167 000001A8 00000000 DCD GPDMA2_Channel0_IRQHandler ; GP - DMA2 Channel 0 glob - al interrupt - 168 000001AC 00000000 DCD GPDMA2_Channel1_IRQHandler ; GP - DMA2 Channel 1 glob - al interrupt - 169 000001B0 00000000 DCD GPDMA2_Channel2_IRQHandler ; GP - DMA2 Channel 2 glob - al interrupt - 170 000001B4 00000000 DCD GPDMA2_Channel3_IRQHandler ; GP - DMA2 Channel 3 glob - al interrupt - 171 000001B8 00000000 DCD GPDMA2_Channel4_IRQHandler ; GP - DMA2 Channel 4 glob - al interrupt - 172 000001BC 00000000 DCD GPDMA2_Channel5_IRQHandler ; GP - DMA2 Channel 5 glob - al interrupt - 173 000001C0 00000000 DCD GPDMA2_Channel6_IRQHandler ; GP - DMA2 Channel 6 glob - al interrupt - 174 000001C4 00000000 DCD GPDMA2_Channel7_IRQHandler ; GP - DMA2 Channel 7 glob - al interrupt - 175 000001C8 00000000 DCD UART7_IRQHandler ; UART7 global - interrupt - 176 000001CC 00000000 DCD UART8_IRQHandler ; UART8 global - interrupt - 177 000001D0 00000000 DCD UART9_IRQHandler ; UART9 global - interrupt - 178 000001D4 00000000 DCD UART12_IRQHandler ; UART12 glob - al interrupt - 179 000001D8 00000000 DCD SDMMC2_IRQHandler ; SDMMC2 glob - al interrupt - 180 000001DC 00000000 DCD FPU_IRQHandler ; FPU global int - errupt - 181 000001E0 00000000 DCD ICACHE_IRQHandler ; Instruction - cache global inter - rupt - 182 000001E4 00000000 DCD DCACHE1_IRQHandler ; DCACHE1 gl - obal interrupt - 183 000001E8 00000000 DCD ETH_IRQHandler ; Ethernet globa - l interrupt - 184 000001EC 00000000 DCD ETH_WKUP_IRQHandler ; Ethernet - Wakeup global inter - rupt - 185 000001F0 00000000 DCD DCMI_PSSI_IRQHandler ; DCMI PSS - I global interrupt - 186 000001F4 00000000 DCD FDCAN2_IT0_IRQHandler ; FDCAN2 - - - -ARM Macro Assembler Page 7 - - - interrupt 0 - 187 000001F8 00000000 DCD FDCAN2_IT1_IRQHandler ; FDCAN2 - interrupt 1 - 188 000001FC 00000000 DCD CORDIC_IRQHandler ; CORDIC glob - al interrupt - 189 00000200 00000000 DCD FMAC_IRQHandler ; FMAC global i - nterrupt - 190 00000204 00000000 DCD DTS_IRQHandler ; DTS global int - errupt - 191 00000208 00000000 DCD RNG_IRQHandler ; RNG global int - errupt - 192 0000020C 00000000 DCD 0 ; Reserved - 193 00000210 00000000 DCD 0 ; Reserved - 194 00000214 00000000 DCD HASH_IRQHandler ; HASH global i - nterrupt - 195 00000218 00000000 DCD 0 ; Reserved - 196 0000021C 00000000 DCD CEC_IRQHandler ; CEC global int - errupt - 197 00000220 00000000 DCD TIM12_IRQHandler ; TIM12 global - interrupt - 198 00000224 00000000 DCD TIM13_IRQHandler ; TIM13 global - interrupt - 199 00000228 00000000 DCD TIM14_IRQHandler ; TIM14 global - interrupt - 200 0000022C 00000000 DCD I3C1_EV_IRQHandler ; I3C1 Event - interrupt - 201 00000230 00000000 DCD I3C1_ER_IRQHandler ; I3C1 Error - interrupt - 202 00000234 00000000 DCD I2C4_EV_IRQHandler ; I2C4 Event - interrupt - 203 00000238 00000000 DCD I2C4_ER_IRQHandler ; I2C4 Error - interrupt - 204 0000023C 00000000 DCD LPTIM3_IRQHandler ; LPTIM3 glob - al interrupt - 205 00000240 00000000 DCD LPTIM4_IRQHandler ; LPTIM4 glob - al interrupt - 206 00000244 00000000 DCD LPTIM5_IRQHandler ; LPTIM5 glob - al interrupt - 207 00000248 00000000 DCD LPTIM6_IRQHandler ; LPTIM6 glob - al interrupt - 208 0000024C - 209 0000024C - 210 0000024C __Vectors_End - 211 0000024C - 212 0000024C 0000024C - __Vectors_Size - EQU __Vectors_End - __Vectors - 213 0000024C - 214 0000024C AREA |.text|, CODE, READONLY - 215 00000000 - 216 00000000 - 217 00000000 ; Reset Handler - 218 00000000 - 219 00000000 Reset_Handler - PROC - 220 00000000 EXPORT Reset_Handler [WEAK -] - 221 00000000 IMPORT SystemInit - 222 00000000 IMPORT __main - - - -ARM Macro Assembler Page 8 - - - 223 00000000 480A LDR R0, =SystemInit - 224 00000002 4780 BLX R0 - 225 00000004 480A LDR R0, =__main - 226 00000006 4700 BX R0 - 227 00000008 ENDP - 228 00000008 - 229 00000008 - 230 00000008 ; Dummy Exception Handlers (infinite loops which can be - modified) - 231 00000008 - 233 00000008 NMI_Handler - PROC - 234 00000008 EXPORT NMI_Handler [WEAK -] - 235 00000008 E7FE B . - 236 0000000A ENDP - 238 0000000A HardFault_Handler - PROC - 239 0000000A EXPORT HardFault_Handler [WEAK -] - 240 0000000A E7FE B . - 241 0000000C ENDP - 243 0000000C MemManage_Handler - PROC - 244 0000000C EXPORT MemManage_Handler [WEAK -] - 245 0000000C E7FE B . - 246 0000000E ENDP - 248 0000000E BusFault_Handler - PROC - 249 0000000E EXPORT BusFault_Handler [WEAK -] - 250 0000000E E7FE B . - 251 00000010 ENDP - 253 00000010 UsageFault_Handler - PROC - 254 00000010 EXPORT UsageFault_Handler [WEAK -] - 255 00000010 E7FE B . - 256 00000012 ENDP - 258 00000012 SecureFault_Handler - PROC - 259 00000012 EXPORT SecureFault_Handler [WEAK -] - 260 00000012 E7FE B . - 261 00000014 ENDP - 263 00000014 SVC_Handler - PROC - 264 00000014 EXPORT SVC_Handler [WEAK -] - 265 00000014 E7FE B . - 266 00000016 ENDP - 268 00000016 DebugMon_Handler - PROC - 269 00000016 EXPORT DebugMon_Handler [WEAK -] - 270 00000016 E7FE B . - 271 00000018 ENDP - 273 00000018 PendSV_Handler - - - -ARM Macro Assembler Page 9 - - - PROC - 274 00000018 EXPORT PendSV_Handler [WEAK -] - 275 00000018 E7FE B . - 276 0000001A ENDP - 278 0000001A SysTick_Handler - PROC - 279 0000001A EXPORT SysTick_Handler [WEAK -] - 280 0000001A E7FE B . - 281 0000001C ENDP - 282 0000001C - 283 0000001C Default_Handler - PROC - 284 0000001C - 285 0000001C EXPORT WWDG_IRQHandler - [WEAK] - 286 0000001C EXPORT PVD_AVD_IRQHandler - [WEAK] - 287 0000001C EXPORT RTC_IRQHandler - [WEAK] - 288 0000001C EXPORT RTC_S_IRQHandler - [WEAK] - 289 0000001C EXPORT TAMP_IRQHandler - [WEAK] - 290 0000001C EXPORT RAMCFG_IRQHandler - [WEAK] - 291 0000001C EXPORT FLASH_IRQHandler - [WEAK] - 292 0000001C EXPORT FLASH_S_IRQHandler - [WEAK] - 293 0000001C EXPORT GTZC_IRQHandler - [WEAK] - 294 0000001C EXPORT RCC_IRQHandler - [WEAK] - 295 0000001C EXPORT RCC_S_IRQHandler - [WEAK] - 296 0000001C EXPORT EXTI0_IRQHandler - [WEAK] - 297 0000001C EXPORT EXTI1_IRQHandler - [WEAK] - 298 0000001C EXPORT EXTI2_IRQHandler - [WEAK] - 299 0000001C EXPORT EXTI3_IRQHandler - [WEAK] - 300 0000001C EXPORT EXTI4_IRQHandler - [WEAK] - 301 0000001C EXPORT EXTI5_IRQHandler - [WEAK] - 302 0000001C EXPORT EXTI6_IRQHandler - [WEAK] - 303 0000001C EXPORT EXTI7_IRQHandler - [WEAK] - 304 0000001C EXPORT EXTI8_IRQHandler - [WEAK] - 305 0000001C EXPORT EXTI9_IRQHandler - [WEAK] - 306 0000001C EXPORT EXTI10_IRQHandler - [WEAK] - - - -ARM Macro Assembler Page 10 - - - 307 0000001C EXPORT EXTI11_IRQHandler - [WEAK] - 308 0000001C EXPORT EXTI12_IRQHandler - [WEAK] - 309 0000001C EXPORT EXTI13_IRQHandler - [WEAK] - 310 0000001C EXPORT EXTI14_IRQHandler - [WEAK] - 311 0000001C EXPORT EXTI15_IRQHandler - [WEAK] - 312 0000001C EXPORT GPDMA1_Channel0_IRQHandler - [WEAK] - 313 0000001C EXPORT GPDMA1_Channel1_IRQHandler - [WEAK] - 314 0000001C EXPORT GPDMA1_Channel2_IRQHandler - [WEAK] - 315 0000001C EXPORT GPDMA1_Channel3_IRQHandler - [WEAK] - 316 0000001C EXPORT GPDMA1_Channel4_IRQHandler - [WEAK] - 317 0000001C EXPORT GPDMA1_Channel5_IRQHandler - [WEAK] - 318 0000001C EXPORT GPDMA1_Channel6_IRQHandler - [WEAK] - 319 0000001C EXPORT GPDMA1_Channel7_IRQHandler - [WEAK] - 320 0000001C EXPORT IWDG_IRQHandler - [WEAK] - 321 0000001C EXPORT ADC1_IRQHandler - [WEAK] - 322 0000001C EXPORT DAC1_IRQHandler - [WEAK] - 323 0000001C EXPORT FDCAN1_IT0_IRQHandler - [WEAK] - 324 0000001C EXPORT FDCAN1_IT1_IRQHandler - [WEAK] - 325 0000001C EXPORT TIM1_BRK_IRQHandler - [WEAK] - 326 0000001C EXPORT TIM1_UP_IRQHandler - [WEAK] - 327 0000001C EXPORT TIM1_TRG_COM_IRQHandler - [WEAK] - 328 0000001C EXPORT TIM1_CC_IRQHandler - [WEAK] - 329 0000001C EXPORT TIM2_IRQHandler - [WEAK] - 330 0000001C EXPORT TIM3_IRQHandler - [WEAK] - 331 0000001C EXPORT TIM4_IRQHandler - [WEAK] - 332 0000001C EXPORT TIM5_IRQHandler - [WEAK] - 333 0000001C EXPORT TIM6_IRQHandler - [WEAK] - 334 0000001C EXPORT TIM7_IRQHandler - [WEAK] - 335 0000001C EXPORT I2C1_EV_IRQHandler - [WEAK] - 336 0000001C EXPORT I2C1_ER_IRQHandler - - - -ARM Macro Assembler Page 11 - - - [WEAK] - 337 0000001C EXPORT I2C2_EV_IRQHandler - [WEAK] - 338 0000001C EXPORT I2C2_ER_IRQHandler - [WEAK] - 339 0000001C EXPORT SPI1_IRQHandler - [WEAK] - 340 0000001C EXPORT SPI2_IRQHandler - [WEAK] - 341 0000001C EXPORT SPI3_IRQHandler - [WEAK] - 342 0000001C EXPORT USART1_IRQHandler - [WEAK] - 343 0000001C EXPORT USART2_IRQHandler - [WEAK] - 344 0000001C EXPORT USART3_IRQHandler - [WEAK] - 345 0000001C EXPORT UART4_IRQHandler - [WEAK] - 346 0000001C EXPORT UART5_IRQHandler - [WEAK] - 347 0000001C EXPORT LPUART1_IRQHandler - [WEAK] - 348 0000001C EXPORT LPTIM1_IRQHandler - [WEAK] - 349 0000001C EXPORT TIM8_BRK_IRQHandler - [WEAK] - 350 0000001C EXPORT TIM8_UP_IRQHandler - [WEAK] - 351 0000001C EXPORT TIM8_TRG_COM_IRQHandler - [WEAK] - 352 0000001C EXPORT TIM8_CC_IRQHandler - [WEAK] - 353 0000001C EXPORT ADC2_IRQHandler - [WEAK] - 354 0000001C EXPORT LPTIM2_IRQHandler - [WEAK] - 355 0000001C EXPORT TIM15_IRQHandler - [WEAK] - 356 0000001C EXPORT TIM16_IRQHandler - [WEAK] - 357 0000001C EXPORT TIM17_IRQHandler - [WEAK] - 358 0000001C EXPORT USB_DRD_FS_IRQHandler - [WEAK] - 359 0000001C EXPORT CRS_IRQHandler - [WEAK] - 360 0000001C EXPORT UCPD1_IRQHandler - [WEAK] - 361 0000001C EXPORT FMC_IRQHandler - [WEAK] - 362 0000001C EXPORT OCTOSPI1_IRQHandler - [WEAK] - 363 0000001C EXPORT SDMMC1_IRQHandler - [WEAK] - 364 0000001C EXPORT I2C3_EV_IRQHandler - [WEAK] - 365 0000001C EXPORT I2C3_ER_IRQHandler - [WEAK] - - - -ARM Macro Assembler Page 12 - - - 366 0000001C EXPORT SPI4_IRQHandler - [WEAK] - 367 0000001C EXPORT SPI5_IRQHandler - [WEAK] - 368 0000001C EXPORT SPI6_IRQHandler - [WEAK] - 369 0000001C EXPORT USART6_IRQHandler - [WEAK] - 370 0000001C EXPORT USART10_IRQHandler - [WEAK] - 371 0000001C EXPORT USART11_IRQHandler - [WEAK] - 372 0000001C EXPORT SAI1_IRQHandler - [WEAK] - 373 0000001C EXPORT SAI2_IRQHandler - [WEAK] - 374 0000001C EXPORT GPDMA2_Channel0_IRQHandler - [WEAK] - 375 0000001C EXPORT GPDMA2_Channel1_IRQHandler - [WEAK] - 376 0000001C EXPORT GPDMA2_Channel2_IRQHandler - [WEAK] - 377 0000001C EXPORT GPDMA2_Channel3_IRQHandler - [WEAK] - 378 0000001C EXPORT GPDMA2_Channel4_IRQHandler - [WEAK] - 379 0000001C EXPORT GPDMA2_Channel5_IRQHandler - [WEAK] - 380 0000001C EXPORT GPDMA2_Channel6_IRQHandler - [WEAK] - 381 0000001C EXPORT GPDMA2_Channel7_IRQHandler - [WEAK] - 382 0000001C EXPORT UART7_IRQHandler - [WEAK] - 383 0000001C EXPORT UART8_IRQHandler - [WEAK] - 384 0000001C EXPORT UART9_IRQHandler - [WEAK] - 385 0000001C EXPORT UART12_IRQHandler - [WEAK] - 386 0000001C EXPORT SDMMC2_IRQHandler - [WEAK] - 387 0000001C EXPORT FPU_IRQHandler - [WEAK] - 388 0000001C EXPORT ICACHE_IRQHandler - [WEAK] - 389 0000001C EXPORT DCACHE1_IRQHandler - [WEAK] - 390 0000001C EXPORT ETH_IRQHandler - [WEAK] - 391 0000001C EXPORT ETH_WKUP_IRQHandler - [WEAK] - 392 0000001C EXPORT DCMI_PSSI_IRQHandler - [WEAK] - 393 0000001C EXPORT FDCAN2_IT0_IRQHandler - [WEAK] - 394 0000001C EXPORT FDCAN2_IT1_IRQHandler - [WEAK] - 395 0000001C EXPORT CORDIC_IRQHandler - - - -ARM Macro Assembler Page 13 - - - [WEAK] - 396 0000001C EXPORT FMAC_IRQHandler - [WEAK] - 397 0000001C EXPORT DTS_IRQHandler - [WEAK] - 398 0000001C EXPORT RNG_IRQHandler - [WEAK] - 399 0000001C EXPORT HASH_IRQHandler - [WEAK] - 400 0000001C EXPORT CEC_IRQHandler - [WEAK] - 401 0000001C EXPORT TIM12_IRQHandler - [WEAK] - 402 0000001C EXPORT TIM13_IRQHandler - [WEAK] - 403 0000001C EXPORT TIM14_IRQHandler - [WEAK] - 404 0000001C EXPORT I3C1_EV_IRQHandler - [WEAK] - 405 0000001C EXPORT I3C1_ER_IRQHandler - [WEAK] - 406 0000001C EXPORT I2C4_EV_IRQHandler - [WEAK] - 407 0000001C EXPORT I2C4_ER_IRQHandler - [WEAK] - 408 0000001C EXPORT LPTIM3_IRQHandler - [WEAK] - 409 0000001C EXPORT LPTIM4_IRQHandler - [WEAK] - 410 0000001C EXPORT LPTIM5_IRQHandler - [WEAK] - 411 0000001C EXPORT LPTIM6_IRQHandler - [WEAK] - 412 0000001C - 413 0000001C WWDG_IRQHandler - 414 0000001C PVD_AVD_IRQHandler - 415 0000001C RTC_IRQHandler - 416 0000001C RTC_S_IRQHandler - 417 0000001C TAMP_IRQHandler - 418 0000001C RAMCFG_IRQHandler - 419 0000001C FLASH_IRQHandler - 420 0000001C FLASH_S_IRQHandler - 421 0000001C GTZC_IRQHandler - 422 0000001C RCC_IRQHandler - 423 0000001C RCC_S_IRQHandler - 424 0000001C EXTI0_IRQHandler - 425 0000001C EXTI1_IRQHandler - 426 0000001C EXTI2_IRQHandler - 427 0000001C EXTI3_IRQHandler - 428 0000001C EXTI4_IRQHandler - 429 0000001C EXTI5_IRQHandler - 430 0000001C EXTI6_IRQHandler - 431 0000001C EXTI7_IRQHandler - 432 0000001C EXTI8_IRQHandler - 433 0000001C EXTI9_IRQHandler - 434 0000001C EXTI10_IRQHandler - 435 0000001C EXTI11_IRQHandler - 436 0000001C EXTI12_IRQHandler - 437 0000001C EXTI13_IRQHandler - - - -ARM Macro Assembler Page 14 - - - 438 0000001C EXTI14_IRQHandler - 439 0000001C EXTI15_IRQHandler - 440 0000001C GPDMA1_Channel0_IRQHandler - 441 0000001C GPDMA1_Channel1_IRQHandler - 442 0000001C GPDMA1_Channel2_IRQHandler - 443 0000001C GPDMA1_Channel3_IRQHandler - 444 0000001C GPDMA1_Channel4_IRQHandler - 445 0000001C GPDMA1_Channel5_IRQHandler - 446 0000001C GPDMA1_Channel6_IRQHandler - 447 0000001C GPDMA1_Channel7_IRQHandler - 448 0000001C IWDG_IRQHandler - 449 0000001C ADC1_IRQHandler - 450 0000001C DAC1_IRQHandler - 451 0000001C FDCAN1_IT0_IRQHandler - 452 0000001C FDCAN1_IT1_IRQHandler - 453 0000001C TIM1_BRK_IRQHandler - 454 0000001C TIM1_UP_IRQHandler - 455 0000001C TIM1_TRG_COM_IRQHandler - 456 0000001C TIM1_CC_IRQHandler - 457 0000001C TIM2_IRQHandler - 458 0000001C TIM3_IRQHandler - 459 0000001C TIM4_IRQHandler - 460 0000001C TIM5_IRQHandler - 461 0000001C TIM6_IRQHandler - 462 0000001C TIM7_IRQHandler - 463 0000001C I2C1_EV_IRQHandler - 464 0000001C I2C1_ER_IRQHandler - 465 0000001C I2C2_EV_IRQHandler - 466 0000001C I2C2_ER_IRQHandler - 467 0000001C SPI1_IRQHandler - 468 0000001C SPI2_IRQHandler - 469 0000001C SPI3_IRQHandler - 470 0000001C USART1_IRQHandler - 471 0000001C USART2_IRQHandler - 472 0000001C USART3_IRQHandler - 473 0000001C UART4_IRQHandler - 474 0000001C UART5_IRQHandler - 475 0000001C LPUART1_IRQHandler - 476 0000001C LPTIM1_IRQHandler - 477 0000001C TIM8_BRK_IRQHandler - 478 0000001C TIM8_UP_IRQHandler - 479 0000001C TIM8_TRG_COM_IRQHandler - 480 0000001C TIM8_CC_IRQHandler - 481 0000001C ADC2_IRQHandler - 482 0000001C LPTIM2_IRQHandler - 483 0000001C TIM15_IRQHandler - 484 0000001C TIM16_IRQHandler - 485 0000001C TIM17_IRQHandler - 486 0000001C USB_DRD_FS_IRQHandler - 487 0000001C CRS_IRQHandler - 488 0000001C UCPD1_IRQHandler - 489 0000001C FMC_IRQHandler - 490 0000001C OCTOSPI1_IRQHandler - 491 0000001C SDMMC1_IRQHandler - 492 0000001C I2C3_EV_IRQHandler - 493 0000001C I2C3_ER_IRQHandler - 494 0000001C SPI4_IRQHandler - 495 0000001C SPI5_IRQHandler - 496 0000001C SPI6_IRQHandler - - - -ARM Macro Assembler Page 15 - - - 497 0000001C USART6_IRQHandler - 498 0000001C USART10_IRQHandler - 499 0000001C USART11_IRQHandler - 500 0000001C SAI1_IRQHandler - 501 0000001C SAI2_IRQHandler - 502 0000001C GPDMA2_Channel0_IRQHandler - 503 0000001C GPDMA2_Channel1_IRQHandler - 504 0000001C GPDMA2_Channel2_IRQHandler - 505 0000001C GPDMA2_Channel3_IRQHandler - 506 0000001C GPDMA2_Channel4_IRQHandler - 507 0000001C GPDMA2_Channel5_IRQHandler - 508 0000001C GPDMA2_Channel6_IRQHandler - 509 0000001C GPDMA2_Channel7_IRQHandler - 510 0000001C UART7_IRQHandler - 511 0000001C UART8_IRQHandler - 512 0000001C UART9_IRQHandler - 513 0000001C UART12_IRQHandler - 514 0000001C SDMMC2_IRQHandler - 515 0000001C FPU_IRQHandler - 516 0000001C ICACHE_IRQHandler - 517 0000001C DCACHE1_IRQHandler - 518 0000001C ETH_IRQHandler - 519 0000001C ETH_WKUP_IRQHandler - 520 0000001C DCMI_PSSI_IRQHandler - 521 0000001C FDCAN2_IT0_IRQHandler - 522 0000001C FDCAN2_IT1_IRQHandler - 523 0000001C CORDIC_IRQHandler - 524 0000001C FMAC_IRQHandler - 525 0000001C DTS_IRQHandler - 526 0000001C RNG_IRQHandler - 527 0000001C HASH_IRQHandler - 528 0000001C CEC_IRQHandler - 529 0000001C TIM12_IRQHandler - 530 0000001C TIM13_IRQHandler - 531 0000001C TIM14_IRQHandler - 532 0000001C I3C1_EV_IRQHandler - 533 0000001C I3C1_ER_IRQHandler - 534 0000001C I2C4_EV_IRQHandler - 535 0000001C I2C4_ER_IRQHandler - 536 0000001C LPTIM3_IRQHandler - 537 0000001C LPTIM4_IRQHandler - 538 0000001C LPTIM5_IRQHandler - 539 0000001C LPTIM6_IRQHandler - 540 0000001C - 541 0000001C E7FE B . - 542 0000001E - 543 0000001E ENDP - 544 0000001E - 545 0000001E 00 00 ALIGN - 546 00000020 - 547 00000020 ;******************************************************* - ************************ - 548 00000020 ; User Stack and Heap initialization - 549 00000020 ;******************************************************* - ************************ - 550 00000020 IF :DEF:__MICROLIB - 557 00000020 - 558 00000020 IMPORT __use_two_region_memory - 559 00000020 EXPORT __user_initial_stackheap - - - -ARM Macro Assembler Page 16 - - - 560 00000020 - 561 00000020 __user_initial_stackheap - PROC - 562 00000020 4804 LDR R0, = Heap_Mem - 563 00000022 4905 LDR R1, =(Stack_Mem + Stack_Size) - 564 00000024 4A05 LDR R2, = (Heap_Mem + Heap_Size) - 565 00000026 4B06 LDR R3, = Stack_Mem - 566 00000028 4770 BX LR - 567 0000002A ENDP - 568 0000002A - 569 0000002A 00 00 ALIGN - 570 0000002C - 571 0000002C ENDIF - 572 0000002C - 573 0000002C END - 00000000 - 00000000 - 00000000 - 00000400 - 00000200 - 00000000 -Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M33 --fpu=FPv5-S -P --depend=.\build\keil\obj\startup_stm32h563xx.d -o.\build\keil\obj\startup_st -m32h563xx.o -ID:\1_tool_prog\2_MDK\pack\Keil\STM32H5xx_DFP\1.1.0\Drivers\CMSIS\ -Device\ST\STM32H5xx\Include --predefine="__UVISION_VERSION SETA 536" --predefin -e="STM32H563xx SETA 1" --list=startup_stm32h563xx.lst ..\libraries\stm32h5xx_HA -L\CMSIS\Device\ST\stm32h5xx\Source\Templates\arm\startup_stm32h563xx.s - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -STACK 00000000 - -Symbol: STACK - Definitions - At line 34 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - Uses - None -Comment: STACK unused -Stack_Mem 00000000 - -Symbol: Stack_Mem - Definitions - At line 35 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - Uses - At line 563 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 565 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -__initial_sp 00000400 - -Symbol: __initial_sp - Definitions - At line 36 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - Uses - At line 60 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s -Comment: __initial_sp used once -3 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -HEAP 00000000 - -Symbol: HEAP - Definitions - At line 45 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - Uses - None -Comment: HEAP unused -Heap_Mem 00000000 - -Symbol: Heap_Mem - Definitions - At line 47 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - Uses - At line 562 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 564 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -__heap_base 00000000 - -Symbol: __heap_base - Definitions - At line 46 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - Uses - None -Comment: __heap_base unused -__heap_limit 00000200 - -Symbol: __heap_limit - Definitions - At line 48 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - Uses - None -Comment: __heap_limit unused -4 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -RESET 00000000 - -Symbol: RESET - Definitions - At line 55 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - Uses - None -Comment: RESET unused -__Vectors 00000000 - -Symbol: __Vectors - Definitions - At line 60 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - Uses - At line 56 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 212 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -__Vectors_End 0000024C - -Symbol: __Vectors_End - Definitions - At line 210 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 57 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 212 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -3 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -.text 00000000 - -Symbol: .text - Definitions - At line 214 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - None -Comment: .text unused -ADC1_IRQHandler 0000001C - -Symbol: ADC1_IRQHandler - Definitions - At line 449 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 114 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 321 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -ADC2_IRQHandler 0000001C - -Symbol: ADC2_IRQHandler - Definitions - At line 481 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 146 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 353 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -BusFault_Handler 0000000E - -Symbol: BusFault_Handler - Definitions - At line 248 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 65 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 249 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -CEC_IRQHandler 0000001C - -Symbol: CEC_IRQHandler - Definitions - At line 528 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 196 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 400 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -CORDIC_IRQHandler 0000001C - - - - -ARM Macro Assembler Page 2 Alphabetic symbol ordering -Relocatable symbols - -Symbol: CORDIC_IRQHandler - Definitions - At line 523 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 188 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 395 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -CRS_IRQHandler 0000001C - -Symbol: CRS_IRQHandler - Definitions - At line 487 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 152 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 359 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -DAC1_IRQHandler 0000001C - -Symbol: DAC1_IRQHandler - Definitions - At line 450 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 115 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 322 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -DCACHE1_IRQHandler 0000001C - -Symbol: DCACHE1_IRQHandler - Definitions - At line 517 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 182 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 389 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -DCMI_PSSI_IRQHandler 0000001C - -Symbol: DCMI_PSSI_IRQHandler - Definitions - At line 520 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 185 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 392 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -DTS_IRQHandler 0000001C - - - -ARM Macro Assembler Page 3 Alphabetic symbol ordering -Relocatable symbols - - -Symbol: DTS_IRQHandler - Definitions - At line 525 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 190 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 397 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -DebugMon_Handler 00000016 - -Symbol: DebugMon_Handler - Definitions - At line 268 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 72 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 269 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -Default_Handler 0000001C - -Symbol: Default_Handler - Definitions - At line 283 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - None -Comment: Default_Handler unused -ETH_IRQHandler 0000001C - -Symbol: ETH_IRQHandler - Definitions - At line 518 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 183 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 390 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -ETH_WKUP_IRQHandler 0000001C - -Symbol: ETH_WKUP_IRQHandler - Definitions - At line 519 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 184 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 391 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -EXTI0_IRQHandler 0000001C - -Symbol: EXTI0_IRQHandler - - - -ARM Macro Assembler Page 4 Alphabetic symbol ordering -Relocatable symbols - - Definitions - At line 424 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 88 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 296 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -EXTI10_IRQHandler 0000001C - -Symbol: EXTI10_IRQHandler - Definitions - At line 434 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 98 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 306 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -EXTI11_IRQHandler 0000001C - -Symbol: EXTI11_IRQHandler - Definitions - At line 435 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 99 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 307 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -EXTI12_IRQHandler 0000001C - -Symbol: EXTI12_IRQHandler - Definitions - At line 436 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 100 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 308 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -EXTI13_IRQHandler 0000001C - -Symbol: EXTI13_IRQHandler - Definitions - At line 437 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 101 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 309 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -EXTI14_IRQHandler 0000001C - - - - -ARM Macro Assembler Page 5 Alphabetic symbol ordering -Relocatable symbols - -Symbol: EXTI14_IRQHandler - Definitions - At line 438 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 102 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 310 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -EXTI15_IRQHandler 0000001C - -Symbol: EXTI15_IRQHandler - Definitions - At line 439 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 103 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 311 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -EXTI1_IRQHandler 0000001C - -Symbol: EXTI1_IRQHandler - Definitions - At line 425 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 89 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 297 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -EXTI2_IRQHandler 0000001C - -Symbol: EXTI2_IRQHandler - Definitions - At line 426 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 90 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 298 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -EXTI3_IRQHandler 0000001C - -Symbol: EXTI3_IRQHandler - Definitions - At line 427 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 91 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 299 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -EXTI4_IRQHandler 0000001C - - - -ARM Macro Assembler Page 6 Alphabetic symbol ordering -Relocatable symbols - - -Symbol: EXTI4_IRQHandler - Definitions - At line 428 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 92 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 300 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -EXTI5_IRQHandler 0000001C - -Symbol: EXTI5_IRQHandler - Definitions - At line 429 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 93 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 301 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -EXTI6_IRQHandler 0000001C - -Symbol: EXTI6_IRQHandler - Definitions - At line 430 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 94 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 302 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -EXTI7_IRQHandler 0000001C - -Symbol: EXTI7_IRQHandler - Definitions - At line 431 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 95 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 303 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -EXTI8_IRQHandler 0000001C - -Symbol: EXTI8_IRQHandler - Definitions - At line 432 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 96 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 304 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - - - - -ARM Macro Assembler Page 7 Alphabetic symbol ordering -Relocatable symbols - -EXTI9_IRQHandler 0000001C - -Symbol: EXTI9_IRQHandler - Definitions - At line 433 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 97 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 305 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -FDCAN1_IT0_IRQHandler 0000001C - -Symbol: FDCAN1_IT0_IRQHandler - Definitions - At line 451 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 116 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 323 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -FDCAN1_IT1_IRQHandler 0000001C - -Symbol: FDCAN1_IT1_IRQHandler - Definitions - At line 452 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 117 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 324 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -FDCAN2_IT0_IRQHandler 0000001C - -Symbol: FDCAN2_IT0_IRQHandler - Definitions - At line 521 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 186 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 393 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -FDCAN2_IT1_IRQHandler 0000001C - -Symbol: FDCAN2_IT1_IRQHandler - Definitions - At line 522 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 187 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 394 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - - - -ARM Macro Assembler Page 8 Alphabetic symbol ordering -Relocatable symbols - - -FLASH_IRQHandler 0000001C - -Symbol: FLASH_IRQHandler - Definitions - At line 419 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 83 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 291 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -FLASH_S_IRQHandler 0000001C - -Symbol: FLASH_S_IRQHandler - Definitions - At line 420 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 84 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 292 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -FMAC_IRQHandler 0000001C - -Symbol: FMAC_IRQHandler - Definitions - At line 524 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 189 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 396 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -FMC_IRQHandler 0000001C - -Symbol: FMC_IRQHandler - Definitions - At line 489 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 154 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 361 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -FPU_IRQHandler 0000001C - -Symbol: FPU_IRQHandler - Definitions - At line 515 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 180 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 387 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ - - - -ARM Macro Assembler Page 9 Alphabetic symbol ordering -Relocatable symbols - -Source\Templates\arm\startup_stm32h563xx.s - -GPDMA1_Channel0_IRQHandler 0000001C - -Symbol: GPDMA1_Channel0_IRQHandler - Definitions - At line 440 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 104 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 312 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -GPDMA1_Channel1_IRQHandler 0000001C - -Symbol: GPDMA1_Channel1_IRQHandler - Definitions - At line 441 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 105 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 313 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -GPDMA1_Channel2_IRQHandler 0000001C - -Symbol: GPDMA1_Channel2_IRQHandler - Definitions - At line 442 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 106 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 314 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -GPDMA1_Channel3_IRQHandler 0000001C - -Symbol: GPDMA1_Channel3_IRQHandler - Definitions - At line 443 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 107 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 315 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -GPDMA1_Channel4_IRQHandler 0000001C - -Symbol: GPDMA1_Channel4_IRQHandler - Definitions - At line 444 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 108 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - - - -ARM Macro Assembler Page 10 Alphabetic symbol ordering -Relocatable symbols - - At line 316 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -GPDMA1_Channel5_IRQHandler 0000001C - -Symbol: GPDMA1_Channel5_IRQHandler - Definitions - At line 445 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 109 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 317 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -GPDMA1_Channel6_IRQHandler 0000001C - -Symbol: GPDMA1_Channel6_IRQHandler - Definitions - At line 446 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 110 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 318 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -GPDMA1_Channel7_IRQHandler 0000001C - -Symbol: GPDMA1_Channel7_IRQHandler - Definitions - At line 447 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 111 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 319 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -GPDMA2_Channel0_IRQHandler 0000001C - -Symbol: GPDMA2_Channel0_IRQHandler - Definitions - At line 502 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 167 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 374 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -GPDMA2_Channel1_IRQHandler 0000001C - -Symbol: GPDMA2_Channel1_IRQHandler - Definitions - At line 503 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 168 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ - - - -ARM Macro Assembler Page 11 Alphabetic symbol ordering -Relocatable symbols - -Source\Templates\arm\startup_stm32h563xx.s - At line 375 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -GPDMA2_Channel2_IRQHandler 0000001C - -Symbol: GPDMA2_Channel2_IRQHandler - Definitions - At line 504 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 169 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 376 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -GPDMA2_Channel3_IRQHandler 0000001C - -Symbol: GPDMA2_Channel3_IRQHandler - Definitions - At line 505 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 170 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 377 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -GPDMA2_Channel4_IRQHandler 0000001C - -Symbol: GPDMA2_Channel4_IRQHandler - Definitions - At line 506 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 171 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 378 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -GPDMA2_Channel5_IRQHandler 0000001C - -Symbol: GPDMA2_Channel5_IRQHandler - Definitions - At line 507 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 172 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 379 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -GPDMA2_Channel6_IRQHandler 0000001C - -Symbol: GPDMA2_Channel6_IRQHandler - Definitions - At line 508 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - - - -ARM Macro Assembler Page 12 Alphabetic symbol ordering -Relocatable symbols - - At line 173 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 380 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -GPDMA2_Channel7_IRQHandler 0000001C - -Symbol: GPDMA2_Channel7_IRQHandler - Definitions - At line 509 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 174 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 381 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -GTZC_IRQHandler 0000001C - -Symbol: GTZC_IRQHandler - Definitions - At line 421 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 85 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 293 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -HASH_IRQHandler 0000001C - -Symbol: HASH_IRQHandler - Definitions - At line 527 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 194 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 399 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -HardFault_Handler 0000000A - -Symbol: HardFault_Handler - Definitions - At line 238 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 63 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 239 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -I2C1_ER_IRQHandler 0000001C - -Symbol: I2C1_ER_IRQHandler - Definitions - At line 464 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - - - -ARM Macro Assembler Page 13 Alphabetic symbol ordering -Relocatable symbols - - Uses - At line 129 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 336 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -I2C1_EV_IRQHandler 0000001C - -Symbol: I2C1_EV_IRQHandler - Definitions - At line 463 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 128 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 335 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -I2C2_ER_IRQHandler 0000001C - -Symbol: I2C2_ER_IRQHandler - Definitions - At line 466 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 131 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 338 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -I2C2_EV_IRQHandler 0000001C - -Symbol: I2C2_EV_IRQHandler - Definitions - At line 465 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 130 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 337 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -I2C3_ER_IRQHandler 0000001C - -Symbol: I2C3_ER_IRQHandler - Definitions - At line 493 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 158 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 365 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -I2C3_EV_IRQHandler 0000001C - -Symbol: I2C3_EV_IRQHandler - Definitions - At line 492 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ - - - -ARM Macro Assembler Page 14 Alphabetic symbol ordering -Relocatable symbols - -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 157 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 364 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -I2C4_ER_IRQHandler 0000001C - -Symbol: I2C4_ER_IRQHandler - Definitions - At line 535 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 203 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 407 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -I2C4_EV_IRQHandler 0000001C - -Symbol: I2C4_EV_IRQHandler - Definitions - At line 534 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 202 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 406 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -I3C1_ER_IRQHandler 0000001C - -Symbol: I3C1_ER_IRQHandler - Definitions - At line 533 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 201 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 405 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -I3C1_EV_IRQHandler 0000001C - -Symbol: I3C1_EV_IRQHandler - Definitions - At line 532 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 200 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 404 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -ICACHE_IRQHandler 0000001C - -Symbol: ICACHE_IRQHandler - Definitions - - - -ARM Macro Assembler Page 15 Alphabetic symbol ordering -Relocatable symbols - - At line 516 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 181 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 388 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -IWDG_IRQHandler 0000001C - -Symbol: IWDG_IRQHandler - Definitions - At line 448 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 112 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 320 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -LPTIM1_IRQHandler 0000001C - -Symbol: LPTIM1_IRQHandler - Definitions - At line 476 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 141 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 348 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -LPTIM2_IRQHandler 0000001C - -Symbol: LPTIM2_IRQHandler - Definitions - At line 482 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 147 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 354 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -LPTIM3_IRQHandler 0000001C - -Symbol: LPTIM3_IRQHandler - Definitions - At line 536 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 204 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 408 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -LPTIM4_IRQHandler 0000001C - -Symbol: LPTIM4_IRQHandler - - - -ARM Macro Assembler Page 16 Alphabetic symbol ordering -Relocatable symbols - - Definitions - At line 537 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 205 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 409 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -LPTIM5_IRQHandler 0000001C - -Symbol: LPTIM5_IRQHandler - Definitions - At line 538 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 206 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 410 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -LPTIM6_IRQHandler 0000001C - -Symbol: LPTIM6_IRQHandler - Definitions - At line 539 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 207 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 411 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -LPUART1_IRQHandler 0000001C - -Symbol: LPUART1_IRQHandler - Definitions - At line 475 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 140 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 347 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -MemManage_Handler 0000000C - -Symbol: MemManage_Handler - Definitions - At line 243 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 64 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 244 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -NMI_Handler 00000008 - - - - -ARM Macro Assembler Page 17 Alphabetic symbol ordering -Relocatable symbols - -Symbol: NMI_Handler - Definitions - At line 233 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 62 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 234 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -OCTOSPI1_IRQHandler 0000001C - -Symbol: OCTOSPI1_IRQHandler - Definitions - At line 490 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 155 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 362 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -PVD_AVD_IRQHandler 0000001C - -Symbol: PVD_AVD_IRQHandler - Definitions - At line 414 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 78 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 286 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -PendSV_Handler 00000018 - -Symbol: PendSV_Handler - Definitions - At line 273 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 74 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 274 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -RAMCFG_IRQHandler 0000001C - -Symbol: RAMCFG_IRQHandler - Definitions - At line 418 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 82 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 290 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -RCC_IRQHandler 0000001C - - - -ARM Macro Assembler Page 18 Alphabetic symbol ordering -Relocatable symbols - - -Symbol: RCC_IRQHandler - Definitions - At line 422 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 86 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 294 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -RCC_S_IRQHandler 0000001C - -Symbol: RCC_S_IRQHandler - Definitions - At line 423 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 87 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 295 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -RNG_IRQHandler 0000001C - -Symbol: RNG_IRQHandler - Definitions - At line 526 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 191 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 398 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -RTC_IRQHandler 0000001C - -Symbol: RTC_IRQHandler - Definitions - At line 415 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 79 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 287 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -RTC_S_IRQHandler 0000001C - -Symbol: RTC_S_IRQHandler - Definitions - At line 416 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 80 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 288 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - - - - -ARM Macro Assembler Page 19 Alphabetic symbol ordering -Relocatable symbols - -Reset_Handler 00000000 - -Symbol: Reset_Handler - Definitions - At line 219 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 61 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 220 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -SAI1_IRQHandler 0000001C - -Symbol: SAI1_IRQHandler - Definitions - At line 500 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 165 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 372 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -SAI2_IRQHandler 0000001C - -Symbol: SAI2_IRQHandler - Definitions - At line 501 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 166 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 373 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -SDMMC1_IRQHandler 0000001C - -Symbol: SDMMC1_IRQHandler - Definitions - At line 491 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 156 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 363 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -SDMMC2_IRQHandler 0000001C - -Symbol: SDMMC2_IRQHandler - Definitions - At line 514 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 179 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 386 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - - - -ARM Macro Assembler Page 20 Alphabetic symbol ordering -Relocatable symbols - - -SPI1_IRQHandler 0000001C - -Symbol: SPI1_IRQHandler - Definitions - At line 467 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 132 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 339 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -SPI2_IRQHandler 0000001C - -Symbol: SPI2_IRQHandler - Definitions - At line 468 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 133 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 340 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -SPI3_IRQHandler 0000001C - -Symbol: SPI3_IRQHandler - Definitions - At line 469 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 134 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 341 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -SPI4_IRQHandler 0000001C - -Symbol: SPI4_IRQHandler - Definitions - At line 494 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 159 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 366 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -SPI5_IRQHandler 0000001C - -Symbol: SPI5_IRQHandler - Definitions - At line 495 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 160 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 367 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ - - - -ARM Macro Assembler Page 21 Alphabetic symbol ordering -Relocatable symbols - -Source\Templates\arm\startup_stm32h563xx.s - -SPI6_IRQHandler 0000001C - -Symbol: SPI6_IRQHandler - Definitions - At line 496 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 161 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 368 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -SVC_Handler 00000014 - -Symbol: SVC_Handler - Definitions - At line 263 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 71 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 264 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -SecureFault_Handler 00000012 - -Symbol: SecureFault_Handler - Definitions - At line 258 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 67 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 259 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -SysTick_Handler 0000001A - -Symbol: SysTick_Handler - Definitions - At line 278 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 75 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 279 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TAMP_IRQHandler 0000001C - -Symbol: TAMP_IRQHandler - Definitions - At line 417 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 81 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - - - -ARM Macro Assembler Page 22 Alphabetic symbol ordering -Relocatable symbols - - At line 289 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TIM12_IRQHandler 0000001C - -Symbol: TIM12_IRQHandler - Definitions - At line 529 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 197 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 401 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TIM13_IRQHandler 0000001C - -Symbol: TIM13_IRQHandler - Definitions - At line 530 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 198 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 402 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TIM14_IRQHandler 0000001C - -Symbol: TIM14_IRQHandler - Definitions - At line 531 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 199 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 403 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TIM15_IRQHandler 0000001C - -Symbol: TIM15_IRQHandler - Definitions - At line 483 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 148 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 355 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TIM16_IRQHandler 0000001C - -Symbol: TIM16_IRQHandler - Definitions - At line 484 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 149 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ - - - -ARM Macro Assembler Page 23 Alphabetic symbol ordering -Relocatable symbols - -Source\Templates\arm\startup_stm32h563xx.s - At line 356 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TIM17_IRQHandler 0000001C - -Symbol: TIM17_IRQHandler - Definitions - At line 485 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 150 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 357 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TIM1_BRK_IRQHandler 0000001C - -Symbol: TIM1_BRK_IRQHandler - Definitions - At line 453 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 118 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 325 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TIM1_CC_IRQHandler 0000001C - -Symbol: TIM1_CC_IRQHandler - Definitions - At line 456 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 121 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 328 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TIM1_TRG_COM_IRQHandler 0000001C - -Symbol: TIM1_TRG_COM_IRQHandler - Definitions - At line 455 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 120 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 327 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TIM1_UP_IRQHandler 0000001C - -Symbol: TIM1_UP_IRQHandler - Definitions - At line 454 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - - - -ARM Macro Assembler Page 24 Alphabetic symbol ordering -Relocatable symbols - - At line 119 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 326 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TIM2_IRQHandler 0000001C - -Symbol: TIM2_IRQHandler - Definitions - At line 457 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 122 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 329 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TIM3_IRQHandler 0000001C - -Symbol: TIM3_IRQHandler - Definitions - At line 458 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 123 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 330 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TIM4_IRQHandler 0000001C - -Symbol: TIM4_IRQHandler - Definitions - At line 459 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 124 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 331 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TIM5_IRQHandler 0000001C - -Symbol: TIM5_IRQHandler - Definitions - At line 460 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 125 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 332 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TIM6_IRQHandler 0000001C - -Symbol: TIM6_IRQHandler - Definitions - At line 461 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - - - -ARM Macro Assembler Page 25 Alphabetic symbol ordering -Relocatable symbols - - Uses - At line 126 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 333 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TIM7_IRQHandler 0000001C - -Symbol: TIM7_IRQHandler - Definitions - At line 462 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 127 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 334 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TIM8_BRK_IRQHandler 0000001C - -Symbol: TIM8_BRK_IRQHandler - Definitions - At line 477 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 142 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 349 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TIM8_CC_IRQHandler 0000001C - -Symbol: TIM8_CC_IRQHandler - Definitions - At line 480 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 145 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 352 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TIM8_TRG_COM_IRQHandler 0000001C - -Symbol: TIM8_TRG_COM_IRQHandler - Definitions - At line 479 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 144 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 351 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -TIM8_UP_IRQHandler 0000001C - -Symbol: TIM8_UP_IRQHandler - Definitions - At line 478 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ - - - -ARM Macro Assembler Page 26 Alphabetic symbol ordering -Relocatable symbols - -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 143 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 350 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -UART12_IRQHandler 0000001C - -Symbol: UART12_IRQHandler - Definitions - At line 513 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 178 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 385 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -UART4_IRQHandler 0000001C - -Symbol: UART4_IRQHandler - Definitions - At line 473 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 138 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 345 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -UART5_IRQHandler 0000001C - -Symbol: UART5_IRQHandler - Definitions - At line 474 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 139 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 346 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -UART7_IRQHandler 0000001C - -Symbol: UART7_IRQHandler - Definitions - At line 510 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 175 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 382 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -UART8_IRQHandler 0000001C - -Symbol: UART8_IRQHandler - Definitions - - - -ARM Macro Assembler Page 27 Alphabetic symbol ordering -Relocatable symbols - - At line 511 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 176 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 383 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -UART9_IRQHandler 0000001C - -Symbol: UART9_IRQHandler - Definitions - At line 512 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 177 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 384 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -UCPD1_IRQHandler 0000001C - -Symbol: UCPD1_IRQHandler - Definitions - At line 488 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 153 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 360 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -USART10_IRQHandler 0000001C - -Symbol: USART10_IRQHandler - Definitions - At line 498 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 163 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 370 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -USART11_IRQHandler 0000001C - -Symbol: USART11_IRQHandler - Definitions - At line 499 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 164 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 371 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -USART1_IRQHandler 0000001C - -Symbol: USART1_IRQHandler - - - -ARM Macro Assembler Page 28 Alphabetic symbol ordering -Relocatable symbols - - Definitions - At line 470 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 135 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 342 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -USART2_IRQHandler 0000001C - -Symbol: USART2_IRQHandler - Definitions - At line 471 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 136 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 343 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -USART3_IRQHandler 0000001C - -Symbol: USART3_IRQHandler - Definitions - At line 472 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 137 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 344 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -USART6_IRQHandler 0000001C - -Symbol: USART6_IRQHandler - Definitions - At line 497 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 162 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 369 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -USB_DRD_FS_IRQHandler 0000001C - -Symbol: USB_DRD_FS_IRQHandler - Definitions - At line 486 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 151 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - At line 358 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -UsageFault_Handler 00000010 - - - - -ARM Macro Assembler Page 29 Alphabetic symbol ordering -Relocatable symbols - -Symbol: UsageFault_Handler - Definitions - At line 253 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 66 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 254 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -WWDG_IRQHandler 0000001C - -Symbol: WWDG_IRQHandler - Definitions - At line 413 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 77 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 285 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -__user_initial_stackheap 00000020 - -Symbol: __user_initial_stackheap - Definitions - At line 561 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 559 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s -Comment: __user_initial_stackheap used once -141 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Absolute symbols - -Heap_Size 00000200 - -Symbol: Heap_Size - Definitions - At line 43 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - Uses - At line 47 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 564 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -Stack_Size 00000400 - -Symbol: Stack_Size - Definitions - At line 32 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - Uses - At line 35 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s - At line 563 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - -__Vectors_Size 0000024C - -Symbol: __Vectors_Size - Definitions - At line 212 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 58 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\S -ource\Templates\arm\startup_stm32h563xx.s -Comment: __Vectors_Size used once -3 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -External symbols - -SystemInit 00000000 - -Symbol: SystemInit - Definitions - At line 221 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 223 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s -Comment: SystemInit used once -__main 00000000 - -Symbol: __main - Definitions - At line 222 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - At line 225 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s -Comment: __main used once -__use_two_region_memory 00000000 - -Symbol: __use_two_region_memory - Definitions - At line 558 in file ..\libraries\stm32h5xx_HAL\CMSIS\Device\ST\stm32h5xx\ -Source\Templates\arm\startup_stm32h563xx.s - Uses - None -Comment: __use_two_region_memory unused -3 symbols -494 symbols in table diff --git a/bsp/stm32/stm32h563-st-nucleo/syscall_rvds.lst b/bsp/stm32/stm32h563-st-nucleo/syscall_rvds.lst deleted file mode 100644 index 920ceefcd8b..00000000000 --- a/bsp/stm32/stm32h563-st-nucleo/syscall_rvds.lst +++ /dev/null @@ -1,177 +0,0 @@ - - - -ARM Macro Assembler Page 1 - - - 1 00000000 ;/* - 2 00000000 ; * Copyright (c) 2006-2022, RT-Thread Development Team - 3 00000000 ; * - 4 00000000 ; * SPDX-License-Identifier: Apache-2.0 - 5 00000000 ; * - 6 00000000 ; * Change Logs: - 7 00000000 ; * Date Author Notes - 8 00000000 ; * 2019-10-25 tyx first version - 9 00000000 ; */ - 10 00000000 - 11 00000000 AREA |.text|, CODE, READONLY, ALIGN= -2 - 12 00000000 THUMB - 13 00000000 REQUIRE8 - 14 00000000 PRESERVE8 - 15 00000000 - 16 00000000 IMPORT rt_secure_svc_handle - 17 00000000 - 18 00000000 ;/* - 19 00000000 ; * int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, - rt_ubase_t arg2); - 20 00000000 ; */ - 21 00000000 tzcall PROC - 22 00000000 EXPORT tzcall - 23 00000000 DF01 SVC 1 ;call SVC 1 - 24 00000002 4770 BX LR - 25 00000004 - 26 00000004 ENDP - 27 00000004 - 28 00000004 tzcall_entry - PROC - 29 00000004 B512 PUSH {R1, R4, LR} - 30 00000006 460C MOV R4, R1 ; copy thread SP to - R4 - 31 00000008 CC0F LDMFD R4!, {r0 - r3} ; pop user stack - , get input arg0, a - rg1, arg2 - 32 0000000A E924 000F STMFD R4!, {r0 - r3} ; push stack, us - er stack recovery - 33 0000000E F7FF FFFE BL rt_secure_svc_handle ; call fun - - 34 00000012 E8BD 4012 POP {R1, R4, LR} - 35 00000016 6008 STR R0, [R1] ; update return val - ue - 36 00000018 4770 BX LR ; return to thread - 37 0000001A - 38 0000001A ENDP - 39 0000001A - 40 0000001A syscall_entry - PROC - 41 0000001A 4770 BX LR ; return to user ap - p - 42 0000001C - 43 0000001C ENDP - 44 0000001C - 45 0000001C ;/* - 46 0000001C ; * void SVC_Handler(void); - 47 0000001C ; */ - 48 0000001C SVC_Handler - - - -ARM Macro Assembler Page 2 - - - PROC - 49 0000001C EXPORT SVC_Handler - 50 0000001C - 51 0000001C ; get SP, save to R1 - 52 0000001C F3EF 8108 MRS R1, MSP ;get fault context - from handler - 53 00000020 F01E 0F04 TST LR, #0x04 ;if(!EXC_RETURN[2]) - - 54 00000024 D001 BEQ get_sp_done - 55 00000026 F3EF 8109 MRS R1, PSP ;get fault context - from thread - 56 0000002A get_sp_done - 57 0000002A - 58 0000002A ; get svc index - 59 0000002A 6988 LDR R0, [R1, #24] - 60 0000002C F810 0C02 LDRB R0, [R0, #-2] - 61 00000030 - 62 00000030 ;if svc == 0, do system call - 63 00000030 2800 CMP R0, #0x0 - 64 00000032 D0FE BEQ syscall_entry - 65 00000034 - 66 00000034 ;if svc == 1, do TrustZone call - 67 00000034 2801 CMP R0, #0x1 - 68 00000036 D0FE BEQ tzcall_entry - 69 00000038 - 70 00000038 ENDP - 71 00000038 - 72 00000038 ALIGN - 73 00000038 - 74 00000038 END -Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M33 --fpu=FPv5-S -P --depend=.\build\keil\obj\syscall_rvds.d -o.\build\keil\obj\syscall_rvds.o -I -D:\1_tool_prog\2_MDK\pack\Keil\STM32H5xx_DFP\1.1.0\Drivers\CMSIS\Device\ST\STM3 -2H5xx\Include --predefine="__UVISION_VERSION SETA 536" --predefine="STM32H563xx - SETA 1" --list=syscall_rvds.lst ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -.text 00000000 - -Symbol: .text - Definitions - At line 11 in file ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S - Uses - None -Comment: .text unused -SVC_Handler 0000001C - -Symbol: SVC_Handler - Definitions - At line 48 in file ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S - Uses - At line 49 in file ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S -Comment: SVC_Handler used once -get_sp_done 0000002A - -Symbol: get_sp_done - Definitions - At line 56 in file ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S - Uses - At line 54 in file ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S -Comment: get_sp_done used once -syscall_entry 0000001A - -Symbol: syscall_entry - Definitions - At line 40 in file ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S - Uses - At line 64 in file ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S -Comment: syscall_entry used once -tzcall 00000000 - -Symbol: tzcall - Definitions - At line 21 in file ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S - Uses - At line 22 in file ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S -Comment: tzcall used once -tzcall_entry 00000004 - -Symbol: tzcall_entry - Definitions - At line 28 in file ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S - Uses - At line 68 in file ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S -Comment: tzcall_entry used once -6 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -External symbols - -rt_secure_svc_handle 00000000 - -Symbol: rt_secure_svc_handle - Definitions - At line 16 in file ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S - Uses - At line 33 in file ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S -Comment: rt_secure_svc_handle used once -1 symbol -340 symbols in table diff --git a/components/drivers/graphic/logo/logo.html b/components/drivers/graphic/logo/logo.html deleted file mode 100644 index 81e78c4aa1e..00000000000 --- a/components/drivers/graphic/logo/logo.html +++ /dev/null @@ -1,243 +0,0 @@ - - - - - - - - - Logo PPM Previews - - - -
-
-
-
-
- - - - -
-
-
- -
-
- -
-
-
- -
-
-
- - - diff --git a/components/net/lwip/lwip-2.0.3/doc/doxygen/output/index.html b/components/net/lwip/lwip-2.0.3/doc/doxygen/output/index.html deleted file mode 100644 index a52e09fcf25..00000000000 --- a/components/net/lwip/lwip-2.0.3/doc/doxygen/output/index.html +++ /dev/null @@ -1,10 +0,0 @@ - - - - Redirection - - - - index.html - - diff --git a/components/net/lwip/lwip-2.0.3/src/apps/httpd/fs/404.html b/components/net/lwip/lwip-2.0.3/src/apps/httpd/fs/404.html deleted file mode 100644 index 40b343a91e2..00000000000 --- a/components/net/lwip/lwip-2.0.3/src/apps/httpd/fs/404.html +++ /dev/null @@ -1,21 +0,0 @@ - -lwIP - A Lightweight TCP/IP Stack - - - - -
- SICS logo - -

lwIP - A Lightweight TCP/IP Stack

-

404 - Page not found

-

- Sorry, the page you are requesting was not found on this - server. -

- 		-   -
- - diff --git a/components/net/lwip/lwip-2.0.3/src/apps/httpd/fs/index.html b/components/net/lwip/lwip-2.0.3/src/apps/httpd/fs/index.html deleted file mode 100644 index ab575ef0891..00000000000 --- a/components/net/lwip/lwip-2.0.3/src/apps/httpd/fs/index.html +++ /dev/null @@ -1,47 +0,0 @@ - -lwIP - A Lightweight TCP/IP Stack - - - - -
- SICS logo - -

lwIP - A Lightweight TCP/IP Stack

-

- The web page you are watching was served by a simple web - server running on top of the lightweight TCP/IP stack lwIP. -

-

- lwIP is an open source implementation of the TCP/IP - protocol suite that was originally written by Adam Dunkels - of the Swedish Institute of Computer Science but now is - being actively developed by a team of developers - distributed world-wide. Since it's release, lwIP has - spurred a lot of interest and has been ported to several - platforms and operating systems. lwIP can be used either - with or without an underlying OS. -

-

- The focus of the lwIP TCP/IP implementation is to reduce - the RAM usage while still having a full scale TCP. This - makes lwIP suitable for use in embedded systems with tens - of kilobytes of free RAM and room for around 40 kilobytes - of code ROM. -

-

- More information about lwIP can be found at the lwIP - homepage at http://savannah.nongnu.org/projects/lwip/ - or at the lwIP wiki at http://lwip.wikia.com/. -

- 		-   -
- - - diff --git a/components/net/lwip/lwip-2.1.2/doc/doxygen/output/index.html b/components/net/lwip/lwip-2.1.2/doc/doxygen/output/index.html deleted file mode 100644 index a52e09fcf25..00000000000 --- a/components/net/lwip/lwip-2.1.2/doc/doxygen/output/index.html +++ /dev/null @@ -1,10 +0,0 @@ - - - - Redirection - - - - index.html - - diff --git a/components/net/lwip/lwip-2.1.2/src/apps/http/fs/404.html b/components/net/lwip/lwip-2.1.2/src/apps/http/fs/404.html deleted file mode 100644 index 40b343a91e2..00000000000 --- a/components/net/lwip/lwip-2.1.2/src/apps/http/fs/404.html +++ /dev/null @@ -1,21 +0,0 @@ - -lwIP - A Lightweight TCP/IP Stack - - - - -
- SICS logo - -

lwIP - A Lightweight TCP/IP Stack

-

404 - Page not found

-

- Sorry, the page you are requesting was not found on this - server. -

- 		-   -
- - diff --git a/components/net/lwip/lwip-2.1.2/src/apps/http/fs/index.html b/components/net/lwip/lwip-2.1.2/src/apps/http/fs/index.html deleted file mode 100644 index ab575ef0891..00000000000 --- a/components/net/lwip/lwip-2.1.2/src/apps/http/fs/index.html +++ /dev/null @@ -1,47 +0,0 @@ - -lwIP - A Lightweight TCP/IP Stack - - - - -
- SICS logo - -

lwIP - A Lightweight TCP/IP Stack

-

- The web page you are watching was served by a simple web - server running on top of the lightweight TCP/IP stack lwIP. -

-

- lwIP is an open source implementation of the TCP/IP - protocol suite that was originally written by Adam Dunkels - of the Swedish Institute of Computer Science but now is - being actively developed by a team of developers - distributed world-wide. Since it's release, lwIP has - spurred a lot of interest and has been ported to several - platforms and operating systems. lwIP can be used either - with or without an underlying OS. -

-

- The focus of the lwIP TCP/IP implementation is to reduce - the RAM usage while still having a full scale TCP. This - makes lwIP suitable for use in embedded systems with tens - of kilobytes of free RAM and room for around 40 kilobytes - of code ROM. -

-

- More information about lwIP can be found at the lwIP - homepage at http://savannah.nongnu.org/projects/lwip/ - or at the lwIP wiki at http://lwip.wikia.com/. -

- 		-   -
- - -