cortex_m: Enable fpu on startup (#749)

tact1m4n3 · web-flow · commit 2b600a4e2a6f · 2025-12-08T14:40:55.000+02:00
diff --git a/core/src/cpus/cortex_m.zig b/core/src/cpus/cortex_m.zig
@@ -33,8 +33,25 @@ pub const InterruptOptions = microzig.utilities.GenerateInterruptOptions(&.{
     .{ .InterruptEnum = Interrupt, .HandlerFn = Handler },
 });
 
-/// Allowable `platform` options for microzig.options.
-pub const CPU_Options = core.CPU_Options;
+/// Allowable `cpu` options for microzig.options.
+pub const CPU_Options = struct {
+    /// If true, interrupt vectors are moved to RAM so handlers can be set at runtime.
+    ///
+    /// NOTE: Not supported on cortex_m0.
+    ram_vector_table: bool = false,
+
+    /// If true, the Cortex-M interrupts will be initialized with a more verbose variant
+    /// of the interrupt handlers which print the interrupt name.
+    ///
+    /// NOTE: This option is enabled in debug builds by default.
+    verbose_unhandled_irq: bool = (builtin.mode == .Debug),
+
+    /// If true, the FPU will be enabled in the startup code.
+    ///
+    /// NOTE: This option is enabled by default if hard float is enabled.
+    /// NOTE: Not supported on cortex_m0, cortex_m0plus and cortex_m3.
+    enable_fpu: bool = builtin.abi.float() == .hard,
+};
 
 /// External Interrupts
 /// These are the interrupts generated by the NVIC.
@@ -643,6 +660,37 @@ pub const atomic = struct {
     }
 };
 
+/// Enables the FPU.
+///
+/// NOTE: This function is automatically called on cpu startup if the cpu has
+/// an fpu and hard float is enabled. HALs also call this in the startup of
+/// other cores.
+pub inline fn enable_fpu() void {
+    switch (cortex_m) {
+        inline .cortex_m0,
+        .cortex_m0plus,
+        .cortex_m3,
+        => |flavour| @compileError("FPU not supported on " ++ @tagName(flavour)),
+        else => {},
+    }
+
+    // Taken from the rust crate cortex-m-rt.
+    asm volatile (
+        \\ldr r0, =0xE000ED88
+        \\ldr r1, =(0b1111 << 20)
+        \\ldr r2, [r0]
+        \\orr r2, r2, r1
+        \\str r2, [r0]
+        \\dsb
+        \\isb
+        ::: .{
+            .r0 = true,
+            .r1 = true,
+            .r2 = true,
+            .memory = true,
+        });
+}
+
 /// The RAM vector table used. You can swap interrupt handlers at runtime here.
 /// Available when using a RAM vector table or a RAM image.
 pub var ram_vector_table: VectorTable align(256) = if (using_ram_vector_table or is_ram_image)
@@ -654,7 +702,7 @@ else
 pub const startup_logic = struct {
     extern fn microzig_main() noreturn;
 
-    pub fn ram_image_start() linksection("microzig_ram_start") callconv(.naked) void {
+    pub fn ram_image_start() linksection("microzig_ram_start") callconv(.naked) noreturn {
         const eos = comptime microzig.utilities.get_end_of_stack();
         asm volatile (
             \\
@@ -672,6 +720,11 @@ pub const startup_logic = struct {
         microzig.utilities.initialize_system_memories(.auto);
 
         if (using_ram_vector_table or is_ram_image) {
+            switch (cortex_m) {
+                .cortex_m0 => @compileError("RAM image and RAM vector table are not supported on cortex_m0"),
+                else => {},
+            }
+
             asm volatile (
                 \\
                 // Set VTOR to point to ram table
@@ -684,6 +737,25 @@ pub const startup_logic = struct {
                 : .{ .memory = true, .r0 = true, .r1 = true });
         }
 
+        if (fpu_present and microzig.options.cpu.enable_fpu) {
+            enable_fpu();
+        } else if (!fpu_present and microzig.options.cpu.enable_fpu) {
+            @compileError(
+                \\FPU enable requested though the chip doesn't appear to have an
+                \\FPU. If your chip does have an FPU please add the `fpu_present`
+                \\equal to `true` property to your chip file, either manually or via
+                \\patches. If you want to use patches, you can use something like
+                \\this:
+                \\```
+                \\.{ .set_device_property = .{
+                \\    .device_name = "CHIP_NAME",
+                \\    .key = "fpu_present",
+                \\    .value = "true"
+                \\} },
+                \\```
+            );
+        }
+
         if (@hasField(types.peripherals.SystemControlBlock, "SHCSR")) {
             // Enable distinction between MemFault, BusFault and UsageFault:
             peripherals.scb.SHCSR.modify(.{
@@ -694,7 +766,9 @@ pub const startup_logic = struct {
             enable_fault_irq();
         }
 
-        microzig_main();
+        // If the compiler gets too aggressive with inlining we might get some
+        // floating point operations before the FPU is enabled.
+        @call(.never_inline, microzig_main, .{});
     }
 
     // Validate that the VectorTable type has all the fault handlers that the CPU expects
@@ -970,10 +1044,17 @@ const scb_base = scs_base + core.scb_base_offset;
 const mpu_base = scs_base + 0x0D90;
 const fpu_base = scs_base + 0x0F34;
 
-const properties = microzig.chip.properties;
 // TODO: will have to standardize this with regz code generation
-const mpu_present = @hasDecl(properties, "cpu.mpuPresent") and std.mem.eql(u8, properties.@"cpu.mpuPresent", "true");
-const fpu_present = @hasDecl(properties, "cpu.fpuPresent") and std.mem.eql(u8, properties.@"cpu.fpuPresent", "true");
+const mpu_present = @hasDecl(microzig.chip, "properties") and
+    @hasDecl(microzig.chip.properties, "mpu_present") and
+    is_property_true(microzig.chip.properties.mpu_present);
+const fpu_present = @hasDecl(microzig.chip, "properties") and
+    @hasDecl(microzig.chip.properties, "fpu_present") and
+    is_property_true(microzig.chip.properties.fpu_present);
+
+fn is_property_true(value: []const u8) bool {
+    return std.mem.eql(u8, value, "true") or std.mem.eql(u8, value, "1");
+}
 
 const core = blk: {
     break :blk switch (cortex_m) {
diff --git a/core/src/cpus/cortex_m/m0.zig b/core/src/cpus/cortex_m/m0.zig
@@ -3,14 +3,6 @@ const builtin = @import("builtin");
 const mmio = microzig.mmio;
 const shared = @import("shared_types.zig");
 
-pub const CPU_Options = struct {
-    /// If true, the Cortex-M interrupts will be initialized with a more verbose variant
-    /// of the interrupt handlers which print the interrupt name.
-    ///
-    /// NOTE: This option is enabled in debug builds by default.
-    verbose_unhandled_irq: bool = (builtin.mode == .Debug),
-};
-
 pub const scb_base_offset = 0x0d00;
 
 pub const SystemControlBlock = extern struct {
diff --git a/core/src/cpus/cortex_m/m0plus.zig b/core/src/cpus/cortex_m/m0plus.zig
@@ -3,8 +3,6 @@ const mmio = microzig.mmio;
 
 const shared = @import("shared_types.zig");
 
-pub const CPU_Options = shared.options.Ram_Vector_Options;
-
 pub const scb_base_offset = 0x0d00;
 
 pub const SystemControlBlock = extern struct {
diff --git a/core/src/cpus/cortex_m/m3.zig b/core/src/cpus/cortex_m/m3.zig
@@ -3,8 +3,6 @@ const mmio = microzig.mmio;
 
 const shared = @import("shared_types.zig");
 
-pub const CPU_Options = shared.options.Ram_Vector_Options;
-
 pub const scb_base_offset = 0x0d00;
 
 pub const SystemControlBlock = extern struct {
diff --git a/core/src/cpus/cortex_m/m33.zig b/core/src/cpus/cortex_m/m33.zig
@@ -10,8 +10,6 @@ pub const cpu_flags: shared.CpuFlags = .{
     .has_usage_fault = true,
 };
 
-pub const CPU_Options = shared.options.Ram_Vector_Options;
-
 pub const scb_base_offset = 0x0cfc;
 
 pub const SystemControlBlock = extern struct {
diff --git a/core/src/cpus/cortex_m/m4.zig b/core/src/cpus/cortex_m/m4.zig
@@ -3,8 +3,6 @@ const mmio = microzig.mmio;
 
 const shared = @import("shared_types.zig");
 
-pub const CPU_Options = shared.options.Ram_Vector_Options;
-
 pub const scb_base_offset = 0x0d00;
 
 pub const SystemControlBlock = extern struct {
diff --git a/core/src/cpus/cortex_m/m55.zig b/core/src/cpus/cortex_m/m55.zig
@@ -5,8 +5,6 @@ const mmio = microzig.mmio;
 
 const shared = @import("shared_types.zig");
 
-pub const CPU_Options = shared.options.Ram_Vector_Options;
-
 pub const scb_base_offset = 0x0cfc;
 
 pub const SystemControlBlock = extern struct {
diff --git a/core/src/cpus/cortex_m/m7.zig b/core/src/cpus/cortex_m/m7.zig
@@ -3,8 +3,6 @@ const mmio = microzig.mmio;
 
 const shared = @import("shared_types.zig");
 
-pub const CPU_Options = shared.options.Ram_Vector_Options;
-
 pub const scb_base_offset = 0x0d00;
 
 pub const SystemControlBlock = extern struct {
diff --git a/core/src/cpus/cortex_m/shared_types.zig b/core/src/cpus/cortex_m/shared_types.zig
@@ -11,19 +11,6 @@ pub const CpuFlags = struct {
     has_mem_manage_fault: bool,
 };
 
-pub const options = struct {
-    pub const Ram_Vector_Options = struct {
-        /// If true, interrupt vectors are moved to RAM so handlers can be set at runtime.
-        ram_vector_table: bool = false,
-
-        /// If true, the Cortex-M interrupts will be initialized with a more verbose variant
-        /// of the interrupt handlers which print the interrupt name.
-        ///
-        /// NOTE: This option is enabled in debug builds by default.
-        verbose_unhandled_irq: bool = (builtin.mode == .Debug),
-    };
-};
-
 pub const scb = struct {
     pub const SHCSR = packed struct(u32) {
         /// [0]
diff --git a/port/raspberrypi/rp2xxx/src/hal.zig b/port/raspberrypi/rp2xxx/src/hal.zig
@@ -43,10 +43,6 @@ comptime {
     // HACK: tests can't access microzig. maybe there's a better way to do this.
     if (!builtin.is_test and compatibility.chip == .RP2350) {
         _ = bootmeta;
-
-        if (compatibility.arch == .arm and microzig.options.hal.use_dcp) {
-            _ = dcp;
-        }
     }
 
     // On the RP2040, we need to import the `atomic.zig` file to export some global
@@ -69,12 +65,6 @@ pub const HAL_Options = switch (compatibility.chip) {
             next_block: ?*const anyopaque = null,
         } = .{},
 
-        /// Enable the FPU and lazy state preservation. Leads to much faster
-        /// single precision floating point arithmetic. If you want a custom
-        /// setup set this to false and configure the fpu yourself. Ignored on
-        /// riscv.
-        enable_fpu: bool = is_fpu_used,
-
         /// Enable the DCP and export intrinsics. Leads to faster double
         /// precision floating point arithmetic. Ignored on riscv.
         use_dcp: bool = true,
@@ -94,12 +84,17 @@ pub inline fn init() void {
     init_sequence(clock_config);
 }
 
-const is_fpu_used: bool = builtin.abi.float() == .hard;
-
 /// Allows user to easily swap in their own clock config while still
 /// using the recommended initialization sequence
 pub fn init_sequence(comptime clock_cfg: clocks.config.Global) void {
-    maybe_enable_fpu_and_dcp();
+    if (compatibility.chip == .RP2350 and compatibility.arch == .arm and
+        microzig.options.hal.use_dcp)
+    {
+        // Export double floating point intrinsics
+        _ = dcp;
+
+        enable_dcp();
+    }
 
     // Disable the watchdog as a soft reset doesn't disable the WD automatically!
     watchdog.disable();
@@ -129,38 +124,19 @@ pub fn init_sequence(comptime clock_cfg: clocks.config.Global) void {
     resets.unreset_block_wait(resets.masks.all);
 }
 
-/// Enables fpu and/or dcp on RP2350 arm if requested in HAL options. On RP2350
-/// riscv and RP2040 this is a noop. Called in init_sequence and on core1
+/// Enables dcp on RP2350 arm.
+///
+/// NOTE: Called automatically in the hal startup sequence and in core1
 /// startup.
-pub fn maybe_enable_fpu_and_dcp() void {
-    if (compatibility.chip == .RP2350 and
-        compatibility.arch == .arm)
-    {
-        if (microzig.options.hal.enable_fpu) {
-            if (is_fpu_used) {
-                // enable lazy state preservation
-                microzig.cpu.peripherals.fpu.FPCCR.modify(.{
-                    .ASPEN = 1,
-                    .LSPEN = 1,
-                });
-
-                // enable the FPU for the current core
-                microzig.cpu.peripherals.scb.CPACR.modify(.{
-                    .CP10 = .full_access,
-                    .CP11 = .full_access,
-                });
-            } else {
-                @compileError("target doesn't have FPU features enabled");
-            }
-        }
-
-        if (microzig.options.hal.use_dcp) {
-            // enable the DCP for the current core
-            microzig.cpu.peripherals.scb.CPACR.modify(.{
-                .CP4 = .full_access,
-            });
-        }
+pub inline fn enable_dcp() void {
+    if (!(compatibility.chip == .RP2350 and compatibility.arch == .arm)) {
+        @compileError("DCP is only available on RP2350 arm");
     }
+
+    // enable the DCP for the current core
+    microzig.cpu.peripherals.scb.CPACR.modify(.{
+        .CP4 = .full_access,
+    });
 }
 
 pub fn get_cpu_id() u32 {
diff --git a/port/raspberrypi/rp2xxx/src/hal/multicore.zig b/port/raspberrypi/rp2xxx/src/hal/multicore.zig
@@ -1,3 +1,4 @@
+const builtin = @import("builtin");
 const std = @import("std");
 const assert = std.debug.assert;
 
@@ -77,7 +78,15 @@ pub fn launch_core1_with_stack(entrypoint: *const fn () void, stack: []u32) void
         fn _wrapper(_: u32, _: u32, _: u32, _: u32, entry: u32, stack_base: [*]u32) callconv(.c) void {
             // TODO: protect stack using MPU
             _ = stack_base;
-            microzig.hal.maybe_enable_fpu_and_dcp();
+            if (microzig.hal.compatibility.chip == .RP2350) {
+                if (microzig.options.cpu.enable_fpu) {
+                    microzig.cpu.enable_fpu();
+                }
+
+                if (microzig.options.hal.use_dcp) {
+                    microzig.hal.enable_dcp();
+                }
+            }
             @as(*const fn () void, @ptrFromInt(entry))();
         }
     }._wrapper;
diff --git a/port/stmicro/stm32/src/boards/STM32F3DISCOVERY.zig b/port/stmicro/stm32/src/boards/STM32F3DISCOVERY.zig
@@ -29,7 +29,6 @@ pub const pin_map = .{
 };
 
 pub fn init() void {
-    hal.enable_fpu();
     rcc.enable_hse(8_000_000);
     rcc.enable_pll(.HSE, .Div1, .Mul5) catch {
         @panic("PLL faile to enable");
diff --git a/port/stmicro/stm32/src/hals/STM32F303.zig b/port/stmicro/stm32/src/hals/STM32F303.zig
@@ -18,17 +18,6 @@ pub const i2c = @import("STM32F303/i2c.zig");
 pub const pins = @import("STM32F303/pins.zig");
 pub const enums = @import("STM32F303/enums.zig");
 
-pub fn enable_fpu() void {
-    microzig.cpu.peripherals.scb.CPACR.modify(.{
-        .CP10 = .full_access,
-        .CP11 = .full_access,
-    });
-    microzig.cpu.peripherals.fpu.FPCCR.modify(.{
-        .ASPEN = 1,
-        .LSPEN = 1,
-    });
-}
-
 pub fn parse_pin(comptime spec: []const u8) type {
     const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme.";
 
diff --git a/tools/regz/src/Database.zig b/tools/regz/src/Database.zig
diff --git a/tools/regz/src/arch/arm/nvic.zig b/tools/regz/src/arch/arm/nvic.zig
diff --git a/tools/regz/src/atdf.zig b/tools/regz/src/atdf.zig
diff --git a/tools/regz/src/embassy.zig b/tools/regz/src/embassy.zig
diff --git a/tools/regz/src/patch.zig b/tools/regz/src/patch.zig
diff --git a/tools/regz/src/svd.zig b/tools/regz/src/svd.zig
