From 93bdc53f99801b5cd552ebb0c1dd6ad5bbd80c11 Mon Sep 17 00:00:00 2001
From: Grazfather <grazfather@gmail.com>
Date: Sat, 6 Dec 2025 08:43:57 -0500
Subject: [PATCH] ch32v: Define structs for CSRs

---
 modules/riscv32-common/src/riscv32_common.zig |  7 +-
 port/wch/ch32v/src/cpus/main.zig              | 70 +++++++++++++++----
 2 files changed, 61 insertions(+), 16 deletions(-)

diff --git a/modules/riscv32-common/src/riscv32_common.zig b/modules/riscv32-common/src/riscv32_common.zig
index 4d1384846..50800d448 100644
--- a/modules/riscv32-common/src/riscv32_common.zig
+++ b/modules/riscv32-common/src/riscv32_common.zig
@@ -53,8 +53,9 @@ pub fn wfi() void {
     asm volatile ("wfi");
 }
 
-// NOTE: Contains all csrs from the riscv manual and should follow their spec. Cpu implementations can
-// reexport what they need from here.
+// NOTE: Contains all CSRs (Control Status Registers) from the riscv manual and should follow their
+// spec. Cpu implementations can reexport what they need from here.
+// See https://docs.riscv.org/reference/isa/priv/priv-csrs.html
 pub const csr = struct {
     pub const fflags = Csr(0x001, u32);
     pub const frm = Csr(0x002, u32);
@@ -158,7 +159,7 @@ pub const csr = struct {
 
     pub const mscratch = Csr(0x340, u32);
     pub const mepc = Csr(0x341, u32);
-    pub const mcause = Csr(0x342, packed struct {
+    pub const mcause = Csr(0x342, packed struct(u32) {
         code: u31,
         is_interrupt: u1,
     });
diff --git a/port/wch/ch32v/src/cpus/main.zig b/port/wch/ch32v/src/cpus/main.zig
index 8c8cc5c0d..593ac98d2 100644
--- a/port/wch/ch32v/src/cpus/main.zig
+++ b/port/wch/ch32v/src/cpus/main.zig
@@ -397,11 +397,27 @@ pub const csr = struct {
     pub const Csr = riscv32_common.csr.Csr;
 
     /// Architecture Number Register
+    /// Fields correspond to individual letters. 1=A, 2=B, etc.
     /// Examples:
     /// - 0xDC68D841 - WCH-V2A
     /// - 0xDC68D886 - WCH-V4F
-    pub const marchid = riscv32_common.csr.marchid;
-    pub const mimpid = riscv32_common.csr.mimpid;
+    pub const marchid = Csr(0xF12, packed struct(u32) {
+        version: u4 = 0,
+        serial: u5 = 0,
+        arch: u5 = 0,
+        reserved15: u1 = 0,
+        vendor2: u5 = 0, // 'H'
+        vendor1: u5 = 0, // 'C'
+        vendor0: u5 = 0, // 'W'
+        reserved: u1 = 0,
+    });
+    pub const mimpid = Csr(0xF13, packed struct(u32) {
+        reserved0: u16 = 0,
+        vendor2: u5 = 0, // 'H'
+        vendor1: u5 = 0, // 'C'
+        vendor0: u5 = 0, // 'W'
+        reserved31: u1 = 0,
+    });
 
     /// Machine Mode Status Register
     pub const mstatus = Csr(0x300, packed struct(u32) {
@@ -414,26 +430,29 @@ pub const csr = struct {
         };
 
         /// [2:0] Reserved
-        reserved4: u3 = 0,
+        reserved0: u3 = 0,
         /// [3] Machine mode interrupt enable
         mie: u1,
         /// [6:4] Reserved
-        reserved3: u3 = 0,
+        reserved4: u3 = 0,
         /// [7] Interrupt enable state before entering interrupt
         mpie: u1,
         /// [10:8] Reserved
-        reserved2: u3 = 0,
+        reserved8: u3 = 0,
         /// [12:11] Privileged mode before entering break
         mpp: u2 = 0,
-        /// [14:13] Reserved
-        reserved1: u2 = 0,
         /// [14:13] Floating-point unit status
         /// Valid only for WCH-V4F
+        /// NOTE: reserved on other chips
         fs: Fs = .off,
         /// [31:15] Reserved
-        reserved0: u15 = 0,
+        reserved15: u17 = 0,
+    });
+    pub const misa = Csr(0x301, packed struct(u32) {
+        extensions: u26 = 0,
+        reserved26: u4 = 0,
+        mxl: u2 = 0,
     });
-    pub const misa = riscv32_common.csr.misa;
     /// Machine Mode Exception Base Address Register
     pub const mtvec = Csr(0x305, packed struct(u32) {
         /// [0] Mode 0
@@ -463,7 +482,15 @@ pub const csr = struct {
     pub const pmpaddr2 = riscv32_common.csr.pmpaddr2;
     pub const pmpaddr3 = riscv32_common.csr.pmpaddr3;
 
-    pub const fcsr = riscv32_common.csr.fcsr;
+    pub const fcsr = Csr(0x003, packed struct(u32) {
+        nx: u1 = 0,
+        uf: u1 = 0,
+        of: u1 = 0,
+        dz: u1 = 0,
+        nv: u1 = 0,
+        frm: u3 = 0,
+        reserved8: u24 = 0,
+    });
     pub const fflags = riscv32_common.csr.fflags;
     pub const frm = riscv32_common.csr.frm;
 
@@ -475,8 +502,25 @@ pub const csr = struct {
     pub const gintenr = Csr(0x800, u32);
     pub const intsyscr = Csr(0x804, cpu_impl.csr_types.intsyscr);
     pub const corecfgr = Csr(0xBC0, u32);
-    pub const cstrcr = Csr(0xBC2, u32);
+    pub const cstrcr = Csr(0xBC2, packed struct(u32) {
+        reserved0: u1 = 0,
+        icddisable: u1 = 0,
+        reserved2: u22 = 0,
+        iccodestren: u1 = 0,
+        icsramstren: u1 = 0,
+        reserved26: u6 = 0,
+    });
     pub const cpmpocr = Csr(0xBC3, u32);
-    pub const cmcr = Csr(0xBD0, u32);
-    pub const cinfor = Csr(0xFC0, u32);
+    pub const cmcr = Csr(0xBD0, packed struct(u32) {
+        opcode: u2 = 0,
+        idxmode: u1 = 0,
+        reserved3: u2 = 0,
+        vaddr: u27 = 0,
+    });
+    pub const cinfor = Csr(0xFC0, packed struct(u32) {
+        iclinesize: u2 = 0,
+        icszie: u3 = 0,
+        icway: u2 = 0,
+        reserved7: u25 = 0,
+    });
 };