From f34bdc5f9b7f70c42902bbb2cedddf888ec60f9e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Arkadiusz=20W=C3=B3jcik?= Date: Mon, 19 Jan 2026 01:58:35 +0100 Subject: [PATCH 1/5] Introduce FreeRTOS port - right now only RP2040 --- examples/raspberrypi/rp2xxx/build.zig | 12 + examples/raspberrypi/rp2xxx/build.zig.zon | 1 + .../rp2xxx/src/freertos/hello_task.zig | 111 ++ modules/freertos/build.zig | 100 + modules/freertos/build.zig.zon | 27 + modules/freertos/config/FreeRTOSConfig.h | 140 ++ .../config/FreeRTOSConfig.multicore.h | 140 ++ .../include_common/hardware/address_mapped.h | 26 + .../picosdk/include_common/hardware/clocks.h | 10 + .../include_common/hardware/exception.h | 27 + .../picosdk/include_common/hardware/irq.h | 14 + .../picosdk/include_common/hardware/sync.h | 90 + .../include_common/hardware/sync/spin_lock.h | 68 + .../picosdk/include_common/hardware/timer.h | 10 + .../freertos/picosdk/include_common/pico.h | 9 + .../picosdk/include_common/pico/assert.h | 62 + .../picosdk/include_common/pico/lock_core.h | 16 + .../picosdk/include_common/pico/multicore.h | 24 + .../include_common/pico/platform/common.h | 19 + .../include_common/pico/platform/compiler.h | 210 +++ .../picosdk/include_common/pico/time.h | 20 + .../picosdk/include_common/pico/types.h | 121 ++ .../picosdk/include_common/sys/cdefs.h | 30 + .../include_rp2040/hardware/platform_defs.h | 139 ++ .../include_rp2040/hardware/regs/addressmap.h | 80 + .../include_rp2040/hardware/regs/intctrl.h | 123 ++ .../include_rp2040/hardware/regs/sio.h | 1658 +++++++++++++++++ .../include_rp2040/hardware/structs/clocks.h | 18 + .../include_rp2040/hardware/structs/interp.h | 85 + .../include_rp2040/hardware/structs/sio.h | 199 ++ .../picosdk/include_rp2040/pico/platform.h | 21 + modules/freertos/src/root.zig | 50 + 32 files changed, 3660 insertions(+) create mode 100644 examples/raspberrypi/rp2xxx/src/freertos/hello_task.zig create mode 100644 modules/freertos/build.zig create mode 100644 modules/freertos/build.zig.zon create mode 100644 modules/freertos/config/FreeRTOSConfig.h create mode 100644 modules/freertos/config/FreeRTOSConfig.multicore.h create mode 100644 modules/freertos/picosdk/include_common/hardware/address_mapped.h create mode 100644 modules/freertos/picosdk/include_common/hardware/clocks.h create mode 100644 modules/freertos/picosdk/include_common/hardware/exception.h create mode 100644 modules/freertos/picosdk/include_common/hardware/irq.h create mode 100644 modules/freertos/picosdk/include_common/hardware/sync.h create mode 100644 modules/freertos/picosdk/include_common/hardware/sync/spin_lock.h create mode 100644 modules/freertos/picosdk/include_common/hardware/timer.h create mode 100644 modules/freertos/picosdk/include_common/pico.h create mode 100644 modules/freertos/picosdk/include_common/pico/assert.h create mode 100644 modules/freertos/picosdk/include_common/pico/lock_core.h create mode 100644 modules/freertos/picosdk/include_common/pico/multicore.h create mode 100644 modules/freertos/picosdk/include_common/pico/platform/common.h create mode 100644 modules/freertos/picosdk/include_common/pico/platform/compiler.h create mode 100644 modules/freertos/picosdk/include_common/pico/time.h create mode 100644 modules/freertos/picosdk/include_common/pico/types.h create mode 100644 modules/freertos/picosdk/include_common/sys/cdefs.h create mode 100644 modules/freertos/picosdk/include_rp2040/hardware/platform_defs.h create mode 100644 modules/freertos/picosdk/include_rp2040/hardware/regs/addressmap.h create mode 100644 modules/freertos/picosdk/include_rp2040/hardware/regs/intctrl.h create mode 100644 modules/freertos/picosdk/include_rp2040/hardware/regs/sio.h create mode 100644 modules/freertos/picosdk/include_rp2040/hardware/structs/clocks.h create mode 100644 modules/freertos/picosdk/include_rp2040/hardware/structs/interp.h create mode 100644 modules/freertos/picosdk/include_rp2040/hardware/structs/sio.h create mode 100644 modules/freertos/picosdk/include_rp2040/pico/platform.h create mode 100644 modules/freertos/src/root.zig diff --git a/examples/raspberrypi/rp2xxx/build.zig b/examples/raspberrypi/rp2xxx/build.zig index 822ef2bbe..248c8a2b7 100644 --- a/examples/raspberrypi/rp2xxx/build.zig +++ b/examples/raspberrypi/rp2xxx/build.zig @@ -25,6 +25,7 @@ pub fn build(b: *std.Build) void { .{ .target = raspberrypi.pico, .name = "pico_hd44780", .file = "src/rp2040_only/hd44780.zig" }, .{ .target = raspberrypi.pico, .name = "pico_pcf8574", .file = "src/rp2040_only/pcf8574.zig" }, .{ .target = raspberrypi.pico, .name = "pico_i2c_slave", .file = "src/rp2040_only/i2c_slave.zig" }, + .{ .target = raspberrypi.pico, .name = "pico_freertos-hello", .file = "src/freertos/hello_task.zig" }, .{ .target = raspberrypi.pico2_arm, .name = "pico2_arm_multicore", .file = "src/blinky_core1.zig" }, .{ .target = raspberrypi.pico2_arm, .name = "pico2_arm_board_blinky", .file = "src/board_blinky.zig" }, @@ -160,6 +161,17 @@ pub fn build(b: *std.Build) void { firmware.app_mod.addImport("net", net_mod); } + // Import freertos module for some examples + if (std.mem.indexOf(u8, example.name, "_freertos-") != null) { + const freertos_dep = b.dependency("freertos", .{ + .target = b.resolveTargetQuery(firmware.target.zig_target), + .optimize = optimize, + .port_name = "RP2040", + }); + const freertos_mod = freertos_dep.module("freertos"); + firmware.app_mod.addImport("freertos", freertos_mod); + } + // `install_firmware()` is the MicroZig pendant to `Build.installArtifact()` // and allows installing the firmware as a typical firmware file. // diff --git a/examples/raspberrypi/rp2xxx/build.zig.zon b/examples/raspberrypi/rp2xxx/build.zig.zon index 2e0f00ad7..2f0e8fe4d 100644 --- a/examples/raspberrypi/rp2xxx/build.zig.zon +++ b/examples/raspberrypi/rp2xxx/build.zig.zon @@ -10,6 +10,7 @@ .hash = "ssd1306_font_8x8-0.0.0-oGb_cERcAAA6NJzWDOMepgnY6r4blNEHjpkldDaRAui5", }, .net = .{ .path = "../../../modules/network/" }, + .freertos = .{ .path = "../../../modules/freertos/" }, }, .paths = .{ "README.md", diff --git a/examples/raspberrypi/rp2xxx/src/freertos/hello_task.zig b/examples/raspberrypi/rp2xxx/src/freertos/hello_task.zig new file mode 100644 index 000000000..ea49a0e16 --- /dev/null +++ b/examples/raspberrypi/rp2xxx/src/freertos/hello_task.zig @@ -0,0 +1,111 @@ +const std = @import("std"); +const microzig = @import("microzig"); + +const freertos = @import("freertos"); +const freertos_os = freertos.OS; + +const rp2xxx = microzig.hal; +const time = rp2xxx.time; +const gpio = rp2xxx.gpio; + +const uart = rp2xxx.uart.instance.num(0); +const uart_tx_pin = gpio.num(0); + +pub const microzig_options = microzig.Options{ + .log_level = .debug, + .logFn = rp2xxx.uart.log, + //.overwrite_hal_interrupts = true, + //.interrupts = .{ .PendSV = .{ .naked = freertos.isr_pendsv }, .SysTick = .{ .c = freertos.isr_systick }, .SVCall = .{ .c = freertos.isr_svcall } }, + .cpu = .{ + .ram_vector_table = true, + }, +}; + +pub fn main() !void { + uart_tx_pin.set_function(.uart); + + uart.apply(.{ + .clock_config = rp2xxx.clock_config, + }); + + rp2xxx.uart.init_logger(uart); + + // Give it large stack because printing is demanding + _ = freertos_os.xTaskCreate(hello_task, "hello_task", freertos_os.MINIMAL_STACK_SIZE * 8, null, freertos_os.MAX_PRIORITIES - 1, null); + + freertos_os.vTaskStartScheduler(); +} + +pub fn hello_task(_: ?*anyopaque) callconv(.c) void { + var i: u32 = 0; + while (true) : (i += 1) { + std.log.info("Hello from FreeRTOS task {}", .{i}); + freertos_os.vTaskDelay(500); + } +} + +/// +/// Some ugly glue code to implement required functions from FreeRTOS and Pico SDK +/// - This can be improved later +/// - Multicore not supported yet - multicore_reset_core1 have to be implemented +/// +export fn panic_unsupported() callconv(.c) noreturn { + @panic("not supported"); +} + +export fn irq_set_priority(num: c_uint, priority: u8) callconv(.c) void { + const p: *volatile u32 = @ptrFromInt(@intFromPtr(µzig.chip.peripherals.PPB.NVIC_IPR0) + (num >> 2)); + const shift: u5 = @intCast(8 * (@as(u32, @intCast(num)) & 3)); + const mask: u32 = @as(u32, 0xff) << shift; + p.* = (p.* & ~mask) | (@as(u32, priority) << shift); +} + +export fn irq_set_enabled(_: c_uint, enabled: bool) callconv(.c) void { + if (enabled) { + microzig.cpu.interrupt.enable(@enumFromInt(0)); + } else { + microzig.cpu.interrupt.disable(@enumFromInt(0)); + } +} + +export fn irq_set_exclusive_handler(_: u8) callconv(.c) void { + panic_unsupported(); +} + +export fn multicore_launch_core1(entry: *const fn () callconv(.c) void) callconv(.c) void { + microzig.hal.multicore.launch_core1(@ptrCast(entry)); +} + +export fn multicore_reset_core1() callconv(.c) void { + // TODO +} + +export fn clock_get_hz(_: u32) callconv(.c) u32 { + std.log.info("clock_get_hz called", .{}); + // FIXME: this seems to return null + // return microzig.hal.clock_config.sys_freq.?; + return 125_000_000; +} + +export fn spin_lock_claim(_: c_uint) callconv(.c) void {} + +export fn next_striped_spin_lock_num() callconv(.c) c_uint { + return 16; +} + +export fn exception_set_exclusive_handler(num: c_uint, handler: *const fn () callconv(.c) void) callconv(.c) void { + const cs = microzig.interrupt.enter_critical_section(); + defer cs.leave(); + + // very ugly code but good for now + if (num == 11) { + microzig.cpu.ram_vector_table.SVCall = .{ .c = handler }; + } else if (num == 14) { + microzig.cpu.ram_vector_table.PendSV = .{ .naked = @ptrCast(handler) }; + } else if (num == 15) { + microzig.cpu.ram_vector_table.SysTick = .{ .c = handler }; + } + + // used in PicoSDK - do we need this? + asm volatile ("DMB" ::: .{ .memory = true }); +} diff --git a/modules/freertos/build.zig b/modules/freertos/build.zig new file mode 100644 index 000000000..367d41d5a --- /dev/null +++ b/modules/freertos/build.zig @@ -0,0 +1,100 @@ +const std = @import("std"); + +const FreeRTOSPort = enum { + RP2040, + RP2350_ARM, + RP2350_RISCV, +}; + +pub fn build(b: *std.Build) void { + const target = b.standardTargetOptions(.{}); + const optimize = b.standardOptimizeOption(.{}); + + // Configurable options + const port_name = b.option( + FreeRTOSPort, + "port_name", + "FreeRTOS port to use", + ) orelse .RP2040; + + if (port_name != .RP2040) { + @panic("Right now only RP2040 port is supported"); + } + + const foundationlibc_dep = b.dependency("foundationlibc", .{ + .target = target, + .optimize = optimize, + .single_threaded = true, + }); + + const freertos_lib = b.addModule("freertos_lib", .{ + .target = target, + .optimize = optimize, + }); + + // Link libc + freertos_lib.linkLibrary(foundationlibc_dep.artifact("foundation")); + + const freertos_kernel_dep = b.dependency("freertos_kernel", .{}); + + // Add FreeRTOS kernel source files + freertos_lib.addCSourceFiles(.{ + .root = freertos_kernel_dep.path("."), + .files = &files, + .flags = &flags, + }); + + // FreeRTOS include paths + freertos_lib.addIncludePath(b.path("config")); + freertos_lib.addIncludePath(freertos_kernel_dep.path("include")); + + // Add FreeRTOS port source files + freertos_lib.addCSourceFiles(.{ + .root = freertos_kernel_dep.path("./portable/ThirdParty/GCC/RP2040/"), + .files = &files_port, + .flags = &flags, + }); + + // FreeRTOS port include paths + freertos_lib.addIncludePath(freertos_kernel_dep.path("./portable/ThirdParty/GCC/RP2040/include/")); + + // Pico SDK include paths + freertos_lib.addIncludePath(b.path("picosdk/include_common/")); + freertos_lib.addIncludePath(b.path("picosdk/include_rp2040/")); + + // TODO: USE addConfigHeader instead? + freertos_lib.addCMacro("configSMP_SPINLOCK_0", "PICO_SPINLOCK_ID_OS1"); + freertos_lib.addCMacro("configSMP_SPINLOCK_1", "PICO_SPINLOCK_ID_OS2"); + + freertos_lib.addCMacro("LIB_PICO_MULTICORE", "0"); + // Set this because otherwise we have to implment exception_set_exclusive_handler (for now we don't use it) + freertos_lib.addCMacro("PICO_NO_RAM_VECTOR_TABLE", "0"); + + // Should be defined in change in FreeRTOSConfig.h + //freertos_lib.addCMacro("configNUMBER_OF_CORES", "1"); + + const mod = b.addModule("freertos", .{ .root_source_file = b.path("src/root.zig"), .target = target, .optimize = optimize }); + mod.addImport("freertos_lib", freertos_lib); + + for (freertos_lib.c_macros.items) |m| { + mod.c_macros.append(b.allocator, m) catch @panic("out of memory"); + } + for (freertos_lib.include_dirs.items) |dir| { + mod.include_dirs.append(b.allocator, dir) catch @panic("out of memory"); + } +} + +const flags = [_][]const u8{ "-std=c11", "-fno-sanitize=undefined", "-Wno-pointer-to-int-cast" }; +const files = [_][]const u8{ + "croutine.c", + "event_groups.c", + "list.c", + "queue.c", + "stream_buffer.c", + "tasks.c", + "timers.c", + "portable/MemMang/heap_1.c", +}; +const files_port = [_][]const u8{ + "port.c", +}; diff --git a/modules/freertos/build.zig.zon b/modules/freertos/build.zig.zon new file mode 100644 index 000000000..cc700cef0 --- /dev/null +++ b/modules/freertos/build.zig.zon @@ -0,0 +1,27 @@ +.{ + .name = .zig_rtos, + .version = "0.0.0", + .fingerprint = 0x5089c38a1e0691c8, // Changing this has security and trust implications. + .minimum_zig_version = "0.16.0-dev.2193+fc517bd01", + .dependencies = .{ + .freertos_kernel = .{ + .url = "git+https://github.com/FreeRTOS/FreeRTOS-Kernel.git#52822473466cfa5cdd2146d02dae5f924b8552e4", + .hash = "N-V-__8AAMb4CQGTaQBhmyNrZe5AydR8ZY3met6pGoXDe1MC", + }, + .freertos_kernel_community = .{ + .url = "git+https://github.com/FreeRTOS/FreeRTOS-Kernel-Community-Supported-Ports.git#9ab3b5fb235838b3fc03d4f1cdcfab22007413d2", + .hash = "N-V-__8AAPdlHQB-Q5duFJp5D3hmNoJsOsWXr84CsPai1Pk9", + }, + .foundationlibc = .{ + .path = "../foundation-libc/", + }, + }, + .paths = .{ + "build.zig", + "build.zig.zon", + "src", + // For example... + //"LICENSE", + //"README.md", + }, +} diff --git a/modules/freertos/config/FreeRTOSConfig.h b/modules/freertos/config/FreeRTOSConfig.h new file mode 100644 index 000000000..a9a2ae710 --- /dev/null +++ b/modules/freertos/config/FreeRTOSConfig.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS V202107.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + #ifndef FREERTOS_CONFIG_H + #define FREERTOS_CONFIG_H + + /*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + + /* Scheduler Related */ + #define configUSE_PREEMPTION 1 + #define configUSE_TICKLESS_IDLE 0 + #define configUSE_IDLE_HOOK 0 + #define configUSE_TICK_HOOK 0 + #define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) + #define configMAX_PRIORITIES 32 + #define configMINIMAL_STACK_SIZE ( uint32_t ) 256 + #define configUSE_16_BIT_TICKS 0 + + #define configIDLE_SHOULD_YIELD 1 + + /* Synchronization Related */ + #define configUSE_MUTEXES 1 + #define configUSE_RECURSIVE_MUTEXES 1 + #define configUSE_APPLICATION_TASK_TAG 0 + #define configUSE_COUNTING_SEMAPHORES 1 + #define configQUEUE_REGISTRY_SIZE 8 + #define configUSE_QUEUE_SETS 1 + #define configUSE_TIME_SLICING 1 + #define configUSE_NEWLIB_REENTRANT 0 + #define configENABLE_BACKWARD_COMPATIBILITY 0 + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + + /* System */ + #define configSTACK_DEPTH_TYPE uint32_t + #define configMESSAGE_BUFFER_LENGTH_TYPE size_t + + /* Memory allocation related definitions. */ + #define configSUPPORT_STATIC_ALLOCATION 0 + #define configSUPPORT_DYNAMIC_ALLOCATION 1 + #define configTOTAL_HEAP_SIZE (128*1024) + #define configAPPLICATION_ALLOCATED_HEAP 0 + + /* Hook function related definitions. */ + #define configCHECK_FOR_STACK_OVERFLOW 0 + #define configUSE_MALLOC_FAILED_HOOK 0 + #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + + /* Run time and task stats gathering related definitions. */ + #define configGENERATE_RUN_TIME_STATS 0 + #define configUSE_TRACE_FACILITY 1 + #define configUSE_STATS_FORMATTING_FUNCTIONS 0 + + /* Co-routine related definitions. */ + #define configUSE_CO_ROUTINES 0 + #define configMAX_CO_ROUTINE_PRIORITIES 1 + + /* Software timer related definitions. */ + #define configUSE_TIMERS 1 + #define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) + #define configTIMER_QUEUE_LENGTH 10 + #define configTIMER_TASK_STACK_DEPTH 1024 + + /* Interrupt nesting behaviour configuration. */ + /* + #define configKERNEL_INTERRUPT_PRIORITY [dependent of processor] + #define configMAX_SYSCALL_INTERRUPT_PRIORITY [dependent on processor and application] + #define configMAX_API_CALL_INTERRUPT_PRIORITY [dependent on processor and application] + */ + + /* SMP port only */ + #define configNUMBER_OF_CORES 1 + #define configTICK_CORE 0 + #define configRUN_MULTIPLE_PRIORITIES 1 + #define configUSE_CORE_AFFINITY 0 + #define configUSE_PASSIVE_IDLE_HOOK 0 + + /* RP2040 specific */ + #define configSUPPORT_PICO_SYNC_INTEROP 1 + #define configSUPPORT_PICO_TIME_INTEROP 1 + + #include + /* Define to trap errors during development. */ + #define configASSERT(x) assert(x) + + /* Set the following definitions to 1 to include the API function, or zero + to exclude the API function. */ + #define INCLUDE_vTaskPrioritySet 1 + #define INCLUDE_uxTaskPriorityGet 1 + #define INCLUDE_vTaskDelete 1 + #define INCLUDE_vTaskSuspend 1 + #define INCLUDE_vTaskDelayUntil 1 + #define INCLUDE_vTaskDelay 1 + #define INCLUDE_xTaskGetSchedulerState 1 + #define INCLUDE_xTaskGetCurrentTaskHandle 1 + #define INCLUDE_uxTaskGetStackHighWaterMark 1 + #define INCLUDE_xTaskGetIdleTaskHandle 1 + #define INCLUDE_eTaskGetState 1 + #define INCLUDE_xTimerPendFunctionCall 1 + #define INCLUDE_xTaskAbortDelay 1 + #define INCLUDE_xTaskGetHandle 1 + #define INCLUDE_xTaskResumeFromISR 1 + #define INCLUDE_xQueueGetMutexHolder 1 + + /* A header file that defines trace macro can be included here. */ + + #endif /* FREERTOS_CONFIG_H */ \ No newline at end of file diff --git a/modules/freertos/config/FreeRTOSConfig.multicore.h b/modules/freertos/config/FreeRTOSConfig.multicore.h new file mode 100644 index 000000000..fb2df9a9d --- /dev/null +++ b/modules/freertos/config/FreeRTOSConfig.multicore.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS V202107.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + #ifndef FREERTOS_CONFIG_H + #define FREERTOS_CONFIG_H + + /*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + + /* Scheduler Related */ + #define configUSE_PREEMPTION 1 + #define configUSE_TICKLESS_IDLE 0 + #define configUSE_IDLE_HOOK 0 + #define configUSE_TICK_HOOK 0 + #define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) + #define configMAX_PRIORITIES 32 + #define configMINIMAL_STACK_SIZE ( configSTACK_DEPTH_TYPE ) 256 + #define configUSE_16_BIT_TICKS 0 + + #define configIDLE_SHOULD_YIELD 1 + + /* Synchronization Related */ + #define configUSE_MUTEXES 1 + #define configUSE_RECURSIVE_MUTEXES 1 + #define configUSE_APPLICATION_TASK_TAG 0 + #define configUSE_COUNTING_SEMAPHORES 1 + #define configQUEUE_REGISTRY_SIZE 8 + #define configUSE_QUEUE_SETS 1 + #define configUSE_TIME_SLICING 1 + #define configUSE_NEWLIB_REENTRANT 0 + #define configENABLE_BACKWARD_COMPATIBILITY 0 + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + + /* System */ + #define configSTACK_DEPTH_TYPE uint32_t + #define configMESSAGE_BUFFER_LENGTH_TYPE size_t + + /* Memory allocation related definitions. */ + #define configSUPPORT_STATIC_ALLOCATION 0 + #define configSUPPORT_DYNAMIC_ALLOCATION 1 + #define configTOTAL_HEAP_SIZE (128*1024) + #define configAPPLICATION_ALLOCATED_HEAP 0 + + /* Hook function related definitions. */ + #define configCHECK_FOR_STACK_OVERFLOW 0 + #define configUSE_MALLOC_FAILED_HOOK 0 + #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + + /* Run time and task stats gathering related definitions. */ + #define configGENERATE_RUN_TIME_STATS 0 + #define configUSE_TRACE_FACILITY 1 + #define configUSE_STATS_FORMATTING_FUNCTIONS 0 + + /* Co-routine related definitions. */ + #define configUSE_CO_ROUTINES 0 + #define configMAX_CO_ROUTINE_PRIORITIES 1 + + /* Software timer related definitions. */ + #define configUSE_TIMERS 1 + #define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) + #define configTIMER_QUEUE_LENGTH 10 + #define configTIMER_TASK_STACK_DEPTH 1024 + + /* Interrupt nesting behaviour configuration. */ + /* + #define configKERNEL_INTERRUPT_PRIORITY [dependent of processor] + #define configMAX_SYSCALL_INTERRUPT_PRIORITY [dependent on processor and application] + #define configMAX_API_CALL_INTERRUPT_PRIORITY [dependent on processor and application] + */ + + /* SMP port only */ + #define configNUMBER_OF_CORES 2 + #define configTICK_CORE 0 + #define configRUN_MULTIPLE_PRIORITIES 1 + #define configUSE_CORE_AFFINITY 1 + #define configUSE_PASSIVE_IDLE_HOOK 0 + + /* RP2040 specific */ + #define configSUPPORT_PICO_SYNC_INTEROP 1 + #define configSUPPORT_PICO_TIME_INTEROP 1 + + #include + /* Define to trap errors during development. */ + #define configASSERT(x) assert(x) + + /* Set the following definitions to 1 to include the API function, or zero + to exclude the API function. */ + #define INCLUDE_vTaskPrioritySet 1 + #define INCLUDE_uxTaskPriorityGet 1 + #define INCLUDE_vTaskDelete 1 + #define INCLUDE_vTaskSuspend 1 + #define INCLUDE_vTaskDelayUntil 1 + #define INCLUDE_vTaskDelay 1 + #define INCLUDE_xTaskGetSchedulerState 1 + #define INCLUDE_xTaskGetCurrentTaskHandle 1 + #define INCLUDE_uxTaskGetStackHighWaterMark 1 + #define INCLUDE_xTaskGetIdleTaskHandle 1 + #define INCLUDE_eTaskGetState 1 + #define INCLUDE_xTimerPendFunctionCall 1 + #define INCLUDE_xTaskAbortDelay 1 + #define INCLUDE_xTaskGetHandle 1 + #define INCLUDE_xTaskResumeFromISR 1 + #define INCLUDE_xQueueGetMutexHolder 1 + + /* A header file that defines trace macro can be included here. */ + + #endif /* FREERTOS_CONFIG_H */ \ No newline at end of file diff --git a/modules/freertos/picosdk/include_common/hardware/address_mapped.h b/modules/freertos/picosdk/include_common/hardware/address_mapped.h new file mode 100644 index 000000000..06a9ae2ca --- /dev/null +++ b/modules/freertos/picosdk/include_common/hardware/address_mapped.h @@ -0,0 +1,26 @@ +#ifndef _HARDWARE_ADDRESS_MAPPED_H +#define _HARDWARE_ADDRESS_MAPPED_H + +#include "hardware/regs/addressmap.h" + +typedef volatile uint64_t io_rw_64; +typedef const volatile uint64_t io_ro_64; +typedef volatile uint64_t io_wo_64; +typedef volatile uint32_t io_rw_32; +typedef const volatile uint32_t io_ro_32; +typedef volatile uint32_t io_wo_32; +typedef volatile uint16_t io_rw_16; +typedef const volatile uint16_t io_ro_16; +typedef volatile uint16_t io_wo_16; +typedef volatile uint8_t io_rw_8; +typedef const volatile uint8_t io_ro_8; +typedef volatile uint8_t io_wo_8; + +// A non-functional (empty) helper macro to help IDEs follow links from the autogenerated +// hardware struct headers in hardware/structs/xxx.h to the raw register definitions +// in hardware/regs/xxx.h. A preprocessor define such as TIMER_TIMEHW_OFFSET (a timer register offset) +// is not generally clickable (in an IDE) if placed in a C comment, so _REG_(TIMER_TIMEHW_OFFSET) is +// included outside of a comment instead +#define _REG_(x) + +#endif \ No newline at end of file diff --git a/modules/freertos/picosdk/include_common/hardware/clocks.h b/modules/freertos/picosdk/include_common/hardware/clocks.h new file mode 100644 index 000000000..fda73cb4d --- /dev/null +++ b/modules/freertos/picosdk/include_common/hardware/clocks.h @@ -0,0 +1,10 @@ +#ifndef _HARDWARE_CLOCKS_H +#define _HARDWARE_CLOCKS_H + +#include "hardware/structs/clocks.h" + +typedef clock_num_t clock_handle_t; + +uint32_t clock_get_hz(clock_handle_t clock); + +#endif \ No newline at end of file diff --git a/modules/freertos/picosdk/include_common/hardware/exception.h b/modules/freertos/picosdk/include_common/hardware/exception.h new file mode 100644 index 000000000..5cbbde848 --- /dev/null +++ b/modules/freertos/picosdk/include_common/hardware/exception.h @@ -0,0 +1,27 @@ +#ifndef _HARDWARE_EXCEPTION_H +#define _HARDWARE_EXCEPTION_H + +#include "hardware/address_mapped.h" + +enum exception_number { + // Assigned to VTOR indices + MIN_EXCEPTION_NUM = 2, + NMI_EXCEPTION = 2, ///< Non Maskable Interrupt + HARDFAULT_EXCEPTION = 3, ///< HardFault Interrupt +#if PICO_RP2350 + MEMMANAGE_EXCEPTION = 4, ///< MemManage Interrupt + BUSFAULT_EXCEPTION = 5, ///< BusFault Interrupt + USAGEFAULT_EXCEPTION = 6, ///< UsageFault Interrupt + SECUREFAULT_EXCEPTION = 7, ///< SecureFault Interrupt +#endif + SVCALL_EXCEPTION = 11, ///< SV Call Interrupt + PENDSV_EXCEPTION = 14, ///< Pend SV Interrupt + SYSTICK_EXCEPTION = 15, ///< System Tick Interrupt + MAX_EXCEPTION_NUM = 15 +}; + +typedef void (*exception_handler_t)(void); + +exception_handler_t exception_set_exclusive_handler(enum exception_number num, exception_handler_t handler); + +#endif \ No newline at end of file diff --git a/modules/freertos/picosdk/include_common/hardware/irq.h b/modules/freertos/picosdk/include_common/hardware/irq.h new file mode 100644 index 000000000..9ab3986d1 --- /dev/null +++ b/modules/freertos/picosdk/include_common/hardware/irq.h @@ -0,0 +1,14 @@ +#ifndef _HARDWARE_IRQ_H +#define _HARDWARE_IRQ_H + +#include "hardware/regs/intctrl.h" + +typedef void (*irq_handler_t)(void); + +void irq_set_priority(uint num, uint8_t hardware_priority); + +void irq_set_exclusive_handler(uint num, irq_handler_t handler); + +void irq_set_enabled(uint num, bool enabled); + +#endif \ No newline at end of file diff --git a/modules/freertos/picosdk/include_common/hardware/sync.h b/modules/freertos/picosdk/include_common/hardware/sync.h new file mode 100644 index 000000000..7e00b65f0 --- /dev/null +++ b/modules/freertos/picosdk/include_common/hardware/sync.h @@ -0,0 +1,90 @@ +#ifndef _HARDWARE_SYNC_H +#define _HARDWARE_SYNC_H + +#include "pico.h" +#include "hardware/address_mapped.h" + +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_SYNC +#ifdef PARAM_ASSERTIONS_ENABLED_SYNC // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_SYNC PARAM_ASSERTIONS_ENABLED_SYNC +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_SYNC 0 +#endif +#endif + +#if !__has_builtin(__sev) +__force_inline static void __sev(void) { +#ifdef __riscv + __hazard3_unblock(); +#else + pico_default_asm_volatile ("sev"); +#endif +} +#endif + +/*! \brief Insert a WFE instruction in to the code path. + * \ingroup hardware_sync + * + * The WFE (wait for event) instruction waits until one of a number of + * events occurs, including events signalled by the SEV instruction on either core. + */ +#if !__has_builtin(__wfe) +__force_inline static void __wfe(void) { +#ifdef __riscv + __hazard3_block(); +#else + pico_default_asm_volatile ("wfe"); +#endif +} +#endif + +/*! \brief Insert a DMB instruction in to the code path. + * \ingroup hardware_sync + * + * The DMB (data memory barrier) acts as a memory barrier, all memory accesses prior to this + * instruction will be observed before any explicit access after the instruction. + */ +__force_inline static void __dmb(void) { +#ifdef __riscv + __asm volatile ("fence rw, rw" : : : "memory"); +#else + pico_default_asm_volatile ("dmb" : : : "memory"); +#endif +} + +__force_inline static void __mem_fence_acquire(void) { + // the original code below makes it hard for us to be included from C++ via a header + // which itself is in an extern "C", so just use __dmb instead, which is what + // is required on Cortex M0+ + __dmb(); +//#ifndef __cplusplus +// atomic_thread_fence(memory_order_acquire); +//#else +// std::atomic_thread_fence(std::memory_order_acquire); +//#endif +} + +__force_inline static void __mem_fence_release(void) { + // the original code below makes it hard for us to be included from C++ via a header + // which itself is in an extern "C", so just use __dmb instead, which is what + // is required on Cortex M0+ + __dmb(); +//#ifndef __cplusplus +// atomic_thread_fence(memory_order_release); +//#else +// std::atomic_thread_fence(std::memory_order_release); +//#endif +} + +uint next_striped_spin_lock_num(void); + +void spin_lock_claim(uint lock_num); + +__force_inline static void restore_interrupts_from_disabled(uint32_t status) { + // on ARM, this behaves the same as restore_interrupts() + pico_default_asm_volatile ("msr PRIMASK,%0"::"r" (status) : "memory" ); +} + +#include "hardware/sync/spin_lock.h" + +#endif \ No newline at end of file diff --git a/modules/freertos/picosdk/include_common/hardware/sync/spin_lock.h b/modules/freertos/picosdk/include_common/hardware/sync/spin_lock.h new file mode 100644 index 000000000..eb392d766 --- /dev/null +++ b/modules/freertos/picosdk/include_common/hardware/sync/spin_lock.h @@ -0,0 +1,68 @@ +#ifndef _HARDWARE_SYNC_SPIN_LOCK_H +#define _HARDWARE_SYNC_SPIN_LOCK_H + +#include "pico.h" + +// PICO_CONFIG: PICO_SPINLOCK_ID_OS1, First Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=14, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_OS1 +#define PICO_SPINLOCK_ID_OS1 14 +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_OS2, Second Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=15, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_OS2 +#define PICO_SPINLOCK_ID_OS2 15 +#endif + +typedef io_rw_32 spin_lock_t; + +__force_inline static spin_lock_t *spin_lock_instance(uint lock_num) { + invalid_params_if(HARDWARE_SYNC, lock_num >= NUM_SPIN_LOCKS); +#if PICO_USE_SW_SPIN_LOCKS + return SW_SPIN_LOCK_INSTANCE(lock_num); +#else + return (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET + lock_num * 4); +#endif +} + +__force_inline static void spin_lock_unsafe_blocking(spin_lock_t *lock) { + // Note we don't do a wfe or anything, because by convention these spin_locks are VERY SHORT LIVED and NEVER BLOCK and run + // with INTERRUPTS disabled (to ensure that)... therefore nothing on our core could be blocking us, so we just need to wait on another core + // anyway which should be finished soon +#if PICO_USE_SW_SPIN_LOCKS + SW_SPIN_LOCK_LOCK(lock); +#else + while (__builtin_expect(!*lock, 0)) { // read from spinlock register (tries to acquire the lock) + tight_loop_contents(); + } + __mem_fence_acquire(); +#endif +} + +__force_inline static void spin_unlock_unsafe(spin_lock_t *lock) { +#if PICO_USE_SW_SPIN_LOCKS + SW_SPIN_LOCK_UNLOCK(lock); +#else + __mem_fence_release(); + *lock = 0; // write to spinlock register (release lock) +#endif +} + +__force_inline static void spin_unlock(spin_lock_t *lock, uint32_t saved_irq) { + spin_unlock_unsafe(lock); + restore_interrupts_from_disabled(saved_irq); +} + +__force_inline static uint spin_lock_get_num(spin_lock_t *lock) { +#if PICO_USE_SW_SPIN_LOCKS + uint lock_num = SW_SPIN_LOCK_NUM(lock); + invalid_params_if(HARDWARE_SYNC, lock_num >= (uint)NUM_SPIN_LOCKS); + return lock_num; +#else + invalid_params_if(HARDWARE_SYNC, (uint) lock < SIO_BASE + SIO_SPINLOCK0_OFFSET || + (uint) lock >= NUM_SPIN_LOCKS * sizeof(spin_lock_t) + SIO_BASE + SIO_SPINLOCK0_OFFSET || + ((uint) lock - SIO_BASE + SIO_SPINLOCK0_OFFSET) % sizeof(spin_lock_t) != 0); + return (uint) (lock - (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET)); +#endif +} + +#endif \ No newline at end of file diff --git a/modules/freertos/picosdk/include_common/hardware/timer.h b/modules/freertos/picosdk/include_common/hardware/timer.h new file mode 100644 index 000000000..bc0e21d15 --- /dev/null +++ b/modules/freertos/picosdk/include_common/hardware/timer.h @@ -0,0 +1,10 @@ +#ifndef _HARDWARE_TIMER_H +#define _HARDWARE_TIMER_H + +#include "hardware/address_mapped.h" + +uint64_t time_us_64(); + +bool time_reached(absolute_time_t t); + +#endif \ No newline at end of file diff --git a/modules/freertos/picosdk/include_common/pico.h b/modules/freertos/picosdk/include_common/pico.h new file mode 100644 index 000000000..1115d63a0 --- /dev/null +++ b/modules/freertos/picosdk/include_common/pico.h @@ -0,0 +1,9 @@ +#ifndef _PICO_H +#define _PICO_H + +#include "pico/platform.h" + +// Microzig Hack, so port can compile when configNUMBER_OF_CORES is 1 otherwise port include lock_core.h that already includes this file +#include "hardware/structs/sio.h" + +#endif \ No newline at end of file diff --git a/modules/freertos/picosdk/include_common/pico/assert.h b/modules/freertos/picosdk/include_common/pico/assert.h new file mode 100644 index 000000000..5f11f6857 --- /dev/null +++ b/modules/freertos/picosdk/include_common/pico/assert.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_ASSERT_H +#define _PICO_ASSERT_H + +#include + +#ifdef __cplusplus + +#include + +extern "C" { +#else +#include +#endif + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLE_ALL, Global assert enable, type=bool, default=0, group=pico_base +// PICO_CONFIG: PARAM_ASSERTIONS_DISABLE_ALL, Global assert disable, type=bool, default=0, group=pico_base + +#ifndef PARAM_ASSERTIONS_ENABLE_ALL +#define PARAM_ASSERTIONS_ENABLE_ALL 0 +#endif + +#ifndef PARAM_ASSERTIONS_DISABLE_ALL +#define PARAM_ASSERTIONS_DISABLE_ALL 0 +#endif + +#define PARAM_ASSERTIONS_ENABLED(x) ((PARAM_ASSERTIONS_ENABLED_ ## x || PARAM_ASSERTIONS_ENABLE_ALL) && !PARAM_ASSERTIONS_DISABLE_ALL) + +#define invalid_params_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) assert(!(test));}) +#define valid_params_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) assert(test);}) +#define hard_assert_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) hard_assert(!(test));}) +#define invalid_params_if_and_return(x, test, rc) ({/*if (PARAM_ASSERTIONS_ENABLED(x)) assert(!(test)); */ if (test) return rc; }) + +#ifdef NDEBUG +extern void hard_assertion_failure(void); + +/*! \brief Perform a runtime assertion always (i.e. not just when NDEBUG is undefined) +* \ingroup pico_base +* +* This function is intended to provide useful information in debug builds like a normal assertion, but also +* prevent execution proceeding in other builds +* +* In debug builds this is equivalent to \ref assert, however in release builds it calls \ref hard_assertion_failure +* which, by default, just calls \ref panic with the string "Hard assert" +*/ +static inline void hard_assert(bool condition, ...) { + if (!condition) + hard_assertion_failure(); +} +#else +#define hard_assert assert +#endif + +#ifdef __cplusplus +} +#endif +#endif \ No newline at end of file diff --git a/modules/freertos/picosdk/include_common/pico/lock_core.h b/modules/freertos/picosdk/include_common/pico/lock_core.h new file mode 100644 index 000000000..7297d51c8 --- /dev/null +++ b/modules/freertos/picosdk/include_common/pico/lock_core.h @@ -0,0 +1,16 @@ +#ifndef _PICO_LOCK_CORE_H +#define _PICO_LOCK_CORE_H + +#include "pico/time.h" + +struct lock_core { + // spin lock protecting this lock's state + spin_lock_t *spin_lock; + + // note any lock members in containing structures need not be volatile; + // they are protected by memory/compiler barriers when gaining and release spin locks +}; + +typedef struct lock_core lock_core_t; + +#endif \ No newline at end of file diff --git a/modules/freertos/picosdk/include_common/pico/multicore.h b/modules/freertos/picosdk/include_common/pico/multicore.h new file mode 100644 index 000000000..b9d8412b1 --- /dev/null +++ b/modules/freertos/picosdk/include_common/pico/multicore.h @@ -0,0 +1,24 @@ +#ifndef _PICO_MULTICORE_H +#define _PICO_MULTICORE_H + +#include "hardware/structs/sio.h" + +void multicore_reset_core1(void); + +void multicore_launch_core1(void (*entry)(void)); + +static inline bool multicore_fifo_rvalid(void) { + return sio_hw->fifo_st & SIO_FIFO_ST_VLD_BITS; +} + +static inline void multicore_fifo_drain(void) { + while (multicore_fifo_rvalid()) + (void) sio_hw->fifo_rd; +} + +static inline void multicore_fifo_clear_irq(void) { + // Write any value to clear the error flags + sio_hw->fifo_st = 0xff; +} + +#endif \ No newline at end of file diff --git a/modules/freertos/picosdk/include_common/pico/platform/common.h b/modules/freertos/picosdk/include_common/pico/platform/common.h new file mode 100644 index 000000000..0a0d10729 --- /dev/null +++ b/modules/freertos/picosdk/include_common/pico/platform/common.h @@ -0,0 +1,19 @@ +#ifndef _PICO_PLATFORM_COMMON_H +#define _PICO_PLATFORM_COMMON_H + +// PICO_CONFIG: PICO_MINIMAL_STORED_VECTOR_TABLE, Only store a very minimal vector table in the binary on Arm, type=bool, default=0, advanced=true, group=pico_crt0 +#ifndef PICO_MINIMAL_STORED_VECTOR_TABLE +#define PICO_MINIMAL_STORED_VECTOR_TABLE 0 +#endif + +/*! \brief No-op function for the body of tight loops + * \ingroup pico_platform + * + * No-op function intended to be called by any tight hardware polling loop. Using this ubiquitously + * makes it much easier to find tight loops, but also in the future \#ifdef-ed support for lockup + * debugging might be added + */ +static __force_inline void tight_loop_contents(void) {} + + +#endif \ No newline at end of file diff --git a/modules/freertos/picosdk/include_common/pico/platform/compiler.h b/modules/freertos/picosdk/include_common/pico/platform/compiler.h new file mode 100644 index 000000000..773406e50 --- /dev/null +++ b/modules/freertos/picosdk/include_common/pico/platform/compiler.h @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_PLATFORM_COMPILER_H +#define _PICO_PLATFORM_COMPILER_H + +/** \file pico/platform/compiler.h + * \ingroup pico_platform + * + * \brief Macros and definitions (and functions when included by non assembly code) to adapt for different compilers + * + * This header may be included by assembly code + */ + +#include "hardware/platform_defs.h" + +#ifndef __ASSEMBLER__ + +#if defined __GNUC__ +#include +// note LLVM defines __GNUC__ +#ifdef __clang__ +#define PICO_C_COMPILER_IS_CLANG 1 +#else +#define PICO_C_COMPILER_IS_GNU 1 +#endif +#elif defined __ICCARM__ +#ifndef __aligned +#define __aligned(x) __attribute__((__aligned__(x))) +#endif +#ifndef __always_inline +#define __always_inline __attribute__((__always_inline__)) +#endif +#ifndef __noinline +#define __noinline __attribute__((__noinline__)) +#endif +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif +#ifndef __printflike +#define __printflike(a, b) +#endif +#ifndef __unused +#define __unused __attribute__((__unused__)) +#endif +#ifndef __used +#define __used __attribute__((__used__)) +#endif +#ifndef __CONCAT1 +#define __CONCAT1(a, b) a ## b +#endif +#ifndef __CONCAT +#define __CONCAT(a, b) __CONCAT1(a, b) +#endif +#ifndef __STRING +#define __STRING(a) #a +#endif +/* Compatible definitions of GCC builtins */ + +static inline uint __builtin_ctz(uint x) { + extern uint32_t __ctzsi2(uint32_t); + return __ctzsi2(x); +} +#define __builtin_expect(x, y) (x) +#define __builtin_isnan(x) __iar_isnan(x) +#else +#error Unsupported toolchain +#endif + +#define __weak __attribute__((weak)) + +#include "pico/types.h" + +// GCC_Like_Pragma(x) is a pragma on GNUC compatible compilers +#ifdef __GNUC__ +#define GCC_Like_Pragma _Pragma +#else +#define GCC_Like_Pragma(x) +#endif + +// Clang_Pragma(x) is a pragma on Clang only +#ifdef __clang__ +#define Clang_Pragma _Pragma +#else +#define Clang_Pragma(x) +#endif + +// GCC_Pragma(x) is a pragma on GCC only +#if PICO_C_COMPILER_IS_GNU +#define GCC_Pragma _Pragma +#else +#define GCC_Pragma(x) +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*! \brief Marker for an interrupt handler + * \ingroup pico_platform + * + * For example an IRQ handler function called my_interrupt_handler: + * + * void __isr my_interrupt_handler(void) { + */ +#define __isr + +#define __packed_aligned __packed __aligned(4) + +/*! \brief Attribute to force inlining of a function regardless of optimization level + * \ingroup pico_platform + * + * For example my_function here will always be inlined: + * + * int __force_inline my_function(int x) { + * + */ + +#if PICO_C_COMPILER_IS_GNU && (__GNUC__ <= 6 || (__GNUC__ == 7 && (__GNUC_MINOR__ < 3 || !defined(__cplusplus)))) +#define __force_inline inline __always_inline +#else +#define __force_inline __always_inline +#endif + +/*! \brief Macro to determine the number of elements in an array + * \ingroup pico_platform + */ +#ifndef count_of +#define count_of(a) (sizeof(a)/sizeof((a)[0])) +#endif + +/*! \brief Macro to return the maximum of two comparable values + * \ingroup pico_platform + */ +#ifndef MAX +#define MAX(a, b) ((a)>(b)?(a):(b)) +#endif + +/*! \brief Macro to return the minimum of two comparable values + * \ingroup pico_platform + */ +#ifndef MIN +#define MIN(a, b) ((b)>(a)?(a):(b)) +#endif + +#ifdef __ARM_ARCH_ISA_THUMB +#define pico_default_asm(...) __asm (".syntax unified\n" __VA_ARGS__) +#define pico_default_asm_volatile(...) __asm volatile (".syntax unified\n" __VA_ARGS__) +#define pico_default_asm_goto(...) __asm goto (".syntax unified\n" __VA_ARGS__) +#define pico_default_asm_volatile_goto(...) __asm volatile goto (".syntax unified\n" __VA_ARGS__) +#else +#define pico_default_asm(...) __asm (__VA_ARGS__) +#define pico_default_asm_volatile(...) __asm volatile (__VA_ARGS__) +#define pico_default_asm_goto(...) __asm goto (__VA_ARGS__) +#define pico_default_asm_volatile_goto(...) __asm volatile goto (__VA_ARGS__) +#endif + +/*! \brief Ensure that the compiler does not move memory access across this method call + * \ingroup pico_platform + * + * For example in the following code: + * + * *some_memory_location = var_a; + * __compiler_memory_barrier(); + * uint32_t var_b = *some_other_memory_location + * + * The compiler will not move the load from `some_other_memory_location` above the memory barrier (which it otherwise + * might - even above the memory store!) + */ +__force_inline static void __compiler_memory_barrier(void) { + pico_default_asm_volatile ("" : : : "memory"); +} + +/*! \brief Utility macro to assert two types are equivalent. + * \ingroup pico_platform + * + * This macro can be useful in other macros along with `typeof` to assert that two parameters are of equivalent type + * (or that a single parameter is of an expected type) + */ +#define __check_type_compatible(type_a, type_b) static_assert(__builtin_types_compatible_p(type_a, type_b), __STRING(type_a) " is not compatible with " __STRING(type_b)); + +#define WRAPPER_FUNC(x) __wrap_ ## x +#define REAL_FUNC(x) __real_ ## x + +#ifdef __cplusplus +} +#endif + +#else // __ASSEMBLER__ + +#if defined __GNUC__ +// note LLVM defines __GNUC__ +#ifdef __clang__ +#define PICO_ASSEMBLER_IS_CLANG 1 +#else +#define PICO_ASSEMBLER_IS_GNU 1 +#endif +#elif defined __ICCARM__ +#else +#error Unsupported toolchain +#endif + +#define WRAPPER_FUNC_NAME(x) __wrap_##x + +#endif // !__ASSEMBLER__ + +#endif \ No newline at end of file diff --git a/modules/freertos/picosdk/include_common/pico/time.h b/modules/freertos/picosdk/include_common/pico/time.h new file mode 100644 index 000000000..9c0782cc6 --- /dev/null +++ b/modules/freertos/picosdk/include_common/pico/time.h @@ -0,0 +1,20 @@ +#ifndef _PICO_TIME_H +#define _PICO_TIME_H + +#include "hardware/timer.h" + +typedef uint64_t absolute_time_t; + +static inline absolute_time_t get_absolute_time(void) { + absolute_time_t t; + update_us_since_boot(&t, time_us_64()); + return t; +} + +static inline int64_t absolute_time_diff_us(absolute_time_t from, absolute_time_t to) { + return (int64_t)(to_us_since_boot(to) - to_us_since_boot(from)); +} + +bool best_effort_wfe_or_timeout(absolute_time_t timeout_timestamp); + +#endif \ No newline at end of file diff --git a/modules/freertos/picosdk/include_common/pico/types.h b/modules/freertos/picosdk/include_common/pico/types.h new file mode 100644 index 000000000..b2e06cf6d --- /dev/null +++ b/modules/freertos/picosdk/include_common/pico/types.h @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_TYPES_H +#define _PICO_TYPES_H + +#ifndef __ASSEMBLER__ + +#include "pico/assert.h" + +#include +#include +#include + +typedef unsigned int uint; + +// PICO_CONFIG: PICO_OPAQUE_ABSOLUTE_TIME_T, Enable opaque type for absolute_time_t to help catch inadvertent confusing uint64_t delays with absolute times, default=0, advanced=true, group=pico_base +#ifndef PICO_OPAQUE_ABSOLUTE_TIME_T +#define PICO_OPAQUE_ABSOLUTE_TIME_T 0 +#endif + +/*! \typedef absolute_time_t + * \brief An opaque 64 bit timestamp in microseconds + * + * The type is used instead of a raw uint64_t to prevent accidentally passing relative times or times in the wrong + * time units where an absolute time is required. + * + * note: As of SDK 2.0.0 this type defaults to being a uin64_t (i.e. no protection); it is enabled + * by setting PICO_OPAQUE_ABSOLUTE_TIME_T to 1 + * + * \see to_us_since_boot() + * \see update_us_since_boot() + * \ingroup timestamp + */ +#if PICO_OPAQUE_ABSOLUTE_TIME_T +typedef struct { + uint64_t _private_us_since_boot; +} absolute_time_t; +#else +typedef uint64_t absolute_time_t; +#endif + +/*! fn to_us_since_boot + * \brief convert an absolute_time_t into a number of microseconds since boot. + * \param t the absolute time to convert + * \return a number of microseconds since boot, equivalent to t + * \ingroup timestamp + */ +static inline uint64_t to_us_since_boot(absolute_time_t t) { +#ifdef PICO_DEBUG_ABSOLUTE_TIME_T + return t._private_us_since_boot; +#else + return t; +#endif +} + +/*! fn update_us_since_boot + * \brief update an absolute_time_t value to represent a given number of microseconds since boot + * \param t the absolute time value to update + * \param us_since_boot the number of microseconds since boot to represent. Note this should be representable + * as a signed 64 bit integer + * \ingroup timestamp + */ +static inline void update_us_since_boot(absolute_time_t *t, uint64_t us_since_boot) { +#ifdef PICO_DEBUG_ABSOLUTE_TIME_T + assert(us_since_boot <= INT64_MAX); + t->_private_us_since_boot = us_since_boot; +#else + *t = us_since_boot; +#endif +} + +/*! fn from_us_since_boot + * \brief convert a number of microseconds since boot to an absolute_time_t + * \param us_since_boot number of microseconds since boot + * \return an absolute time equivalent to us_since_boot + * \ingroup timestamp + */ +static inline absolute_time_t from_us_since_boot(uint64_t us_since_boot) { + absolute_time_t t; + update_us_since_boot(&t, us_since_boot); + return t; +} + +#ifdef NDEBUG +#define ABSOLUTE_TIME_INITIALIZED_VAR(name, value) name = value +#else +#define ABSOLUTE_TIME_INITIALIZED_VAR(name, value) name = {value} +#endif + +// PICO_CONFIG: PICO_INCLUDE_RTC_DATETIME, Whether to include the datetime_t type used with the RP2040 RTC hardware, default=1 on RP2040, group=util_datetime +#ifndef PICO_INCLUDE_RTC_DATETIME +#define PICO_INCLUDE_RTC_DATETIME PICO_RP2040 +#endif + +#if PICO_INCLUDE_RTC_DATETIME +/** \struct datetime_t + * \ingroup util_datetime + * \brief Structure containing date and time information + * + * When setting an RTC alarm, set a field to -1 tells + * the RTC to not match on this field + */ +typedef struct { + int16_t year; ///< 0..4095 + int8_t month; ///< 1..12, 1 is January + int8_t day; ///< 1..28,29,30,31 depending on month + int8_t dotw; ///< 0..6, 0 is Sunday + int8_t hour; ///< 0..23 + int8_t min; ///< 0..59 + int8_t sec; ///< 0..59 +} datetime_t; +#endif + +#define bool_to_bit(x) ((uint)!!(x)) + +#endif +#endif \ No newline at end of file diff --git a/modules/freertos/picosdk/include_common/sys/cdefs.h b/modules/freertos/picosdk/include_common/sys/cdefs.h new file mode 100644 index 000000000..fbff6d2cb --- /dev/null +++ b/modules/freertos/picosdk/include_common/sys/cdefs.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __PICO_LLVM_LIBC_SYS_CDEFS_H +#define __PICO_LLVM_LIBC_SYS_CDEFS_H + +#if defined(__STDC__) || defined(__cplusplus) + +#define __CONCAT1(x,y) x ## y +#define __CONCAT(x,y) __CONCAT1(x,y) +#define __STRING(x) #x +#define __XSTRING(x) __STRING(x) + +#endif + +#define __unused __attribute__((__unused__)) +#define __used __attribute__((__used__)) +#define __packed __attribute__((__packed__)) +#define __aligned(x) __attribute__((__aligned__(x))) + +#define __always_inline __inline__ __attribute__((__always_inline__)) +#define __noinline __attribute__((__noinline__)) + +#define __printflike(fmtarg, firstvararg) \ + __attribute__((__format__ (__printf__, fmtarg, firstvararg))) + +#endif \ No newline at end of file diff --git a/modules/freertos/picosdk/include_rp2040/hardware/platform_defs.h b/modules/freertos/picosdk/include_rp2040/hardware/platform_defs.h new file mode 100644 index 000000000..fe9fd0bf0 --- /dev/null +++ b/modules/freertos/picosdk/include_rp2040/hardware/platform_defs.h @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_PLATFORM_DEFS_H +#define _HARDWARE_PLATFORM_DEFS_H + +// This header is included from C and assembler - intended mostly for #defines; guard other stuff with #ifdef __ASSEMBLER__ + +#ifndef _u +#ifdef __ASSEMBLER__ +#define _u(x) x +#else +#define _u(x) x ## u +#endif +#endif + +#define NUM_CORES _u(2) +#define NUM_DMA_CHANNELS _u(12) +#define NUM_DMA_TIMERS _u(4) +#define NUM_DMA_IRQS _u(2) +#define NUM_IRQS _u(32) +#define NUM_USER_IRQS _u(6) +#define NUM_PIOS _u(2) +#define NUM_PIO_STATE_MACHINES _u(4) +#define NUM_PIO_IRQS _u(2) +#define NUM_PWM_SLICES _u(8) +#define NUM_PWM_IRQS _u(1) +#define NUM_SPIN_LOCKS _u(32) +#define NUM_UARTS _u(2) +#define NUM_I2CS _u(2) +#define NUM_SPIS _u(2) +#define NUM_GENERIC_TIMERS _u(1) +#define NUM_ALARMS _u(4) +#define ADC_BASE_PIN _u(26) +#define NUM_ADC_CHANNELS _u(5) +#define NUM_RESETS _u(24) +#define NUM_BANK0_GPIOS _u(30) +#define NUM_QSPI_GPIOS _u(6) + +#define PIO_INSTRUCTION_COUNT _u(32) + +#define USBCTRL_DPRAM_SIZE _u(4096) + +#define HAS_SIO_DIVIDER 1 +#define HAS_RP2040_RTC 1 + +#ifndef FPGA_CLK_SYS_HZ +#define FPGA_CLK_SYS_HZ (48 * MHZ) +#endif + +#ifndef FPGA_CLK_REF_HZ +#define FPGA_CLK_REF_HZ (12 * MHZ) +#endif + +// PICO_CONFIG: XOSC_HZ, Crystal oscillator frequency in Hz, type=int, default=12000000, advanced=true, group=hardware_base +// NOTE: The system and USB clocks are generated from the frequency using two PLLs. +// If you override this define, or SYS_CLK_HZ/USB_CLK_HZ below, you will *also* need to add your own adjusted PLL set-up defines to +// override the defaults which live in src/rp2_common/hardware_clocks/include/hardware/clocks.h +// Please see the comments there about calculating the new PLL setting values. +#ifndef XOSC_HZ +#ifdef XOSC_KHZ +#define XOSC_HZ ((XOSC_KHZ) * _u(1000)) +#elif defined(XOSC_MHZ) +#define XOSC_HZ ((XOSC_MHZ) * _u(1000000)) +#else +#define XOSC_HZ _u(12000000) +#endif +#endif + +// PICO_CONFIG: PICO_USE_FASTEST_SUPPORTED_CLOCK, Use the fastest officially supported clock by default, type=bool, default=0, group=hardware_base +#ifndef PICO_USE_FASTEST_SUPPORTED_CLOCK +#define PICO_USE_FASTEST_SUPPORTED_CLOCK 0 +#endif + +// PICO_CONFIG: SYS_CLK_HZ, System operating frequency in Hz, type=int, default=125000000, advanced=true, group=hardware_base +#ifndef SYS_CLK_HZ +#ifdef SYS_CLK_KHZ +#define SYS_CLK_HZ ((SYS_CLK_KHZ) * _u(1000)) +#elif defined(SYS_CLK_MHZ) +#define SYS_CLK_HZ ((SYS_CLK_MHZ) * _u(1000000)) +#else +#if PICO_USE_FASTEST_SUPPORTED_CLOCK +#define SYS_CLK_HZ _u(200000000) +#else +#define SYS_CLK_HZ _u(125000000) +#endif +#endif +#endif + +// PICO_CONFIG: USB_CLK_HZ, USB clock frequency. Must be 48MHz for the USB interface to operate correctly, type=int, default=48000000, advanced=true, group=hardware_base +#ifndef USB_CLK_HZ +#ifdef USB_CLK_KHZ +#define USB_CLK_HZ ((USB_CLK_KHZ) * _u(1000)) +#elif defined(USB_CLK_MHZ) +#define USB_CLK_HZ ((USB_CLK_MHZ) * _u(1000000)) +#else +#define USB_CLK_HZ _u(48000000) +#endif +#endif + +// For backwards compatibility define XOSC_KHZ if the frequency is indeed an integer number of Khz. +#if defined(XOSC_HZ) && !defined(XOSC_KHZ) && (XOSC_HZ % 1000 == 0) +#define XOSC_KHZ (XOSC_HZ / 1000) +#endif + +// For backwards compatibility define XOSC_MHZ if the frequency is indeed an integer number of Mhz. +#if defined(XOSC_KHZ) && !defined(XOSC_MHZ) && (XOSC_KHZ % 1000 == 0) +#define XOSC_MHZ (XOSC_KHZ / 1000) +#endif + +// For backwards compatibility define SYS_CLK_KHZ if the frequency is indeed an integer number of Khz. +#if defined(SYS_CLK_HZ) && !defined(SYS_CLK_KHZ) && (SYS_CLK_HZ % 1000 == 0) +#define SYS_CLK_KHZ (SYS_CLK_HZ / 1000) +#endif + +// For backwards compatibility define SYS_CLK_MHZ if the frequency is indeed an integer number of Mhz. +#if defined(SYS_CLK_KHZ) && !defined(SYS_CLK_MHZ) && (SYS_CLK_KHZ % 1000 == 0) +#define SYS_CLK_MHZ (SYS_CLK_KHZ / 1000) +#endif + +// For backwards compatibility define USB_CLK_KHZ if the frequency is indeed an integer number of Khz. +#if defined(USB_CLK_HZ) && !defined(USB_CLK_KHZ) && (USB_CLK_HZ % 1000 == 0) +#define USB_CLK_KHZ (USB_CLK_HZ / 1000) +#endif + +// For backwards compatibility define USB_CLK_MHZ if the frequency is indeed an integer number of Mhz. +#if defined(USB_CLK_KHZ) && !defined(USB_CLK_MHZ) && (USB_CLK_KHZ % 1000 == 0) +#define USB_CLK_MHZ (USB_CLK_KHZ / 1000) +#endif + +#define FIRST_USER_IRQ (NUM_IRQS - NUM_USER_IRQS) +#define VTABLE_FIRST_IRQ 16 + +#define REG_FIELD_WIDTH(f) (f ## _MSB + 1 - f ## _LSB) + +#endif \ No newline at end of file diff --git a/modules/freertos/picosdk/include_rp2040/hardware/regs/addressmap.h b/modules/freertos/picosdk/include_rp2040/hardware/regs/addressmap.h new file mode 100644 index 000000000..bc4b466ea --- /dev/null +++ b/modules/freertos/picosdk/include_rp2040/hardware/regs/addressmap.h @@ -0,0 +1,80 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _ADDRESSMAP_H +#define _ADDRESSMAP_H + +/** + * \file rp2040/addressmap.h + */ + +#include "hardware/platform_defs.h" + +// Register address offsets for atomic RMW aliases +#define REG_ALIAS_RW_BITS (_u(0x0) << _u(12)) +#define REG_ALIAS_XOR_BITS (_u(0x1) << _u(12)) +#define REG_ALIAS_SET_BITS (_u(0x2) << _u(12)) +#define REG_ALIAS_CLR_BITS (_u(0x3) << _u(12)) + +#define ROM_BASE _u(0x00000000) +#define XIP_BASE _u(0x10000000) +#define XIP_MAIN_BASE _u(0x10000000) +#define XIP_NOALLOC_BASE _u(0x11000000) +#define XIP_NOCACHE_BASE _u(0x12000000) +#define XIP_NOCACHE_NOALLOC_BASE _u(0x13000000) +#define XIP_CTRL_BASE _u(0x14000000) +#define XIP_SRAM_BASE _u(0x15000000) +#define XIP_SRAM_END _u(0x15004000) +#define XIP_SSI_BASE _u(0x18000000) +#define SRAM_BASE _u(0x20000000) +#define SRAM_STRIPED_BASE _u(0x20000000) +#define SRAM_STRIPED_END _u(0x20040000) +#define SRAM4_BASE _u(0x20040000) +#define SRAM5_BASE _u(0x20041000) +#define SRAM_END _u(0x20042000) +#define SRAM0_BASE _u(0x21000000) +#define SRAM1_BASE _u(0x21010000) +#define SRAM2_BASE _u(0x21020000) +#define SRAM3_BASE _u(0x21030000) +#define SYSINFO_BASE _u(0x40000000) +#define SYSCFG_BASE _u(0x40004000) +#define CLOCKS_BASE _u(0x40008000) +#define RESETS_BASE _u(0x4000c000) +#define PSM_BASE _u(0x40010000) +#define IO_BANK0_BASE _u(0x40014000) +#define IO_QSPI_BASE _u(0x40018000) +#define PADS_BANK0_BASE _u(0x4001c000) +#define PADS_QSPI_BASE _u(0x40020000) +#define XOSC_BASE _u(0x40024000) +#define PLL_SYS_BASE _u(0x40028000) +#define PLL_USB_BASE _u(0x4002c000) +#define BUSCTRL_BASE _u(0x40030000) +#define UART0_BASE _u(0x40034000) +#define UART1_BASE _u(0x40038000) +#define SPI0_BASE _u(0x4003c000) +#define SPI1_BASE _u(0x40040000) +#define I2C0_BASE _u(0x40044000) +#define I2C1_BASE _u(0x40048000) +#define ADC_BASE _u(0x4004c000) +#define PWM_BASE _u(0x40050000) +#define TIMER_BASE _u(0x40054000) +#define WATCHDOG_BASE _u(0x40058000) +#define RTC_BASE _u(0x4005c000) +#define ROSC_BASE _u(0x40060000) +#define VREG_AND_CHIP_RESET_BASE _u(0x40064000) +#define TBMAN_BASE _u(0x4006c000) +#define DMA_BASE _u(0x50000000) +#define USBCTRL_DPRAM_BASE _u(0x50100000) +#define USBCTRL_BASE _u(0x50100000) +#define USBCTRL_REGS_BASE _u(0x50110000) +#define PIO0_BASE _u(0x50200000) +#define PIO1_BASE _u(0x50300000) +#define XIP_AUX_BASE _u(0x50400000) +#define SIO_BASE _u(0xd0000000) +#define PPB_BASE _u(0xe0000000) + +#endif // _ADDRESSMAP_H \ No newline at end of file diff --git a/modules/freertos/picosdk/include_rp2040/hardware/regs/intctrl.h b/modules/freertos/picosdk/include_rp2040/hardware/regs/intctrl.h new file mode 100644 index 000000000..9e2a259b2 --- /dev/null +++ b/modules/freertos/picosdk/include_rp2040/hardware/regs/intctrl.h @@ -0,0 +1,123 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _INTCTRL_H +#define _INTCTRL_H + +/** + * \file rp2040/intctrl.h + */ + +#ifdef __ASSEMBLER__ +#define TIMER_IRQ_0 0 +#define TIMER_IRQ_1 1 +#define TIMER_IRQ_2 2 +#define TIMER_IRQ_3 3 +#define PWM_IRQ_WRAP 4 +#define USBCTRL_IRQ 5 +#define XIP_IRQ 6 +#define PIO0_IRQ_0 7 +#define PIO0_IRQ_1 8 +#define PIO1_IRQ_0 9 +#define PIO1_IRQ_1 10 +#define DMA_IRQ_0 11 +#define DMA_IRQ_1 12 +#define IO_IRQ_BANK0 13 +#define IO_IRQ_QSPI 14 +#define SIO_IRQ_PROC0 15 +#define SIO_IRQ_PROC1 16 +#define CLOCKS_IRQ 17 +#define SPI0_IRQ 18 +#define SPI1_IRQ 19 +#define UART0_IRQ 20 +#define UART1_IRQ 21 +#define ADC_IRQ_FIFO 22 +#define I2C0_IRQ 23 +#define I2C1_IRQ 24 +#define RTC_IRQ 25 +#define SPARE_IRQ_0 26 +#define SPARE_IRQ_1 27 +#define SPARE_IRQ_2 28 +#define SPARE_IRQ_3 29 +#define SPARE_IRQ_4 30 +#define SPARE_IRQ_5 31 +#else +/** + * \brief Interrupt numbers on RP2040 (used as typedef \ref irq_num_t) + * \ingroup hardware_irq + */ +typedef enum irq_num_rp2040 { + TIMER_IRQ_0 = 0, ///< Select TIMER's IRQ 0 output + TIMER_IRQ_1 = 1, ///< Select TIMER's IRQ 1 output + TIMER_IRQ_2 = 2, ///< Select TIMER's IRQ 2 output + TIMER_IRQ_3 = 3, ///< Select TIMER's IRQ 3 output + PWM_IRQ_WRAP = 4, ///< Select PWM's IRQ_WRAP output + USBCTRL_IRQ = 5, ///< Select USBCTRL's IRQ output + XIP_IRQ = 6, ///< Select XIP's IRQ output + PIO0_IRQ_0 = 7, ///< Select PIO0's IRQ 0 output + PIO0_IRQ_1 = 8, ///< Select PIO0's IRQ 1 output + PIO1_IRQ_0 = 9, ///< Select PIO1's IRQ 0 output + PIO1_IRQ_1 = 10, ///< Select PIO1's IRQ 1 output + DMA_IRQ_0 = 11, ///< Select DMA's IRQ 0 output + DMA_IRQ_1 = 12, ///< Select DMA's IRQ 1 output + IO_IRQ_BANK0 = 13, ///< Select IO_BANK0's IRQ output + IO_IRQ_QSPI = 14, ///< Select IO_QSPI's IRQ output + SIO_IRQ_PROC0 = 15, ///< Select SIO_PROC0's IRQ output + SIO_IRQ_PROC1 = 16, ///< Select SIO_PROC1's IRQ output + CLOCKS_IRQ = 17, ///< Select CLOCKS's IRQ output + SPI0_IRQ = 18, ///< Select SPI0's IRQ output + SPI1_IRQ = 19, ///< Select SPI1's IRQ output + UART0_IRQ = 20, ///< Select UART0's IRQ output + UART1_IRQ = 21, ///< Select UART1's IRQ output + ADC_IRQ_FIFO = 22, ///< Select ADC's IRQ_FIFO output + I2C0_IRQ = 23, ///< Select I2C0's IRQ output + I2C1_IRQ = 24, ///< Select I2C1's IRQ output + RTC_IRQ = 25, ///< Select RTC's IRQ output + SPARE_IRQ_0 = 26, ///< Select SPARE IRQ 0 + SPARE_IRQ_1 = 27, ///< Select SPARE IRQ 1 + SPARE_IRQ_2 = 28, ///< Select SPARE IRQ 2 + SPARE_IRQ_3 = 29, ///< Select SPARE IRQ 3 + SPARE_IRQ_4 = 30, ///< Select SPARE IRQ 4 + SPARE_IRQ_5 = 31, ///< Select SPARE IRQ 5 + IRQ_COUNT +} irq_num_t; +#endif + +#define isr_timer_0 isr_irq0 +#define isr_timer_1 isr_irq1 +#define isr_timer_2 isr_irq2 +#define isr_timer_3 isr_irq3 +#define isr_pwm_wrap isr_irq4 +#define isr_usbctrl isr_irq5 +#define isr_xip isr_irq6 +#define isr_pio0_0 isr_irq7 +#define isr_pio0_1 isr_irq8 +#define isr_pio1_0 isr_irq9 +#define isr_pio1_1 isr_irq10 +#define isr_dma_0 isr_irq11 +#define isr_dma_1 isr_irq12 +#define isr_io_bank0 isr_irq13 +#define isr_io_qspi isr_irq14 +#define isr_sio_proc0 isr_irq15 +#define isr_sio_proc1 isr_irq16 +#define isr_clocks isr_irq17 +#define isr_spi0 isr_irq18 +#define isr_spi1 isr_irq19 +#define isr_uart0 isr_irq20 +#define isr_uart1 isr_irq21 +#define isr_adc_fifo isr_irq22 +#define isr_i2c0 isr_irq23 +#define isr_i2c1 isr_irq24 +#define isr_rtc isr_irq25 +#define isr_spare_0 isr_irq26 +#define isr_spare_1 isr_irq27 +#define isr_spare_2 isr_irq28 +#define isr_spare_3 isr_irq29 +#define isr_spare_4 isr_irq30 +#define isr_spare_5 isr_irq31 + +#endif // _INTCTRL_H \ No newline at end of file diff --git a/modules/freertos/picosdk/include_rp2040/hardware/regs/sio.h b/modules/freertos/picosdk/include_rp2040/hardware/regs/sio.h new file mode 100644 index 000000000..37755ac6a --- /dev/null +++ b/modules/freertos/picosdk/include_rp2040/hardware/regs/sio.h @@ -0,0 +1,1658 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SIO +// Version : 1 +// Bus type : apb +// Description : Single-cycle IO block +// Provides core-local and inter-core hardware for the two +// processors, with single-cycle access. +// ============================================================================= +#ifndef _HARDWARE_REGS_SIO_H +#define _HARDWARE_REGS_SIO_H +// ============================================================================= +// Register : SIO_CPUID +// Description : Processor core identifier +// Value is 0 when read from processor core 0, and 1 when read +// from processor core 1. +#define SIO_CPUID_OFFSET _u(0x00000000) +#define SIO_CPUID_BITS _u(0xffffffff) +#define SIO_CPUID_RESET "-" +#define SIO_CPUID_MSB _u(31) +#define SIO_CPUID_LSB _u(0) +#define SIO_CPUID_ACCESS "RO" +// ============================================================================= +// Register : SIO_GPIO_IN +// Description : Input value for GPIO pins +// Input value for GPIO0...29 +#define SIO_GPIO_IN_OFFSET _u(0x00000004) +#define SIO_GPIO_IN_BITS _u(0x3fffffff) +#define SIO_GPIO_IN_RESET _u(0x00000000) +#define SIO_GPIO_IN_MSB _u(29) +#define SIO_GPIO_IN_LSB _u(0) +#define SIO_GPIO_IN_ACCESS "RO" +// ============================================================================= +// Register : SIO_GPIO_HI_IN +// Description : Input value for QSPI pins +// Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, +// SD3 +#define SIO_GPIO_HI_IN_OFFSET _u(0x00000008) +#define SIO_GPIO_HI_IN_BITS _u(0x0000003f) +#define SIO_GPIO_HI_IN_RESET _u(0x00000000) +#define SIO_GPIO_HI_IN_MSB _u(5) +#define SIO_GPIO_HI_IN_LSB _u(0) +#define SIO_GPIO_HI_IN_ACCESS "RO" +// ============================================================================= +// Register : SIO_GPIO_OUT +// Description : GPIO output value +// Set output level (1/0 -> high/low) for GPIO0...29. +// Reading back gives the last value written, NOT the input value +// from the pins. +// If core 0 and core 1 both write to GPIO_OUT simultaneously (or +// to a SET/CLR/XOR alias), +// the result is as though the write from core 0 took place first, +// and the write from core 1 was then applied to that intermediate +// result. +#define SIO_GPIO_OUT_OFFSET _u(0x00000010) +#define SIO_GPIO_OUT_BITS _u(0x3fffffff) +#define SIO_GPIO_OUT_RESET _u(0x00000000) +#define SIO_GPIO_OUT_MSB _u(29) +#define SIO_GPIO_OUT_LSB _u(0) +#define SIO_GPIO_OUT_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_OUT_SET +// Description : GPIO output value set +// Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` +#define SIO_GPIO_OUT_SET_OFFSET _u(0x00000014) +#define SIO_GPIO_OUT_SET_BITS _u(0x3fffffff) +#define SIO_GPIO_OUT_SET_RESET _u(0x00000000) +#define SIO_GPIO_OUT_SET_MSB _u(29) +#define SIO_GPIO_OUT_SET_LSB _u(0) +#define SIO_GPIO_OUT_SET_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_OUT_CLR +// Description : GPIO output value clear +// Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= +// ~wdata` +#define SIO_GPIO_OUT_CLR_OFFSET _u(0x00000018) +#define SIO_GPIO_OUT_CLR_BITS _u(0x3fffffff) +#define SIO_GPIO_OUT_CLR_RESET _u(0x00000000) +#define SIO_GPIO_OUT_CLR_MSB _u(29) +#define SIO_GPIO_OUT_CLR_LSB _u(0) +#define SIO_GPIO_OUT_CLR_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_OUT_XOR +// Description : GPIO output value XOR +// Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= +// wdata` +#define SIO_GPIO_OUT_XOR_OFFSET _u(0x0000001c) +#define SIO_GPIO_OUT_XOR_BITS _u(0x3fffffff) +#define SIO_GPIO_OUT_XOR_RESET _u(0x00000000) +#define SIO_GPIO_OUT_XOR_MSB _u(29) +#define SIO_GPIO_OUT_XOR_LSB _u(0) +#define SIO_GPIO_OUT_XOR_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_OE +// Description : GPIO output enable +// Set output enable (1/0 -> output/input) for GPIO0...29. +// Reading back gives the last value written. +// If core 0 and core 1 both write to GPIO_OE simultaneously (or +// to a SET/CLR/XOR alias), +// the result is as though the write from core 0 took place first, +// and the write from core 1 was then applied to that intermediate +// result. +#define SIO_GPIO_OE_OFFSET _u(0x00000020) +#define SIO_GPIO_OE_BITS _u(0x3fffffff) +#define SIO_GPIO_OE_RESET _u(0x00000000) +#define SIO_GPIO_OE_MSB _u(29) +#define SIO_GPIO_OE_LSB _u(0) +#define SIO_GPIO_OE_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_OE_SET +// Description : GPIO output enable set +// Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` +#define SIO_GPIO_OE_SET_OFFSET _u(0x00000024) +#define SIO_GPIO_OE_SET_BITS _u(0x3fffffff) +#define SIO_GPIO_OE_SET_RESET _u(0x00000000) +#define SIO_GPIO_OE_SET_MSB _u(29) +#define SIO_GPIO_OE_SET_LSB _u(0) +#define SIO_GPIO_OE_SET_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_OE_CLR +// Description : GPIO output enable clear +// Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= +// ~wdata` +#define SIO_GPIO_OE_CLR_OFFSET _u(0x00000028) +#define SIO_GPIO_OE_CLR_BITS _u(0x3fffffff) +#define SIO_GPIO_OE_CLR_RESET _u(0x00000000) +#define SIO_GPIO_OE_CLR_MSB _u(29) +#define SIO_GPIO_OE_CLR_LSB _u(0) +#define SIO_GPIO_OE_CLR_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_OE_XOR +// Description : GPIO output enable XOR +// Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= +// wdata` +#define SIO_GPIO_OE_XOR_OFFSET _u(0x0000002c) +#define SIO_GPIO_OE_XOR_BITS _u(0x3fffffff) +#define SIO_GPIO_OE_XOR_RESET _u(0x00000000) +#define SIO_GPIO_OE_XOR_MSB _u(29) +#define SIO_GPIO_OE_XOR_LSB _u(0) +#define SIO_GPIO_OE_XOR_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_HI_OUT +// Description : QSPI output value +// Set output level (1/0 -> high/low) for QSPI IO0...5. +// Reading back gives the last value written, NOT the input value +// from the pins. +// If core 0 and core 1 both write to GPIO_HI_OUT simultaneously +// (or to a SET/CLR/XOR alias), +// the result is as though the write from core 0 took place first, +// and the write from core 1 was then applied to that intermediate +// result. +#define SIO_GPIO_HI_OUT_OFFSET _u(0x00000030) +#define SIO_GPIO_HI_OUT_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OUT_RESET _u(0x00000000) +#define SIO_GPIO_HI_OUT_MSB _u(5) +#define SIO_GPIO_HI_OUT_LSB _u(0) +#define SIO_GPIO_HI_OUT_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OUT_SET +// Description : QSPI output value set +// Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= +// wdata` +#define SIO_GPIO_HI_OUT_SET_OFFSET _u(0x00000034) +#define SIO_GPIO_HI_OUT_SET_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OUT_SET_RESET _u(0x00000000) +#define SIO_GPIO_HI_OUT_SET_MSB _u(5) +#define SIO_GPIO_HI_OUT_SET_LSB _u(0) +#define SIO_GPIO_HI_OUT_SET_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_HI_OUT_CLR +// Description : QSPI output value clear +// Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT +// &= ~wdata` +#define SIO_GPIO_HI_OUT_CLR_OFFSET _u(0x00000038) +#define SIO_GPIO_HI_OUT_CLR_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OUT_CLR_RESET _u(0x00000000) +#define SIO_GPIO_HI_OUT_CLR_MSB _u(5) +#define SIO_GPIO_HI_OUT_CLR_LSB _u(0) +#define SIO_GPIO_HI_OUT_CLR_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_HI_OUT_XOR +// Description : QSPI output value XOR +// Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT +// ^= wdata` +#define SIO_GPIO_HI_OUT_XOR_OFFSET _u(0x0000003c) +#define SIO_GPIO_HI_OUT_XOR_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OUT_XOR_RESET _u(0x00000000) +#define SIO_GPIO_HI_OUT_XOR_MSB _u(5) +#define SIO_GPIO_HI_OUT_XOR_LSB _u(0) +#define SIO_GPIO_HI_OUT_XOR_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_HI_OE +// Description : QSPI output enable +// Set output enable (1/0 -> output/input) for QSPI IO0...5. +// Reading back gives the last value written. +// If core 0 and core 1 both write to GPIO_HI_OE simultaneously +// (or to a SET/CLR/XOR alias), +// the result is as though the write from core 0 took place first, +// and the write from core 1 was then applied to that intermediate +// result. +#define SIO_GPIO_HI_OE_OFFSET _u(0x00000040) +#define SIO_GPIO_HI_OE_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OE_RESET _u(0x00000000) +#define SIO_GPIO_HI_OE_MSB _u(5) +#define SIO_GPIO_HI_OE_LSB _u(0) +#define SIO_GPIO_HI_OE_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OE_SET +// Description : QSPI output enable set +// Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= +// wdata` +#define SIO_GPIO_HI_OE_SET_OFFSET _u(0x00000044) +#define SIO_GPIO_HI_OE_SET_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OE_SET_RESET _u(0x00000000) +#define SIO_GPIO_HI_OE_SET_MSB _u(5) +#define SIO_GPIO_HI_OE_SET_LSB _u(0) +#define SIO_GPIO_HI_OE_SET_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_HI_OE_CLR +// Description : QSPI output enable clear +// Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= +// ~wdata` +#define SIO_GPIO_HI_OE_CLR_OFFSET _u(0x00000048) +#define SIO_GPIO_HI_OE_CLR_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OE_CLR_RESET _u(0x00000000) +#define SIO_GPIO_HI_OE_CLR_MSB _u(5) +#define SIO_GPIO_HI_OE_CLR_LSB _u(0) +#define SIO_GPIO_HI_OE_CLR_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_HI_OE_XOR +// Description : QSPI output enable XOR +// Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE +// ^= wdata` +#define SIO_GPIO_HI_OE_XOR_OFFSET _u(0x0000004c) +#define SIO_GPIO_HI_OE_XOR_BITS _u(0x0000003f) +#define SIO_GPIO_HI_OE_XOR_RESET _u(0x00000000) +#define SIO_GPIO_HI_OE_XOR_MSB _u(5) +#define SIO_GPIO_HI_OE_XOR_LSB _u(0) +#define SIO_GPIO_HI_OE_XOR_ACCESS "WO" +// ============================================================================= +// Register : SIO_FIFO_ST +// Description : Status register for inter-core FIFOs (mailboxes). +// There is one FIFO in the core 0 -> core 1 direction, and one +// core 1 -> core 0. Both are 32 bits wide and 8 words deep. +// Core 0 can see the read side of the 1->0 FIFO (RX), and the +// write side of 0->1 FIFO (TX). +// Core 1 can see the read side of the 0->1 FIFO (RX), and the +// write side of 1->0 FIFO (TX). +// The SIO IRQ for each core is the logical OR of the VLD, WOF and +// ROE fields of its FIFO_ST register. +#define SIO_FIFO_ST_OFFSET _u(0x00000050) +#define SIO_FIFO_ST_BITS _u(0x0000000f) +#define SIO_FIFO_ST_RESET _u(0x00000002) +// ----------------------------------------------------------------------------- +// Field : SIO_FIFO_ST_ROE +// Description : Sticky flag indicating the RX FIFO was read when empty. This +// read was ignored by the FIFO. +#define SIO_FIFO_ST_ROE_RESET _u(0x0) +#define SIO_FIFO_ST_ROE_BITS _u(0x00000008) +#define SIO_FIFO_ST_ROE_MSB _u(3) +#define SIO_FIFO_ST_ROE_LSB _u(3) +#define SIO_FIFO_ST_ROE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : SIO_FIFO_ST_WOF +// Description : Sticky flag indicating the TX FIFO was written when full. This +// write was ignored by the FIFO. +#define SIO_FIFO_ST_WOF_RESET _u(0x0) +#define SIO_FIFO_ST_WOF_BITS _u(0x00000004) +#define SIO_FIFO_ST_WOF_MSB _u(2) +#define SIO_FIFO_ST_WOF_LSB _u(2) +#define SIO_FIFO_ST_WOF_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : SIO_FIFO_ST_RDY +// Description : Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR +// is ready for more data) +#define SIO_FIFO_ST_RDY_RESET _u(0x1) +#define SIO_FIFO_ST_RDY_BITS _u(0x00000002) +#define SIO_FIFO_ST_RDY_MSB _u(1) +#define SIO_FIFO_ST_RDY_LSB _u(1) +#define SIO_FIFO_ST_RDY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_FIFO_ST_VLD +// Description : Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD +// is valid) +#define SIO_FIFO_ST_VLD_RESET _u(0x0) +#define SIO_FIFO_ST_VLD_BITS _u(0x00000001) +#define SIO_FIFO_ST_VLD_MSB _u(0) +#define SIO_FIFO_ST_VLD_LSB _u(0) +#define SIO_FIFO_ST_VLD_ACCESS "RO" +// ============================================================================= +// Register : SIO_FIFO_WR +// Description : Write access to this core's TX FIFO +#define SIO_FIFO_WR_OFFSET _u(0x00000054) +#define SIO_FIFO_WR_BITS _u(0xffffffff) +#define SIO_FIFO_WR_RESET _u(0x00000000) +#define SIO_FIFO_WR_MSB _u(31) +#define SIO_FIFO_WR_LSB _u(0) +#define SIO_FIFO_WR_ACCESS "WF" +// ============================================================================= +// Register : SIO_FIFO_RD +// Description : Read access to this core's RX FIFO +#define SIO_FIFO_RD_OFFSET _u(0x00000058) +#define SIO_FIFO_RD_BITS _u(0xffffffff) +#define SIO_FIFO_RD_RESET "-" +#define SIO_FIFO_RD_MSB _u(31) +#define SIO_FIFO_RD_LSB _u(0) +#define SIO_FIFO_RD_ACCESS "RF" +// ============================================================================= +// Register : SIO_SPINLOCK_ST +// Description : Spinlock state +// A bitmap containing the state of all 32 spinlocks (1=locked). +// Mainly intended for debugging. +#define SIO_SPINLOCK_ST_OFFSET _u(0x0000005c) +#define SIO_SPINLOCK_ST_BITS _u(0xffffffff) +#define SIO_SPINLOCK_ST_RESET _u(0x00000000) +#define SIO_SPINLOCK_ST_MSB _u(31) +#define SIO_SPINLOCK_ST_LSB _u(0) +#define SIO_SPINLOCK_ST_ACCESS "RO" +// ============================================================================= +// Register : SIO_DIV_UDIVIDEND +// Description : Divider unsigned dividend +// Write to the DIVIDEND operand of the divider, i.e. the p in `p +// / q`. +// Any operand write starts a new calculation. The results appear +// in QUOTIENT, REMAINDER. +// UDIVIDEND/SDIVIDEND are aliases of the same internal register. +// The U alias starts an +// unsigned calculation, and the S alias starts a signed +// calculation. +#define SIO_DIV_UDIVIDEND_OFFSET _u(0x00000060) +#define SIO_DIV_UDIVIDEND_BITS _u(0xffffffff) +#define SIO_DIV_UDIVIDEND_RESET _u(0x00000000) +#define SIO_DIV_UDIVIDEND_MSB _u(31) +#define SIO_DIV_UDIVIDEND_LSB _u(0) +#define SIO_DIV_UDIVIDEND_ACCESS "RW" +// ============================================================================= +// Register : SIO_DIV_UDIVISOR +// Description : Divider unsigned divisor +// Write to the DIVISOR operand of the divider, i.e. the q in `p / +// q`. +// Any operand write starts a new calculation. The results appear +// in QUOTIENT, REMAINDER. +// UDIVISOR/SDIVISOR are aliases of the same internal register. +// The U alias starts an +// unsigned calculation, and the S alias starts a signed +// calculation. +#define SIO_DIV_UDIVISOR_OFFSET _u(0x00000064) +#define SIO_DIV_UDIVISOR_BITS _u(0xffffffff) +#define SIO_DIV_UDIVISOR_RESET _u(0x00000000) +#define SIO_DIV_UDIVISOR_MSB _u(31) +#define SIO_DIV_UDIVISOR_LSB _u(0) +#define SIO_DIV_UDIVISOR_ACCESS "RW" +// ============================================================================= +// Register : SIO_DIV_SDIVIDEND +// Description : Divider signed dividend +// The same as UDIVIDEND, but starts a signed calculation, rather +// than unsigned. +#define SIO_DIV_SDIVIDEND_OFFSET _u(0x00000068) +#define SIO_DIV_SDIVIDEND_BITS _u(0xffffffff) +#define SIO_DIV_SDIVIDEND_RESET _u(0x00000000) +#define SIO_DIV_SDIVIDEND_MSB _u(31) +#define SIO_DIV_SDIVIDEND_LSB _u(0) +#define SIO_DIV_SDIVIDEND_ACCESS "RW" +// ============================================================================= +// Register : SIO_DIV_SDIVISOR +// Description : Divider signed divisor +// The same as UDIVISOR, but starts a signed calculation, rather +// than unsigned. +#define SIO_DIV_SDIVISOR_OFFSET _u(0x0000006c) +#define SIO_DIV_SDIVISOR_BITS _u(0xffffffff) +#define SIO_DIV_SDIVISOR_RESET _u(0x00000000) +#define SIO_DIV_SDIVISOR_MSB _u(31) +#define SIO_DIV_SDIVISOR_LSB _u(0) +#define SIO_DIV_SDIVISOR_ACCESS "RW" +// ============================================================================= +// Register : SIO_DIV_QUOTIENT +// Description : Divider result quotient +// The result of `DIVIDEND / DIVISOR` (division). Contents +// undefined while CSR_READY is low. +// For signed calculations, QUOTIENT is negative when the signs of +// DIVIDEND and DIVISOR differ. +// This register can be written to directly, for context +// save/restore purposes. This halts any +// in-progress calculation and sets the CSR_READY and CSR_DIRTY +// flags. +// Reading from QUOTIENT clears the CSR_DIRTY flag, so should read +// results in the order +// REMAINDER, QUOTIENT if CSR_DIRTY is used. +#define SIO_DIV_QUOTIENT_OFFSET _u(0x00000070) +#define SIO_DIV_QUOTIENT_BITS _u(0xffffffff) +#define SIO_DIV_QUOTIENT_RESET _u(0x00000000) +#define SIO_DIV_QUOTIENT_MSB _u(31) +#define SIO_DIV_QUOTIENT_LSB _u(0) +#define SIO_DIV_QUOTIENT_ACCESS "RW" +// ============================================================================= +// Register : SIO_DIV_REMAINDER +// Description : Divider result remainder +// The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined +// while CSR_READY is low. +// For signed calculations, REMAINDER is negative only when +// DIVIDEND is negative. +// This register can be written to directly, for context +// save/restore purposes. This halts any +// in-progress calculation and sets the CSR_READY and CSR_DIRTY +// flags. +#define SIO_DIV_REMAINDER_OFFSET _u(0x00000074) +#define SIO_DIV_REMAINDER_BITS _u(0xffffffff) +#define SIO_DIV_REMAINDER_RESET _u(0x00000000) +#define SIO_DIV_REMAINDER_MSB _u(31) +#define SIO_DIV_REMAINDER_LSB _u(0) +#define SIO_DIV_REMAINDER_ACCESS "RW" +// ============================================================================= +// Register : SIO_DIV_CSR +// Description : Control and status register for divider. +#define SIO_DIV_CSR_OFFSET _u(0x00000078) +#define SIO_DIV_CSR_BITS _u(0x00000003) +#define SIO_DIV_CSR_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : SIO_DIV_CSR_DIRTY +// Description : Changes to 1 when any register is written, and back to 0 when +// QUOTIENT is read. +// Software can use this flag to make save/restore more efficient +// (skip if not DIRTY). +// If the flag is used in this way, it's recommended to either +// read QUOTIENT only, +// or REMAINDER and then QUOTIENT, to prevent data loss on context +// switch. +#define SIO_DIV_CSR_DIRTY_RESET _u(0x0) +#define SIO_DIV_CSR_DIRTY_BITS _u(0x00000002) +#define SIO_DIV_CSR_DIRTY_MSB _u(1) +#define SIO_DIV_CSR_DIRTY_LSB _u(1) +#define SIO_DIV_CSR_DIRTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_DIV_CSR_READY +// Description : Reads as 0 when a calculation is in progress, 1 otherwise. +// Writing an operand (xDIVIDEND, xDIVISOR) will immediately start +// a new calculation, no +// matter if one is already in progress. +// Writing to a result register will immediately terminate any in- +// progress calculation +// and set the READY and DIRTY flags. +#define SIO_DIV_CSR_READY_RESET _u(0x1) +#define SIO_DIV_CSR_READY_BITS _u(0x00000001) +#define SIO_DIV_CSR_READY_MSB _u(0) +#define SIO_DIV_CSR_READY_LSB _u(0) +#define SIO_DIV_CSR_READY_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_ACCUM0 +// Description : Read/write access to accumulator 0 +#define SIO_INTERP0_ACCUM0_OFFSET _u(0x00000080) +#define SIO_INTERP0_ACCUM0_BITS _u(0xffffffff) +#define SIO_INTERP0_ACCUM0_RESET _u(0x00000000) +#define SIO_INTERP0_ACCUM0_MSB _u(31) +#define SIO_INTERP0_ACCUM0_LSB _u(0) +#define SIO_INTERP0_ACCUM0_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_ACCUM1 +// Description : Read/write access to accumulator 1 +#define SIO_INTERP0_ACCUM1_OFFSET _u(0x00000084) +#define SIO_INTERP0_ACCUM1_BITS _u(0xffffffff) +#define SIO_INTERP0_ACCUM1_RESET _u(0x00000000) +#define SIO_INTERP0_ACCUM1_MSB _u(31) +#define SIO_INTERP0_ACCUM1_LSB _u(0) +#define SIO_INTERP0_ACCUM1_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_BASE0 +// Description : Read/write access to BASE0 register. +#define SIO_INTERP0_BASE0_OFFSET _u(0x00000088) +#define SIO_INTERP0_BASE0_BITS _u(0xffffffff) +#define SIO_INTERP0_BASE0_RESET _u(0x00000000) +#define SIO_INTERP0_BASE0_MSB _u(31) +#define SIO_INTERP0_BASE0_LSB _u(0) +#define SIO_INTERP0_BASE0_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_BASE1 +// Description : Read/write access to BASE1 register. +#define SIO_INTERP0_BASE1_OFFSET _u(0x0000008c) +#define SIO_INTERP0_BASE1_BITS _u(0xffffffff) +#define SIO_INTERP0_BASE1_RESET _u(0x00000000) +#define SIO_INTERP0_BASE1_MSB _u(31) +#define SIO_INTERP0_BASE1_LSB _u(0) +#define SIO_INTERP0_BASE1_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_BASE2 +// Description : Read/write access to BASE2 register. +#define SIO_INTERP0_BASE2_OFFSET _u(0x00000090) +#define SIO_INTERP0_BASE2_BITS _u(0xffffffff) +#define SIO_INTERP0_BASE2_RESET _u(0x00000000) +#define SIO_INTERP0_BASE2_MSB _u(31) +#define SIO_INTERP0_BASE2_LSB _u(0) +#define SIO_INTERP0_BASE2_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_POP_LANE0 +// Description : Read LANE0 result, and simultaneously write lane results to +// both accumulators (POP). +#define SIO_INTERP0_POP_LANE0_OFFSET _u(0x00000094) +#define SIO_INTERP0_POP_LANE0_BITS _u(0xffffffff) +#define SIO_INTERP0_POP_LANE0_RESET _u(0x00000000) +#define SIO_INTERP0_POP_LANE0_MSB _u(31) +#define SIO_INTERP0_POP_LANE0_LSB _u(0) +#define SIO_INTERP0_POP_LANE0_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_POP_LANE1 +// Description : Read LANE1 result, and simultaneously write lane results to +// both accumulators (POP). +#define SIO_INTERP0_POP_LANE1_OFFSET _u(0x00000098) +#define SIO_INTERP0_POP_LANE1_BITS _u(0xffffffff) +#define SIO_INTERP0_POP_LANE1_RESET _u(0x00000000) +#define SIO_INTERP0_POP_LANE1_MSB _u(31) +#define SIO_INTERP0_POP_LANE1_LSB _u(0) +#define SIO_INTERP0_POP_LANE1_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_POP_FULL +// Description : Read FULL result, and simultaneously write lane results to both +// accumulators (POP). +#define SIO_INTERP0_POP_FULL_OFFSET _u(0x0000009c) +#define SIO_INTERP0_POP_FULL_BITS _u(0xffffffff) +#define SIO_INTERP0_POP_FULL_RESET _u(0x00000000) +#define SIO_INTERP0_POP_FULL_MSB _u(31) +#define SIO_INTERP0_POP_FULL_LSB _u(0) +#define SIO_INTERP0_POP_FULL_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_PEEK_LANE0 +// Description : Read LANE0 result, without altering any internal state (PEEK). +#define SIO_INTERP0_PEEK_LANE0_OFFSET _u(0x000000a0) +#define SIO_INTERP0_PEEK_LANE0_BITS _u(0xffffffff) +#define SIO_INTERP0_PEEK_LANE0_RESET _u(0x00000000) +#define SIO_INTERP0_PEEK_LANE0_MSB _u(31) +#define SIO_INTERP0_PEEK_LANE0_LSB _u(0) +#define SIO_INTERP0_PEEK_LANE0_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_PEEK_LANE1 +// Description : Read LANE1 result, without altering any internal state (PEEK). +#define SIO_INTERP0_PEEK_LANE1_OFFSET _u(0x000000a4) +#define SIO_INTERP0_PEEK_LANE1_BITS _u(0xffffffff) +#define SIO_INTERP0_PEEK_LANE1_RESET _u(0x00000000) +#define SIO_INTERP0_PEEK_LANE1_MSB _u(31) +#define SIO_INTERP0_PEEK_LANE1_LSB _u(0) +#define SIO_INTERP0_PEEK_LANE1_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_PEEK_FULL +// Description : Read FULL result, without altering any internal state (PEEK). +#define SIO_INTERP0_PEEK_FULL_OFFSET _u(0x000000a8) +#define SIO_INTERP0_PEEK_FULL_BITS _u(0xffffffff) +#define SIO_INTERP0_PEEK_FULL_RESET _u(0x00000000) +#define SIO_INTERP0_PEEK_FULL_MSB _u(31) +#define SIO_INTERP0_PEEK_FULL_LSB _u(0) +#define SIO_INTERP0_PEEK_FULL_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_CTRL_LANE0 +// Description : Control register for lane 0 +#define SIO_INTERP0_CTRL_LANE0_OFFSET _u(0x000000ac) +#define SIO_INTERP0_CTRL_LANE0_BITS _u(0x03bfffff) +#define SIO_INTERP0_CTRL_LANE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_OVERF +// Description : Set if either OVERF0 or OVERF1 is set. +#define SIO_INTERP0_CTRL_LANE0_OVERF_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_OVERF_BITS _u(0x02000000) +#define SIO_INTERP0_CTRL_LANE0_OVERF_MSB _u(25) +#define SIO_INTERP0_CTRL_LANE0_OVERF_LSB _u(25) +#define SIO_INTERP0_CTRL_LANE0_OVERF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_OVERF1 +// Description : Indicates if any masked-off MSBs in ACCUM1 are set. +#define SIO_INTERP0_CTRL_LANE0_OVERF1_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_OVERF1_BITS _u(0x01000000) +#define SIO_INTERP0_CTRL_LANE0_OVERF1_MSB _u(24) +#define SIO_INTERP0_CTRL_LANE0_OVERF1_LSB _u(24) +#define SIO_INTERP0_CTRL_LANE0_OVERF1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_OVERF0 +// Description : Indicates if any masked-off MSBs in ACCUM0 are set. +#define SIO_INTERP0_CTRL_LANE0_OVERF0_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_OVERF0_BITS _u(0x00800000) +#define SIO_INTERP0_CTRL_LANE0_OVERF0_MSB _u(23) +#define SIO_INTERP0_CTRL_LANE0_OVERF0_LSB _u(23) +#define SIO_INTERP0_CTRL_LANE0_OVERF0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_BLEND +// Description : Only present on INTERP0 on each core. If BLEND mode is enabled: +// - LANE1 result is a linear interpolation between BASE0 and +// BASE1, controlled +// by the 8 LSBs of lane 1 shift and mask value (a fractional +// number between +// 0 and 255/256ths) +// - LANE0 result does not have BASE0 added (yields only the 8 +// LSBs of lane 1 shift+mask value) +// - FULL result does not have lane 1 shift+mask value added +// (BASE2 + lane 0 shift+mask) +// LANE1 SIGNED flag controls whether the interpolation is signed +// or unsigned. +#define SIO_INTERP0_CTRL_LANE0_BLEND_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_BLEND_BITS _u(0x00200000) +#define SIO_INTERP0_CTRL_LANE0_BLEND_MSB _u(21) +#define SIO_INTERP0_CTRL_LANE0_BLEND_LSB _u(21) +#define SIO_INTERP0_CTRL_LANE0_BLEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_FORCE_MSB +// Description : ORed into bits 29:28 of the lane result presented to the +// processor on the bus. +// No effect on the internal 32-bit datapath. Handy for using a +// lane to generate sequence +// of pointers into flash or SRAM. +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS _u(0x00180000) +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MSB _u(20) +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB _u(19) +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_ADD_RAW +// Description : If 1, mask + shift is bypassed for LANE0 result. This does not +// affect FULL result. +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS _u(0x00040000) +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_MSB _u(18) +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_LSB _u(18) +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_CROSS_RESULT +// Description : If 1, feed the opposite lane's result into this lane's +// accumulator on POP. +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS _u(0x00020000) +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_MSB _u(17) +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_LSB _u(17) +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_CROSS_INPUT +// Description : If 1, feed the opposite lane's accumulator into this lane's +// shift + mask hardware. +// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is +// before the shift+mask bypass) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS _u(0x00010000) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_MSB _u(16) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_LSB _u(16) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_SIGNED +// Description : If SIGNED is set, the shifted and masked accumulator value is +// sign-extended to 32 bits +// before adding to BASE0, and LANE0 PEEK/POP appear extended to +// 32 bits when read by processor. +#define SIO_INTERP0_CTRL_LANE0_SIGNED_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_SIGNED_BITS _u(0x00008000) +#define SIO_INTERP0_CTRL_LANE0_SIGNED_MSB _u(15) +#define SIO_INTERP0_CTRL_LANE0_SIGNED_LSB _u(15) +#define SIO_INTERP0_CTRL_LANE0_SIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_MASK_MSB +// Description : The most-significant bit allowed to pass by the mask +// (inclusive) +// Setting MSB < LSB may cause chip to turn inside-out +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS _u(0x00007c00) +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_MSB _u(14) +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB _u(10) +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_MASK_LSB +// Description : The least-significant bit allowed to pass by the mask +// (inclusive) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS _u(0x000003e0) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_MSB _u(9) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB _u(5) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_SHIFT +// Description : Logical right-shift applied to accumulator before masking +#define SIO_INTERP0_CTRL_LANE0_SHIFT_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE0_SHIFT_BITS _u(0x0000001f) +#define SIO_INTERP0_CTRL_LANE0_SHIFT_MSB _u(4) +#define SIO_INTERP0_CTRL_LANE0_SHIFT_LSB _u(0) +#define SIO_INTERP0_CTRL_LANE0_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_CTRL_LANE1 +// Description : Control register for lane 1 +#define SIO_INTERP0_CTRL_LANE1_OFFSET _u(0x000000b0) +#define SIO_INTERP0_CTRL_LANE1_BITS _u(0x001fffff) +#define SIO_INTERP0_CTRL_LANE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_FORCE_MSB +// Description : ORed into bits 29:28 of the lane result presented to the +// processor on the bus. +// No effect on the internal 32-bit datapath. Handy for using a +// lane to generate sequence +// of pointers into flash or SRAM. +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_BITS _u(0x00180000) +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MSB _u(20) +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_LSB _u(19) +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_ADD_RAW +// Description : If 1, mask + shift is bypassed for LANE1 result. This does not +// affect FULL result. +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_BITS _u(0x00040000) +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_MSB _u(18) +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_LSB _u(18) +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_CROSS_RESULT +// Description : If 1, feed the opposite lane's result into this lane's +// accumulator on POP. +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_BITS _u(0x00020000) +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_MSB _u(17) +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_LSB _u(17) +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_CROSS_INPUT +// Description : If 1, feed the opposite lane's accumulator into this lane's +// shift + mask hardware. +// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is +// before the shift+mask bypass) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_BITS _u(0x00010000) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_MSB _u(16) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_LSB _u(16) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_SIGNED +// Description : If SIGNED is set, the shifted and masked accumulator value is +// sign-extended to 32 bits +// before adding to BASE1, and LANE1 PEEK/POP appear extended to +// 32 bits when read by processor. +#define SIO_INTERP0_CTRL_LANE1_SIGNED_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_SIGNED_BITS _u(0x00008000) +#define SIO_INTERP0_CTRL_LANE1_SIGNED_MSB _u(15) +#define SIO_INTERP0_CTRL_LANE1_SIGNED_LSB _u(15) +#define SIO_INTERP0_CTRL_LANE1_SIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_MASK_MSB +// Description : The most-significant bit allowed to pass by the mask +// (inclusive) +// Setting MSB < LSB may cause chip to turn inside-out +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_BITS _u(0x00007c00) +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_MSB _u(14) +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_LSB _u(10) +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_MASK_LSB +// Description : The least-significant bit allowed to pass by the mask +// (inclusive) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_BITS _u(0x000003e0) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_MSB _u(9) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_LSB _u(5) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_SHIFT +// Description : Logical right-shift applied to accumulator before masking +#define SIO_INTERP0_CTRL_LANE1_SHIFT_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE1_SHIFT_BITS _u(0x0000001f) +#define SIO_INTERP0_CTRL_LANE1_SHIFT_MSB _u(4) +#define SIO_INTERP0_CTRL_LANE1_SHIFT_LSB _u(0) +#define SIO_INTERP0_CTRL_LANE1_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_ACCUM0_ADD +// Description : Values written here are atomically added to ACCUM0 +// Reading yields lane 0's raw shift and mask value (BASE0 not +// added). +#define SIO_INTERP0_ACCUM0_ADD_OFFSET _u(0x000000b4) +#define SIO_INTERP0_ACCUM0_ADD_BITS _u(0x00ffffff) +#define SIO_INTERP0_ACCUM0_ADD_RESET _u(0x00000000) +#define SIO_INTERP0_ACCUM0_ADD_MSB _u(23) +#define SIO_INTERP0_ACCUM0_ADD_LSB _u(0) +#define SIO_INTERP0_ACCUM0_ADD_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_ACCUM1_ADD +// Description : Values written here are atomically added to ACCUM1 +// Reading yields lane 1's raw shift and mask value (BASE1 not +// added). +#define SIO_INTERP0_ACCUM1_ADD_OFFSET _u(0x000000b8) +#define SIO_INTERP0_ACCUM1_ADD_BITS _u(0x00ffffff) +#define SIO_INTERP0_ACCUM1_ADD_RESET _u(0x00000000) +#define SIO_INTERP0_ACCUM1_ADD_MSB _u(23) +#define SIO_INTERP0_ACCUM1_ADD_LSB _u(0) +#define SIO_INTERP0_ACCUM1_ADD_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_BASE_1AND0 +// Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1 +// simultaneously. +// Each half is sign-extended to 32 bits if that lane's SIGNED +// flag is set. +#define SIO_INTERP0_BASE_1AND0_OFFSET _u(0x000000bc) +#define SIO_INTERP0_BASE_1AND0_BITS _u(0xffffffff) +#define SIO_INTERP0_BASE_1AND0_RESET _u(0x00000000) +#define SIO_INTERP0_BASE_1AND0_MSB _u(31) +#define SIO_INTERP0_BASE_1AND0_LSB _u(0) +#define SIO_INTERP0_BASE_1AND0_ACCESS "WO" +// ============================================================================= +// Register : SIO_INTERP1_ACCUM0 +// Description : Read/write access to accumulator 0 +#define SIO_INTERP1_ACCUM0_OFFSET _u(0x000000c0) +#define SIO_INTERP1_ACCUM0_BITS _u(0xffffffff) +#define SIO_INTERP1_ACCUM0_RESET _u(0x00000000) +#define SIO_INTERP1_ACCUM0_MSB _u(31) +#define SIO_INTERP1_ACCUM0_LSB _u(0) +#define SIO_INTERP1_ACCUM0_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_ACCUM1 +// Description : Read/write access to accumulator 1 +#define SIO_INTERP1_ACCUM1_OFFSET _u(0x000000c4) +#define SIO_INTERP1_ACCUM1_BITS _u(0xffffffff) +#define SIO_INTERP1_ACCUM1_RESET _u(0x00000000) +#define SIO_INTERP1_ACCUM1_MSB _u(31) +#define SIO_INTERP1_ACCUM1_LSB _u(0) +#define SIO_INTERP1_ACCUM1_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_BASE0 +// Description : Read/write access to BASE0 register. +#define SIO_INTERP1_BASE0_OFFSET _u(0x000000c8) +#define SIO_INTERP1_BASE0_BITS _u(0xffffffff) +#define SIO_INTERP1_BASE0_RESET _u(0x00000000) +#define SIO_INTERP1_BASE0_MSB _u(31) +#define SIO_INTERP1_BASE0_LSB _u(0) +#define SIO_INTERP1_BASE0_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_BASE1 +// Description : Read/write access to BASE1 register. +#define SIO_INTERP1_BASE1_OFFSET _u(0x000000cc) +#define SIO_INTERP1_BASE1_BITS _u(0xffffffff) +#define SIO_INTERP1_BASE1_RESET _u(0x00000000) +#define SIO_INTERP1_BASE1_MSB _u(31) +#define SIO_INTERP1_BASE1_LSB _u(0) +#define SIO_INTERP1_BASE1_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_BASE2 +// Description : Read/write access to BASE2 register. +#define SIO_INTERP1_BASE2_OFFSET _u(0x000000d0) +#define SIO_INTERP1_BASE2_BITS _u(0xffffffff) +#define SIO_INTERP1_BASE2_RESET _u(0x00000000) +#define SIO_INTERP1_BASE2_MSB _u(31) +#define SIO_INTERP1_BASE2_LSB _u(0) +#define SIO_INTERP1_BASE2_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_POP_LANE0 +// Description : Read LANE0 result, and simultaneously write lane results to +// both accumulators (POP). +#define SIO_INTERP1_POP_LANE0_OFFSET _u(0x000000d4) +#define SIO_INTERP1_POP_LANE0_BITS _u(0xffffffff) +#define SIO_INTERP1_POP_LANE0_RESET _u(0x00000000) +#define SIO_INTERP1_POP_LANE0_MSB _u(31) +#define SIO_INTERP1_POP_LANE0_LSB _u(0) +#define SIO_INTERP1_POP_LANE0_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_POP_LANE1 +// Description : Read LANE1 result, and simultaneously write lane results to +// both accumulators (POP). +#define SIO_INTERP1_POP_LANE1_OFFSET _u(0x000000d8) +#define SIO_INTERP1_POP_LANE1_BITS _u(0xffffffff) +#define SIO_INTERP1_POP_LANE1_RESET _u(0x00000000) +#define SIO_INTERP1_POP_LANE1_MSB _u(31) +#define SIO_INTERP1_POP_LANE1_LSB _u(0) +#define SIO_INTERP1_POP_LANE1_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_POP_FULL +// Description : Read FULL result, and simultaneously write lane results to both +// accumulators (POP). +#define SIO_INTERP1_POP_FULL_OFFSET _u(0x000000dc) +#define SIO_INTERP1_POP_FULL_BITS _u(0xffffffff) +#define SIO_INTERP1_POP_FULL_RESET _u(0x00000000) +#define SIO_INTERP1_POP_FULL_MSB _u(31) +#define SIO_INTERP1_POP_FULL_LSB _u(0) +#define SIO_INTERP1_POP_FULL_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_PEEK_LANE0 +// Description : Read LANE0 result, without altering any internal state (PEEK). +#define SIO_INTERP1_PEEK_LANE0_OFFSET _u(0x000000e0) +#define SIO_INTERP1_PEEK_LANE0_BITS _u(0xffffffff) +#define SIO_INTERP1_PEEK_LANE0_RESET _u(0x00000000) +#define SIO_INTERP1_PEEK_LANE0_MSB _u(31) +#define SIO_INTERP1_PEEK_LANE0_LSB _u(0) +#define SIO_INTERP1_PEEK_LANE0_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_PEEK_LANE1 +// Description : Read LANE1 result, without altering any internal state (PEEK). +#define SIO_INTERP1_PEEK_LANE1_OFFSET _u(0x000000e4) +#define SIO_INTERP1_PEEK_LANE1_BITS _u(0xffffffff) +#define SIO_INTERP1_PEEK_LANE1_RESET _u(0x00000000) +#define SIO_INTERP1_PEEK_LANE1_MSB _u(31) +#define SIO_INTERP1_PEEK_LANE1_LSB _u(0) +#define SIO_INTERP1_PEEK_LANE1_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_PEEK_FULL +// Description : Read FULL result, without altering any internal state (PEEK). +#define SIO_INTERP1_PEEK_FULL_OFFSET _u(0x000000e8) +#define SIO_INTERP1_PEEK_FULL_BITS _u(0xffffffff) +#define SIO_INTERP1_PEEK_FULL_RESET _u(0x00000000) +#define SIO_INTERP1_PEEK_FULL_MSB _u(31) +#define SIO_INTERP1_PEEK_FULL_LSB _u(0) +#define SIO_INTERP1_PEEK_FULL_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_CTRL_LANE0 +// Description : Control register for lane 0 +#define SIO_INTERP1_CTRL_LANE0_OFFSET _u(0x000000ec) +#define SIO_INTERP1_CTRL_LANE0_BITS _u(0x03dfffff) +#define SIO_INTERP1_CTRL_LANE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_OVERF +// Description : Set if either OVERF0 or OVERF1 is set. +#define SIO_INTERP1_CTRL_LANE0_OVERF_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_OVERF_BITS _u(0x02000000) +#define SIO_INTERP1_CTRL_LANE0_OVERF_MSB _u(25) +#define SIO_INTERP1_CTRL_LANE0_OVERF_LSB _u(25) +#define SIO_INTERP1_CTRL_LANE0_OVERF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_OVERF1 +// Description : Indicates if any masked-off MSBs in ACCUM1 are set. +#define SIO_INTERP1_CTRL_LANE0_OVERF1_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_OVERF1_BITS _u(0x01000000) +#define SIO_INTERP1_CTRL_LANE0_OVERF1_MSB _u(24) +#define SIO_INTERP1_CTRL_LANE0_OVERF1_LSB _u(24) +#define SIO_INTERP1_CTRL_LANE0_OVERF1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_OVERF0 +// Description : Indicates if any masked-off MSBs in ACCUM0 are set. +#define SIO_INTERP1_CTRL_LANE0_OVERF0_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_OVERF0_BITS _u(0x00800000) +#define SIO_INTERP1_CTRL_LANE0_OVERF0_MSB _u(23) +#define SIO_INTERP1_CTRL_LANE0_OVERF0_LSB _u(23) +#define SIO_INTERP1_CTRL_LANE0_OVERF0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_CLAMP +// Description : Only present on INTERP1 on each core. If CLAMP mode is enabled: +// - LANE0 result is shifted and masked ACCUM0, clamped by a lower +// bound of +// BASE0 and an upper bound of BASE1. +// - Signedness of these comparisons is determined by +// LANE0_CTRL_SIGNED +#define SIO_INTERP1_CTRL_LANE0_CLAMP_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_CLAMP_BITS _u(0x00400000) +#define SIO_INTERP1_CTRL_LANE0_CLAMP_MSB _u(22) +#define SIO_INTERP1_CTRL_LANE0_CLAMP_LSB _u(22) +#define SIO_INTERP1_CTRL_LANE0_CLAMP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_FORCE_MSB +// Description : ORed into bits 29:28 of the lane result presented to the +// processor on the bus. +// No effect on the internal 32-bit datapath. Handy for using a +// lane to generate sequence +// of pointers into flash or SRAM. +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_BITS _u(0x00180000) +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MSB _u(20) +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_LSB _u(19) +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_ADD_RAW +// Description : If 1, mask + shift is bypassed for LANE0 result. This does not +// affect FULL result. +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_BITS _u(0x00040000) +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_MSB _u(18) +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_LSB _u(18) +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_CROSS_RESULT +// Description : If 1, feed the opposite lane's result into this lane's +// accumulator on POP. +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_BITS _u(0x00020000) +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_MSB _u(17) +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_LSB _u(17) +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_CROSS_INPUT +// Description : If 1, feed the opposite lane's accumulator into this lane's +// shift + mask hardware. +// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is +// before the shift+mask bypass) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_BITS _u(0x00010000) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_MSB _u(16) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_LSB _u(16) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_SIGNED +// Description : If SIGNED is set, the shifted and masked accumulator value is +// sign-extended to 32 bits +// before adding to BASE0, and LANE0 PEEK/POP appear extended to +// 32 bits when read by processor. +#define SIO_INTERP1_CTRL_LANE0_SIGNED_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_SIGNED_BITS _u(0x00008000) +#define SIO_INTERP1_CTRL_LANE0_SIGNED_MSB _u(15) +#define SIO_INTERP1_CTRL_LANE0_SIGNED_LSB _u(15) +#define SIO_INTERP1_CTRL_LANE0_SIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_MASK_MSB +// Description : The most-significant bit allowed to pass by the mask +// (inclusive) +// Setting MSB < LSB may cause chip to turn inside-out +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_BITS _u(0x00007c00) +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_MSB _u(14) +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_LSB _u(10) +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_MASK_LSB +// Description : The least-significant bit allowed to pass by the mask +// (inclusive) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_BITS _u(0x000003e0) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_MSB _u(9) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_LSB _u(5) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_SHIFT +// Description : Logical right-shift applied to accumulator before masking +#define SIO_INTERP1_CTRL_LANE0_SHIFT_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE0_SHIFT_BITS _u(0x0000001f) +#define SIO_INTERP1_CTRL_LANE0_SHIFT_MSB _u(4) +#define SIO_INTERP1_CTRL_LANE0_SHIFT_LSB _u(0) +#define SIO_INTERP1_CTRL_LANE0_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_CTRL_LANE1 +// Description : Control register for lane 1 +#define SIO_INTERP1_CTRL_LANE1_OFFSET _u(0x000000f0) +#define SIO_INTERP1_CTRL_LANE1_BITS _u(0x001fffff) +#define SIO_INTERP1_CTRL_LANE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_FORCE_MSB +// Description : ORed into bits 29:28 of the lane result presented to the +// processor on the bus. +// No effect on the internal 32-bit datapath. Handy for using a +// lane to generate sequence +// of pointers into flash or SRAM. +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_BITS _u(0x00180000) +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MSB _u(20) +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_LSB _u(19) +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_ADD_RAW +// Description : If 1, mask + shift is bypassed for LANE1 result. This does not +// affect FULL result. +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_BITS _u(0x00040000) +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_MSB _u(18) +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_LSB _u(18) +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_CROSS_RESULT +// Description : If 1, feed the opposite lane's result into this lane's +// accumulator on POP. +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_BITS _u(0x00020000) +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_MSB _u(17) +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_LSB _u(17) +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_CROSS_INPUT +// Description : If 1, feed the opposite lane's accumulator into this lane's +// shift + mask hardware. +// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is +// before the shift+mask bypass) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_BITS _u(0x00010000) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_MSB _u(16) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_LSB _u(16) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_SIGNED +// Description : If SIGNED is set, the shifted and masked accumulator value is +// sign-extended to 32 bits +// before adding to BASE1, and LANE1 PEEK/POP appear extended to +// 32 bits when read by processor. +#define SIO_INTERP1_CTRL_LANE1_SIGNED_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_SIGNED_BITS _u(0x00008000) +#define SIO_INTERP1_CTRL_LANE1_SIGNED_MSB _u(15) +#define SIO_INTERP1_CTRL_LANE1_SIGNED_LSB _u(15) +#define SIO_INTERP1_CTRL_LANE1_SIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_MASK_MSB +// Description : The most-significant bit allowed to pass by the mask +// (inclusive) +// Setting MSB < LSB may cause chip to turn inside-out +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_BITS _u(0x00007c00) +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_MSB _u(14) +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_LSB _u(10) +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_MASK_LSB +// Description : The least-significant bit allowed to pass by the mask +// (inclusive) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_BITS _u(0x000003e0) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_MSB _u(9) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_LSB _u(5) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_SHIFT +// Description : Logical right-shift applied to accumulator before masking +#define SIO_INTERP1_CTRL_LANE1_SHIFT_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE1_SHIFT_BITS _u(0x0000001f) +#define SIO_INTERP1_CTRL_LANE1_SHIFT_MSB _u(4) +#define SIO_INTERP1_CTRL_LANE1_SHIFT_LSB _u(0) +#define SIO_INTERP1_CTRL_LANE1_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_ACCUM0_ADD +// Description : Values written here are atomically added to ACCUM0 +// Reading yields lane 0's raw shift and mask value (BASE0 not +// added). +#define SIO_INTERP1_ACCUM0_ADD_OFFSET _u(0x000000f4) +#define SIO_INTERP1_ACCUM0_ADD_BITS _u(0x00ffffff) +#define SIO_INTERP1_ACCUM0_ADD_RESET _u(0x00000000) +#define SIO_INTERP1_ACCUM0_ADD_MSB _u(23) +#define SIO_INTERP1_ACCUM0_ADD_LSB _u(0) +#define SIO_INTERP1_ACCUM0_ADD_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_ACCUM1_ADD +// Description : Values written here are atomically added to ACCUM1 +// Reading yields lane 1's raw shift and mask value (BASE1 not +// added). +#define SIO_INTERP1_ACCUM1_ADD_OFFSET _u(0x000000f8) +#define SIO_INTERP1_ACCUM1_ADD_BITS _u(0x00ffffff) +#define SIO_INTERP1_ACCUM1_ADD_RESET _u(0x00000000) +#define SIO_INTERP1_ACCUM1_ADD_MSB _u(23) +#define SIO_INTERP1_ACCUM1_ADD_LSB _u(0) +#define SIO_INTERP1_ACCUM1_ADD_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_BASE_1AND0 +// Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1 +// simultaneously. +// Each half is sign-extended to 32 bits if that lane's SIGNED +// flag is set. +#define SIO_INTERP1_BASE_1AND0_OFFSET _u(0x000000fc) +#define SIO_INTERP1_BASE_1AND0_BITS _u(0xffffffff) +#define SIO_INTERP1_BASE_1AND0_RESET _u(0x00000000) +#define SIO_INTERP1_BASE_1AND0_MSB _u(31) +#define SIO_INTERP1_BASE_1AND0_LSB _u(0) +#define SIO_INTERP1_BASE_1AND0_ACCESS "WO" +// ============================================================================= +// Register : SIO_SPINLOCK0 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK0_OFFSET _u(0x00000100) +#define SIO_SPINLOCK0_BITS _u(0xffffffff) +#define SIO_SPINLOCK0_RESET _u(0x00000000) +#define SIO_SPINLOCK0_MSB _u(31) +#define SIO_SPINLOCK0_LSB _u(0) +#define SIO_SPINLOCK0_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK1 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK1_OFFSET _u(0x00000104) +#define SIO_SPINLOCK1_BITS _u(0xffffffff) +#define SIO_SPINLOCK1_RESET _u(0x00000000) +#define SIO_SPINLOCK1_MSB _u(31) +#define SIO_SPINLOCK1_LSB _u(0) +#define SIO_SPINLOCK1_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK2 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK2_OFFSET _u(0x00000108) +#define SIO_SPINLOCK2_BITS _u(0xffffffff) +#define SIO_SPINLOCK2_RESET _u(0x00000000) +#define SIO_SPINLOCK2_MSB _u(31) +#define SIO_SPINLOCK2_LSB _u(0) +#define SIO_SPINLOCK2_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK3 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK3_OFFSET _u(0x0000010c) +#define SIO_SPINLOCK3_BITS _u(0xffffffff) +#define SIO_SPINLOCK3_RESET _u(0x00000000) +#define SIO_SPINLOCK3_MSB _u(31) +#define SIO_SPINLOCK3_LSB _u(0) +#define SIO_SPINLOCK3_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK4 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK4_OFFSET _u(0x00000110) +#define SIO_SPINLOCK4_BITS _u(0xffffffff) +#define SIO_SPINLOCK4_RESET _u(0x00000000) +#define SIO_SPINLOCK4_MSB _u(31) +#define SIO_SPINLOCK4_LSB _u(0) +#define SIO_SPINLOCK4_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK5 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK5_OFFSET _u(0x00000114) +#define SIO_SPINLOCK5_BITS _u(0xffffffff) +#define SIO_SPINLOCK5_RESET _u(0x00000000) +#define SIO_SPINLOCK5_MSB _u(31) +#define SIO_SPINLOCK5_LSB _u(0) +#define SIO_SPINLOCK5_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK6 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK6_OFFSET _u(0x00000118) +#define SIO_SPINLOCK6_BITS _u(0xffffffff) +#define SIO_SPINLOCK6_RESET _u(0x00000000) +#define SIO_SPINLOCK6_MSB _u(31) +#define SIO_SPINLOCK6_LSB _u(0) +#define SIO_SPINLOCK6_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK7 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK7_OFFSET _u(0x0000011c) +#define SIO_SPINLOCK7_BITS _u(0xffffffff) +#define SIO_SPINLOCK7_RESET _u(0x00000000) +#define SIO_SPINLOCK7_MSB _u(31) +#define SIO_SPINLOCK7_LSB _u(0) +#define SIO_SPINLOCK7_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK8 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK8_OFFSET _u(0x00000120) +#define SIO_SPINLOCK8_BITS _u(0xffffffff) +#define SIO_SPINLOCK8_RESET _u(0x00000000) +#define SIO_SPINLOCK8_MSB _u(31) +#define SIO_SPINLOCK8_LSB _u(0) +#define SIO_SPINLOCK8_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK9 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK9_OFFSET _u(0x00000124) +#define SIO_SPINLOCK9_BITS _u(0xffffffff) +#define SIO_SPINLOCK9_RESET _u(0x00000000) +#define SIO_SPINLOCK9_MSB _u(31) +#define SIO_SPINLOCK9_LSB _u(0) +#define SIO_SPINLOCK9_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK10 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK10_OFFSET _u(0x00000128) +#define SIO_SPINLOCK10_BITS _u(0xffffffff) +#define SIO_SPINLOCK10_RESET _u(0x00000000) +#define SIO_SPINLOCK10_MSB _u(31) +#define SIO_SPINLOCK10_LSB _u(0) +#define SIO_SPINLOCK10_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK11 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK11_OFFSET _u(0x0000012c) +#define SIO_SPINLOCK11_BITS _u(0xffffffff) +#define SIO_SPINLOCK11_RESET _u(0x00000000) +#define SIO_SPINLOCK11_MSB _u(31) +#define SIO_SPINLOCK11_LSB _u(0) +#define SIO_SPINLOCK11_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK12 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK12_OFFSET _u(0x00000130) +#define SIO_SPINLOCK12_BITS _u(0xffffffff) +#define SIO_SPINLOCK12_RESET _u(0x00000000) +#define SIO_SPINLOCK12_MSB _u(31) +#define SIO_SPINLOCK12_LSB _u(0) +#define SIO_SPINLOCK12_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK13 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK13_OFFSET _u(0x00000134) +#define SIO_SPINLOCK13_BITS _u(0xffffffff) +#define SIO_SPINLOCK13_RESET _u(0x00000000) +#define SIO_SPINLOCK13_MSB _u(31) +#define SIO_SPINLOCK13_LSB _u(0) +#define SIO_SPINLOCK13_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK14 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK14_OFFSET _u(0x00000138) +#define SIO_SPINLOCK14_BITS _u(0xffffffff) +#define SIO_SPINLOCK14_RESET _u(0x00000000) +#define SIO_SPINLOCK14_MSB _u(31) +#define SIO_SPINLOCK14_LSB _u(0) +#define SIO_SPINLOCK14_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK15 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK15_OFFSET _u(0x0000013c) +#define SIO_SPINLOCK15_BITS _u(0xffffffff) +#define SIO_SPINLOCK15_RESET _u(0x00000000) +#define SIO_SPINLOCK15_MSB _u(31) +#define SIO_SPINLOCK15_LSB _u(0) +#define SIO_SPINLOCK15_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK16 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK16_OFFSET _u(0x00000140) +#define SIO_SPINLOCK16_BITS _u(0xffffffff) +#define SIO_SPINLOCK16_RESET _u(0x00000000) +#define SIO_SPINLOCK16_MSB _u(31) +#define SIO_SPINLOCK16_LSB _u(0) +#define SIO_SPINLOCK16_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK17 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK17_OFFSET _u(0x00000144) +#define SIO_SPINLOCK17_BITS _u(0xffffffff) +#define SIO_SPINLOCK17_RESET _u(0x00000000) +#define SIO_SPINLOCK17_MSB _u(31) +#define SIO_SPINLOCK17_LSB _u(0) +#define SIO_SPINLOCK17_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK18 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK18_OFFSET _u(0x00000148) +#define SIO_SPINLOCK18_BITS _u(0xffffffff) +#define SIO_SPINLOCK18_RESET _u(0x00000000) +#define SIO_SPINLOCK18_MSB _u(31) +#define SIO_SPINLOCK18_LSB _u(0) +#define SIO_SPINLOCK18_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK19 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK19_OFFSET _u(0x0000014c) +#define SIO_SPINLOCK19_BITS _u(0xffffffff) +#define SIO_SPINLOCK19_RESET _u(0x00000000) +#define SIO_SPINLOCK19_MSB _u(31) +#define SIO_SPINLOCK19_LSB _u(0) +#define SIO_SPINLOCK19_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK20 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK20_OFFSET _u(0x00000150) +#define SIO_SPINLOCK20_BITS _u(0xffffffff) +#define SIO_SPINLOCK20_RESET _u(0x00000000) +#define SIO_SPINLOCK20_MSB _u(31) +#define SIO_SPINLOCK20_LSB _u(0) +#define SIO_SPINLOCK20_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK21 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK21_OFFSET _u(0x00000154) +#define SIO_SPINLOCK21_BITS _u(0xffffffff) +#define SIO_SPINLOCK21_RESET _u(0x00000000) +#define SIO_SPINLOCK21_MSB _u(31) +#define SIO_SPINLOCK21_LSB _u(0) +#define SIO_SPINLOCK21_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK22 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK22_OFFSET _u(0x00000158) +#define SIO_SPINLOCK22_BITS _u(0xffffffff) +#define SIO_SPINLOCK22_RESET _u(0x00000000) +#define SIO_SPINLOCK22_MSB _u(31) +#define SIO_SPINLOCK22_LSB _u(0) +#define SIO_SPINLOCK22_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK23 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK23_OFFSET _u(0x0000015c) +#define SIO_SPINLOCK23_BITS _u(0xffffffff) +#define SIO_SPINLOCK23_RESET _u(0x00000000) +#define SIO_SPINLOCK23_MSB _u(31) +#define SIO_SPINLOCK23_LSB _u(0) +#define SIO_SPINLOCK23_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK24 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK24_OFFSET _u(0x00000160) +#define SIO_SPINLOCK24_BITS _u(0xffffffff) +#define SIO_SPINLOCK24_RESET _u(0x00000000) +#define SIO_SPINLOCK24_MSB _u(31) +#define SIO_SPINLOCK24_LSB _u(0) +#define SIO_SPINLOCK24_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK25 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK25_OFFSET _u(0x00000164) +#define SIO_SPINLOCK25_BITS _u(0xffffffff) +#define SIO_SPINLOCK25_RESET _u(0x00000000) +#define SIO_SPINLOCK25_MSB _u(31) +#define SIO_SPINLOCK25_LSB _u(0) +#define SIO_SPINLOCK25_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK26 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK26_OFFSET _u(0x00000168) +#define SIO_SPINLOCK26_BITS _u(0xffffffff) +#define SIO_SPINLOCK26_RESET _u(0x00000000) +#define SIO_SPINLOCK26_MSB _u(31) +#define SIO_SPINLOCK26_LSB _u(0) +#define SIO_SPINLOCK26_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK27 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK27_OFFSET _u(0x0000016c) +#define SIO_SPINLOCK27_BITS _u(0xffffffff) +#define SIO_SPINLOCK27_RESET _u(0x00000000) +#define SIO_SPINLOCK27_MSB _u(31) +#define SIO_SPINLOCK27_LSB _u(0) +#define SIO_SPINLOCK27_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK28 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK28_OFFSET _u(0x00000170) +#define SIO_SPINLOCK28_BITS _u(0xffffffff) +#define SIO_SPINLOCK28_RESET _u(0x00000000) +#define SIO_SPINLOCK28_MSB _u(31) +#define SIO_SPINLOCK28_LSB _u(0) +#define SIO_SPINLOCK28_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK29 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK29_OFFSET _u(0x00000174) +#define SIO_SPINLOCK29_BITS _u(0xffffffff) +#define SIO_SPINLOCK29_RESET _u(0x00000000) +#define SIO_SPINLOCK29_MSB _u(31) +#define SIO_SPINLOCK29_LSB _u(0) +#define SIO_SPINLOCK29_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK30 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK30_OFFSET _u(0x00000178) +#define SIO_SPINLOCK30_BITS _u(0xffffffff) +#define SIO_SPINLOCK30_RESET _u(0x00000000) +#define SIO_SPINLOCK30_MSB _u(31) +#define SIO_SPINLOCK30_LSB _u(0) +#define SIO_SPINLOCK30_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK31 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK31_OFFSET _u(0x0000017c) +#define SIO_SPINLOCK31_BITS _u(0xffffffff) +#define SIO_SPINLOCK31_RESET _u(0x00000000) +#define SIO_SPINLOCK31_MSB _u(31) +#define SIO_SPINLOCK31_LSB _u(0) +#define SIO_SPINLOCK31_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_SIO_H \ No newline at end of file diff --git a/modules/freertos/picosdk/include_rp2040/hardware/structs/clocks.h b/modules/freertos/picosdk/include_rp2040/hardware/structs/clocks.h new file mode 100644 index 000000000..b19305b03 --- /dev/null +++ b/modules/freertos/picosdk/include_rp2040/hardware/structs/clocks.h @@ -0,0 +1,18 @@ +#ifndef _HARDWARE_STRUCTS_CLOCKS_H +#define _HARDWARE_STRUCTS_CLOCKS_H + +typedef enum clock_num_rp2040 { + clk_gpout0 = 0, ///< Select CLK_GPOUT0 as clock source + clk_gpout1 = 1, ///< Select CLK_GPOUT1 as clock source + clk_gpout2 = 2, ///< Select CLK_GPOUT2 as clock source + clk_gpout3 = 3, ///< Select CLK_GPOUT3 as clock source + clk_ref = 4, ///< Select CLK_REF as clock source + clk_sys = 5, ///< Select CLK_SYS as clock source + clk_peri = 6, ///< Select CLK_PERI as clock source + clk_usb = 7, ///< Select CLK_USB as clock source + clk_adc = 8, ///< Select CLK_ADC as clock source + clk_rtc = 9, ///< Select CLK_RTC as clock source + CLK_COUNT +} clock_num_t; + +#endif // _HARDWARE_STRUCTS_CLOCKS_H \ No newline at end of file diff --git a/modules/freertos/picosdk/include_rp2040/hardware/structs/interp.h b/modules/freertos/picosdk/include_rp2040/hardware/structs/interp.h new file mode 100644 index 000000000..db6ff5177 --- /dev/null +++ b/modules/freertos/picosdk/include_rp2040/hardware/structs/interp.h @@ -0,0 +1,85 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_INTERP_H +#define _HARDWARE_STRUCTS_INTERP_H + +/** + * \file rp2040/interp.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sio.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + // (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0 + // Read/write access to accumulator 0 + // 0xffffffff [31:0] INTERP0_ACCUM0 (0x00000000) + io_rw_32 accum[2]; + + // (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0 + // Read/write access to BASE0 register + // 0xffffffff [31:0] INTERP0_BASE0 (0x00000000) + io_rw_32 base[3]; + + // (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0 + // Read LANE0 result, and simultaneously write lane results to both accumulators (POP) + // 0xffffffff [31:0] INTERP0_POP_LANE0 (0x00000000) + io_ro_32 pop[3]; + + // (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0 + // Read LANE0 result, without altering any internal state (PEEK) + // 0xffffffff [31:0] INTERP0_PEEK_LANE0 (0x00000000) + io_ro_32 peek[3]; + + // (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0 + // Control register for lane 0 + // 0x02000000 [25] OVERF (0) Set if either OVERF0 or OVERF1 is set + // 0x01000000 [24] OVERF1 (0) Indicates if any masked-off MSBs in ACCUM1 are set + // 0x00800000 [23] OVERF0 (0) Indicates if any masked-off MSBs in ACCUM0 are set + // 0x00200000 [21] BLEND (0) Only present on INTERP0 on each core + // 0x00180000 [20:19] FORCE_MSB (0x0) ORed into bits 29:28 of the lane result presented to the... + // 0x00040000 [18] ADD_RAW (0) If 1, mask + shift is bypassed for LANE0 result + // 0x00020000 [17] CROSS_RESULT (0) If 1, feed the opposite lane's result into this lane's... + // 0x00010000 [16] CROSS_INPUT (0) If 1, feed the opposite lane's accumulator into this... + // 0x00008000 [15] SIGNED (0) If SIGNED is set, the shifted and masked accumulator... + // 0x00007c00 [14:10] MASK_MSB (0x00) The most-significant bit allowed to pass by the mask... + // 0x000003e0 [9:5] MASK_LSB (0x00) The least-significant bit allowed to pass by the mask (inclusive) + // 0x0000001f [4:0] SHIFT (0x00) Logical right-shift applied to accumulator before masking + io_rw_32 ctrl[2]; + + // (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes) + _REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD + // Values written here are atomically added to ACCUM0 + // 0x00ffffff [23:0] INTERP0_ACCUM0_ADD (0x000000) + io_rw_32 add_raw[2]; + + _REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0 + // On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + // 0xffffffff [31:0] INTERP0_BASE_1AND0 (0x00000000) + io_wo_32 base01; +} interp_hw_t; + +#define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET)) +static_assert(sizeof (interp_hw_t) == 0x0040, ""); +#define interp0_hw (&interp_hw_array[0]) +#define interp1_hw (&interp_hw_array[1]) + +#endif // _HARDWARE_STRUCTS_INTERP_H \ No newline at end of file diff --git a/modules/freertos/picosdk/include_rp2040/hardware/structs/sio.h b/modules/freertos/picosdk/include_rp2040/hardware/structs/sio.h new file mode 100644 index 000000000..a809b2669 --- /dev/null +++ b/modules/freertos/picosdk/include_rp2040/hardware/structs/sio.h @@ -0,0 +1,199 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SIO_H +#define _HARDWARE_STRUCTS_SIO_H + +/** + * \file rp2040/sio.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sio.h" +#include "hardware/structs/interp.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + + +typedef struct { + _REG_(SIO_CPUID_OFFSET) // SIO_CPUID + // Processor core identifier + // 0xffffffff [31:0] CPUID (-) Value is 0 when read from processor core 0, and 1 when... + io_ro_32 cpuid; + + _REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN + // Input value for GPIO pins + // 0x3fffffff [29:0] GPIO_IN (0x00000000) Input value for GPIO0 + io_ro_32 gpio_in; + + _REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN + // Input value for QSPI pins + // 0x0000003f [5:0] GPIO_HI_IN (0x00) Input value on QSPI IO in order 0 + io_ro_32 gpio_hi_in; + + uint32_t _pad0; + + _REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT + // GPIO output value + // 0x3fffffff [29:0] GPIO_OUT (0x00000000) Set output level (1/0 -> high/low) for GPIO0 + io_rw_32 gpio_out; + + _REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET + // GPIO output value set + // 0x3fffffff [29:0] GPIO_OUT_SET (0x00000000) Perform an atomic bit-set on GPIO_OUT, i + io_wo_32 gpio_set; + + _REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR + // GPIO output value clear + // 0x3fffffff [29:0] GPIO_OUT_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OUT, i + io_wo_32 gpio_clr; + + _REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR + // GPIO output value XOR + // 0x3fffffff [29:0] GPIO_OUT_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OUT, i + io_wo_32 gpio_togl; + + _REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE + // GPIO output enable + // 0x3fffffff [29:0] GPIO_OE (0x00000000) Set output enable (1/0 -> output/input) for GPIO0 + io_rw_32 gpio_oe; + + _REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET + // GPIO output enable set + // 0x3fffffff [29:0] GPIO_OE_SET (0x00000000) Perform an atomic bit-set on GPIO_OE, i + io_wo_32 gpio_oe_set; + + _REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR + // GPIO output enable clear + // 0x3fffffff [29:0] GPIO_OE_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OE, i + io_wo_32 gpio_oe_clr; + + _REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR + // GPIO output enable XOR + // 0x3fffffff [29:0] GPIO_OE_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OE, i + io_wo_32 gpio_oe_togl; + + _REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT + // QSPI output value + // 0x0000003f [5:0] GPIO_HI_OUT (0x00) Set output level (1/0 -> high/low) for QSPI IO0 + io_rw_32 gpio_hi_out; + + _REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET + // QSPI output value set + // 0x0000003f [5:0] GPIO_HI_OUT_SET (0x00) Perform an atomic bit-set on GPIO_HI_OUT, i + io_wo_32 gpio_hi_set; + + _REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR + // QSPI output value clear + // 0x0000003f [5:0] GPIO_HI_OUT_CLR (0x00) Perform an atomic bit-clear on GPIO_HI_OUT, i + io_wo_32 gpio_hi_clr; + + _REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR + // QSPI output value XOR + // 0x0000003f [5:0] GPIO_HI_OUT_XOR (0x00) Perform an atomic bitwise XOR on GPIO_HI_OUT, i + io_wo_32 gpio_hi_togl; + + _REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE + // QSPI output enable + // 0x0000003f [5:0] GPIO_HI_OE (0x00) Set output enable (1/0 -> output/input) for QSPI IO0 + io_rw_32 gpio_hi_oe; + + _REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET + // QSPI output enable set + // 0x0000003f [5:0] GPIO_HI_OE_SET (0x00) Perform an atomic bit-set on GPIO_HI_OE, i + io_wo_32 gpio_hi_oe_set; + + _REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR + // QSPI output enable clear + // 0x0000003f [5:0] GPIO_HI_OE_CLR (0x00) Perform an atomic bit-clear on GPIO_HI_OE, i + io_wo_32 gpio_hi_oe_clr; + + _REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR + // QSPI output enable XOR + // 0x0000003f [5:0] GPIO_HI_OE_XOR (0x00) Perform an atomic bitwise XOR on GPIO_HI_OE, i + io_wo_32 gpio_hi_oe_togl; + + _REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST + // Status register for inter-core FIFOs (mailboxes). + // 0x00000008 [3] ROE (0) Sticky flag indicating the RX FIFO was read when empty + // 0x00000004 [2] WOF (0) Sticky flag indicating the TX FIFO was written when full + // 0x00000002 [1] RDY (1) Value is 1 if this core's TX FIFO is not full (i + // 0x00000001 [0] VLD (0) Value is 1 if this core's RX FIFO is not empty (i + io_rw_32 fifo_st; + + _REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR + // Write access to this core's TX FIFO + // 0xffffffff [31:0] FIFO_WR (0x00000000) + io_wo_32 fifo_wr; + + _REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD + // Read access to this core's RX FIFO + // 0xffffffff [31:0] FIFO_RD (-) + io_ro_32 fifo_rd; + + _REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST + // Spinlock state + // 0xffffffff [31:0] SPINLOCK_ST (0x00000000) + io_ro_32 spinlock_st; + + _REG_(SIO_DIV_UDIVIDEND_OFFSET) // SIO_DIV_UDIVIDEND + // Divider unsigned dividend + // 0xffffffff [31:0] DIV_UDIVIDEND (0x00000000) + io_rw_32 div_udividend; + + _REG_(SIO_DIV_UDIVISOR_OFFSET) // SIO_DIV_UDIVISOR + // Divider unsigned divisor + // 0xffffffff [31:0] DIV_UDIVISOR (0x00000000) + io_rw_32 div_udivisor; + + _REG_(SIO_DIV_SDIVIDEND_OFFSET) // SIO_DIV_SDIVIDEND + // Divider signed dividend + // 0xffffffff [31:0] DIV_SDIVIDEND (0x00000000) + io_rw_32 div_sdividend; + + _REG_(SIO_DIV_SDIVISOR_OFFSET) // SIO_DIV_SDIVISOR + // Divider signed divisor + // 0xffffffff [31:0] DIV_SDIVISOR (0x00000000) + io_rw_32 div_sdivisor; + + _REG_(SIO_DIV_QUOTIENT_OFFSET) // SIO_DIV_QUOTIENT + // Divider result quotient + // 0xffffffff [31:0] DIV_QUOTIENT (0x00000000) + io_rw_32 div_quotient; + + _REG_(SIO_DIV_REMAINDER_OFFSET) // SIO_DIV_REMAINDER + // Divider result remainder + // 0xffffffff [31:0] DIV_REMAINDER (0x00000000) + io_rw_32 div_remainder; + + _REG_(SIO_DIV_CSR_OFFSET) // SIO_DIV_CSR + // Control and status register for divider + // 0x00000002 [1] DIRTY (0) Changes to 1 when any register is written, and back to 0... + // 0x00000001 [0] READY (1) Reads as 0 when a calculation is in progress, 1 otherwise + io_ro_32 div_csr; + + uint32_t _pad1; + + interp_hw_t interp[2]; + + // (Description copied from array index 0 register SIO_SPINLOCK0 applies similarly to other array indexes) + _REG_(SIO_SPINLOCK0_OFFSET) // SIO_SPINLOCK0 + // Spinlock register 0 + // 0xffffffff [31:0] SPINLOCK0 (0x00000000) + io_rw_32 spinlock[32]; +} sio_hw_t; + +#define sio_hw ((sio_hw_t *)SIO_BASE) +static_assert(sizeof (sio_hw_t) == 0x0180, ""); + +#endif // _HARDWARE_STRUCTS_SIO_H \ No newline at end of file diff --git a/modules/freertos/picosdk/include_rp2040/pico/platform.h b/modules/freertos/picosdk/include_rp2040/pico/platform.h new file mode 100644 index 000000000..a013bb8ad --- /dev/null +++ b/modules/freertos/picosdk/include_rp2040/pico/platform.h @@ -0,0 +1,21 @@ +#ifndef _PICO_PLATFORM_H +#define _PICO_PLATFORM_H + +#include "pico/platform/compiler.h" +#include "pico/platform/common.h" +#include "hardware/regs/addressmap.h" +#include "hardware/regs/sio.h" + +__force_inline static uint get_core_num(void) { + return (*(uint32_t *) (SIO_BASE + SIO_CPUID_OFFSET)); +} + +void __attribute__((noreturn)) panic_unsupported(void); + +static __force_inline uint __get_current_exception(void) { + uint exception; + pico_default_asm_volatile ( "mrs %0, ipsr" : "=l" (exception)); + return exception; +} + +#endif \ No newline at end of file diff --git a/modules/freertos/src/root.zig b/modules/freertos/src/root.zig new file mode 100644 index 000000000..71d37eebc --- /dev/null +++ b/modules/freertos/src/root.zig @@ -0,0 +1,50 @@ +const std = @import("std"); + +pub const c = @cImport({ + @cInclude("FreeRTOS.h"); + @cInclude("task.h"); +}); + +// Used when PICO_NO_RAM_VECTOR_TABLE is 1 (but don't work - VTOR is not set to 0x10000100 during boot) +// pub const microzig_options = microzig.Options{ +// .overwrite_hal_interrupts = true, +// .interrupts = .{ .PendSV = .{ .naked = freertos.isr_pendsv }, .SysTick = .{ .c = freertos.isr_systick }, .SVCall = .{ .c = freertos.isr_svcall } }, +// .cpu = .{ +// .ram_vector_table = false, +// }, +//}; +pub extern fn isr_pendsv() callconv(.naked) void; +pub extern fn isr_svcall() callconv(.c) void; +pub extern fn isr_systick() callconv(.c) void; + +pub const OS = struct { + pub const MINIMAL_STACK_SIZE: usize = c.configMINIMAL_STACK_SIZE; + pub const MAX_PRIORITIES: usize = c.configMAX_PRIORITIES; + + pub fn vTaskStartScheduler() noreturn { + c.vTaskStartScheduler(); + unreachable; + } + + pub fn vTaskDelay(ticks: c.TickType_t) void { + c.vTaskDelay(ticks); + } + + pub fn xTaskCreate( + task_function: c.TaskFunction_t, + name: [*:0]const u8, + stack_depth: u16, + parameters: ?*anyopaque, + priority: u32, + task_handle: ?*c.TaskHandle_t, + ) c.BaseType_t { + return c.xTaskCreate( + task_function, + name, + stack_depth, + parameters, + priority, + task_handle, + ); + } +}; From da38460a5445a10749e3b9d920a049bba039fc73 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Arkadiusz=20W=C3=B3jcik?= Date: Mon, 19 Jan 2026 17:23:44 +0100 Subject: [PATCH 2/5] final bits --- examples/raspberrypi/rp2xxx/build.zig | 2 +- modules/freertos/build.zig | 6 ++---- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/examples/raspberrypi/rp2xxx/build.zig b/examples/raspberrypi/rp2xxx/build.zig index 248c8a2b7..df7445391 100644 --- a/examples/raspberrypi/rp2xxx/build.zig +++ b/examples/raspberrypi/rp2xxx/build.zig @@ -25,7 +25,7 @@ pub fn build(b: *std.Build) void { .{ .target = raspberrypi.pico, .name = "pico_hd44780", .file = "src/rp2040_only/hd44780.zig" }, .{ .target = raspberrypi.pico, .name = "pico_pcf8574", .file = "src/rp2040_only/pcf8574.zig" }, .{ .target = raspberrypi.pico, .name = "pico_i2c_slave", .file = "src/rp2040_only/i2c_slave.zig" }, - .{ .target = raspberrypi.pico, .name = "pico_freertos-hello", .file = "src/freertos/hello_task.zig" }, + .{ .target = raspberrypi.pico, .name = "pico_freertos-hello-task", .file = "src/freertos/hello_task.zig" }, .{ .target = raspberrypi.pico2_arm, .name = "pico2_arm_multicore", .file = "src/blinky_core1.zig" }, .{ .target = raspberrypi.pico2_arm, .name = "pico2_arm_board_blinky", .file = "src/board_blinky.zig" }, diff --git a/modules/freertos/build.zig b/modules/freertos/build.zig index 367d41d5a..8d1f7369e 100644 --- a/modules/freertos/build.zig +++ b/modules/freertos/build.zig @@ -67,11 +67,9 @@ pub fn build(b: *std.Build) void { freertos_lib.addCMacro("configSMP_SPINLOCK_1", "PICO_SPINLOCK_ID_OS2"); freertos_lib.addCMacro("LIB_PICO_MULTICORE", "0"); - // Set this because otherwise we have to implment exception_set_exclusive_handler (for now we don't use it) - freertos_lib.addCMacro("PICO_NO_RAM_VECTOR_TABLE", "0"); - // Should be defined in change in FreeRTOSConfig.h - //freertos_lib.addCMacro("configNUMBER_OF_CORES", "1"); + // Had problems when this was enabled. Microzig but also Pico SDK? dont set VTOR to 0x10000100 for RP2040 at boot even when ram_vector_table is set to false + freertos_lib.addCMacro("PICO_NO_RAM_VECTOR_TABLE", "0"); const mod = b.addModule("freertos", .{ .root_source_file = b.path("src/root.zig"), .target = target, .optimize = optimize }); mod.addImport("freertos_lib", freertos_lib); From 6ee60015d8fcb2377f432d3a7bd88bf027eb491d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Arkadiusz=20W=C3=B3jcik?= Date: Tue, 20 Jan 2026 19:28:12 +0100 Subject: [PATCH 3/5] formatting changes after code review --- examples/raspberrypi/rp2xxx/build.zig | 3 ++- examples/raspberrypi/rp2xxx/src/freertos/hello_task.zig | 6 ++---- modules/freertos/build.zig.zon | 9 +-------- 3 files changed, 5 insertions(+), 13 deletions(-) diff --git a/examples/raspberrypi/rp2xxx/build.zig b/examples/raspberrypi/rp2xxx/build.zig index df7445391..1d6df32dc 100644 --- a/examples/raspberrypi/rp2xxx/build.zig +++ b/examples/raspberrypi/rp2xxx/build.zig @@ -161,7 +161,8 @@ pub fn build(b: *std.Build) void { firmware.app_mod.addImport("net", net_mod); } - // Import freertos module for some examples + // Import freertos module for some examples, kind of a hack + // probably list of required modules should be specified in each example independently if (std.mem.indexOf(u8, example.name, "_freertos-") != null) { const freertos_dep = b.dependency("freertos", .{ .target = b.resolveTargetQuery(firmware.target.zig_target), diff --git a/examples/raspberrypi/rp2xxx/src/freertos/hello_task.zig b/examples/raspberrypi/rp2xxx/src/freertos/hello_task.zig index ea49a0e16..459622eb6 100644 --- a/examples/raspberrypi/rp2xxx/src/freertos/hello_task.zig +++ b/examples/raspberrypi/rp2xxx/src/freertos/hello_task.zig @@ -14,8 +14,6 @@ const uart_tx_pin = gpio.num(0); pub const microzig_options = microzig.Options{ .log_level = .debug, .logFn = rp2xxx.uart.log, - //.overwrite_hal_interrupts = true, - //.interrupts = .{ .PendSV = .{ .naked = freertos.isr_pendsv }, .SysTick = .{ .c = freertos.isr_systick }, .SVCall = .{ .c = freertos.isr_svcall } }, .cpu = .{ .ram_vector_table = true, }, @@ -77,7 +75,7 @@ export fn multicore_launch_core1(entry: *const fn () callconv(.c) void) callconv } export fn multicore_reset_core1() callconv(.c) void { - // TODO + // TODO: please implement this in microzig.hal.multicore and call it here } export fn clock_get_hz(_: u32) callconv(.c) u32 { @@ -97,7 +95,7 @@ export fn exception_set_exclusive_handler(num: c_uint, handler: *const fn () cal const cs = microzig.interrupt.enter_critical_section(); defer cs.leave(); - // very ugly code but good for now + // TODO: can this code be simplified? if (num == 11) { microzig.cpu.ram_vector_table.SVCall = .{ .c = handler }; } else if (num == 14) { diff --git a/modules/freertos/build.zig.zon b/modules/freertos/build.zig.zon index cc700cef0..6139b6090 100644 --- a/modules/freertos/build.zig.zon +++ b/modules/freertos/build.zig.zon @@ -16,12 +16,5 @@ .path = "../foundation-libc/", }, }, - .paths = .{ - "build.zig", - "build.zig.zon", - "src", - // For example... - //"LICENSE", - //"README.md", - }, + .paths = .{ "build.zig", "build.zig.zon", "src", "picosdk", "config" }, } From 10a214e0c2789937d1c884ecab7692bf7122eea7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Arkadiusz=20W=C3=B3jcik?= Date: Tue, 20 Jan 2026 19:34:35 +0100 Subject: [PATCH 4/5] break line --- modules/freertos/build.zig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/modules/freertos/build.zig b/modules/freertos/build.zig index 8d1f7369e..eb85a6ed4 100644 --- a/modules/freertos/build.zig +++ b/modules/freertos/build.zig @@ -68,7 +68,8 @@ pub fn build(b: *std.Build) void { freertos_lib.addCMacro("LIB_PICO_MULTICORE", "0"); - // Had problems when this was enabled. Microzig but also Pico SDK? dont set VTOR to 0x10000100 for RP2040 at boot even when ram_vector_table is set to false + // Had problems when this was enabled. + // Microzig but also Pico SDK? dont set VTOR to 0x10000100 for RP2040 at boot even when ram_vector_table is set to false freertos_lib.addCMacro("PICO_NO_RAM_VECTOR_TABLE", "0"); const mod = b.addModule("freertos", .{ .root_source_file = b.path("src/root.zig"), .target = target, .optimize = optimize }); From 5823751cf169dce521c2583f058cccfb4226b826 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Arkadiusz=20W=C3=B3jcik?= Date: Tue, 20 Jan 2026 20:11:18 +0100 Subject: [PATCH 5/5] - remove unused deps - more context in comments --- .../rp2xxx/src/freertos/hello_task.zig | 2 +- modules/freertos/build.zig.zon | 4 - .../config/FreeRTOSConfig.multicore.h | 140 ------------------ modules/freertos/src/root.zig | 32 ++-- 4 files changed, 21 insertions(+), 157 deletions(-) delete mode 100644 modules/freertos/config/FreeRTOSConfig.multicore.h diff --git a/examples/raspberrypi/rp2xxx/src/freertos/hello_task.zig b/examples/raspberrypi/rp2xxx/src/freertos/hello_task.zig index 459622eb6..fd5c79359 100644 --- a/examples/raspberrypi/rp2xxx/src/freertos/hello_task.zig +++ b/examples/raspberrypi/rp2xxx/src/freertos/hello_task.zig @@ -45,8 +45,8 @@ pub fn hello_task(_: ?*anyopaque) callconv(.c) void { /// /// Some ugly glue code to implement required functions from FreeRTOS and Pico SDK /// - This can be improved later +/// - Some or even all of these could be implemented in freertos module directly? /// - Multicore not supported yet - multicore_reset_core1 have to be implemented -/// export fn panic_unsupported() callconv(.c) noreturn { @panic("not supported"); } diff --git a/modules/freertos/build.zig.zon b/modules/freertos/build.zig.zon index 6139b6090..d1347d02c 100644 --- a/modules/freertos/build.zig.zon +++ b/modules/freertos/build.zig.zon @@ -8,10 +8,6 @@ .url = "git+https://github.com/FreeRTOS/FreeRTOS-Kernel.git#52822473466cfa5cdd2146d02dae5f924b8552e4", .hash = "N-V-__8AAMb4CQGTaQBhmyNrZe5AydR8ZY3met6pGoXDe1MC", }, - .freertos_kernel_community = .{ - .url = "git+https://github.com/FreeRTOS/FreeRTOS-Kernel-Community-Supported-Ports.git#9ab3b5fb235838b3fc03d4f1cdcfab22007413d2", - .hash = "N-V-__8AAPdlHQB-Q5duFJp5D3hmNoJsOsWXr84CsPai1Pk9", - }, .foundationlibc = .{ .path = "../foundation-libc/", }, diff --git a/modules/freertos/config/FreeRTOSConfig.multicore.h b/modules/freertos/config/FreeRTOSConfig.multicore.h deleted file mode 100644 index fb2df9a9d..000000000 --- a/modules/freertos/config/FreeRTOSConfig.multicore.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * FreeRTOS V202107.00 - * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - - #ifndef FREERTOS_CONFIG_H - #define FREERTOS_CONFIG_H - - /*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html - *----------------------------------------------------------*/ - - /* Scheduler Related */ - #define configUSE_PREEMPTION 1 - #define configUSE_TICKLESS_IDLE 0 - #define configUSE_IDLE_HOOK 0 - #define configUSE_TICK_HOOK 0 - #define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) - #define configMAX_PRIORITIES 32 - #define configMINIMAL_STACK_SIZE ( configSTACK_DEPTH_TYPE ) 256 - #define configUSE_16_BIT_TICKS 0 - - #define configIDLE_SHOULD_YIELD 1 - - /* Synchronization Related */ - #define configUSE_MUTEXES 1 - #define configUSE_RECURSIVE_MUTEXES 1 - #define configUSE_APPLICATION_TASK_TAG 0 - #define configUSE_COUNTING_SEMAPHORES 1 - #define configQUEUE_REGISTRY_SIZE 8 - #define configUSE_QUEUE_SETS 1 - #define configUSE_TIME_SLICING 1 - #define configUSE_NEWLIB_REENTRANT 0 - #define configENABLE_BACKWARD_COMPATIBILITY 0 - #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 - - /* System */ - #define configSTACK_DEPTH_TYPE uint32_t - #define configMESSAGE_BUFFER_LENGTH_TYPE size_t - - /* Memory allocation related definitions. */ - #define configSUPPORT_STATIC_ALLOCATION 0 - #define configSUPPORT_DYNAMIC_ALLOCATION 1 - #define configTOTAL_HEAP_SIZE (128*1024) - #define configAPPLICATION_ALLOCATED_HEAP 0 - - /* Hook function related definitions. */ - #define configCHECK_FOR_STACK_OVERFLOW 0 - #define configUSE_MALLOC_FAILED_HOOK 0 - #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 - - /* Run time and task stats gathering related definitions. */ - #define configGENERATE_RUN_TIME_STATS 0 - #define configUSE_TRACE_FACILITY 1 - #define configUSE_STATS_FORMATTING_FUNCTIONS 0 - - /* Co-routine related definitions. */ - #define configUSE_CO_ROUTINES 0 - #define configMAX_CO_ROUTINE_PRIORITIES 1 - - /* Software timer related definitions. */ - #define configUSE_TIMERS 1 - #define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) - #define configTIMER_QUEUE_LENGTH 10 - #define configTIMER_TASK_STACK_DEPTH 1024 - - /* Interrupt nesting behaviour configuration. */ - /* - #define configKERNEL_INTERRUPT_PRIORITY [dependent of processor] - #define configMAX_SYSCALL_INTERRUPT_PRIORITY [dependent on processor and application] - #define configMAX_API_CALL_INTERRUPT_PRIORITY [dependent on processor and application] - */ - - /* SMP port only */ - #define configNUMBER_OF_CORES 2 - #define configTICK_CORE 0 - #define configRUN_MULTIPLE_PRIORITIES 1 - #define configUSE_CORE_AFFINITY 1 - #define configUSE_PASSIVE_IDLE_HOOK 0 - - /* RP2040 specific */ - #define configSUPPORT_PICO_SYNC_INTEROP 1 - #define configSUPPORT_PICO_TIME_INTEROP 1 - - #include - /* Define to trap errors during development. */ - #define configASSERT(x) assert(x) - - /* Set the following definitions to 1 to include the API function, or zero - to exclude the API function. */ - #define INCLUDE_vTaskPrioritySet 1 - #define INCLUDE_uxTaskPriorityGet 1 - #define INCLUDE_vTaskDelete 1 - #define INCLUDE_vTaskSuspend 1 - #define INCLUDE_vTaskDelayUntil 1 - #define INCLUDE_vTaskDelay 1 - #define INCLUDE_xTaskGetSchedulerState 1 - #define INCLUDE_xTaskGetCurrentTaskHandle 1 - #define INCLUDE_uxTaskGetStackHighWaterMark 1 - #define INCLUDE_xTaskGetIdleTaskHandle 1 - #define INCLUDE_eTaskGetState 1 - #define INCLUDE_xTimerPendFunctionCall 1 - #define INCLUDE_xTaskAbortDelay 1 - #define INCLUDE_xTaskGetHandle 1 - #define INCLUDE_xTaskResumeFromISR 1 - #define INCLUDE_xQueueGetMutexHolder 1 - - /* A header file that defines trace macro can be included here. */ - - #endif /* FREERTOS_CONFIG_H */ \ No newline at end of file diff --git a/modules/freertos/src/root.zig b/modules/freertos/src/root.zig index 71d37eebc..8162c43c7 100644 --- a/modules/freertos/src/root.zig +++ b/modules/freertos/src/root.zig @@ -5,18 +5,6 @@ pub const c = @cImport({ @cInclude("task.h"); }); -// Used when PICO_NO_RAM_VECTOR_TABLE is 1 (but don't work - VTOR is not set to 0x10000100 during boot) -// pub const microzig_options = microzig.Options{ -// .overwrite_hal_interrupts = true, -// .interrupts = .{ .PendSV = .{ .naked = freertos.isr_pendsv }, .SysTick = .{ .c = freertos.isr_systick }, .SVCall = .{ .c = freertos.isr_svcall } }, -// .cpu = .{ -// .ram_vector_table = false, -// }, -//}; -pub extern fn isr_pendsv() callconv(.naked) void; -pub extern fn isr_svcall() callconv(.c) void; -pub extern fn isr_systick() callconv(.c) void; - pub const OS = struct { pub const MINIMAL_STACK_SIZE: usize = c.configMINIMAL_STACK_SIZE; pub const MAX_PRIORITIES: usize = c.configMAX_PRIORITIES; @@ -48,3 +36,23 @@ pub const OS = struct { ); } }; + +// Those 3 exported interrupt functions are used when PICO_NO_RAM_VECTOR_TABLE is 1 +// This doesn't work because Microzig but also Pico SDK? dont set VTOR to 0x10000100 for RP2040 at boot +// even if proper configuration is set: +// pub const microzig_options = microzig.Options{ +// .overwrite_hal_interrupts = true, +// .interrupts = .{ +// .PendSV = .{ .naked = freertos.isr_pendsv }, +// .SysTick = .{ .c = freertos.isr_systick }, +// .SVCall = .{ .c = freertos.isr_svcall } +// }, +// .cpu = .{ +// .ram_vector_table = false, +// }, +//}; +// probably related to: https://github.com/raspberrypi/pico-sdk/issues/6 +// In most scenarious we are not interested in no ram vector case anyway +pub extern fn isr_pendsv() callconv(.naked) void; +pub extern fn isr_svcall() callconv(.c) void; +pub extern fn isr_systick() callconv(.c) void;