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hathachhathach
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get most of the sketches compiled with 833 except though with external flash since 833 does not have qspi
1 parent 820beaf commit a373b2c

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15 files changed

+233
-17
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15 files changed

+233
-17
lines changed

‎cores/nRF5/HardwarePWM.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -41,10 +41,10 @@
4141
#include <atomic>
4242
#include <cstdint>
4343

44-
#ifdef NRF52840_XXAA
45-
#define HWPWM_MODULE_NUM 4
44+
#ifdef NRF_PWM3
45+
#define HWPWM_MODULE_NUM 4
4646
#else
47-
#define HWPWM_MODULE_NUM 3
47+
#define HWPWM_MODULE_NUM 3
4848
#endif
4949

5050
class HardwarePWM

‎cores/nRF5/HardwareSerial.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@
4949
#ifdef NRF52832_XXAA
5050
#define SERIAL_8N1 (UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos)
5151
#define SERIAL_8E1 (UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos)
52-
#elif defined(NRF52840_XXAA)
52+
#elif defined(NRF52840_XXAA) || defined(NRF52833_XXAA)
5353
#define SERIAL_8N1 ((UARTE_CONFIG_STOP_One << UARTE_CONFIG_STOP_Pos) | (UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos))
5454
#define SERIAL_8N2 ((UARTE_CONFIG_STOP_Two << UARTE_CONFIG_STOP_Pos) | (UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos))
5555
#define SERIAL_8E1 ((UARTE_CONFIG_STOP_One << UARTE_CONFIG_STOP_Pos) | (UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos))

‎cores/nRF5/linker/gcc_startup_nrf52833.S‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
2020
2121
*/
2222

23-
#ifdef NRF52840_XXAA
23+
#ifdef NRF52833_XXAA
2424

2525
.syntax unified
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.arch armv7e-m

‎cores/nRF5/nordic/nrfx/mdk/system_nrf52833.c‎

Lines changed: 159 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,159 @@
1+
/*
2+
3+
Copyright (c) 2009-2018 ARM Limited. All rights reserved.
4+
5+
SPDX-License-Identifier: Apache-2.0
6+
7+
Licensed under the Apache License, Version 2.0 (the License); you may
8+
not use this file except in compliance with the License.
9+
You may obtain a copy of the License at
10+
11+
www.apache.org/licenses/LICENSE-2.0
12+
13+
Unless required by applicable law or agreed to in writing, software
14+
distributed under the License is distributed on an AS IS BASIS, WITHOUT
15+
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16+
See the License for the specific language governing permissions and
17+
limitations under the License.
18+
19+
NOTICE: This file has been modified by Nordic Semiconductor ASA.
20+
21+
*/
22+
23+
/* NOTE: Template files (including this one) are application specific and therefore expected to
24+
be copied into the application project folder prior to its use! */
25+
26+
#ifdef NRF52833_XXAA
27+
28+
#include <stdint.h>
29+
#include <stdbool.h>
30+
#include "nrf.h"
31+
#include "nrf_erratas.h"
32+
#include "system_nrf52833.h"
33+
34+
/*lint ++flb "Enter library region" */
35+
36+
#define __SYSTEM_CLOCK_64M (64000000UL)
37+
38+
#if defined ( __CC_ARM )
39+
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
40+
#elif defined ( __ICCARM__ )
41+
__root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M;
42+
#elif defined ( __GNUC__ )
43+
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
44+
#endif
45+
46+
void SystemCoreClockUpdate(void)
47+
{
48+
SystemCoreClock = __SYSTEM_CLOCK_64M;
49+
}
50+
51+
void SystemInit(void)
52+
{
53+
/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
54+
Specification to see which one). */
55+
#if defined (ENABLE_SWO)
56+
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
57+
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
58+
NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
59+
#endif
60+
61+
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
62+
Specification to see which ones). */
63+
#if defined (ENABLE_TRACE)
64+
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
65+
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
66+
NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
67+
NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
68+
NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
69+
NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
70+
NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
71+
#endif
72+
73+
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
74+
for your device located at https://infocenter.nordicsemi.com/index.jsp */
75+
if (nrf52_errata_36()){
76+
NRF_CLOCK->EVENTS_DONE = 0;
77+
NRF_CLOCK->EVENTS_CTTO = 0;
78+
NRF_CLOCK->CTIV = 0;
79+
}
80+
81+
/* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
82+
for your device located at https://infocenter.nordicsemi.com/index.jsp */
83+
if (nrf52_errata_66()){
84+
NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
85+
NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
86+
NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
87+
NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
88+
NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
89+
NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
90+
NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
91+
NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
92+
NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
93+
NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
94+
NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
95+
NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
96+
NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
97+
NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
98+
NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
99+
NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
100+
NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
101+
}
102+
103+
/* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
104+
for your device located at https://infocenter.nordicsemi.com/index.jsp */
105+
if (nrf52_errata_136()){
106+
if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
107+
NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
108+
}
109+
}
110+
111+
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
112+
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
113+
* operations are not used in your code. */
114+
#if (__FPU_USED == 1)
115+
SCB->CPACR |= (3UL << 20) | (3UL << 22);
116+
__DSB();
117+
__ISB();
118+
#endif
119+
120+
/* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
121+
two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
122+
normal GPIOs. */
123+
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
124+
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
125+
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
126+
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
127+
NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
128+
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
129+
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
130+
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
131+
NVIC_SystemReset();
132+
}
133+
#endif
134+
135+
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
136+
defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
137+
reserved for PinReset and not available as normal GPIO. */
138+
#if defined (CONFIG_GPIO_AS_PINRESET)
139+
if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
140+
((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
141+
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
142+
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
143+
NRF_UICR->PSELRESET[0] = 18;
144+
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
145+
NRF_UICR->PSELRESET[1] = 18;
146+
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
147+
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
148+
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
149+
NVIC_SystemReset();
150+
}
151+
#endif
152+
153+
SystemCoreClockUpdate();
154+
}
155+
156+
/*lint --flb "Leave library region" */
157+
158+
#endif
159+

‎cores/nRF5/nordic/nrfx/mdk/system_nrf52833.h‎

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1+
/*
2+
3+
Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
4+
5+
Redistribution and use in source and binary forms, with or without
6+
modification, are permitted provided that the following conditions are met:
7+
8+
1. Redistributions of source code must retain the above copyright notice, this
9+
list of conditions and the following disclaimer.
10+
11+
2. Redistributions in binary form must reproduce the above copyright
12+
notice, this list of conditions and the following disclaimer in the
13+
documentation and/or other materials provided with the distribution.
14+
15+
3. Neither the name of Nordic Semiconductor ASA nor the names of its
16+
contributors may be used to endorse or promote products derived from this
17+
software without specific prior written permission.
18+
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20+
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21+
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
22+
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
23+
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24+
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25+
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26+
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27+
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28+
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29+
POSSIBILITY OF SUCH DAMAGE.
30+
31+
*/
32+
33+
#ifndef SYSTEM_NRF52833_H
34+
#define SYSTEM_NRF52833_H
35+
36+
#ifdef __cplusplus
37+
extern "C" {
38+
#endif
39+
40+
#include "system_nrf.h"
41+
42+
#ifdef __cplusplus
43+
}
44+
#endif
45+
46+
#endif /* SYSTEM_NRF52833_H */

‎cores/nRF5/nordic/nrfx_config.h‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,9 +26,12 @@
2626
#define NRFX_TIMER2_ENABLED 0
2727
#define NRFX_TIMER3_ENABLED 0
2828

29-
#ifdef NRF52840_XXAA
29+
#if defined(NRF52840_XXAA)
3030
#define NRFX_QSPI_ENABLED 1
3131
#define NRFX_SPIM3_ENABLED 1
32+
#elif defined(NRF52833_XXAA)
33+
#define NRFX_QSPI_ENABLED 0
34+
#define NRFX_SPIM3_ENABLED 1
3235
#else
3336
#define NRFX_QSPI_ENABLED 0
3437
#define NRFX_SPIM3_ENABLED 0

‎libraries/Adafruit_nRFCrypto‎

‎libraries/Bluefruit52Lib/examples/Peripheral/image_eink_transfer/image_eink_transfer.ino‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -99,7 +99,7 @@ void setup()
9999
// changing the default "deferred" option to false to invoke callback immediately.
100100
// However, the transfer speed will be affected since immediate callback will block BLE task
101101
// to process data especially when tft.drawRGBBitmap() is calling.
102-
#ifdef NRF52840_XXAA
102+
#if defined(NRF52840_XXAA) || defined(NRF52833_XXAA)
103103
// 2nd argument is true to deferred callbacks i.e queue it up in separated callback Task
104104
bleuart.setRxCallback(bleuart_rx_callback, true);
105105
#else

‎libraries/Bluefruit52Lib/examples/Peripheral/image_transfer/image_transfer.ino‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -166,7 +166,7 @@ void setup()
166166
// changing the default "deferred" option to false to invoke callback immediately.
167167
// However, the transfer speed will be affected since immediate callback will block BLE task
168168
// to process data especially when tft.drawRGBBitmap() is calling.
169-
#ifdef NRF52840_XXAA
169+
#if defined(NRF52840_XXAA) || defined(NRF52833_XXAA)
170170
// 2nd argument is true to deferred callbacks i.e queue it up in separated callback Task
171171
bleuart.setRxCallback(bleuart_rx_callback, true);
172172
#else

‎libraries/Bluefruit52Lib/src/BLEConnection.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -149,7 +149,7 @@ static inline bool is_tx_power_valid(int8_t power)
149149
{
150150
#if defined(NRF52832_XXAA)
151151
int8_t const accepted[] = { -40, -20, -16, -12, -8, -4, 0, 3, 4 };
152-
#elif defined( NRF52840_XXAA)
152+
#elif defined(NRF52840_XXAA) || defined(NRF52833_XXAA)
153153
int8_t const accepted[] = { -40, -20, -16, -12, -8, -4, 0, 2, 3, 4, 5, 6, 7, 8 };
154154
#endif
155155

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