Copyediting

In the interest of not making people chase links, the FAQ reproduces the
text at `getting-started/installing.md` instead of linking to it.

Author: DigitalBrains1

compiler-user-guide/src/developing-hardware/annotations.md

@@ -15,7 +15,7 @@ Functions with a `Synthesize` annotation must adhere to the following restrictio
 Also take the following into account when using `Synthesize` annotations.
 
   * The Clash compiler is based on the GHC Haskell compiler, and the GHC machinery does not understand `Synthesize` annotations and it might subsequently decide to inline those functions.
-    You should therefor also add a `{-# OPAQUE f #-}` pragma to the functions which you give a `Synthesize` functions.
+    You should therefore also add a `{-# OPAQUE f #-}` pragma to the functions which you give a `Synthesize` annotation.
   * Functions with a `Synthesize` annotation will not be specialized on constants.
 
 Finally, the root module, the module which you pass as an argument to the Clash compiler must either have:

compiler-user-guide/src/developing-hardware/primitives.md

@@ -259,7 +259,7 @@ Instead of discussing what the individual template holes mean in the above conte
 
 Some final remarks to end this section: HDL primitives are there to instruct the Clash compiler to use the given HDL template, instead of trying to do normal synthesis.
 As a consequence you can use constructs inside the Haskell definitions that are normally not synthesizable by the Clash compiler.
-However, VHDL primitives do not give us _co-simulation_: where you would be able to simulate VHDL and Haskell in a _single_ environment.
+However, VHDL primitives do not give us _co-simulation_, where you would be able to simulate VHDL and Haskell in a _single_ environment.
 If you still want to simulate your design in Haskell, you will have to describe, in a cycle- and bit-accurate way, the behavior of that (potentially complex) IP you are trying to include in your design.
 
 ## Verilog examples

compiler-user-guide/src/general/faqs.md

@@ -4,7 +4,7 @@
 
 - **Q**: How do I install Clash?
 
-  **A**: Check out the `installing` page in the *Getting Started* section of the manual.
+  **A**: Check out [clash-lang.org/install](https://clash-lang.org/install) to install the latest stable release of Clash, or to setup a Clash project.
 
 ------------------------------------------------------------------------
 
@@ -19,10 +19,10 @@
 
 ------------------------------------------------------------------------
 
-- **Q**: Is Clash a "high level synthesis" tool?
+- **Q**: Is Clash a "high-level synthesis" tool?
 
-  **A**: While clash provides a high level language features, hardware descriptions written in Clash are not decoupled from clock-level timing.
-  Clash does therefore not offer what is generally understood as "high level synthesis".
+  **A**: While clash provides high-level language features, hardware descriptions written in Clash are not decoupled from clock-level timing.
+  Clash does therefore not offer what is generally understood as "high-level synthesis".
   Compared to the big three hardware description languages, *VHDL*, *Verilog*, and *SystemVerilog*, Clash arguably *is* high-level.
   It offers many of the powerful abstractions that modern software programming languages offer.
   In fact, it inherits many of the software industry's bleeding-edge features by virtue of basing its implementation on Haskell.
@@ -32,7 +32,7 @@
 - **Q**: Is Clash production ready?
 
   **A**: Clash is constantly evolving, and since the 1.0 release there is a focus on maintaining API backwards compatibility.
-  Clash is used successfully in real-world scenarios, and [QBayLogic Clash support](https://qbaylogic.com/clash-support.html) can help with education and implementation of Clash projects.
+  Clash is used successfully in real-world scenarios, and [QBayLogic Clash support](https://qbaylogic.com/services/) can help with education and implementation of Clash projects.
 
 ------------------------------------------------------------------------
 
@@ -43,7 +43,7 @@
 
   For most toolchains, the default primitives supplied by Clash should work with minimal effort.
   If not, it is possible to call your vendor's library manually, or use a tool like [Yosys](http://clifford.at/yosys) to do mapping.
-  It is also possible to consult [QBayLogic Clash support](https://qbaylogic.com/clash-support.html) for more assistance.
+  It is also possible to consult [QBayLogic Clash support](https://qbaylogic.com/services/) for more assistance.
 
 ------------------------------------------------------------------------
 
@@ -60,7 +60,7 @@
   Clash can be used for ASIC designs, however the RTL produced by Clash may not be immediately suitable as it is largely platform agnostic.
   While this is not a problem for FPGAs, it can make developing ASICs more complicated as many ASIC vendors have different proprietary tool flows, with limited information available about their workings.
 
-  If you are using Clash to develop for ASIC, and need assistance with getting your toolchain to work, you can contact [QBayLogic Clash support](https://qbaylogic.com/clash-support.html) for assistance.
+  If you are using Clash to develop for ASIC, and need assistance with getting your toolchain to work, you can contact [QBayLogic Clash support](https://qbaylogic.com/services/) for assistance.
 
 ## Clash and Haskell
 

compiler-user-guide/src/general/index.md

@@ -90,7 +90,7 @@ Note
 
 </div>
 
-Due to the Clash's tight integration with GHC, updates to the GHC version that Clash uses result in changes to the Clash version.
+Due to Clash's tight integration with GHC, updates to the GHC version that Clash uses result in changes to the Clash version.
 As GHC's internals change frequently, even for minor bumps, it cannot be guaranteed that these changes will not result in Clash changes.
 
 </div>