Update outdated information

These things were correct in the past, but have since changed.

Author: DigitalBrains1

compiler-user-guide/src/developing-hardware/prelude.md

@@ -151,7 +151,7 @@ There are also implementations of typical classes in Haskell which have been cha
 Currently these are
 
 - `ShowX`, which works like the `Show` class in Haskell.
-  When an undefined value is encountered an "X" is printed.
+  When an undefined value is encountered, `undefined` is printed.
   `Show` can still be used, but will throw an exception if an undefined value is encountered.
 - `NFDataX`, which works like the `NFData` class in the `deepseq` library.
   This allows evaluating values to normal form in code when `XException` may be present.

compiler-user-guide/src/hacking-on-clash/index.md

@@ -8,7 +8,9 @@ This means you need:
 
 - [ghdl](https://github.com/ghdl/ghdl) installed to test *VHDL*
 - [iverilog](https://github.com/steveicarus/iverilog) installed to test *Verilog*
+- [Verilator](http://verilator.org/) installed to test *Verilog* and *SystemVerilog*
 - [ModelSim](https://fpgasoftware.intel.com/?product=modelsim_ae#tabs-2) installed to test *SystemVerilog*
+- [Vivado](https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vivado.html) installed to test *VHDL*, *Verilog* and *SystemVerilog*
 - [SymbiYosys](https://github.com/YosysHQ/SymbiYosys) and [Z3](https://github.com/Z3Prover/z3) installed to test *Verilog* and *SystemVerilog*
 
 ## Get Clash from source
@@ -47,7 +49,7 @@ Windows users are recommended to use the [Haskell Platform](https://www.haskell.
 To run <span class="title-ref">clash</span> use:
 
 ``` bash
-cabal v2-run --write-ghc-environment-files=always -- clash
+cabal v2-run -- clash
 ```
 
 If this fails, make sure you've got an up-to-date package index:
@@ -69,7 +71,7 @@ stack run -- clash
 Or [use Nix](https://nixos.org/nix/download.html) to get a shell with the `clash` and `clashi` binaries on your PATH:
 
 ``` bash
-nix-shell
+nix develop
 ```
 ## Subprojects
 

tutorial/src/first-steps/test-bench.md

@@ -63,10 +63,10 @@ The reason is that `stimuliGenerator` will keep on producing the last sample, (4
 In the VHDL test bench these errors will not show, as the global clock will be stopped after 4 ticks.
 
 You should now again run `:vhdl` in the interpreter; this time the compiler will take a bit longer to generate all the circuits.
-Inside the `./vhdl/MAC` directory you will now also find a `testbench` subdirectory containing all the `vhdl` files for the *test bench*.
+Inside the `./vhdl/MAC.testBench` directory you will now find all the `vhdl` files for the *test bench*.
 
 After compilation is finished you load all the files in your favorite VHDL simulation tool.
-Once all files are loaded into the VHDL simulator, run the simulation on the `testbench` entity.
+Once all files are loaded into the VHDL simulator, run the simulation on the `testBench` entity.
 On questasim / modelsim: doing a `run -all` will finish once the output verifier will assert its output to `true`.
 The generated test bench, modulo the clock signal generator(s), is completely synthesizable.
 This means that if you want to test your circuit on an FPGA, you will only have to replace the clock signal generator(s) by actual clock sources, such as an onboard PLL.

tutorial/src/first-steps/verilog.md

@@ -2,7 +2,7 @@
 
 Aside from being able to generate VHDL, the Clash compiler can also generate Verilog and SystemVerilog.
 You can repeat the previous two parts of the tutorial, but instead of executing the `:vhdl` command, you execute the `:verilog` or `:sytemverilog` command in the interpreter.
-This will create a directory called `verilog`, respectively `systemverilog`, which contains a directory called `MAC`, which ultimately contains all the generated Verilog and SystemVerilog files.
+This will create a directory called `verilog`, respectively `systemverilog`, which contains a directory called `MAC.topEntity`, which ultimately contains all the generated Verilog and SystemVerilog files.
 Verilog files end in the file extension `.v`, while SystemVerilog files end in the file extension `.sv`.
 
 This concludes the tutorial for "Your first circuit".

tutorial/src/first-steps/vhdl.md

@@ -49,5 +49,5 @@ It must meet the following restrictions in order for the Clash compiler to work:
 -   Although not strictly necessary, it is recommended to *expose* `Hidden` clock and reset arguments, as it makes user-controlled name assignment in the generated HDL easier to do.
 
 Our `topEntity` meets those restrictions, and so we can convert it successfully to VHDL by executing the `:vhdl` command in the interpreter.
-This will create a directory called `vhdl`, which contains a directory called `MAC`, which ultimately contains all the generated VHDL files.
-You can now load these files into your favorite VHDL synthesis tool, marking `topentity.vhdl` as the file containing the top level entity.
+This will create a directory called `vhdl`, which contains a directory called `MAC.topEntity`, which ultimately contains all the generated VHDL files.
+You can now load these files into your favorite VHDL synthesis tool, marking `topEntity.vhdl` as the file containing the top level entity.