Updated host code and added more board support

Author: alex-yang-upenn

hls4ml/backends/vitis_accelerator/supported_boards.json

@@ -1,17 +1,26 @@
 {
     "alveo-u55c": {
+      "board_type": "alveo",
       "part": "xcu55c-fsvh2892-2L-e",
       "platform": "xilinx_u55c_gen3x16_xdma_3_202210_1",
       "memory": {"type": "hbm", "channels": 32, "capacity": 16}
     },
     "alveo-u50": {
+      "board_type": "alveo",
       "part": "xcu50-fsvh2104-2-e",
       "platform": "xilinx_u50_gen3x16_xdma_5_202210_1",
       "memory": {"type": "hbm", "channels": 32, "capacity": 8}
     },
     "alveo-u250": {
+      "board_type": "alveo",
       "part": "xcu250-figd2104-2L-e",
       "platform": "xilinx_u250_xdma_201830_2",
       "memory": {"type": "ddr", "channels": 4, "capacity": 64}
+    },
+    "vck5000": {
+      "board_type": "versal",
+      "part": "xcvc1902-2msevsvd1760", 
+      "platform": "xilinx_vck5000_gen4x8_qdma_2_202220_1",
+      "memory":{"type": "ddr", "channels": 3, "capacity": 12}
     }
   }

hls4ml/backends/vitis_accelerator/vitis_accelerator_config.py

@@ -12,6 +12,7 @@ def __init__(self, config):
         self.supported_boards = json.load(open(os.path.dirname(__file__) + '/supported_boards.json'))
         if self.board in self.supported_boards.keys():
             board_info = self.supported_boards[self.board]
+            self.board_type = board_info['board_type']
             self.part = board_info['part']
             self.platform = board_info['platform']
             self.memory_type = board_info['memory']['type']
@@ -31,6 +32,9 @@ def __init__(self, config):
         self.num_thread = accel_config.get('Num_Thread')
         self.batchsize = accel_config.get('Batchsize')        
 
+    def get_board_type(self):
+        return self.board_type
+
     def get_platform(self):
         return self.platform
 

hls4ml/templates/vitis_accelerator/Makefile

@@ -31,9 +31,8 @@ all: host kernel
 ./build/myproject_kernel.xo: kernel_wrapper.cpp
 	mkdir -p ./build
 	v++ -c -t hw --config ./accelerator_card.cfg kernel_wrapper.cpp firmware/myproject.cpp -o ./build/myproject_kernel.xo $(KERN_LIBRARIES)
- 
-myproject_kernel.xclbin: ./build/myproject_kernel.xo
-	v++ -l -t hw --config ./accelerator_card.cfg ./build/myproject_kernel.xo -o kernel_wrapper.xclbin
+
+# hls-fpga-machine-learning packaging 
 
 # Building Host 
 INCLUDES += -I$(XILINX_XRT)/include/ -I$(XILINX_VIVADO)/include/ -I$(XILINX_HLS)/include/ \
@@ -45,7 +44,7 @@ host: myproject_host_cl.cpp libs/xcl2.cpp
 	$(CXX) $(CXXFLAGS) $^ -o $@ $(INCLUDES) $(LDFLAGS) 
 
 .PHONY: kernel
-kernel: myproject_kernel.xclbin
+kernel: kernel_wrapper.xclbin
 
 # Cleaning stuff
 .PHONY: clean

hls4ml/templates/vitis_accelerator/myproject_host_cl.cpp

@@ -83,13 +83,13 @@ int main(int argc, char **argv) {
     }
 
     // Copying in testbench data
-    int n = inputData.size();
+    int n = std::min((int) inputData.size(), INSTREAMSIZE * NUM_CU * NUM_THREAD);
     for (int i = 0; i < n; i++) {
         fpga.source_in[i] = inputData[i];
     }
 
     // Padding rest of buffer with arbitrary values
-    for (int i = n; i < NUM_CU * NUM_THREAD * INSTREAMSIZE; i++) {
+    for (int i = n; i < INSTREAMSIZE * NUM_CU * NUM_THREAD; i++) {
         fpga.source_in[i] = (in_buffer_t)(1234.567);
     }
 
@@ -115,16 +115,34 @@ int main(int argc, char **argv) {
             float(std::chrono::duration_cast<std::chrono::nanoseconds>(ts_end - ts_start).count())) *
             1000000000.;
 
+    std::cout << "Throughput = "
+            << throughput
+            <<" predictions/second\n" << std::endl;
+
+    std::cout << "Writing hw resaults to file" << std::endl;
+    std::ofstream resultsFile;
+    resultsFile.open("tb_data/hw_results.dat", std::ios::trunc);
+    if (resultsFile.is_open()) {   
+        for (int i = 0; i < NUM_THREAD * NUM_CU * BATCHSIZE; i++) {
+            std::stringstream line;
+            for (int n = 0; n < DATA_SIZE_OUT; n++) {
+                line << (float)fpga.source_hw_results[(i * DATA_SIZE_OUT) + n] << " ";
+            }
+            resultsFile << line.str() << "\n";
+        }
+        resultsFile.close();
+    } else {
+        std::cerr << "Error writing hw results to file" << std::endl;
+    }
+
+    std::cout << "\nWriting run logs to file" << std::endl;
     std::ofstream outFile("u55c_executable_logfile.log", std::ios::trunc);
     if (outFile.is_open()) {
         outFile << fpga.ss.rdbuf();
         outFile.close();
     } else {
-        std::cerr << "Error opening file for writing." << std::endl;
+        std::cerr << "Error opening file for logging" << std::endl;
     }
-
-    std::cout << "Throughput = "
-            << throughput
-            <<" predictions/second" << std::endl;
+    
     return EXIT_SUCCESS;
 }

hls4ml/writer/vitis_accelerator_writer.py

@@ -171,14 +171,27 @@ def write_makefile(self, model):
         Args:
             model (ModelGraph): the hls4ml model.
         """
+        from hls4ml.backends import VitisAcceleratorConfig
 
         filedir = os.path.dirname(os.path.abspath(__file__))
         f = open(os.path.join(filedir, '../templates/vitis_accelerator/Makefile'))
         fout = open(f'{model.config.get_output_dir()}/Makefile', 'w')
 
+        board_type = self.vitis_accelerator_config.get_board_type()
+        project_name = format(model.config.get_project_name())
+
         for line in f.readlines():
             if 'myproject' in line:
-                newline = line.replace('myproject', format(model.config.get_project_name()))
+                newline = line.replace('myproject', project_name)
+            elif '# hls-fpga-machine-learning packaging' in line:
+                if board_type == "alveo":
+                    newline = f'kernel_wrapper.xclbin: ./build/{project_name}_kernel.xo\n'
+                    newline += f'    v++ -l -t hw --config ./accelerator_card.cfg ./build/{project_name}_kernel.xo -o kernel_wrapper.xclbin\n'
+                elif board_type == "versal":
+                    newline = f'kernel_wrapper.xsa: ./build/{project_name}_kernel.xo\n'
+                    newline += f'    v++ -l -t hw --config ./accelerator_card.cfg ./build/{project_name}_kernel.xo -o kernel_wrapper.xsa\n\n'
+                    newline += f'kernel_wrapper.xclbin: ./kernel_wrapper.xsa\n'
+                    newline += f'    v++ --package -t hw --config ./accelerator_card.cfg ./kernel_wrapper.xsa -o kernel_wrapper.xclbin\n'
             else:
                 newline = line
             fout.write(newline)
@@ -219,17 +232,18 @@ def write_accelerator_card_cfg(self, model):
             elif '# hls-fpga-machine-learning kernel control' in line:
                 newline = '[connectivity]\n'
                 newline += 'nk=kernel_wrapper:' + format(num_kernels) + '\n\n'
-                if memory_type == 'hbm':
-                    for i in range(0, num_kernels):
-                        newline += 'sp=kernel_wrapper_{}.in:HBM[{}:{}]\n'.format(i + 1, (i*2)*num_channels_per_cu, ((i*2 + 1)*num_channels_per_cu) - 1)
-                        newline += 'sp=kernel_wrapper_{}.out:HBM[{}:{}]\n'.format(i + 1, (i*2 + 1)*num_channels_per_cu, ((i+1) * 2)*num_channels_per_cu - 1)
-                elif memory_type == 'ddr':
-                    for i in range(0, num_kernels):
-                        newline += 'sp=kernel_wrapper_{}.in:DDR[{}]\n'.format(i + 1, i)
-                        newline += 'sp=kernel_wrapper_{}.out:HBM[{}]\n'.format(i + 1, i)
-                        newline += '\n'
-                    for i in range(0, num_kernels):
-                        newline += 'slr=kernel_wrapper_{}:SLR{}\n'.format(i + 1, i)
+                if self.vitis_accelerator_config.get_board_type() == "alveo":
+                    if memory_type == 'hbm':
+                        for i in range(0, num_kernels):
+                            newline += 'sp=kernel_wrapper_{}.in:HBM[{}:{}]\n'.format(i + 1, (i*2)*num_channels_per_cu, ((i*2 + 1)*num_channels_per_cu) - 1)
+                            newline += 'sp=kernel_wrapper_{}.out:HBM[{}:{}]\n'.format(i + 1, (i*2 + 1)*num_channels_per_cu, ((i+1) * 2)*num_channels_per_cu - 1)
+                    elif memory_type == 'ddr':
+                        for i in range(0, num_kernels):
+                            newline += 'sp=kernel_wrapper_{}.in:DDR[{}]\n'.format(i + 1, i)
+                            newline += 'sp=kernel_wrapper_{}.out:HBM[{}]\n'.format(i + 1, i)
+                            newline += '\n'
+                        for i in range(0, num_kernels):
+                            newline += 'slr=kernel_wrapper_{}:SLR{}\n'.format(i + 1, i)
             else:
                 newline = line
             fout.write(newline)