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alex-yang-upennalex-yang-upenn
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Default directives + HLS Clock control
1 parent 6744a08 commit 93f67b6

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5 files changed

+172
-23
lines changed

5 files changed

+172
-23
lines changed

‎hls4ml/backends/vitis_accelerator/vitis_accelerator_backend.py‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,8 @@ def create_initial_config(
2121
io_type='io_parallel',
2222
num_kernel=1,
2323
num_thread=1,
24-
batchsize=8192
24+
batchsize=8192,
25+
vivado_directives=[]
2526
):
2627
'''
2728
Create initial accelerator config with default parameters
@@ -32,6 +33,8 @@ def create_initial_config(
3233
io_type: io_parallel or io_stream
3334
num_kernel: how many compute units to create on the fpga
3435
num_thread: how many threads the host cpu uses to drive the fpga
36+
batchsize: how many samples to process within a single buffer on the fpga
37+
vivado_directives: Directives passed down to Vivado that controls the hardware synthesis and implementation steps
3538
Returns:
3639
populated config
3740
'''
@@ -42,9 +45,10 @@ def create_initial_config(
4245
config['AcceleratorConfig']['Num_Kernel'] = num_kernel
4346
config['AcceleratorConfig']['Num_Thread'] = num_thread
4447
config['AcceleratorConfig']['Batchsize'] = batchsize
48+
config['AcceleratorConfig']['Vivado_Directives'] = vivado_directives
4549
return config
4650

47-
def build(self, model, reset=False, synth=True, vsynth=True):
51+
def build(self, model, reset=False, synth=True, vsynth=True, **kwargs):
4852
if 'linux' in sys.platform:
4953
if 'XILINX_VITIS' not in os.environ:
5054
raise Exception("XILINX_VITIS environmental variable missing. Please install XRT and Vitis, and run the setup scripts before building")

‎hls4ml/backends/vitis_accelerator/vitis_accelerator_config.py‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,9 @@ def __init__(self, config):
3030

3131
self.num_kernel = accel_config.get('Num_Kernel')
3232
self.num_thread = accel_config.get('Num_Thread')
33-
self.batchsize = accel_config.get('Batchsize')
33+
self.batchsize = accel_config.get('Batchsize')
34+
35+
self.vivado_directives = accel_config.get('Vivado_Directives')
3436

3537
def get_board_type(self):
3638
return self.board_type
@@ -52,3 +54,6 @@ def get_memory_type(self):
5254

5355
def get_memory_channel_count(self):
5456
return self.memory_channel_count
57+
58+
def get_vivado_directives(self):
59+
return self.vivado_directives

‎hls4ml/backends/vitis_accelerator/vivado_directives.json‎

Lines changed: 137 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,137 @@
1+
{
2+
"impl.strategies": [
3+
"Performance_Explore",
4+
"Performance_ExplorePostRoutePhysOpt",
5+
"Performance_LBlockPlacement",
6+
"Performance_LBlockPlacementFanoutOpt",
7+
"Performance_NetDelay_high",
8+
"Performance_NetDelay_low",
9+
"Performance_Retiming",
10+
"Performance_ExtraTimingOpt",
11+
"Performance_RefinePlacement",
12+
"Performance_SpreadSLL",
13+
"Performance_BalanceSLL",
14+
"Congestion_SpreadLogic_high",
15+
"Congestion_SpreadLogic_medium",
16+
"Congestion_SpreadLogic_low",
17+
"Congestion_SpreadLogic_Explore",
18+
"Congestion_SSI_SpreadLogic_high",
19+
"Congestion_SSI_SpreadLogic_low",
20+
"Area_Explore",
21+
"Area_ExploreSequential",
22+
"Area_ExploreWithRemap",
23+
"Power_DefaultOpt",
24+
"Power_ExploreArea",
25+
"Flow_RunPhysOpt",
26+
"Flow_RunPostRoutePhysOpt",
27+
"Flow_RuntimeOptimized",
28+
"Flow_Quick",
29+
"ALL"
30+
],
31+
"prop": {
32+
"run": {
33+
"impl": {
34+
"STEPS": {
35+
"OPT_DESIGN": {
36+
"ARGS": {
37+
"DIRECTIVE": [
38+
"Explore",
39+
"ExploreArea",
40+
"ExploreSequentialArea",
41+
"RuntimeOptimized",
42+
"ExploreWithRemap"
43+
]
44+
}
45+
},
46+
"POWER_OPT_DESIGN": {
47+
"IS_ENABLED": [
48+
"true"
49+
]
50+
},
51+
"PLACE_DESIGN": {
52+
"ARGS": {
53+
"DIRECTIVE": [
54+
"Explore",
55+
"WLDrivenBlockPlacement",
56+
"EarlyBlockPlacement",
57+
"ExtraNetDelay_high",
58+
"ExtraNetDelay_low",
59+
"SSI_SpreadLogic_high",
60+
"SSI_SpreadLogic_low",
61+
"AltSpreadLogic_high",
62+
"AltSpreadLogic_medium",
63+
"AltSpreadLogic_low",
64+
"ExtraPostPlacementOpt",
65+
"ExtraTimingOpt",
66+
"SSI_SpreadSLLs",
67+
"SSI_BalanceSLLs",
68+
"SSI_Balance_SLRs",
69+
"SSI_HighUtilSLRs",
70+
"RuntimeOptimized",
71+
"Quick",
72+
"Auto_1",
73+
"Auto_2",
74+
"Auto_3"
75+
]
76+
}
77+
},
78+
"POST_PLACE_POWER_OPT_DESIGN": {
79+
"IS_ENABLED": [
80+
"true"
81+
]
82+
},
83+
"PHYS_OPT_DESIGN": {
84+
"IS_ENABLED": [
85+
"true"
86+
],
87+
"ARGS": {
88+
"DIRECTIVE": [
89+
"Explore",
90+
"ExploreWithHoldFix",
91+
"ExploreWithAggressiveHoldFix",
92+
"AggressiveExplore",
93+
"AlternateReplication",
94+
"AggressiveFanoutOpt",
95+
"AddRetime",
96+
"AlternateFlowWithRetiming",
97+
"RuntimeOptimized"
98+
]
99+
}
100+
},
101+
"ROUTE_DESIGN": {
102+
"ARGS": {
103+
"DIRECTIVE": [
104+
"Explore",
105+
"AggressiveExplore",
106+
"NoTimingRelaxation",
107+
"MoreGlobalIterations",
108+
"HigherDelayCost",
109+
"RuntimeOptimized",
110+
"AlternateCLBRouting",
111+
"Quick"
112+
]
113+
}
114+
},
115+
"POST_ROUTE_PHYS_OPT_DESIGN": {
116+
"IS_ENABLED": [
117+
"true"
118+
],
119+
"ARGS": {
120+
"DIRECTIVE": [
121+
"Explore",
122+
"ExploreWithHoldFix",
123+
"ExploreWithAggressiveHoldFix",
124+
"AggressiveExplore",
125+
"AlternateReplication",
126+
"AggressiveFanoutOpt",
127+
"AddRetime",
128+
"AlternateFlowWithRetiming",
129+
"RuntimeOptimized"
130+
]
131+
}
132+
}
133+
}
134+
}
135+
}
136+
}
137+
}

‎hls4ml/templates/vitis_accelerator/accelerator_card.cfg‎

Lines changed: 2 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -8,19 +8,8 @@ prop=kernel.kernel_wrapper.kernel_flags=-std=c++11
88

99
[hls]
1010
pre_tcl=./hls_config.tcl
11+
# hls-fpga-machine-learning clock control
1112

1213
# hls-fpga-machine-learning kernel control
1314

14-
[vivado]
15-
prop=run.impl_1.STEPS.OPT_DESIGN.IS_ENABLED=true
16-
prop=run.impl_1.STEPS.OPT_DESIGN.ARGS.DIRECTIVE=Explore
17-
18-
prop=run.impl_1.STEPS.PLACE_DESIGN.ARGS.DIRECTIVE=AltSpreadLogic_high
19-
20-
prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=true
21-
prop=run.imp1_1.STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE=AggressiveExplore
22-
23-
prop=run.impl_1.STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE=Explore
24-
25-
prop=run.impl_1.STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED=true
26-
prop=run.impl_1.STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE=AggressiveExplore
15+
# hls-fpga-machine-learning vivado directives

‎hls4ml/writer/vitis_accelerator_writer.py‎

Lines changed: 21 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -229,13 +229,18 @@ def write_accelerator_card_cfg(self, model):
229229
raise Exception(format(self.vitis_accelerator_config.get_platform()) +
230230
' has only ' + format(num_channels) + ' memory banks.')
231231

232+
directives = self.vitis_accelerator_config.get_vivado_directives()
233+
232234
for line in f.readlines():
233235
if 'MYPLATFORM' in line:
234236
newline = line.replace('MYPLATFORM', format(self.vitis_accelerator_config.get_platform()))
237+
elif "# hls-fpga-machine-learning clock control" in line:
238+
freq = round(1e9 / model.config.get_config_value('ClockPeriod'))
239+
newline = 'clock={}:kernel_wrapper\n'.format(freq)
235240
elif '# hls-fpga-machine-learning kernel control' in line:
236241
newline = '[connectivity]\n'
237242
newline += 'nk=kernel_wrapper:' + format(num_kernels) + '\n\n'
238-
if self.vitis_accelerator_config.get_board_type() == "alveo":
243+
if self.vitis_accelerator_config.get_board_type() == 'alveo':
239244
if memory_type == 'hbm':
240245
for i in range(0, num_kernels):
241246
newline += 'sp=kernel_wrapper_{}.in:HBM[{}:{}]\n'.format(i + 1, (i*2)*num_channels_per_cu, ((i*2 + 1)*num_channels_per_cu) - 1)
@@ -247,18 +252,27 @@ def write_accelerator_card_cfg(self, model):
247252
newline += '\n'
248253
for i in range(0, num_kernels):
249254
newline += 'slr=kernel_wrapper_{}:SLR{}\n'.format(i + 1, i)
255+
elif '# hls-fpga-machine-learning vivado directives' in line:
256+
newline = ''
257+
if directives:
258+
newline += '[vivado]\n'
259+
for x in directives:
260+
newline += x + '\n'
250261
else:
251262
newline = line
252263
fout.write(newline)
253264
f.close()
254265
fout.close()
255266

256-
# Copy hls_config.tcl
257-
filedir = os.path.dirname(os.path.abspath(__file__))
258-
srcpath = os.path.join(filedir, '../templates/vitis_accelerator/hls_config.tcl')
259-
dstpath = f'{model.config.get_output_dir()}/hls_config.tcl'
260-
copy(srcpath, dstpath)
261-
267+
# Write hls_config.tcl
268+
tcl_f = open(os.path.join(filedir, '../templates/vitis_accelerator/hls_config.tcl'))
269+
tcl_fout = open(f'{model.config.get_output_dir()}/hls_config.tcl', 'w')
270+
for line in tcl_f.readlines():
271+
newline = line
272+
tcl_fout.write(newline)
273+
tcl_fout.write('\nset_clock_uncertainty {}\n'.format(model.config.get_config_value('ClockUncertainty', '12.5%')))
274+
tcl_f.close()
275+
tcl_fout.close()
262276

263277
def write_nnet_utils_overrides(self, model):
264278
"""Override nnet_types.h pointer comparison

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