@@ -995,7 +995,7 @@ module Internal {
995995 // pre-SSA predicates
996996 private module PreCFG {
997997 private import semmle.code.csharp.controlflow.internal.PreBasicBlocks as PreBasicBlocks
998- private import semmle.code.csharp.controlflow.internal.PreSsa as PreSsa
998+ private import semmle.code.csharp.controlflow.internal.PreSsa
999999
10001000 /**
10011001 * Holds if pre-basic-block `bb` only is reached when guard `g` has abstract value `v`,
@@ -1081,25 +1081,25 @@ module Internal {
10811081
10821082 pragma [ noinline]
10831083 private predicate conditionalAssign0 (
1084- Guard guard , AbstractValue vGuard , PreSsa:: Definition def , Expr e , PreSsa:: Definition upd ,
1084+ Guard guard , AbstractValue vGuard , PreSsa:: PhiNode phi , Expr e , PreSsa:: Definition upd ,
10851085 PreBasicBlocks:: PreBasicBlock bbGuard
10861086 ) {
10871087 e = upd .getDefinition ( ) .getSource ( ) and
1088- upd = def . getAPhiInput ( ) and
1088+ upd = phi . getAnInput ( ) and
10891089 preControlsDirect ( guard , upd .getBasicBlock ( ) , vGuard ) and
10901090 bbGuard .getAnElement ( ) = guard and
1091- bbGuard .strictlyDominates ( def .getBasicBlock ( ) ) and
1092- not preControlsDirect ( guard , def .getBasicBlock ( ) , vGuard )
1091+ bbGuard .strictlyDominates ( phi .getBasicBlock ( ) ) and
1092+ not preControlsDirect ( guard , phi .getBasicBlock ( ) , vGuard )
10931093 }
10941094
10951095 pragma [ noinline]
10961096 private predicate conditionalAssign1 (
1097- Guard guard , AbstractValue vGuard , PreSsa:: Definition def , Expr e , PreSsa:: Definition upd ,
1097+ Guard guard , AbstractValue vGuard , PreSsa:: PhiNode phi , Expr e , PreSsa:: Definition upd ,
10981098 PreBasicBlocks:: PreBasicBlock bbGuard , PreSsa:: Definition other
10991099 ) {
1100- conditionalAssign0 ( guard , vGuard , def , e , upd , bbGuard ) and
1100+ conditionalAssign0 ( guard , vGuard , phi , e , upd , bbGuard ) and
11011101 other != upd and
1102- other = def . getAPhiInput ( )
1102+ other = phi . getAnInput ( )
11031103 }
11041104
11051105 pragma [ noinline]
@@ -1127,7 +1127,7 @@ module Internal {
11271127 ) {
11281128 conditionalAssign1 ( guard , vGuard , def , e , upd , bbGuard , other ) and
11291129 other .getBasicBlock ( ) .dominates ( bbGuard ) and
1130- not PreSsa :: ssaDefReachesEndOfBlock ( getConditionalSuccessor ( guard , vGuard ) , other , _ )
1130+ not other . isLiveAtEndOfBlock ( getConditionalSuccessor ( guard , vGuard ) )
11311131 }
11321132
11331133 /**
@@ -1315,14 +1315,14 @@ module Internal {
13151315 */
13161316 private PreSsa:: Definition getADefinition ( PreSsa:: Definition def , boolean fromBackEdge ) {
13171317 result = def and
1318- not exists ( def . getAPhiInput ( ) ) and
1318+ not def instanceof PreSsa :: PhiNode and
13191319 fromBackEdge = false
13201320 or
13211321 exists ( PreSsa:: Definition input , PreBasicBlocks:: PreBasicBlock pred , boolean fbe |
1322- input = def .getAPhiInput ( )
1322+ input = def .( PreSsa :: PhiNode ) . getAnInput ( )
13231323 |
13241324 pred = def .getBasicBlock ( ) .getAPredecessor ( ) and
1325- PreSsa :: ssaDefReachesEndOfBlock ( pred , input , _ ) and
1325+ input . isLiveAtEndOfBlock ( pred ) and
13261326 result = getADefinition ( input , fbe ) and
13271327 ( if def .getBasicBlock ( ) .dominates ( pred ) then fromBackEdge = true else fromBackEdge = fbe )
13281328 )
@@ -1446,7 +1446,7 @@ module Internal {
14461446 private predicate firstReadSameVarUniquePredecesssor (
14471447 PreSsa:: Definition def , AssignableRead read
14481448 ) {
1449- PreSsa :: firstReadSameVar ( def , read ) and
1449+ read = def . getAFirstRead ( ) and
14501450 not exists ( AssignableRead other | PreSsa:: adjacentReadPairSameVar ( other , read ) |
14511451 other != read
14521452 )
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