@@ -262,7 +262,9 @@ void SPIClass::transfer(const void* txbuf, void* rxbuf, size_t count,
262262 true ); // Increment dest address
263263 readChannel.setTrigger (getDMAC_ID_RX ());
264264 readChannel.setAction (DMA_TRIGGER_ACTON_BEAT);
265- readChannel.setCallback (dmaCallback);
265+ // Since all RX transfers involve a TX,
266+ // I don't think this separate callback is necessary.
267+ // readChannel.setCallback(dmaCallback);
266268 spiPtr[readChannel.getChannel ()] = this ;
267269 }
268270 }
@@ -328,43 +330,29 @@ void SPIClass::transfer(const void* txbuf, void* rxbuf, size_t count,
328330 }
329331
330332 // Issue 'bytesThisPass' bytes...
331- dma_busy = true ;
332333 if (rxbuf) {
333334 // Reading, or reading + writing.
334- // Set up read descriptor for reading .
335+ // Set up read descriptor.
335336 // Src address doesn't change, only dest & count.
336337 // DMA needs address set to END of buffer, so
337338 // increment the address now, before the transfer.
338339 readDescriptor->DSTADDR .reg += bytesThisPass;
339340 readDescriptor->BTCNT .reg = bytesThisPass;
340- if (txbuf) {
341- // Writing and reading simultaneously.
342- // Set up write descriptor for writing real data.
343- // Src address and count both change.
344- // DMA needs address set to END of buffer, so
345- // increment the address now, before the transfer.
346- writeDescriptor->SRCADDR .reg += bytesThisPass;
347- writeDescriptor->BTCNT .reg = bytesThisPass;
348- } else {
349- // Reading only.
350- // Write descriptor was already set up for dummy
351- // writes outside loop, only BTCNT needs set.
352- writeDescriptor->SRCADDR .reg = (uint32_t )&dum;
353- writeDescriptor->BTCNT .reg = bytesThisPass;
354- }
355341 // Start the RX job BEFORE the TX job!
356342 // That's the whole secret sauce to the two-channel transfer.
343+ // Nothing will actually happen until the write channel job
344+ // is also started.
357345 readChannel.startJob ();
358- } else if (txbuf) {
359- // Writing only.
360- // Set up write descriptor for writing real data.
346+ }
347+ if (txbuf) {
361348 // DMA needs address set to END of buffer, so
362349 // increment the address now, before the transfer.
363350 writeDescriptor->SRCADDR .reg += bytesThisPass;
364- writeDescriptor->BTCNT .reg = bytesThisPass;
365351 }
352+ writeDescriptor->BTCNT .reg = bytesThisPass;
353+ dma_busy = true ;
366354 writeChannel.startJob ();
367- count -= bytesThisPass;
355+ count -= bytesThisPass;
368356 if (block) {
369357 while (dma_busy);
370358 }
0 commit comments