[ImportVerilog] Functionality for real number format specifiers not defined

[liamslj13]

I initially added added some basic support for real number format specifiers in PR #8848 some months ago. Due to school I have been busy and unable to follow up. I believe the functionality still needs to be implemented. I apologize for forgetting about this until now. More info at IEEE 1800-2017 § 21.2.1.2 "Format specifications".

[fabianschuiki]

Hey @liamslj13, sorry for the delay! I remember that @Scheremo added a few things around the real type, but we might not yet have support for the real number formatters. Or we might have support in the Moore dialect, but not yet in the Sim dialect.

[liamslj13]

No problems at all, I apologize for delays on my end as well. I have looked through some of the commits that Scheremo has made and I think they are definitely related but they may not directly answer to the issue here. I will need to take a closer look after exams are over though. Thank you for the reply, and I apologize again for how late this is becoming!

[fabianschuiki]

Haha no worries at all, there's only so much spare time one has. Feel free to ping me or @Scheremo if you need some pointers or want to chat about what may still be missing 😃