Project by Max Nigri — GitHub · LinkedIn
This repository represents the results of two years of intense development, creating the first logic simulator based on a dedicated hardware architecture rather than standard software.
In 2001, right on the precipice of the dot-com collapse, I was serving as an ASIC Director for a wireless communication startup called Bungee. I was planning for a group of five engineers handling front-end digital design. In those days, there was no cloud; we purchased personal SUN Sparc stations—expensive hardware, yet practically cheap compared to the costs of the EDA software running on them.
I needed five logic simulators. It was December, close to the end of the year, and I engaged in aggressive negotiations with Cadence. I managed to press the salesman for a discount and even secured a seat for their "Build Gates" synthesizer as a bonus. The final price tag? $250,000. Looking back, after all that aggressive negotiation for a discount, I'm still not sure who was fooling whom.
That was $50,000 per simulation seat. It was a massive amount of money, but at the time, chips were small enough that you could simulate the entire design with a single simulator instance. It was a productive tool, and the price made sense.
Less than a year later, the bubble burst. The startup shut down, and those licenses vanished into thin air. Since there was no way to port them to another company.
That story never left my mind. I began to wonder about the nature of the EDA industry—it seemed like an industry designed to print money. I kept tracking it as the years passed.
As process technology advanced, we began making complex chips with exponentially more logic. But a problem emerged: with these massive chips, we could no longer simulate the whole design on a single seat. Designers started breaking simulation models into smaller, fragmented parts. Each part brought its own test bench maintenance overhead, and each model consumed a simulator seat and server resources.
While the price per seat dropped significantly (from $50k to roughly $500, or "all you can eat" models for giants like Intel), the fundamental technical problem remained. Simulation dominates the project length and cost. Worse yet, server CPU clock speeds have effectively flatlined at ~2GHz since 2010. The industry offers more cores, but logic simulation is inherently a single-thread workload. More cores don’t help us run faster.
There was a clear call for innovation: a need for simulation technology that improves performance by orders of magnitude, not just incremental steps.
In 2013, seeing the opportunity ahead, I quit my day job as a chip designer/architect and began a two-year journey to design a Proof of Concept (POC) for a radically new type of logic simulator.
I deeply examined the standard simulation algorithms and drew a new data path architecture that implements the simulation flow directly in Hardware rather than Software.
The reference platform here is not a standard CPU. It is a new breed of machine—a Domain Specific Compute Architecture. I stripped away the semantics of general-purpose CPUs (MMUs, multi-level caches, OS locks, multi-core management, etc.) and built a data path architecture composed of novel data structures, FSMs, NoCs, FIFOs, priority queues, custom micro-code driven processors, etc. along with a simple compiler to compile user design and testbecnh
This architecture is implemented on a chip (ASIC, or FPGA for the POC), attached to large banks of memory.
How it works: The user's design and test bench are compiled into a binary image. This image is loaded into the memory banks next to the simulator chip before the simulation starts. Crucially, the customer’s design is not synthesized into the simulation chip itself. The chip remains static; the cutomer compiled RTL and verification logic resides in the memory next to the simulator chip.
The POC simulator supports 4-value logic (#34) and operates without the constraints of a designated clock or reset signals.
To bring this to life, I utilized an FPGA board with a Spartan 6 and 128MB of attached memory. The board connects to a host PC via USB3.
To complete the ecosystem, I constructed a GUI application with even a wave viewer (wave viewer - Courtesy of my colleague, Misha Blech). The result is that I have successfully reconstructed the typical logic simulation experience design engineers are used to—but this time, it's powered by a custom engine under the hood. Crucially, this setup delivers a significant, enhanced speedup compared to state-of-the-art (SOTA) commercial simulators.
Below is a brief description of the directory structure found in this repository.
| Directory/File | Description |
|---|---|
| README.md | This primary documentation file. |
| all_files.txt | Listing of all files from the top directory, generated by find . -type f. Used by analyze_files.py to determine which files should be tracked. |
| analyze_files.py | Python script used to decide which files to track, typically via git add. |
| ok_artsim.xise | The top-level Xilinx ISE project file for the hardware simulator implementation (targeting the Spartan 6). |
| benchmarks/ | Contains various logic designs and circuits used for performance benchmarking against commercial SOTA simulators. |
| c#/ | Source code for the Host PC GUI application (likely the wave viewer and control interface). |
| cxx/ | Source code for the Host PC console application (contains the logic to send the compiled image to the simulator board and receive the wave output file). |
| docs_2015/ | Archival documentation and design specifications from the initial 2013-2015 Proof of Concept development phase. |
| ipcore_dir/ | Xilinx IP Core directory containing generated building blocks (FIFOs, BRAMs, clock managers) used in the FPGA implementation. |
| ise_work/ | Working directory for the Xilinx ISE synthesis and implementation flow. |
| iseconfig/ | Configuration files related to the Xilinx ISE build environment. |
| ok_files/ | Contains all data, drivers, and DLLs from the Opal Kelly board manufacturer. |
| ref_model/ | A software reference model (Perl) used to verify the correctness of the hardware simulation logic. |
| rtl/ | Core Register Transfer Level (RTL) source code (VHDL/Verilog) defining the Domain Specific Compute Architecture. |
| sim/ | Testbench and environment files used for simulating the core RTL hardware design before FPGA synthesis. |
| side_models/ | Miscellaneous block-level models used during the early development stages. |
| test_cases/ | HDL user designs and testbenches used to verify the functional correctness of the custom simulator. |
| utils/ | General utility scripts, used for format conversion and automating the design flow (CAD). |