From 03553961a9401fa8668db4538bf0294b1ab8e49d Mon Sep 17 00:00:00 2001 From: Domagoj Stolfa Date: Thu, 27 Mar 2025 11:34:38 +0000 Subject: [PATCH] deps: V8: cherry-pick 1441665e0d87 Original commit message: [riscv] Fix the RISC-V build. Due to recent changes, there were missing implementations of various methods needed in the simulator and Maglev. Additionally, a static_cast is needed in the assembler to silence a warning. Port commit dfc894cd22d86ce42830e3bfdf485d963f6396ad Port commit c33af9bd408eadd6b62571f862bcb5b763c98ad9 Change-Id: Ie37a1cfa8225fc12f367ff62139cc7cd8fa967d0 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/6396542 Reviewed-by: Victor Gomes Commit-Queue: Yahan Lu (LuYahan) Reviewed-by: Ji Qiu Reviewed-by: Yahan Lu (LuYahan) Cr-Commit-Position: refs/heads/main@{#99706} Refs: https://github.com/v8/v8/commit/1441665e0d87b541932390385101840758b44924 --- common.gypi | 2 +- deps/v8/AUTHORS | 1 + .../src/codegen/riscv/assembler-riscv-inl.h | 5 +-- deps/v8/src/execution/riscv/simulator-riscv.h | 1 + deps/v8/src/maglev/riscv/maglev-ir-riscv.cc | 34 +++++++++++++++++++ 5 files changed, 40 insertions(+), 3 deletions(-) diff --git a/common.gypi b/common.gypi index db1625378697d9..eac3302d385349 100644 --- a/common.gypi +++ b/common.gypi @@ -38,7 +38,7 @@ # Reset this number to 0 on major V8 upgrades. # Increment by one for each non-official patch applied to deps/v8. - 'v8_embedder_string': '-node.37', + 'v8_embedder_string': '-node.38', ##### V8 defaults for Node.js ##### diff --git a/deps/v8/AUTHORS b/deps/v8/AUTHORS index e5a0957b3a928e..280e33e6841cc1 100644 --- a/deps/v8/AUTHORS +++ b/deps/v8/AUTHORS @@ -334,3 +334,4 @@ Kotaro Ohsugi Jing Peiyang magic-akari Ryuhei Shima +Domagoj Stolfa diff --git a/deps/v8/src/codegen/riscv/assembler-riscv-inl.h b/deps/v8/src/codegen/riscv/assembler-riscv-inl.h index d5e11e562b334c..2d73dc572ec2d5 100644 --- a/deps/v8/src/codegen/riscv/assembler-riscv-inl.h +++ b/deps/v8/src/codegen/riscv/assembler-riscv-inl.h @@ -115,8 +115,9 @@ void Assembler::set_target_compressed_address_at( Address pc, Address constant_pool, Tagged_t target, WritableJitAllocation* jit_allocation, ICacheFlushMode icache_flush_mode) { if (COMPRESS_POINTERS_BOOL) { - Assembler::set_uint32_constant_at(pc, constant_pool, target, jit_allocation, - icache_flush_mode); + Assembler::set_uint32_constant_at(pc, constant_pool, + static_cast(target), + jit_allocation, icache_flush_mode); } else { UNREACHABLE(); } diff --git a/deps/v8/src/execution/riscv/simulator-riscv.h b/deps/v8/src/execution/riscv/simulator-riscv.h index 0ec51ff3db967c..82164754a904e2 100644 --- a/deps/v8/src/execution/riscv/simulator-riscv.h +++ b/deps/v8/src/execution/riscv/simulator-riscv.h @@ -538,6 +538,7 @@ class Simulator : public SimulatorBase { // Return central stack view, without additional safety margins. // Users, for example wasm::StackMemory, can add their own. base::Vector GetCentralStackView() const; + static constexpr int JSStackLimitMargin() { return kAdditionalStackMargin; } void IterateRegistersAndStack(::heap::base::StackVisitor* visitor); diff --git a/deps/v8/src/maglev/riscv/maglev-ir-riscv.cc b/deps/v8/src/maglev/riscv/maglev-ir-riscv.cc index 53c8c3ce3ac667..2bf5e1f5089825 100644 --- a/deps/v8/src/maglev/riscv/maglev-ir-riscv.cc +++ b/deps/v8/src/maglev/riscv/maglev-ir-riscv.cc @@ -224,6 +224,40 @@ void CheckedIntPtrToInt32::GenerateCode(MaglevAssembler* masm, Operand(std::numeric_limits::min())); } +void CheckFloat64SameValue::SetValueLocationConstraints() { + UseRegister(target_input()); + // We need two because LoadFPRImmediate needs to acquire one as well in the + // case where value() is not 0.0 or -0.0. + set_temporaries_needed((value().get_scalar() == 0) ? 1 : 2); + set_double_temporaries_needed( + value().is_nan() || (value().get_scalar() == 0) ? 0 : 1); +} + +void CheckFloat64SameValue::GenerateCode(MaglevAssembler* masm, + const ProcessingState& state) { + Label* fail = __ GetDeoptLabel(this, deoptimize_reason()); + MaglevAssembler::TemporaryRegisterScope temps(masm); + DoubleRegister target = ToDoubleRegister(target_input()); + if (value().is_nan()) { + __ JumpIfNotNan(target, fail); + } else { + DoubleRegister double_scratch = temps.AcquireScratchDouble(); + Register scratch = temps.AcquireScratch(); + __ Move(double_scratch, value().get_scalar()); + __ CompareF64(scratch, EQ, double_scratch, target); + __ BranchFalseF(scratch, fail); + if (value().get_scalar() == 0) { // +0.0 or -0.0. + __ MacroAssembler::Move(scratch, target); + __ And(scratch, scratch, Operand(1ULL << 63)); + if (value().get_bits() == 0) { + __ BranchTrueF(scratch, fail); + } else { + __ BranchFalseF(scratch, fail); + } + } + } +} + void Int32AddWithOverflow::SetValueLocationConstraints() { UseRegister(left_input()); UseRegister(right_input());