From ebd9a5a7b1c6ab692b12da84c924b2f500b3b366 Mon Sep 17 00:00:00 2001
From: minhtran <trankhaiminh0911@gmail.com>
Date: Sat, 25 Jan 2025 09:02:18 +0700
Subject: [PATCH] Add SystemVerilog function/task_declaration to context

---
 queries/verilog/context.scm | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/queries/verilog/context.scm b/queries/verilog/context.scm
index fa08586d..05eca478 100644
--- a/queries/verilog/context.scm
+++ b/queries/verilog/context.scm
@@ -2,3 +2,5 @@
 (conditional_statement) @context
 (loop_generate_construct) @context
 (hierarchical_instance) @context
+(function_declaration) @context
+(task_declaration) @context