drm/rp1: rp1-dsi: Add support for inverting lane polarities

The D-PHY on RP1 support lane polarity swapping, and there
is a standard device tree mechanism for configuring this,
so tie the two together.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>

Author: 6by9

drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.c

@@ -417,9 +417,11 @@ static const struct mipi_dsi_host_ops rp1dsi_mipi_dsi_host_ops = {
 static int rp1dsi_platform_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
+	struct device_node *node = dev->of_node;
+	struct device_node *endpoint;
 	struct drm_device *drm;
 	struct rp1_dsi *dsi;
-	int i, ret;
+	int i, nr_lanes, ret;
 
 	drm = drm_dev_alloc(&rp1dsi_driver, dev);
 	if (IS_ERR(drm)) {
@@ -459,6 +461,12 @@ static int rp1dsi_platform_probe(struct platform_device *pdev)
 		}
 	}
 
+	endpoint = of_graph_get_endpoint_by_regs(node, 0, -1);
+	nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
+	if (nr_lanes > 0 && nr_lanes <= 4)
+		of_property_read_u32_array(endpoint, "lane-polarities",
+					   dsi->lane_polarities, nr_lanes + 1);
+
 	for (i = 0; i < RP1DSI_NUM_HW_BLOCKS; i++) {
 		dsi->hw_base[i] =
 			devm_ioremap_resource(dev,

drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.h

@@ -49,6 +49,9 @@ struct rp1_dsi {
 	/* Clocks. We need DPI clock; the others are frequency references */
 	struct clk *clocks[RP1DSI_NUM_CLOCKS];
 
+	/* Device tree parsed information */
+	u32 lane_polarities[5];
+
 	/* Block (DSI DMA, DSI Host) base addresses, and current state */
 	void __iomem *hw_base[RP1DSI_NUM_HW_BLOCKS];
 	u32 cur_fmt;

drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c

@@ -145,11 +145,18 @@
 #define DSI_PHYRSTZ_FORCEPLL_LSB 3
 #define DSI_PHYRSTZ_FORCEPLL_BITS  BIT(DSI_PHYRSTZ_FORCEPLL_LSB)
 
+#define DPHY_CLK_PN_SWAP		0x35
+
 #define DPHY_HS_RX_CTRL_LANE0_OFFSET  0x44
 #define DPHY_PLL_INPUT_DIV_OFFSET 0x17
 #define DPHY_PLL_LOOP_DIV_OFFSET 0x18
 #define DPHY_PLL_DIV_CTRL_OFFSET 0x19
 
+#define DPHY_D0_PN_SWAP		0x45
+#define DPHY_D1_PN_SWAP		0x55
+#define DPHY_D2_PN_SWAP		0x85
+#define DPHY_D3_PN_SWAP		0x95
+
 #define DPHY_PLL_BIAS_OFFSET 0x10
 #define DPHY_PLL_BIAS_VCO_RANGE_LSB 3
 #define DPHY_PLL_BIAS_USE_PROGRAMMED_VCO_RANGE BIT(7)
@@ -1290,6 +1297,13 @@ static u32 dphy_init(struct rp1_dsi *dsi, u32 ref_freq, u32 vco_freq)
 	udelay(1);
 	/* Since we are in DSI (not CSI2) mode here, start the PLL */
 	actual_vco_freq = dphy_configure_pll(dsi, ref_freq, vco_freq);
+
+	dphy_transaction(dsi, DPHY_CLK_PN_SWAP, !!dsi->lane_polarities[0]);
+	dphy_transaction(dsi, DPHY_D0_PN_SWAP, !!dsi->lane_polarities[1]);
+	dphy_transaction(dsi, DPHY_D1_PN_SWAP, !!dsi->lane_polarities[2]);
+	dphy_transaction(dsi, DPHY_D2_PN_SWAP, !!dsi->lane_polarities[3]);
+	dphy_transaction(dsi, DPHY_D3_PN_SWAP, !!dsi->lane_polarities[4]);
+
 	udelay(1);
 	/* Unreset */
 	DSI_WRITE(DSI_PHYRSTZ, DSI_PHYRSTZ_SHUTDOWNZ_BITS);