[cc] aarch64 fixes, CI buff

Author: jgarzik

.github/workflows/TestingCI.yml

@@ -6,12 +6,24 @@ on:
 
 env:
   CARGO_TERM_COLOR: always
+  RUST_BACKTRACE: 1
 
 jobs:
   linux-ubuntu:
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v4
+      - name: System info
+        run: |
+          echo "=== Architecture ==="
+          uname -a
+          echo "=== CPU ==="
+          lscpu | head -20
+          echo "=== Toolchain ==="
+          rustc --version
+          cargo --version
+          cc --version || true
+          as --version || true
       - name: Fetch
         run: cargo fetch
       - name: Build
@@ -39,9 +51,26 @@ jobs:
         with:
           path: ~/.cargo/registry/cache
           key: registry-${{ runner.os }}-${{ steps.rust-version.outputs.version }}-${{ hashFiles('Cargo.lock') }}
+      - name: System info
+        run: |
+          echo "=== Architecture ==="
+          uname -a
+          arch
+          echo "=== Toolchain ==="
+          rustc --version
+          cargo --version
+          cc --version || true
+          as -version || true
+          echo "=== Xcode ==="
+          xcodebuild -version || true
       - name: Fetch
         run: cargo fetch
       - name: Build
         run: cargo build --release --verbose
       - name: Run tests
         run: cargo test --release --verbose
+      - name: Run cc tests (detailed)
+        if: failure()
+        run: |
+          echo "=== Re-running cc tests with more detail ==="
+          cargo test --release -p posixutils-cc --verbose -- --nocapture --test-threads=1 2>&1 | head -500

cc/arch/aarch64/codegen.rs

@@ -3457,14 +3457,25 @@ impl Aarch64CodeGen {
         // Load source to FP register
         self.emit_fp_move(src, VReg::V17, src_size, frame_size);
 
-        // Convert between float sizes
+        // Convert between float sizes if they differ
         // fcvt: convert between single and double precision
-        self.push_lir(Aarch64Inst::Fcvt {
-            src_size: src_fp_size,
-            dst_size: dst_fp_size,
-            src: VReg::V17,
-            dst: dst_vreg,
-        });
+        // Note: On Apple Silicon, long double == double (both 64-bit),
+        // so skip fcvt when sizes are equal to avoid invalid "fcvt d, d"
+        if src_fp_size != dst_fp_size {
+            self.push_lir(Aarch64Inst::Fcvt {
+                src_size: src_fp_size,
+                dst_size: dst_fp_size,
+                src: VReg::V17,
+                dst: dst_vreg,
+            });
+        } else if dst_vreg != VReg::V17 {
+            // Same size, just move if needed
+            self.push_lir(Aarch64Inst::FmovReg {
+                size: dst_fp_size,
+                src: VReg::V17,
+                dst: dst_vreg,
+            });
+        }
 
         if !matches!(&dst_loc, Loc::VReg(v) if *v == dst_vreg) {
             self.emit_fp_move_to_loc(dst_vreg, &dst_loc, dst_size, frame_size);