2222
2323#include <sof/lib/memory.h>
2424
25+ #if CONFIG_UAOL_INTEL_ADSP
26+ #include <zephyr/drivers/uaol.h>
27+ #endif
28+
2529#include <ipc4/base_fw.h>
2630#include <rimage/sof/user/manifest.h>
2731
@@ -30,6 +34,20 @@ struct ipc4_modules_info {
3034 struct sof_man_module modules [0 ];
3135} __packed __aligned (4 );
3236
37+ struct ipc4_uaol_link_capabilities {
38+ uint32_t input_streams_supported : 4 ;
39+ uint32_t output_streams_supported : 4 ;
40+ uint32_t bidirectional_streams_supported : 5 ;
41+ uint32_t rsvd : 19 ;
42+ uint32_t max_tx_fifo_size ;
43+ uint32_t max_rx_fifo_size ;
44+ } __packed __aligned (4 );
45+
46+ struct ipc4_uaol_capabilities {
47+ uint32_t link_count ;
48+ struct ipc4_uaol_link_capabilities link_caps [];
49+ } __packed __aligned (4 );
50+
3351/*
3452 * TODO: default to value of ACE1.x platforms. This is defined
3553 * in multiple places in Zephyr, mm_drv_intel_adsp.h and
@@ -54,7 +72,7 @@ int basefw_vendor_fw_config(uint32_t *data_offset, char *data)
5472 tlv_value_uint32_set (tuple , IPC4_SLOW_CLOCK_FREQ_HZ_FW_CFG , IPC4_ALH_CAVS_1_8 );
5573
5674 tuple = tlv_next (tuple );
57- tlv_value_uint32_set (tuple , IPC4_UAOL_SUPPORT , 0 );
75+ tlv_value_uint32_set (tuple , IPC4_UAOL_SUPPORT , 1 );
5876
5977 tuple = tlv_next (tuple );
6078 tlv_value_uint32_set (tuple , IPC4_ALH_SUPPORT_LEVEL_FW_CFG , IPC4_ALH_CAVS_1_8 );
@@ -65,6 +83,41 @@ int basefw_vendor_fw_config(uint32_t *data_offset, char *data)
6583 return 0 ;
6684}
6785
86+ #if CONFIG_UAOL_INTEL_ADSP
87+
88+ #define UAOL_DEV (node ) DEVICE_DT_GET(node),
89+ static const struct device * uaol_devs [] = {
90+ DT_FOREACH_STATUS_OKAY (intel_adsp_uaol , UAOL_DEV )
91+ };
92+
93+ static void tlv_value_set_uaol_caps (struct sof_tlv * tuple , uint32_t type )
94+ {
95+ unsigned int dev_count = ARRAY_SIZE (uaol_devs );
96+ struct uaol_capabilities dev_cap ;
97+ struct ipc4_uaol_capabilities * caps = (struct ipc4_uaol_capabilities * )tuple -> value ;
98+ size_t caps_size = offsetof(struct ipc4_uaol_capabilities , link_caps [dev_count ]);
99+ unsigned int i ;
100+ int ret ;
101+
102+ memset (caps , 0 , caps_size );
103+
104+ caps -> link_count = dev_count ;
105+ for (i = 0 ; i < dev_count ; i ++ ) {
106+ ret = uaol_get_capabilities (uaol_devs [i ], & dev_cap );
107+ if (ret )
108+ continue ;
109+
110+ caps -> link_caps [i ].input_streams_supported = dev_cap .input_streams ;
111+ caps -> link_caps [i ].output_streams_supported = dev_cap .output_streams ;
112+ caps -> link_caps [i ].bidirectional_streams_supported = dev_cap .bidirectional_streams ;
113+ caps -> link_caps [i ].max_tx_fifo_size = dev_cap .max_tx_fifo_size ;
114+ caps -> link_caps [i ].max_rx_fifo_size = dev_cap .max_rx_fifo_size ;
115+ }
116+
117+ tlv_value_set (tuple , type , caps_size , caps );
118+ }
119+ #endif
120+
68121int basefw_vendor_hw_config (uint32_t * data_offset , char * data )
69122{
70123 struct sof_tlv * tuple = (struct sof_tlv * )data ;
@@ -93,6 +146,11 @@ int basefw_vendor_hw_config(uint32_t *data_offset, char *data)
93146 tlv_value_uint32_set (tuple , IPC4_I2S_CAPS_HW_CFG , I2S_VER_30_PTL );
94147#endif
95148
149+ #if CONFIG_UAOL_INTEL_ADSP
150+ tuple = tlv_next (tuple );
151+ tlv_value_set_uaol_caps (tuple , IPC4_UAOL_CAPS_HW_CFG );
152+ #endif
153+
96154 tuple = tlv_next (tuple );
97155 * data_offset = (int )((char * )tuple - data );
98156
@@ -358,6 +416,10 @@ int basefw_vendor_dma_control(uint32_t node_id, const char *config_data, size_t
358416 case ipc4_i2s_link_input_class :
359417 type = DAI_INTEL_SSP ;
360418 break ;
419+ case ipc4_alh_uaol_stream_link_output_class :
420+ case ipc4_alh_uaol_stream_link_input_class :
421+ type = DAI_INTEL_UAOL ;
422+ break ;
361423 default :
362424 return IPC4_INVALID_RESOURCE_ID ;
363425 }
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