intel: nvl-s: Add Nova Lake -S variant

Adds Nova Lake -S (aka NVL-S, Nova Lake PCH-S, NVPS) variant of Nova Lake
ACE 4.x SoC.

  NVL-S  vs  NVL:
      2  vs  4 cores,
438.857  vs  614.4 MHz,
   2048  vs  4608 KB L2 HP SRAM.

Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>

Author: serhiy-katsyuba-intel

app/boards/intel_adsp_ace40_nvls.conf

@@ -0,0 +1,88 @@
+CONFIG_NOVALAKE=y
+CONFIG_RIMAGE_SIGNING_SCHEMA="nvl"
+
+# SOF / IPC configuration
+CONFIG_IPC_MAJOR_4=y
+CONFIG_IPC4_BASE_FW_INTEL=y
+
+# SOF / audio pipeline and module settings
+CONFIG_COMP_SRC=y
+CONFIG_MM_DRV=y
+CONFIG_COMP_ARIA=y
+CONFIG_COMP_CHAIN_DMA=y
+CONFIG_COMP_DRC=y
+CONFIG_COMP_KPB=y
+CONFIG_COMP_SRC_IPC4_FULL_MATRIX=y
+CONFIG_COMP_UP_DOWN_MIXER=y
+CONFIG_COMP_VOLUME_WINDOWS_FADE=y
+CONFIG_FORMAT_CONVERT_HIFI3=n
+CONFIG_FORMAT_U8=y
+CONFIG_PCM_CONVERTER_FORMAT_S16_C16_AND_S16_C32=y
+CONFIG_PCM_CONVERTER_FORMAT_S16_C32_AND_S32_C32=y
+CONFIG_PCM_CONVERTER_FORMAT_S16_C32_AND_S24_C32=y
+CONFIG_PCM_CONVERTER_FORMAT_S24_C24_AND_S24_C32=y
+CONFIG_PCM_CONVERTER_FORMAT_S24_C32_AND_S24_C24=y
+CONFIG_PCM_CONVERTER_FORMAT_S16_C32_AND_S16_C32=y
+CONFIG_PCM_CONVERTER_FORMAT_U8=y
+CONFIG_PIPELINE_2_0=y
+
+# SOF / infrastructure
+CONFIG_PROBE=y
+CONFIG_PROBE_DMA_MAX=2
+CONFIG_ZEPHYR_DP_SCHEDULER=y
+CONFIG_ZEPHYR_NATIVE_DRIVERS=y
+
+# SOF / loadable modules
+CONFIG_INTEL_MODULES=y
+CONFIG_LIBRARY_MANAGER=y
+
+# SOF / logging
+CONFIG_TRACE=n
+CONFIG_SOF_LOG_LEVEL_INF=y
+CONFIG_ZEPHYR_LOG=y
+
+# Zephyr / OS features
+CONFIG_HEAP_MEM_POOL_SIZE=8192
+CONFIG_L3_HEAP=y
+
+# Zephyr / device drivers
+CONFIG_CLOCK_CONTROL=y
+CONFIG_CLOCK_CONTROL_ADSP=y
+CONFIG_DAI=y
+CONFIG_DAI_INIT_PRIORITY=70
+CONFIG_DAI_INTEL_DMIC=y
+CONFIG_DAI_DMIC_HW_IOCLK=38400000
+CONFIG_DAI_INTEL_DMIC_NHLT=y
+CONFIG_DAI_DMIC_HAS_OWNERSHIP=n
+CONFIG_DAI_DMIC_HAS_MULTIPLE_LINE_SYNC=y
+CONFIG_DAI_INTEL_SSP=y
+CONFIG_DMA=y
+CONFIG_DMA_INTEL_ADSP_GPDMA=n
+CONFIG_INTEL_ADSP_IPC=y
+CONFIG_INTEL_ADSP_TIMER=y
+CONFIG_MM_DRV_INTEL_ADSP_TLB_REMAP_UNUSED_RAM=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=12000
+
+# Zephyr / power settings
+CONFIG_ADSP_IMR_CONTEXT_SAVE=y
+CONFIG_PM=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_DEVICE_RUNTIME=y
+CONFIG_PM_DEVICE_POWER_DOMAIN=y
+CONFIG_PM_DEVICE_SYSTEM_MANAGED=y
+CONFIG_PM_POLICY_CUSTOM=y
+CONFIG_PM_PREWAKEUP_CONV_MODE_CEIL=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_POWER_DOMAIN_INTEL_ADSP=y
+CONFIG_SRAM_RETENTION_MODE=n
+
+# Zephyr / logging
+CONFIG_LOG=y
+CONFIG_LOG_BACKEND_ADSP=n
+CONFIG_LOG_BACKEND_ADSP_MTRACE=y
+CONFIG_LOG_FUNC_NAME_PREFIX_ERR=y
+CONFIG_LOG_FUNC_NAME_PREFIX_WRN=y
+CONFIG_LOG_FUNC_NAME_PREFIX_INF=y
+CONFIG_LOG_FUNC_NAME_PREFIX_DBG=y
+CONFIG_LOG_MODE_DEFERRED=y
+CONFIG_WINSTREAM_CONSOLE=n

app/sample.yaml

@@ -19,6 +19,7 @@ tests:
       - intel_adsp/ace30/wcl
       - intel_adsp/ace30/wcl/sim
       - intel_adsp/ace40/nvl
+      - intel_adsp/ace40/nvls
       - imx8qm_mek/mimx8qm6/adsp
       - imx8qxp_mek/mimx8qx6/adsp
       - imx8mp_evk/mimx8ml8/adsp

scripts/xtensa-build-zephyr.py

@@ -186,6 +186,12 @@ class PlatformConfig:
 		"ace4px_HiFi5MMU_PIF_nlib",
 		ipc4 = True
 	),
+	"nvl-s" : PlatformConfig(
+		"intel", "intel_adsp/ace40/nvls",
+		f"RI-2022.10{xtensa_tools_version_postfix}",
+		"ace4px_HiFi5MMU_PIF_nlib",
+		ipc4 = True
+	),
 
 	#  NXP platforms
 	"imx8" : PlatformConfig(