2323
2424#include <sof/lib/memory.h>
2525
26+ #if CONFIG_UAOL_INTEL_ADSP
27+ #include <zephyr/drivers/uaol.h>
28+ #endif
29+
2630#include <ipc4/base_fw.h>
2731#include <ipc4/alh.h>
2832#include <rimage/sof/user/manifest.h>
@@ -33,6 +37,20 @@ struct ipc4_modules_info {
3337 struct sof_man_module modules [0 ];
3438} __packed __aligned (4 );
3539
40+ struct ipc4_uaol_link_capabilities {
41+ uint32_t input_streams_supported : 4 ;
42+ uint32_t output_streams_supported : 4 ;
43+ uint32_t bidirectional_streams_supported : 5 ;
44+ uint32_t rsvd : 19 ;
45+ uint32_t max_tx_fifo_size ;
46+ uint32_t max_rx_fifo_size ;
47+ } __packed __aligned (4 );
48+
49+ struct ipc4_uaol_capabilities {
50+ uint32_t link_count ;
51+ struct ipc4_uaol_link_capabilities link_caps [];
52+ } __packed __aligned (4 );
53+
3654/*
3755 * TODO: default to value of ACE1.x platforms. This is defined
3856 * in multiple places in Zephyr, mm_drv_intel_adsp.h and
@@ -61,7 +79,7 @@ int basefw_vendor_fw_config(uint32_t *data_offset, char *data)
6179 tlv_value_uint32_set (tuple , IPC4_SLOW_CLOCK_FREQ_HZ_FW_CFG , IPC4_ALH_CAVS_1_8 );
6280
6381 tuple = tlv_next (tuple );
64- tlv_value_uint32_set (tuple , IPC4_UAOL_SUPPORT , 0 );
82+ tlv_value_uint32_set (tuple , IPC4_UAOL_SUPPORT , 1 );
6583
6684 tuple = tlv_next (tuple );
6785 tlv_value_uint32_set (tuple , IPC4_ALH_SUPPORT_LEVEL_FW_CFG , IPC4_ALH_CAVS_1_8 );
@@ -72,6 +90,41 @@ int basefw_vendor_fw_config(uint32_t *data_offset, char *data)
7290 return 0 ;
7391}
7492
93+ #if CONFIG_UAOL_INTEL_ADSP
94+
95+ #define UAOL_DEV (node ) DEVICE_DT_GET(node),
96+ static const struct device * uaol_devs [] = {
97+ DT_FOREACH_STATUS_OKAY (intel_adsp_uaol , UAOL_DEV )
98+ };
99+
100+ static void tlv_value_set_uaol_caps (struct sof_tlv * tuple , uint32_t type )
101+ {
102+ const unsigned int dev_count = ARRAY_SIZE (uaol_devs );
103+ struct uaol_capabilities dev_cap ;
104+ struct ipc4_uaol_capabilities * caps = (struct ipc4_uaol_capabilities * )tuple -> value ;
105+ size_t caps_size = offsetof(struct ipc4_uaol_capabilities , link_caps [dev_count ]);
106+ unsigned int i ;
107+ int ret ;
108+
109+ memset (caps , 0 , caps_size );
110+
111+ caps -> link_count = dev_count ;
112+ for (i = 0 ; i < dev_count ; i ++ ) {
113+ ret = uaol_get_capabilities (uaol_devs [i ], & dev_cap );
114+ if (ret )
115+ continue ;
116+
117+ caps -> link_caps [i ].input_streams_supported = dev_cap .input_streams ;
118+ caps -> link_caps [i ].output_streams_supported = dev_cap .output_streams ;
119+ caps -> link_caps [i ].bidirectional_streams_supported = dev_cap .bidirectional_streams ;
120+ caps -> link_caps [i ].max_tx_fifo_size = dev_cap .max_tx_fifo_size ;
121+ caps -> link_caps [i ].max_rx_fifo_size = dev_cap .max_rx_fifo_size ;
122+ }
123+
124+ tlv_value_set (tuple , type , caps_size , caps );
125+ }
126+ #endif
127+
75128int basefw_vendor_hw_config (uint32_t * data_offset , char * data )
76129{
77130 struct sof_tlv * tuple = (struct sof_tlv * )data ;
@@ -100,6 +153,11 @@ int basefw_vendor_hw_config(uint32_t *data_offset, char *data)
100153 tlv_value_uint32_set (tuple , IPC4_I2S_CAPS_HW_CFG , I2S_VER_30_PTL );
101154#endif
102155
156+ #if CONFIG_UAOL_INTEL_ADSP
157+ tuple = tlv_next (tuple );
158+ tlv_value_set_uaol_caps (tuple , IPC4_UAOL_CAPS_HW_CFG );
159+ #endif
160+
103161 tuple = tlv_next (tuple );
104162 * data_offset = (int )((char * )tuple - data );
105163
@@ -376,6 +434,10 @@ int basefw_vendor_dma_control(uint32_t node_id, const char *config_data, size_t
376434 case ipc4_i2s_link_input_class :
377435 type = DAI_INTEL_SSP ;
378436 break ;
437+ case ipc4_alh_uaol_stream_link_output_class :
438+ case ipc4_alh_uaol_stream_link_input_class :
439+ type = DAI_INTEL_UAOL ;
440+ break ;
379441 default :
380442 return IPC4_INVALID_RESOURCE_ID ;
381443 }
0 commit comments