app: boards: imx95_evk: set host and edma buffer alignment to 32

SOF performs cache invalidation operations on the DAI and
HOST DMA buffers to make sure that the firmware doesn't
read/write stale data in the areas shared with the DMAC and Linux.
Currently, these buffers use an 8-byte alignment.

The Cortex-M7 data cache line size is 32-byte. Given this and
the fact that the buffers have an 8-byte alignment what could
end up happening is invalidating useful data by mistake.

In the case of imx95 what seems to happen is the allocated heap
chunk headers get corrupted leading to one of the following
assertions failing:
	1) CHECK(b->next != 0) (from free_list_remove_bidx())
	2) CHECK(chunk_size(h, c) >= sz) (from alloc_chunk())

This implies that free chunks end up in the wrong buckets.

The fix for this is to just align the DAI/HOST buffers to
32 bytes.

Note that we didn't actually catch the moment the chunk headers
get corrupted. Instead, the conclusion was reached based on the
following facts:

	1) Disabling the data cache seems to fix the issue.
	2) Aligning the buffers to 32-byte boundary seems to
	fix the issue.
	3) Removing the invalidation operations on the DAI/HOST
	buffers seems to fix the issue.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>

Author: LaurentiuM1234

app/boards/imx95_evk_mimx9596_m7_ddr.conf

@@ -7,5 +7,7 @@ CONFIG_SAI_HAS_MCLK_CONFIG_OPTION=y
 
 CONFIG_DMA=y
 CONFIG_DMA_NXP_EDMA_ENABLE_HALFMAJOR_IRQ=y
+CONFIG_DMA_NXP_EDMA_ALIGN=32
+CONFIG_DMA_NXP_SOF_HOST_DMA_ALIGN=32
 
 CONFIG_SHARED_INTERRUPTS=y