1919#include <zephyr/drivers/counter.h>
2020#endif
2121
22+ #if CONFIG_UAOL_INTEL_ADSP
23+ #include <zephyr/drivers/uaol.h>
24+ #endif
25+
2226#include <ipc4/base_fw.h>
2327#include <rimage/sof/user/manifest.h>
2428
@@ -27,6 +31,20 @@ struct ipc4_modules_info {
2731 struct sof_man_module modules [0 ];
2832} __packed __aligned (4 );
2933
34+ struct ipc4_uaol_link_capabilities {
35+ uint32_t input_streams_supported : 4 ;
36+ uint32_t output_streams_supported : 4 ;
37+ uint32_t bidirectional_streams_supported : 5 ;
38+ uint32_t rsvd : 19 ;
39+ uint32_t max_tx_fifo_size ;
40+ uint32_t max_rx_fifo_size ;
41+ };
42+
43+ struct ipc4_uaol_capabilities {
44+ uint32_t link_count ;
45+ struct ipc4_uaol_link_capabilities link_caps [];
46+ } __packed __aligned (4 );
47+
3048LOG_MODULE_REGISTER (basefw_intel , CONFIG_SOF_LOG_LEVEL );
3149
3250int basefw_vendor_fw_config (uint32_t * data_offset , char * data )
@@ -36,7 +54,7 @@ int basefw_vendor_fw_config(uint32_t *data_offset, char *data)
3654 tlv_value_uint32_set (tuple , IPC4_SLOW_CLOCK_FREQ_HZ_FW_CFG , IPC4_ALH_CAVS_1_8 );
3755
3856 tuple = tlv_next (tuple );
39- tlv_value_uint32_set (tuple , IPC4_UAOL_SUPPORT , 0 );
57+ tlv_value_uint32_set (tuple , IPC4_UAOL_SUPPORT , 1 );
4058
4159 tuple = tlv_next (tuple );
4260 tlv_value_uint32_set (tuple , IPC4_ALH_SUPPORT_LEVEL_FW_CFG , IPC4_ALH_CAVS_1_8 );
@@ -47,6 +65,41 @@ int basefw_vendor_fw_config(uint32_t *data_offset, char *data)
4765 return 0 ;
4866}
4967
68+ #if CONFIG_UAOL_INTEL_ADSP
69+
70+ #define UAOL_DEV (node ) DEVICE_DT_GET(node),
71+ static const struct device * uaol_devs [] = {
72+ DT_FOREACH_STATUS_OKAY (intel_adsp_uaol , UAOL_DEV )
73+ };
74+
75+ static void tlv_value_set_uaol_caps (struct sof_tlv * tuple , uint32_t type )
76+ {
77+ size_t dev_count = ARRAY_SIZE (uaol_devs );
78+ struct uaol_capabilities dev_cap ;
79+ struct ipc4_uaol_capabilities * caps = (struct ipc4_uaol_capabilities * )tuple -> value ;
80+ size_t caps_size = offsetof(struct ipc4_uaol_capabilities , link_caps [dev_count ]);
81+ size_t i ;
82+ int ret ;
83+
84+ memset (caps , 0 , caps_size );
85+
86+ caps -> link_count = dev_count ;
87+ for (i = 0 ; i < dev_count ; i ++ ) {
88+ ret = uaol_get_capabilities (uaol_devs [i ], & dev_cap );
89+ if (ret )
90+ continue ;
91+
92+ caps -> link_caps [i ].input_streams_supported = dev_cap .input_streams ;
93+ caps -> link_caps [i ].output_streams_supported = dev_cap .output_streams ;
94+ caps -> link_caps [i ].bidirectional_streams_supported = dev_cap .bidirectional_streams ;
95+ caps -> link_caps [i ].max_tx_fifo_size = dev_cap .max_tx_fifo_size ;
96+ caps -> link_caps [i ].max_rx_fifo_size = dev_cap .max_rx_fifo_size ;
97+ }
98+
99+ tlv_value_set (tuple , type , caps_size , caps );
100+ }
101+ #endif
102+
50103int basefw_vendor_hw_config (uint32_t * data_offset , char * data )
51104{
52105 struct sof_tlv * tuple = (struct sof_tlv * )data ;
@@ -63,6 +116,11 @@ int basefw_vendor_hw_config(uint32_t *data_offset, char *data)
63116 tuple = tlv_next (tuple );
64117 tlv_value_uint32_set (tuple , IPC4_LP_EBB_COUNT_HW_CFG , PLATFORM_LPSRAM_EBB_COUNT );
65118
119+ #if CONFIG_UAOL_INTEL_ADSP
120+ tuple = tlv_next (tuple );
121+ tlv_value_set_uaol_caps (tuple , IPC4_UAOL_CAPS_HW_CFG );
122+ #endif
123+
66124 tuple = tlv_next (tuple );
67125 * data_offset = (int )((char * )tuple - data );
68126
@@ -298,6 +356,27 @@ static int basefw_set_fw_config(bool first_block,
298356 return 0 ;
299357}
300358
359+ static int basefw_dma_control (bool first_block , bool last_block ,
360+ uint32_t data_size , const char * data )
361+ {
362+ struct ipc4_dma_control * dma_control ;
363+ int ret ;
364+
365+ if (!(first_block && last_block ))
366+ return IPC4_INVALID_REQUEST ;
367+
368+ dma_control = (struct ipc4_dma_control * )data ;
369+
370+ if (data_size < offsetof(struct ipc4_dma_control , config_data [dma_control -> config_length ]))
371+ return IPC4_INVALID_CONFIG_DATA_STRUCT ;
372+
373+ ret = dai_control (dma_control -> node_id , data );
374+ if (ret )
375+ return IPC4_INVALID_REQUEST ;
376+
377+ return 0 ;
378+ }
379+
301380int basefw_vendor_set_large_config (struct comp_dev * dev ,
302381 uint32_t param_id ,
303382 bool first_block ,
@@ -308,6 +387,8 @@ int basefw_vendor_set_large_config(struct comp_dev *dev,
308387 switch (param_id ) {
309388 case IPC4_FW_CONFIG :
310389 return basefw_set_fw_config (first_block , last_block , data_offset , data );
390+ case IPC4_DMA_CONTROL :
391+ return basefw_dma_control (first_block , last_block , data_offset , data );
311392 default :
312393 break ;
313394 }
0 commit comments