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platform: mtk: add platform driver support for mt8196
Add support for dai, dma platform driver. Signed-off-by: Darren.Ye <darren.ye@mediatek.com>
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‎src/platform/mt8196/CMakeLists.txt‎

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add_subdirectory(lib)
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5-
add_local_sources(sof platform.c)
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add_local_sources(sof platform.c afe-platform.c)
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target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/mt8196/include/arch)
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target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/mt8196/include/platform)

‎src/platform/mt8196/afe-platform.c‎

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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright(c) 2024 MediaTek. All rights reserved.
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*
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* Author: Darren Ye <darren.ye@mediatek.com>
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*/
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#include <sof/common.h>
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#include <errno.h>
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#include <sof/drivers/afe-drv.h>
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#include <mt8196-afe-reg.h>
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#include <mt8196-afe-common.h>
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/*
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* AFE: Audio Front-End
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*
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* frontend (memif):
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* memory interface
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* UL (uplink for capture)
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* DL (downlink for playback)
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* backend:
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* TDM In
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* TDM Out
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* DMIC
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* GASRC
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* I2S Out
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* I2S In
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* etc.
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* interconn:
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* inter-connection,
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* connect frontends and backends as DSP path
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*/
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static const struct mtk_base_memif_data memif_data[MT8196_MEMIF_NUM] = {
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[MT8196_MEMIF_DL1] = {
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.name = "DL1",
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.id = MT8196_MEMIF_DL1,
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.reg_ofs_base = AFE_DL1_BASE,
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.reg_ofs_cur = AFE_DL1_CUR,
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.reg_ofs_end = AFE_DL1_END,
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.reg_ofs_base_msb = AFE_DL1_BASE_MSB,
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.reg_ofs_cur_msb = AFE_DL1_CUR_MSB,
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.reg_ofs_end_msb = AFE_DL1_END_MSB,
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.fs_reg = AFE_DL1_CON0,
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.fs_shift = DL1_SEL_FS_SFT,
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.fs_maskbit = DL1_SEL_FS_MASK,
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.mono_reg = AFE_DL1_CON0,
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.mono_shift = DL1_MONO_SFT,
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.int_odd_flag_reg = -1,
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.int_odd_flag_shift = 0,
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.enable_reg = AFE_DL1_CON0,
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.enable_shift = DL1_ON_SFT,
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.hd_reg = AFE_DL1_CON0,
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.hd_shift = DL1_HD_MODE_SFT,
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.hd_align_reg = AFE_DL1_CON0,
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.hd_align_mshift = DL1_HALIGN_SFT,
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.agent_disable_reg = -1,
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.agent_disable_shift = -1,
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.ch_num_reg = -1,
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.msb_reg = -1,
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.msb_shift = -1,
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.pbuf_reg = AFE_DL1_CON0,
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.pbuf_mask = DL1_PBUF_SIZE_MASK,
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.pbuf_shift = DL1_PBUF_SIZE_SFT,
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.minlen_reg = AFE_DL1_CON0,
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.minlen_mask = DL1_MINLEN_MASK,
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.minlen_shift = DL1_MINLEN_SFT,
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},
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[MT8196_MEMIF_DL_24CH] = {
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.name = "DL_24CH",
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.id = MT8196_MEMIF_DL_24CH,
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.reg_ofs_base = AFE_DL_24CH_BASE,
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.reg_ofs_cur = AFE_DL_24CH_CUR,
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.reg_ofs_end = AFE_DL_24CH_END,
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.reg_ofs_base_msb = AFE_DL_24CH_BASE_MSB,
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.reg_ofs_cur_msb = AFE_DL_24CH_CUR_MSB,
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.reg_ofs_end_msb = AFE_DL_24CH_END_MSB,
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.fs_reg = AFE_DL_24CH_CON0,
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.fs_shift = DL_24CH_SEL_FS_SFT,
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.fs_maskbit = DL_24CH_SEL_FS_MASK,
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.mono_reg = -1,
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.mono_shift = -1,
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.int_odd_flag_reg = -1,
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.int_odd_flag_shift = 0,
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.enable_reg = AFE_DL_24CH_CON0,
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.enable_shift = DL_24CH_ON_SFT,
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.hd_reg = AFE_DL_24CH_CON0,
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.hd_shift = DL_24CH_HD_MODE_SFT,
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.hd_align_reg = AFE_DL_24CH_CON0,
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.hd_align_mshift = DL_24CH_HALIGN_SFT,
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.agent_disable_reg = -1,
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.agent_disable_shift = -1,
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.msb_reg = -1,
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.msb_shift = -1,
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.pbuf_reg = AFE_DL_24CH_CON0,
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.pbuf_mask = DL_24CH_PBUF_SIZE_MASK,
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.pbuf_shift = DL_24CH_PBUF_SIZE_SFT,
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.minlen_reg = AFE_DL_24CH_CON0,
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.minlen_mask = DL_24CH_MINLEN_MASK,
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.minlen_shift = DL_24CH_MINLEN_SFT,
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.ch_num_reg = AFE_DL_24CH_CON0,
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.ch_num_maskbit = DL_24CH_NUM_MASK,
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.ch_num_shift = DL_24CH_NUM_SFT,
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},
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[MT8196_MEMIF_UL0] = {
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.name = "UL0",
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.id = MT8196_MEMIF_UL0,
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.reg_ofs_base = AFE_VUL0_BASE,
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.reg_ofs_cur = AFE_VUL0_CUR,
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.reg_ofs_end = AFE_VUL0_END,
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.reg_ofs_base_msb = AFE_VUL0_BASE_MSB,
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.reg_ofs_cur_msb = AFE_VUL0_CUR_MSB,
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.reg_ofs_end_msb = AFE_VUL0_END_MSB,
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.fs_reg = AFE_VUL0_CON0,
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.fs_shift = VUL0_SEL_FS_SFT,
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.fs_maskbit = VUL0_SEL_FS_MASK,
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.mono_reg = AFE_VUL0_CON0,
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.mono_shift = VUL0_MONO_SFT,
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.int_odd_flag_reg = -1,
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.int_odd_flag_shift = 0,
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.enable_reg = AFE_VUL0_CON0,
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.enable_shift = VUL0_ON_SFT,
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.hd_reg = AFE_VUL0_CON0,
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.hd_shift = VUL0_HD_MODE_SFT,
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.hd_align_reg = AFE_VUL0_CON0,
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.hd_align_mshift = VUL0_HALIGN_SFT,
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.agent_disable_reg = -1,
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.agent_disable_shift = -1,
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.msb_reg = -1,
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.msb_shift = -1,
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},
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[MT8196_MEMIF_UL1] = {
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.name = "UL1",
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.id = MT8196_MEMIF_UL1,
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.reg_ofs_base = AFE_VUL1_BASE,
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.reg_ofs_cur = AFE_VUL1_CUR,
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.reg_ofs_end = AFE_VUL1_END,
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.reg_ofs_base_msb = AFE_VUL1_BASE_MSB,
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.reg_ofs_cur_msb = AFE_VUL1_CUR_MSB,
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.reg_ofs_end_msb = AFE_VUL1_END_MSB,
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.fs_reg = AFE_VUL1_CON0,
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.fs_shift = VUL1_SEL_FS_SFT,
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.fs_maskbit = VUL1_SEL_FS_MASK,
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.mono_reg = AFE_VUL1_CON0,
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.mono_shift = VUL1_MONO_SFT,
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.enable_reg = AFE_VUL1_CON0,
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.enable_shift = VUL1_ON_SFT,
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.hd_reg = AFE_VUL1_CON0,
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.hd_shift = VUL1_HD_MODE_SFT,
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.hd_align_reg = AFE_VUL1_CON0,
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.hd_align_mshift = VUL1_HALIGN_SFT,
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.agent_disable_reg = -1,
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.agent_disable_shift = -1,
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.msb_reg = -1,
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.msb_shift = -1,
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},
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[MT8196_MEMIF_UL2] = {
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.name = "UL2",
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.id = MT8196_MEMIF_UL2,
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.reg_ofs_base = AFE_VUL2_BASE,
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.reg_ofs_cur = AFE_VUL2_CUR,
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.reg_ofs_end = AFE_VUL2_END,
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.reg_ofs_base_msb = AFE_VUL2_BASE_MSB,
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.reg_ofs_cur_msb = AFE_VUL2_CUR_MSB,
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.reg_ofs_end_msb = AFE_VUL2_END_MSB,
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.fs_reg = AFE_VUL2_CON0,
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.fs_shift = VUL2_SEL_FS_SFT,
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.fs_maskbit = VUL2_SEL_FS_MASK,
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.mono_reg = AFE_VUL2_CON0,
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.mono_shift = VUL2_MONO_SFT,
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.int_odd_flag_reg = -1,
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.int_odd_flag_shift = 0,
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.enable_reg = AFE_VUL2_CON0,
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.enable_shift = VUL2_ON_SFT,
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.hd_reg = AFE_VUL2_CON0,
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.hd_shift = VUL2_HD_MODE_SFT,
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.hd_align_reg = AFE_VUL2_CON0,
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.hd_align_mshift = VUL2_HALIGN_SFT,
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.agent_disable_reg = -1,
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.agent_disable_shift = -1,
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.msb_reg = -1,
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.msb_shift = -1,
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},
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};
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struct mt8196_afe_rate {
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unsigned int rate;
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unsigned int reg_value;
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};
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static const struct mt8196_afe_rate mt8196_afe_rates[] = {
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{
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.rate = 8000,
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.reg_value = 0,
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},
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{
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.rate = 12000,
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.reg_value = 2,
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},
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{
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.rate = 16000,
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.reg_value = 4,
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},
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{
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.rate = 24000,
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.reg_value = 6,
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},
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{
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.rate = 32000,
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.reg_value = 8,
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},
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{
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.rate = 48000,
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.reg_value = 0x0a,
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},
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{
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.rate = 96000,
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.reg_value = 14,
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},
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{
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.rate = 192000,
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.reg_value = 18,
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},
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{
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.rate = 384000,
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.reg_value = 22,
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},
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{
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.rate = 11025,
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.reg_value = 1,
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},
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{
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.rate = 22050,
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.reg_value = 5,
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},
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{
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.rate = 44100,
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.reg_value = 9,
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},
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{
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.rate = 88200,
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.reg_value = 13,
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},
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{
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.rate = 176400,
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.reg_value = 17,
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},
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{
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.rate = 352800,
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.reg_value = 21,
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},
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};
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static unsigned int mt8196_afe_fs_timing(unsigned int rate)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(mt8196_afe_rates); i++)
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if (mt8196_afe_rates[i].rate == rate)
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return mt8196_afe_rates[i].reg_value;
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return -EINVAL;
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}
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static unsigned int mt8196_afe_fs(unsigned int rate, int aud_blk)
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{
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return mt8196_afe_fs_timing(rate);
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}
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struct mtk_base_afe_platform mtk_afe_platform = {
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.base_addr = AFE_BASE_ADDR,
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.memif_datas = memif_data,
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.memif_size = MT8196_MEMIF_NUM,
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.memif_dl_num = MT8196_MEMIF_DL_NUM,
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.memif_32bit_supported = 0,
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.irq_datas = NULL,
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.irqs_size = 0,
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.dais_size = MT8196_DAI_NUM,
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.afe_fs = mt8196_afe_fs,
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.irq_fs = mt8196_afe_fs_timing,
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};

‎src/platform/mt8196/include/platform/mt8196-afe-common.h‎

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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright(c) 2024 MediaTek. All rights reserved.
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*
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* Author: Darren Ye <darren.ye@mediatek.com>
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*/
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#ifndef _MT_8196_AFE_COMMON_H_
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#define _MT_8196_AFE_COMMON_H_
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enum {
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MT8196_MEMIF_START,
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MT8196_MEMIF_DL_START = MT8196_MEMIF_START,
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MT8196_MEMIF_DL1 = MT8196_MEMIF_DL_START,
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MT8196_MEMIF_DL_24CH,
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MT8196_MEMIF_DL_END,
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MT8196_MEMIF_UL_START = MT8196_MEMIF_DL_END,
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MT8196_MEMIF_UL0 = MT8196_MEMIF_UL_START,
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MT8196_MEMIF_UL1,
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MT8196_MEMIF_UL2,
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MT8196_MEMIF_UL_END,
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MT8196_MEMIF_END = MT8196_MEMIF_UL_END,
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MT8196_MEMIF_DL_NUM = (MT8196_MEMIF_DL_END - MT8196_MEMIF_DL_START),
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MT8196_MEMIF_UL_NUM = (MT8196_MEMIF_UL_END - MT8196_MEMIF_UL_START),
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MT8196_MEMIF_NUM = (MT8196_MEMIF_END - MT8196_MEMIF_START),
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};
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/* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */
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enum {
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MT8196_IRQ_0,
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MT8196_IRQ_1,
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MT8196_IRQ_2,
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MT8196_IRQ_3,
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MT8196_IRQ_4,
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MT8196_IRQ_5,
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MT8196_IRQ_6,
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MT8196_IRQ_7,
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MT8196_IRQ_8,
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MT8196_IRQ_9,
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MT8196_IRQ_10,
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MT8196_IRQ_11,
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MT8196_IRQ_12,
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MT8196_IRQ_13,
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MT8196_IRQ_14,
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MT8196_IRQ_15,
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MT8196_IRQ_16,
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MT8196_IRQ_17,
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MT8196_IRQ_18,
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MT8196_IRQ_19,
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MT8196_IRQ_20,
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MT8196_IRQ_21,
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MT8196_IRQ_22,
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MT8196_IRQ_23,
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MT8196_IRQ_24,
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MT8196_IRQ_25,
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MT8196_IRQ_26,
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MT8196_IRQ_31, /* used only for TDM */
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MT8196_IRQ_NUM,
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};
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enum {
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MT8196_DAI_I2S_OUT4, /* speaker */
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MT8196_DAI_I2S_OUT6, /* headset out */
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MT8196_DAI_AP_DMIC, /* DMIC */
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MT8196_DAI_I2S_IN6, /* headset mic */
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MT8196_DAI_AP_DMIC_CH34,
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MT8196_DAI_NUM,
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};
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#endif

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