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hailong-fankv2019i
hailong-fan
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kv2019i
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platform: mediatek: Add support for mt8196 platform
mt8196 plaform integrates a single-core HIFI5 DSP. The DSP does not have DVFS scenario. When the system is in an active state, the DSP clock is 800MHz(0.75v). When the system enters a low power scenario, the DSP is in WFI state, and the clock is 26MHz. The DSP core and DMA in DSP subsys both can access DRAM directly. Signed-off-by: hailong.fan <hailong.fan@mediatek.com>
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‎src/platform/mt8196/CMakeLists.txt‎

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# SPDX-License-Identifier: BSD-3-Clause
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add_subdirectory(lib)
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add_local_sources(sof platform.c)
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target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/mt8196/include/arch)
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target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/mt8196/include/platform)

‎src/platform/mt8196/include/platform/drivers/idc.h‎

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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright(c) 2024 MediaTek. All rights reserved.
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*
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* Author: Hailong Fan <hailong.fan@mediatek.com>
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*/
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#if defined(__XTOS_RTOS_IDC_H__) || defined(__ZEPHYR_RTOS_IDC_H__)
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#ifndef __PLATFORM_DRIVERS_IDC_H__
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#define __PLATFORM_DRIVERS_IDC_H__
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#include <stdint.h>
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struct idc_msg;
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static inline int idc_send_msg(struct idc_msg *msg, uint32_t mode)
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{
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return 0;
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}
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static inline int idc_init(void)
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{
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return 0;
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}
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#endif /* __PLATFORM_DRIVERS_IDC_H__ */
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#else
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#error "This file shouldn't be included from outside of Zephyr/XTOS's rtos/idc.h"
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#endif

‎src/platform/mt8196/include/platform/drivers/intc.h‎

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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright(c) 2024 MediaTek. All rights reserved.
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*
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* Author: Hailong Fan <hailong.fan@mediatek.com>
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*/
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#ifndef MTK_INTC_H
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#define MTK_INTC_H
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#include <rtos/bit.h>
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#include <stdint.h>
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#include <platform/drivers/mt_reg_base.h>
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enum IRQn_Type {
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CCU_IRQn = 0,
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SCP_IRQn = 1,
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SPM_IRQn = 2,
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PCIE_IRQn = 3,
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INFRA_HANG_IRQn = 4,
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PERI_TIMEOUT_IRQn = 5,
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MBOX_C0_IRQn = 6,
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MBOX_C1_IRQn = 7,
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TIMER0_IRQn = 8,
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TIMER1_IRQn = 9,
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IPC_C0_IRQn = 10,
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IPC_C1_IRQn = 11,
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IPC1_RSV_IRQn = 12,
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C2C_SW_C0_IRQn = 13,
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C2C_SW_C1_IRQn = 14,
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UART_IRQn = 15,
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UART_BT_IRQn = 16,
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LATENCY_MON_IRQn = 17,
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BUS_TRACKER_IRQn = 18,
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USB0_IRQn = 19,
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USB1_IRQn = 20,
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SCPVOW_IRQn = 21,
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CCIF3_C0_IRQn = 22,
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CCIF3_C1_IRQn = 23,
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PWR_CTRL_IRQn = 24,
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DMA_C0_IRQn = 25,
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DMA_C1_IRQn = 26, // no use as gdma only has one set
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AXI_DMA0_IRQn = 27,
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AXI_DMA1_IRQn = 28,
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AUDIO_C0_IRQn = 29,
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AUDIO_C1_IRQn = 30,
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HIFI5_WDT_C0_IRQn = 31,
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HIFI5_WDT_C1_IRQn = 32,
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APU_MBOX_C0_IRQn = 33,
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APU_MBOX_C1_IRQn = 34,
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TIMER2_IRQn = 35,
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PWR_ON_C0_IRQ = 36,
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PWR_ON_C1_IRQ = 37,
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WAKEUP_SRC_C0_IRQn = 38,
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WAKEUP_SRC_C1_IRQn = 39,
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WDT_IRQn = 40,
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CONNSYS1_IRQn = 41, // BTCVSD
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CONNSYS3_IRQn = 42, // BLEISO
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CONNSYS4_IRQn = 43, // ISOCH, bt2dsp_isoch_irq_mask
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CONNSYS2_IRQn = 44, // A2DP
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IPIC_IRQn = 45,
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AXI_DMA2_IRQn = 46,
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AXI_DMA3_IRQn = 47,
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APSRC_DDREN_IRQn = 48,
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LAT_MON_EMI_IRQn = 49,
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LAT_MON_INFRA_IRQn = 50,
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DEVAPC_VIO_IRQn = 51,
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AO_INFRA_HANG_IRQn = 52,
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BUS_TRA_EMI_IRQn = 53,
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BUS_TRA_INFRA_IRQn = 54,
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L2SRAM_VIO_IRQn = 55,
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L2SRAM_SETERR_IRQn = 56,
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PCIERC_GRP2_IRQn = 57,
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PCIERC_GRP3_IRQn = 58,
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IRQ_MAX_CHANNEL = 59,
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NO_IRQ = 0xFFFFFFFFU, // -1
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};
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#define INTC_GRP_LEN 2
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#define INTC_GRP_GAP 3 // size of group = 2 words = 8 bytes
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#define WORD_LEN 32
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#define INTC_WORD(irq) ((irq) >> 5)
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#define INTC_BIT(irq) (1 << ((irq) & 0x1F))
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#define INTC_WORD_OFS(word) ((word) << 2)
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#ifndef INTC_GROUP_OFS
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#define INTC_GROUP_OFS(grp) ((grp) << INTC_GRP_GAP)
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#endif
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// #define INTC_IRQ_RAW_STA(word) (INTC_IRQ_RAW_STA0 + INTC_WORD_OFS(word))
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#define INTC_IRQ_STA(word) (INTC_IRQ_STA0 + INTC_WORD_OFS(word))
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#define INTC_IRQ_EN(word) (INTC_IRQ_EN0 + INTC_WORD_OFS(word))
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#define INTC_IRQ_WAKE_EN(word) (INTC_IRQ_WAKE_EN0 + INTC_WORD_OFS(word))
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#define INTC_IRQ_STAGE1_EN(word) (INTC_IRQ_STAGE1_EN0 + INTC_WORD_OFS(word))
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#define INTC_IRQ_POL(word) (INTC_IRQ_POL0 + INTC_WORD_OFS(word))
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#define INTC_IRQ_GRP(grp, word) (INTC_IRQ_GRP0_0 + INTC_GROUP_OFS(grp)\
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+ INTC_WORD_OFS(word))
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#define INTC_IRQ_GRP_STA(grp, word) (INTC_IRQ_GRP0_STA0 + INTC_GROUP_OFS(grp)\
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+ INTC_WORD_OFS(word))
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/* intc group level */
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#define INTC_GRP0_LEVEL XCHAL_INT0_LEVEL
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#define INTC_GRP1_LEVEL XCHAL_INT1_LEVEL
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#define INTC_GRP2_LEVEL XCHAL_INT2_LEVEL
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#define INTC_GRP3_LEVEL XCHAL_INT3_LEVEL
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#define INTC_GRP4_LEVEL XCHAL_INT4_LEVEL
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#define INTC_GRP5_LEVEL XCHAL_INT5_LEVEL
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#define INTC_GRP6_LEVEL XCHAL_INT7_LEVEL
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#define INTC_GRP7_LEVEL XCHAL_INT8_LEVEL
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#define INTC_GRP8_LEVEL XCHAL_INT9_LEVEL
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#define INTC_GRP9_LEVEL XCHAL_INT10_LEVEL
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#define INTC_GRP10_LEVEL XCHAL_INT11_LEVEL
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#define INTC_GRP11_LEVEL XCHAL_INT16_LEVEL
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#define INTC_GRP12_LEVEL XCHAL_INT17_LEVEL
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#define INTC_GRP13_LEVEL XCHAL_INT18_LEVEL
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#define INTC_GRP14_LEVEL XCHAL_INT20_LEVEL
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#define INTC_GRP15_LEVEL XCHAL_INT21_LEVEL
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enum INTC_GROUP {
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INTC_GRP0 = 0,
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INTC_GRP1,
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INTC_GRP2,
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INTC_GRP3,
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INTC_GRP4,
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INTC_GRP5,
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INTC_GRP6,
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INTC_GRP7,
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INTC_GRP8,
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INTC_GRP9,
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INTC_GRP10,
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INTC_GRP11,
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INTC_GRP12,
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INTC_GRP13,
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INTC_GRP14,
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INTC_GRP15,
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INTC_GRP_NUM,
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NO_GRP,
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};
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enum INTC_POL {
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INTC_POL_HIGH = 0x0,
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INTC_POL_LOW = 0x1,
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INTC_POL_NUM,
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};
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struct intc_irq_desc_t {
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uint8_t id;
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uint8_t group;
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uint8_t pol;
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};
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struct intc_desc_t {
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uint32_t int_en[INTC_GRP_LEN];
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uint32_t grp_irqs[INTC_GRP_NUM][INTC_GRP_LEN];
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struct intc_irq_desc_t irqs[IRQ_MAX_CHANNEL];
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};
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struct intc_irq_config {
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uint32_t int_en[INTC_GRP_LEN];
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};
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struct intc_grp_config {
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uint32_t grp_irq[INTC_GRP_NUM][INTC_GRP_LEN];
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};
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struct intc_coreoff_wake_en_config {
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uint32_t wake_en[INTC_GRP_LEN];
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};
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struct intc_sleep_wake_en_config {
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uint32_t wake_en[INTC_GRP_LEN];
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};
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extern const unsigned char grp_pri[INTC_GRP_NUM];
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extern const uint8_t irq2grp_map[IRQ_MAX_CHANNEL];
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extern const uint8_t grp2hifi_irq_map[INTC_GRP_NUM];
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void intc_init(void);
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#ifdef CFG_TICKLESS_SUPPORT
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extern struct intc_sleep_wake_en_config sleep_wakeup_src_en;
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#endif
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#ifdef CFG_CORE_OFF_SUPPORT
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extern struct intc_coreoff_wake_en_config coreoff_wakeup_src_en;
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#endif
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#endif /* INTC_H */
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‎src/platform/mt8196/include/platform/drivers/interrupt.h‎

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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright(c) 2024 MediaTek. All rights reserved.
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*
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* Author: Hailong Fan <hailong.fan@mediatek.com>
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*/
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#ifdef __SOF_DRIVERS_INTERRUPT_H__
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#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__
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#define __PLATFORM_DRIVERS_INTERRUPT_H__
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#include <stdint.h>
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#include <platform/drivers/mt_reg_base.h>
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#include <platform/drivers/intc.h>
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#define PLATFORM_IRQ_HW_NUM XCHAL_NUM_INTERRUPTS
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#define PLATFORM_IRQ_FIRST_CHILD PLATFORM_IRQ_HW_NUM
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#define PLATFORM_IRQ_CHILDREN 32
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/* MTK_ADSP_IRQ_MASK */
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#define MTK_DSP_OUT_IRQ_MASK 0x3FF
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#define HIFI_IRQ_MAX_CHANNEL 26
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#define DEFALUT_WAKEUP_SRC_MASK_BIT 0x001A5E13
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#define DEFAULT_WAKEUP_SRC_EN0_BIT 0xA046B550
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#define DEFAULT_WAKEUP_SRC_EN1_BIT 0x00002148
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#define MTK_DSP_IRQ_MBOX_C0 2
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#define MTK_DSP_IRQ_OSTIMER32_C0 1
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#define IPC0_IRQn IPC_C0_IRQn
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#define C2C_SW_IRQn C2C_SW_C0_IRQn
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#define CCIF3_IRQn CCIF3_C0_IRQn
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#define DMA_IRQn DMA_C0_IRQn
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#define AUDIO_IRQn AUDIO_C0_IRQn
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#define HIFI5_WDT_IRQn HIFI5_WDT_C0_IRQn
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#define APU_MBOX_IRQn APU_MBOX_C0_IRQn
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#define PWR_ON_CORE_IRQn PWR_ON_C0_IRQ
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#define WAKEUP_SRC_IRQn WAKEUP_SRC_C0_IRQn
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#define AXI_DMA_CH0_IRQn AXI_DMA0_IRQn
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#define AXI_DMA_CH1_IRQn AXI_DMA2_IRQn
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/* following interrupts are HiFi internal interrupts */
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#define MTK_DSP_IRQ_NMI 25
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#define MTK_DSP_IRQ_PROFILING 29
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#define MTK_DSP_IRQ_WERR 30
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#define MTK_DSP_IRQ_SW 31
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#define MTK_MAX_IRQ_NUM 59
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/* grouped mailbox IRQ */
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#define MTK_DSP_IRQ_MBOX0 59
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#define MTK_DSP_IRQ_MBOX1 60
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#define MTK_DSP_IRQ_MBOX2 61
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#define MTK_DSP_IRQ_MBOX3 62
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#define MTK_DSP_IRQ_MBOX4 63
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#define MTK_DSP_MBOX_MASK 0xF
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int mtk_irq_group_id(uint32_t irq);
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void intc_irq_unmask(enum IRQn_Type irq);
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void intc_irq_mask(enum IRQn_Type irq);
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int intc_irq_enable(enum IRQn_Type irq);
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int intc_irq_disable(enum IRQn_Type irq);
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#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */
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#else
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#error "This file shouldn't be included from outside of sof/drivers/interrupt.h"
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#endif /* __SOF_DRIVERS_INTERRUPT_H__ */

‎src/platform/mt8196/include/platform/drivers/mt_reg_base.h‎

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#define MTK_ADSP_GENERAL_IRQ_CLR (MTK_DSP_CFGREG_BASE + 0x0038)
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#define MTK_ADSP_DVFSRC_STATE (MTK_DSP_CFGREG_BASE + 0x003c)
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#define MTK_ADSP_DVFSRC_REQ (MTK_DSP_CFGREG_BASE + 0x0040)
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//todo
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#define MTK_ADSP_DDREN_REQ_0 (MTK_DSP_CFGREG_BASE + 0x0044)
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#define MTK_ADSP_SPM_ACK (MTK_DSP_CFGREG_BASE + 0x004c)
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#define MTK_ADSP_IRQ_EN (MTK_DSP_CFGREG_BASE + 0x0050)
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#define INTC_IRQ_GRP0_STA0 (MTK_ADSP_INTC_BASE + 0x0C0)
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#define INTC_GRP_IRQ_OUT_STA (MTK_ADSP_INTC_BASE + 0x140)
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//todo
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#define MTK_GPR_RW_REG0 (MTK_DSP_CFGREG_BASE + 0x0440)
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#define MTK_GPR_RW_REG1 (MTK_DSP_CFGREG_BASE + 0x0444)
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#define MTK_GPR_RW_REG2 (MTK_DSP_CFGREG_BASE + 0x0448)
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#define MTK_DSP_CKCTRL_BASE (MTK_DSP_CFGREG_BASE + 0x1000)
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#define MTK_DSP_CKCTRL_SIZE 0x1000
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//todo
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#define MTK_DSP_OS_TIMER_BASE (MTK_DSP_CFGREG_BASE + 0xB000)
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#define MTK_DSP_OS_TIMER_SIZE 0x1000
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#define MTK_DSP_SECURE_BASE (MTK_DSP_CFGREG_BASE + 0x345000)
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#define MTK_MBOX_IRQ_IN (MTK_DSP_SECURE_BASE + 0x70)
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#define MTK_REG_TOPCKGEN_BASE 0x10000000
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#define MTK_REG_TOPCKGEN_SIZE 0x1000
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#define MTK_CLK_CFG_UPDATE1 (MTK_REG_TOPCKGEN_BASE + 0x0008)
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#define MTK_CLK_CFG_13_STA (MTK_REG_TOPCKGEN_BASE + 0x00E0)
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#define MTK_CLK_CFG_13_SET (MTK_REG_TOPCKGEN_BASE + 0x00E4)
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#define MTK_CLK_CFG_13_CLR (MTK_REG_TOPCKGEN_BASE + 0x00E8)
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#define MTK_ADSP_CK_UPDATE (0x1 << 23)
116-
#define MTK_ADSP_SEL_BASE (16)
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118-
//todo
119-
#define MTK_CLK_CFG_UPDATE2 (MTK_REG_TOPCKGEN_BASE + 0x000C)
120-
#define MTK_CLK_CFG_17 (MTK_REG_TOPCKGEN_BASE + 0x0EC)
121-
#define MTK_CLK_CFG_17_SET (MTK_REG_TOPCKGEN_BASE + 0x0F0)
122-
#define MTK_CLK_CFG_17_CLR (MTK_REG_TOPCKGEN_BASE + 0x0F4)
123-
#define MTK_CLK_CFG_17_CLR (MTK_REG_TOPCKGEN_BASE + 0x0F4)
124-
125-
//todo, pll base?
126-
#define MTK_REG_APMIXDSYS_BASE 0x10000800
127-
#define MTK_REG_APMIXDSYS_SIZE 0x1000
128-
129-
//todo
130-
#define MTK_PLLEN_ALL_EN (MTK_REG_APMIXDSYS_BASE + 0x0080)
131-
#define MTK_PLLEN_ALL_SET (MTK_REG_APMIXDSYS_BASE + 0x0084)
132-
#define MTK_PLLEN_ALL_CLR (MTK_REG_APMIXDSYS_BASE + 0x0088)
133-
#define MTK_ADSPPLL_CON0 (MTK_REG_APMIXDSYS_BASE + 0x028c)
134-
#define MTK_ADSPPLL_CON1 (MTK_REG_APMIXDSYS_BASE + 0x0290)
135-
#define MTK_PLL_ADSP_EN_BIT (0x1 << 3)
136-
137-
138106
/* MBOX registers */
139107
#define MTK_ADSP_MBOX_BASE (MTK_DSP_CFGREG_BASE + 0x350000)
140108
#define MTK_ADSP_MBOX_REG_BASE(x) (MTK_ADSP_MBOX_BASE + (0x10000 * (x)))

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