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hailong-fanhailong-fan
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platform: mediatek: update mt8196 platform drivers
update clk and register definition. Signed-off-by: hailong.fan <hailong.fan@mediatek.com>
1 parent 00c9d5e commit ff2a236

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4 files changed

+9
-156
lines changed

4 files changed

+9
-156
lines changed

‎src/platform/mt8196/include/platform/drivers/mt_reg_base.h‎

Lines changed: 0 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,6 @@
2222
#define MTK_ADSP_GENERAL_IRQ_CLR (MTK_DSP_CFGREG_BASE + 0x0038)
2323
#define MTK_ADSP_DVFSRC_STATE (MTK_DSP_CFGREG_BASE + 0x003c)
2424
#define MTK_ADSP_DVFSRC_REQ (MTK_DSP_CFGREG_BASE + 0x0040)
25-
//todo
2625
#define MTK_ADSP_DDREN_REQ_0 (MTK_DSP_CFGREG_BASE + 0x0044)
2726
#define MTK_ADSP_SPM_ACK (MTK_DSP_CFGREG_BASE + 0x004c)
2827
#define MTK_ADSP_IRQ_EN (MTK_DSP_CFGREG_BASE + 0x0050)
@@ -53,7 +52,6 @@
5352
#define INTC_IRQ_GRP0_STA0 (MTK_ADSP_INTC_BASE + 0x0C0)
5453
#define INTC_GRP_IRQ_OUT_STA (MTK_ADSP_INTC_BASE + 0x140)
5554

56-
//todo
5755
#define MTK_GPR_RW_REG0 (MTK_DSP_CFGREG_BASE + 0x0440)
5856
#define MTK_GPR_RW_REG1 (MTK_DSP_CFGREG_BASE + 0x0444)
5957
#define MTK_GPR_RW_REG2 (MTK_DSP_CFGREG_BASE + 0x0448)
@@ -91,7 +89,6 @@
9189
#define MTK_DSP_CKCTRL_BASE (MTK_DSP_CFGREG_BASE + 0x1000)
9290
#define MTK_DSP_CKCTRL_SIZE 0x1000
9391

94-
//todo
9592
#define MTK_DSP_OS_TIMER_BASE (MTK_DSP_CFGREG_BASE + 0xB000)
9693
#define MTK_DSP_OS_TIMER_SIZE 0x1000
9794

@@ -106,35 +103,6 @@
106103
#define MTK_DSP_SECURE_BASE (MTK_DSP_CFGREG_BASE + 0x345000)
107104
#define MTK_MBOX_IRQ_IN (MTK_DSP_SECURE_BASE + 0x70)
108105

109-
#define MTK_REG_TOPCKGEN_BASE 0x10000000
110-
#define MTK_REG_TOPCKGEN_SIZE 0x1000
111-
#define MTK_CLK_CFG_UPDATE1 (MTK_REG_TOPCKGEN_BASE + 0x0008)
112-
#define MTK_CLK_CFG_13_STA (MTK_REG_TOPCKGEN_BASE + 0x00E0)
113-
#define MTK_CLK_CFG_13_SET (MTK_REG_TOPCKGEN_BASE + 0x00E4)
114-
#define MTK_CLK_CFG_13_CLR (MTK_REG_TOPCKGEN_BASE + 0x00E8)
115-
#define MTK_ADSP_CK_UPDATE (0x1 << 23)
116-
#define MTK_ADSP_SEL_BASE (16)
117-
118-
//todo
119-
#define MTK_CLK_CFG_UPDATE2 (MTK_REG_TOPCKGEN_BASE + 0x000C)
120-
#define MTK_CLK_CFG_17 (MTK_REG_TOPCKGEN_BASE + 0x0EC)
121-
#define MTK_CLK_CFG_17_SET (MTK_REG_TOPCKGEN_BASE + 0x0F0)
122-
#define MTK_CLK_CFG_17_CLR (MTK_REG_TOPCKGEN_BASE + 0x0F4)
123-
#define MTK_CLK_CFG_17_CLR (MTK_REG_TOPCKGEN_BASE + 0x0F4)
124-
125-
//todo, pll base?
126-
#define MTK_REG_APMIXDSYS_BASE 0x10000800
127-
#define MTK_REG_APMIXDSYS_SIZE 0x1000
128-
129-
//todo
130-
#define MTK_PLLEN_ALL_EN (MTK_REG_APMIXDSYS_BASE + 0x0080)
131-
#define MTK_PLLEN_ALL_SET (MTK_REG_APMIXDSYS_BASE + 0x0084)
132-
#define MTK_PLLEN_ALL_CLR (MTK_REG_APMIXDSYS_BASE + 0x0088)
133-
#define MTK_ADSPPLL_CON0 (MTK_REG_APMIXDSYS_BASE + 0x028c)
134-
#define MTK_ADSPPLL_CON1 (MTK_REG_APMIXDSYS_BASE + 0x0290)
135-
#define MTK_PLL_ADSP_EN_BIT (0x1 << 3)
136-
137-
138106
/* MBOX registers */
139107
#define MTK_ADSP_MBOX_BASE (MTK_DSP_CFGREG_BASE + 0x350000)
140108
#define MTK_ADSP_MBOX_REG_BASE(x) (MTK_ADSP_MBOX_BASE + (0x10000 * (x)))

‎src/platform/mt8196/include/platform/lib/clk.h‎

Lines changed: 0 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -22,41 +22,6 @@ struct sof;
2222
#define NUM_CLOCKS 1
2323
#define NUM_CPU_FREQ 2
2424

25-
/* MTK_ADSPPLL_CON1 */
26-
#define MTK_PLL_DIV_RATIO_800M 0x810F6276
27-
#define MTK_PLL_DIV_RATIO_400M 0x831EC4ED
28-
29-
/* MTK_ADSPPLL_CON3 */
30-
#define MTK_PLL_EN BIT(9)
31-
#define MTK_PLL_PWR_ON BIT(0)
32-
#define MTK_PLL_ISO_EN BIT(1)
33-
34-
/* MTK_CLK_CFG_UPDATE2 */
35-
#define MTK_CLK_UPDATE_ADSK_CLK BIT(4)
36-
#define MTK_CLK_UPDATE_AUDIO_LOCAL_BUS_CLK BIT(5)
37-
38-
/* MTK_CLK_CFG_17[3:0] */
39-
#define MTK_CLK_ADSP_OFFSET 0
40-
#define MTK_CLK_ADSP_MASK 0xF
41-
#define MTK_CLK_ADSP_26M 0
42-
#define MTK_CLK_ADSP_ADSPPLL 8 /* 800M */
43-
#define MTK_CLK_ADSP_ADSPPLL_D_2 9 /* 400M */
44-
45-
/* MTK_CLK_CFG_17[11:8] */
46-
#define MTK_CLK_AUDIO_LOCAL_BUS_OFFSET 8
47-
#define MTK_CLK_AUDIO_LOCAL_BUS_MASK 0xF
48-
#define MTK_CLK_AUDIO_LOCAL_BUS_26M 0
49-
#define MTK_CLK_AUDIO_LOCAL_BUS_MAINPLL_D_7 6 /* 312M */
50-
#define MTK_CLK_AUDIO_LOCAL_BUS_MAINPLL_D_4 7 /* 546M */
51-
52-
/* List resource from low to high request */
53-
/* 0 is the lowest request */
54-
enum ADSP_HW_DSP_CLK {
55-
ADSP_CLK_26M = 0,
56-
ADSP_CLK_PLL_400M,
57-
ADSP_CLK_PLL_800M,
58-
};
59-
6025
void platform_clock_init(struct sof *sof);
6126

6227
#endif /* __PLATFORM_LIB_CLK_H__ */

‎src/platform/mt8196/lib/clk.c‎

Lines changed: 8 additions & 87 deletions
Original file line numberDiff line numberDiff line change
@@ -32,97 +32,18 @@ STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ,
3232

3333
static SHARED_DATA struct clock_info platform_clocks_info[NUM_CLOCKS];
3434

35-
static void clk_dsppll_enable(uint32_t value)
36-
{
37-
tr_dbg(&clkdrv_tr, "clk_dsppll_enable %d\n", value);
38-
39-
switch (value) {
40-
case ADSP_CLK_PLL_400M:
41-
io_reg_write(MTK_ADSPPLL_CON1, MTK_PLL_DIV_RATIO_400M);
42-
break;
43-
case ADSP_CLK_PLL_800M:
44-
io_reg_write(MTK_ADSPPLL_CON1, MTK_PLL_DIV_RATIO_800M);
45-
break;
46-
default:
47-
tr_err(&clkdrv_tr, "invalid dsppll: %d\n", value);
48-
return;
49-
}
50-
51-
//todo
52-
//io_reg_update_bits(MTK_ADSPPLL_CON3, MTK_PLL_PWR_ON, MTK_PLL_PWR_ON);
53-
wait_delay_us(1);
54-
//io_reg_update_bits(MTK_ADSPPLL_CON3, MTK_PLL_ISO_EN, 0);
55-
wait_delay_us(1);
56-
io_reg_update_bits(MTK_ADSPPLL_CON0, MTK_PLL_EN, MTK_PLL_EN);
57-
wait_delay_us(20);
58-
}
59-
60-
static void clk_dsppll_disable(void)
61-
{
62-
tr_dbg(&clkdrv_tr, "clk_dsppll_disable\n");
63-
64-
io_reg_update_bits(MTK_ADSPPLL_CON0, MTK_PLL_EN, 0);
65-
wait_delay_us(1);
66-
//io_reg_update_bits(MTK_ADSPPLL_CON3, MTK_PLL_ISO_EN, MTK_PLL_ISO_EN);
67-
wait_delay_us(1);
68-
//io_reg_update_bits(MTK_ADSPPLL_CON3, MTK_PLL_PWR_ON, 0);
69-
}
70-
71-
static void set_mux_adsp_sel(uint32_t value)
72-
{
73-
io_reg_write(MTK_CLK_CFG_17_CLR, MTK_CLK_ADSP_MASK << MTK_CLK_ADSP_OFFSET);
74-
io_reg_write(MTK_CLK_CFG_17_SET, value << MTK_CLK_ADSP_OFFSET);
75-
io_reg_write(MTK_CLK_CFG_UPDATE2, MTK_CLK_UPDATE_ADSK_CLK);
76-
77-
tr_dbg(&clkdrv_tr, "adsp_clk_mux=%x, CLK_CFG_17=0x%08x\n",
78-
value, io_reg_read(MTK_CLK_CFG_17));
79-
}
80-
81-
static void set_mux_adsp_bus_sel(uint32_t value)
82-
{
83-
io_reg_write(MTK_CLK_CFG_17_CLR,
84-
MTK_CLK_AUDIO_LOCAL_BUS_MASK << MTK_CLK_AUDIO_LOCAL_BUS_OFFSET);
85-
io_reg_write(MTK_CLK_CFG_17_SET, value << MTK_CLK_AUDIO_LOCAL_BUS_OFFSET);
86-
io_reg_write(MTK_CLK_CFG_UPDATE2, MTK_CLK_UPDATE_AUDIO_LOCAL_BUS_CLK);
87-
88-
tr_dbg(&clkdrv_tr, "audio_local_bus_mux=%x, CLK_CFG_17=0x%08x\n",
89-
value, io_reg_read(MTK_CLK_CFG_17));
90-
}
91-
92-
static int clock_platform_set_dsp_freq(int clock, int freq_idx)
93-
{
94-
int freq = platform_cpu_freq[freq_idx].freq;
95-
96-
tr_info(&clkdrv_tr, "clock_platform_set_cpu_freq %d\n", freq);
97-
98-
switch (freq_idx) {
99-
case ADSP_CLK_26M:
100-
set_mux_adsp_sel(MTK_CLK_ADSP_26M);
101-
set_mux_adsp_bus_sel(MTK_CLK_AUDIO_LOCAL_BUS_26M);
102-
clk_dsppll_disable();
103-
break;
104-
case ADSP_CLK_PLL_400M:
105-
clock_platform_set_dsp_freq(clock, ADSP_CLK_26M);
106-
clk_dsppll_enable(ADSP_CLK_PLL_400M);
107-
set_mux_adsp_sel(MTK_CLK_ADSP_ADSPPLL);
108-
set_mux_adsp_bus_sel(MTK_CLK_AUDIO_LOCAL_BUS_MAINPLL_D_7);
109-
break;
110-
case ADSP_CLK_PLL_800M:
111-
clock_platform_set_dsp_freq(clock, ADSP_CLK_26M);
112-
clk_dsppll_enable(ADSP_CLK_PLL_800M);
113-
set_mux_adsp_sel(MTK_CLK_ADSP_ADSPPLL);
114-
set_mux_adsp_bus_sel(MTK_CLK_AUDIO_LOCAL_BUS_MAINPLL_D_4);
115-
break;
116-
}
117-
118-
return 0;
119-
}
120-
12135
void platform_clock_init(struct sof *sof)
12236
{
12337
int i;
12438

39+
tr_dbg(&clkdrv_tr, "clock init\n");
12540
sof->clocks = platform_shared_get(platform_clocks_info, sizeof(platform_clocks_info));
41+
42+
/* When the system is in an active state, the DSP clock operates at 800MHz (0.75V).
43+
* In a low power scenario, the DSP enters WFI state, and the clock reduces to 26MHz.
44+
* The clock selection is controlled by the host, and we do not allow SOF to change
45+
* the ADSP frequency.
46+
*/
12647
for (i = 0; i < CONFIG_CORE_COUNT; i++) {
12748
sof->clocks[i] = (struct clock_info){
12849
.freqs_num = NUM_CPU_FREQ,
@@ -131,7 +52,7 @@ void platform_clock_init(struct sof *sof)
13152
.current_freq_idx = CPU_DEFAULT_IDX,
13253
.notification_id = NOTIFIER_ID_CPU_FREQ,
13354
.notification_mask = NOTIFIER_TARGET_CORE_MASK(i),
134-
.set_freq = clock_platform_set_dsp_freq,
55+
.set_freq = NULL,
13556
};
13657
}
13758
}

‎src/platform/mt8196/platform.c‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -156,7 +156,6 @@ int platform_boot_complete(uint32_t boot_message)
156156
return 0;
157157
}
158158

159-
160159
int platform_init(struct sof *sof)
161160
{
162161
int ret;
@@ -185,7 +184,7 @@ int platform_init(struct sof *sof)
185184

186185
scheduler_init_ll(sof->platform_dma_domain);
187186

188-
/* initialize the host IPC mechanims */
187+
/* initialize the host IPC mechanisms */
189188
ipc_init(sof);
190189

191190
#if CONFIG_TRACE

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