From 3e6da5fd6e3eb605d98c5acd11b0a85b6aec9aca Mon Sep 17 00:00:00 2001 From: Seppo Ingalsuo Date: Mon, 4 Aug 2025 18:29:16 +0300 Subject: [PATCH 1/3] Audio: SRC: Output zeros to sink buffer when no data in begin The 2nd stage of the sample rate converter may not produce data if the internal processing block is longer than output frames count in a period. E.g. in 48 to 11.025 kHz capture the first two copy() operations are not producing data to sink. Producing the zeros can prevent xruns in the downstream pipeline. Signed-off-by: Seppo Ingalsuo --- src/audio/src/src_common.c | 8 ++++++++ src/audio/src/src_common.h | 1 + 2 files changed, 9 insertions(+) diff --git a/src/audio/src/src_common.c b/src/audio/src/src_common.c index f96b3bc6e358..b58415fd5cbf 100644 --- a/src/audio/src/src_common.c +++ b/src/audio/src/src_common.c @@ -319,6 +319,13 @@ static int src_2s(struct comp_data *cd, n_written += s2.times * cd->src.stage2->blk_out; } + if (n_written == 0) { + if (cd->start_with_no_output_produced) + n_written = cd->sink_frames; + } else { + cd->start_with_no_output_produced = false; + } + /* commit the processed data */ source_release_data(source, n_read * source_get_frame_bytes(source)); sink_commit_buffer(sink, n_written * sink_get_frame_bytes(sink)); @@ -562,6 +569,7 @@ int src_params_general(struct processing_module *mod, break; case 2: cd->src_func = src_2s; /* Default 2 stage SRC */ + cd->start_with_no_output_produced = true; break; default: /* This is possibly due to missing coefficients for diff --git a/src/audio/src/src_common.h b/src/audio/src/src_common.h index 6a8028662ffd..13ba9f20d46d 100644 --- a/src/audio/src/src_common.h +++ b/src/audio/src/src_common.h @@ -164,6 +164,7 @@ struct comp_data { int sink_frames; int sample_container_bytes; int channels_count; + bool start_with_no_output_produced; int (*src_func)(struct comp_data *cd, struct sof_source *source, struct sof_sink *sink); void (*polyphase_func)(struct src_stage_prm *s); From c1b96e508fd15f20e9e433ede826424255d2dc32 Mon Sep 17 00:00:00 2001 From: Seppo Ingalsuo Date: Mon, 4 Aug 2025 14:16:15 +0300 Subject: [PATCH 2/3] Audio: SRC: Tune: Change factors for 48 to 11.025 kHz conversion The conversion from 48 to 11.025 kHz was done with fractions 21/80 * 7/8. With denominator 80 in the first fraction the first stage of SRC needed 80 input frames to consume source buffer produce output internally. The change to fractions 7/20 * 21/32 helps to start consuming source buffer in the first copy. However due to 32 frames (at intermediate 16.8 kHz) need for second stage to process the sink buffer fill starts still after two copies. It is addressed in another patch. The change also impacts conversion 192 to 44.1 kHz and 96 kHz to 22.05 kHz. This change only impact the coefficients generator. The actual coefficients change is in the next patch. Signed-off-by: Seppo Ingalsuo --- src/audio/src/tune/src_factor2_lm.m | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/audio/src/tune/src_factor2_lm.m b/src/audio/src/tune/src_factor2_lm.m index 58eb02227207..c022d4bbf9bc 100644 --- a/src/audio/src/tune/src_factor2_lm.m +++ b/src/audio/src/tune/src_factor2_lm.m @@ -53,7 +53,7 @@ %% Hand fixing for some ratios, guide to reuse some common filters if (l==147) && (m==640) - l01 = 7; m01 = 8; l02 = l/l01; m02 = m/m01; % 192 to 44.1 + l01 = 7; m01 = 20; l02 = l/l01; m02 = m/m01; % 192 to 44.1, 48 to 11.025 end if (l==147) && (m==320) l01 = 7; m01 = 8; l02 = l/l01; m02 = m/m01; % 96 to 44.1 From 9d56d1dcd26a1c3e7d03cafde467bae27024e83c Mon Sep 17 00:00:00 2001 From: Seppo Ingalsuo Date: Fri, 8 Aug 2025 19:16:49 +0300 Subject: [PATCH 3/3] Audio: SRC: Update coefficients for 48 kHz to 11.025 kHz This change updates the actual coefficients for changed fractions for 11.025 kHz. The purpose of the change is to consume and produce slightly data with less jitter in amount of data. Signed-off-by: Seppo Ingalsuo --- .../src/coef/src_ipc4_int32_7_20_2976_5000.h | 465 ++++++++++++++++++ src/audio/src/coef/src_ipc4_int32_define.h | 4 +- src/audio/src/coef/src_ipc4_int32_table.h | 14 +- 3 files changed, 474 insertions(+), 9 deletions(-) create mode 100644 src/audio/src/coef/src_ipc4_int32_7_20_2976_5000.h diff --git a/src/audio/src/coef/src_ipc4_int32_7_20_2976_5000.h b/src/audio/src/coef/src_ipc4_int32_7_20_2976_5000.h new file mode 100644 index 000000000000..f44fdc11575b --- /dev/null +++ b/src/audio/src/coef/src_ipc4_int32_7_20_2976_5000.h @@ -0,0 +1,465 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2025 Intel Corporation. All rights reserved. + * + */ + +/** \cond GENERATED_BY_TOOLS_TUNE_SRC */ +#include + +__cold_rodata static const int32_t src_int32_7_20_2976_5000_fir[448] = { + 96136, + 606866, + 976539, + 389294, + -1415601, + -3291283, + -3026329, + 748055, + 6388870, + 9159801, + 4502606, + -7096360, + -17966427, + -17344289, + -426571, + 24369181, + 37693289, + 22743792, + -18341135, + -59148016, + -63495293, + -13786020, + 66901555, + 120024138, + 88497439, + -35003670, + -183246483, + -238452106, + -99399181, + 246698369, + 695868884, + 1067946576, + 1198103305, + 1026561116, + 631902631, + 187354594, + -132920779, + -240774404, + -164825398, + -13499971, + 99248096, + 116616934, + 55484795, + -23808012, + -66155206, + -54765887, + -11654795, + 26808366, + 37268305, + 21023726, + -3678790, + -18443075, + -16883913, + -5237362, + 5684002, + 9145601, + 5628073, + 15811, + -3271895, + -3100368, + -1109745, + 554512, + 964096, + 525031, + 153041, + 686581, + 968539, + 196587, + -1725091, + -3437216, + -2703623, + 1524407, + 7091268, + 9013377, + 3166003, + -8946965, + -18804138, + -15888565, + 3007520, + 27477173, + 37507074, + 18100416, + -25041728, + -62753796, + -59657734, + -3064714, + 77756467, + 121615360, + 75733512, + -57107366, + -199742754, + -232007486, + -61440703, + 308285292, + 758235944, + 1104206035, + 1191696738, + 980452348, + 566918467, + 130704248, + -161896058, + -239203703, + -144859983, + 7109638, + 107918008, + 111530978, + 43710303, + -33003975, + -67647733, + -49711983, + -5089096, + 30255542, + 36267967, + 17506733, + -6705223, + -19185593, + -15587870, + -3401417, + 6699651, + 8981180, + 4825876, + -662668, + -3441830, + -2871664, + -812999, + 691649, + 933711, + 443296, + 217220, + 761754, + 937824, + -22338, + -2032167, + -3531286, + -2303682, + 2333656, + 7718193, + 8698219, + 1688213, + -10756025, + -19368359, + -14081469, + 6574118, + 30282554, + 36682516, + 12928498, + -31644975, + -65486793, + -54651283, + 8211924, + 87845044, + 121275812, + 61058581, + -79492538, + -213940154, + -221251319, + -19208680, + 371629406, + 818429013, + 1134984843, + 1178947110, + 930066183, + 501497501, + 77157451, + -186269379, + -234005340, + -123732029, + 26558470, + 114473948, + 104922924, + 31778707, + -41265704, + -68001183, + -44096999, + 1256273, + 33058488, + 34735839, + 13883775, + -9467877, + -19578421, + -14111485, + -1617818, + 7542480, + 8678916, + 3998908, + -1279362, + -3538922, + -2612520, + -530201, + 800745, + 888035, + 363647, + 287807, + 829802, + 882423, + -265503, + -2330286, + -3567102, + -1827923, + 3163143, + 8252820, + 8208808, + 86687, + -12489194, + -19633644, + -11935033, + 10218997, + 32722129, + 35202060, + 7289642, + -38035714, + -67260692, + -48504409, + 19884222, + 96965667, + 118915939, + 44609742, + -101819658, + -225476236, + -206038134, + 27080252, + 436214086, + 875886423, + 1159980662, + 1159980662, + 875886423, + 436214086, + 27080252, + -206038134, + -225476236, + -101819658, + 44609742, + 118915939, + 96965667, + 19884222, + -48504409, + -67260692, + -38035714, + 7289642, + 35202060, + 32722129, + 10218997, + -11935033, + -19633644, + -12489194, + 86687, + 8208808, + 8252820, + 3163143, + -1827923, + -3567102, + -2330286, + -265503, + 882423, + 829802, + 287807, + 363647, + 888035, + 800745, + -530201, + -2612520, + -3538922, + -1279362, + 3998908, + 8678916, + 7542480, + -1617818, + -14111485, + -19578421, + -9467877, + 13883775, + 34735839, + 33058488, + 1256273, + -44096999, + -68001183, + -41265704, + 31778707, + 104922924, + 114473948, + 26558470, + -123732029, + -234005340, + -186269379, + 77157451, + 501497501, + 930066183, + 1178947110, + 1134984843, + 818429013, + 371629406, + -19208680, + -221251319, + -213940154, + -79492538, + 61058581, + 121275812, + 87845044, + 8211924, + -54651283, + -65486793, + -31644975, + 12928498, + 36682516, + 30282554, + 6574118, + -14081469, + -19368359, + -10756025, + 1688213, + 8698219, + 7718193, + 2333656, + -2303682, + -3531286, + -2032167, + -22338, + 937824, + 761754, + 217220, + 443296, + 933711, + 691649, + -812999, + -2871664, + -3441830, + -662668, + 4825876, + 8981180, + 6699651, + -3401417, + -15587870, + -19185593, + -6705223, + 17506733, + 36267967, + 30255542, + -5089096, + -49711983, + -67647733, + -33003975, + 43710303, + 111530978, + 107918008, + 7109638, + -144859983, + -239203703, + -161896058, + 130704248, + 566918467, + 980452348, + 1191696738, + 1104206035, + 758235944, + 308285292, + -61440703, + -232007486, + -199742754, + -57107366, + 75733512, + 121615360, + 77756467, + -3064714, + -59657734, + -62753796, + -25041728, + 18100416, + 37507074, + 27477173, + 3007520, + -15888565, + -18804138, + -8946965, + 3166003, + 9013377, + 7091268, + 1524407, + -2703623, + -3437216, + -1725091, + 196587, + 968539, + 686581, + 153041, + 525031, + 964096, + 554512, + -1109745, + -3100368, + -3271895, + 15811, + 5628073, + 9145601, + 5684002, + -5237362, + -16883913, + -18443075, + -3678790, + 21023726, + 37268305, + 26808366, + -11654795, + -54765887, + -66155206, + -23808012, + 55484795, + 116616934, + 99248096, + -13499971, + -164825398, + -240774404, + -132920779, + 187354594, + 631902631, + 1026561116, + 1198103305, + 1067946576, + 695868884, + 246698369, + -99399181, + -238452106, + -183246483, + -35003670, + 88497439, + 120024138, + 66901555, + -13786020, + -63495293, + -59148016, + -18341135, + 22743792, + 37693289, + 24369181, + -426571, + -17344289, + -17966427, + -7096360, + 4502606, + 9159801, + 6388870, + 748055, + -3026329, + -3291283, + -1415601, + 389294, + 976539, + 606866, + 96136 + +}; + +static const struct src_stage src_int32_7_20_2976_5000 = { + 17, 6, 7, 64, 448, 20, 7, 0, 1, + src_int32_7_20_2976_5000_fir}; +/** \endcond */ diff --git a/src/audio/src/coef/src_ipc4_int32_define.h b/src/audio/src/coef/src_ipc4_int32_define.h index 8eb7de206a8b..57412c417622 100644 --- a/src/audio/src/coef/src_ipc4_int32_define.h +++ b/src/audio/src/coef/src_ipc4_int32_define.h @@ -10,13 +10,13 @@ /* SRC constants */ #define MAX_FIR_DELAY_SIZE 1305 #define MAX_OUT_DELAY_SIZE 3844 -#define MAX_BLK_IN 80 +#define MAX_BLK_IN 40 #define MAX_BLK_OUT 64 #define NUM_IN_FS 16 #define NUM_OUT_FS 13 #define STAGE1_TIMES_MAX 32 #define STAGE2_TIMES_MAX 40 #define STAGE_BUF_SIZE 840 -#define NUM_ALL_COEFFICIENTS 76328 +#define NUM_ALL_COEFFICIENTS 73416 #endif /* __SOF_AUDIO_COEFFICIENTS_SRC_SRC_IPC4_INT32_DEFINE_H__ */ diff --git a/src/audio/src/coef/src_ipc4_int32_table.h b/src/audio/src/coef/src_ipc4_int32_table.h index 96bfe2383016..76c005649b1b 100644 --- a/src/audio/src/coef/src_ipc4_int32_table.h +++ b/src/audio/src/coef/src_ipc4_int32_table.h @@ -50,6 +50,7 @@ #include "src_ipc4_int32_7_8_2468_5000.h" #include "src_ipc4_int32_7_8_2721_5000.h" #include "src_ipc4_int32_7_8_4535_5000.h" +#include "src_ipc4_int32_7_20_2976_5000.h" #include "src_ipc4_int32_7_40_2976_5000.h" #include "src_ipc4_int32_8_7_1361_5000.h" #include "src_ipc4_int32_8_7_2468_5000.h" @@ -93,7 +94,6 @@ #include "src_ipc4_int32_21_32_4535_5000.h" #include "src_ipc4_int32_21_40_2381_5000.h" #include "src_ipc4_int32_21_40_3968_5000.h" -#include "src_ipc4_int32_21_80_3968_5000.h" #include "src_ipc4_int32_32_21_4535_5000.h" #include "src_ipc4_int32_40_7_2976_5000.h" #include "src_ipc4_int32_40_21_2381_5000.h" @@ -127,7 +127,7 @@ static const struct src_stage * const src_table1[13][16] = { &src_int32_0_0_0_0, &src_int32_0_0_0_0, &src_int32_0_0_0_0, &src_int32_0_0_0_0, &src_int32_0_0_0_0, &src_int32_0_0_0_0, - &src_int32_21_80_3968_5000, &src_int32_0_0_0_0, + &src_int32_7_20_2976_5000, &src_int32_0_0_0_0, &src_int32_0_0_0_0, &src_int32_7_40_2976_5000, &src_int32_0_0_0_0, &src_int32_0_0_0_0 }, @@ -146,7 +146,7 @@ static const struct src_stage * const src_table1[13][16] = { &src_int32_0_0_0_0, &src_int32_0_0_0_0, &src_int32_0_0_0_0, &src_int32_0_0_0_0, &src_int32_21_40_3968_5000, &src_int32_0_0_0_0, - &src_int32_0_0_0_0, &src_int32_21_80_3968_5000, + &src_int32_0_0_0_0, &src_int32_7_20_2976_5000, &src_int32_0_0_0_0, &src_int32_0_0_0_0 }, { &src_int32_3_1_4535_5000, &src_int32_8_7_4535_5000, @@ -174,7 +174,7 @@ static const struct src_stage * const src_table1[13][16] = { &src_int32_7_3_4535_5000, &src_int32_1_1_0_0, &src_int32_21_20_4167_5000, &src_int32_21_20_3125_5000, &src_int32_1_2_4535_5000, &src_int32_21_40_3968_5000, - &src_int32_1_2_2268_5000, &src_int32_21_80_3968_5000 + &src_int32_1_2_2268_5000, &src_int32_7_20_2976_5000 }, { &src_int32_2_1_4535_5000, &src_int32_32_21_4535_5000, &src_int32_2_1_4535_5000, &src_int32_3_1_4535_5000, @@ -247,7 +247,7 @@ static const struct src_stage * const src_table2[13][16] = { &src_int32_0_0_0_0, &src_int32_0_0_0_0, &src_int32_0_0_0_0, &src_int32_0_0_0_0, &src_int32_0_0_0_0, &src_int32_0_0_0_0, - &src_int32_7_8_4535_5000, &src_int32_0_0_0_0, + &src_int32_21_32_4535_5000, &src_int32_0_0_0_0, &src_int32_0_0_0_0, &src_int32_21_32_4535_5000, &src_int32_0_0_0_0, &src_int32_0_0_0_0 }, @@ -266,7 +266,7 @@ static const struct src_stage * const src_table2[13][16] = { &src_int32_0_0_0_0, &src_int32_0_0_0_0, &src_int32_0_0_0_0, &src_int32_0_0_0_0, &src_int32_7_8_4535_5000, &src_int32_0_0_0_0, - &src_int32_0_0_0_0, &src_int32_7_8_4535_5000, + &src_int32_0_0_0_0, &src_int32_21_32_4535_5000, &src_int32_0_0_0_0, &src_int32_0_0_0_0 }, { &src_int32_1_1_0_0, &src_int32_40_21_3968_5000, @@ -294,7 +294,7 @@ static const struct src_stage * const src_table2[13][16] = { &src_int32_1_2_3887_5000, &src_int32_1_1_0_0, &src_int32_7_8_4535_5000, &src_int32_21_32_4535_5000, &src_int32_1_1_0_0, &src_int32_7_8_4535_5000, - &src_int32_1_2_4535_5000, &src_int32_7_8_4535_5000 + &src_int32_1_2_4535_5000, &src_int32_21_32_4535_5000 }, { &src_int32_3_1_2268_5000, &src_int32_20_7_2976_5000, &src_int32_2_1_2268_5000, &src_int32_1_1_0_0,