dts: arm: renesas: ra: Add support MRAM node on SoC dts layer

- Add support MRAM node on Renesas SoC dts layer for RA8P1, RA8T2
- Move the MRAM and SRAM resource defination to SoC dts layer

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>

Author: khoa-nguyen-18

boards/renesas/ek_ra8p1/ek_ra8p1.dtsi

@@ -113,28 +113,6 @@
 	};
 };
 
-&flash {
-	flash0: flash@2000000 {
-		compatible = "soc-nv-flash";
-		reg = <0x2000000 0x80000>;
-	};
-
-	flash1: flash@2080000 {
-		compatible = "soc-nv-flash";
-		reg = <0x2080000 0x80000>;
-	};
-};
-
-&sram {
-	sram0: sram@22000000 {
-		reg = <0x22000000 0xea000>;
-	};
-
-	sram1: sram@220ea000 {
-		reg = <0x220ea000 0xea000>;
-	};
-};
-
 &sciclk {
 	clocks = <&pll2r>;
 	div = <4>;

boards/renesas/mck_ra8t2/mck_ra8t2.dtsi

@@ -88,13 +88,6 @@
 	};
 };
 
-&flash {
-	flash0: flash@2000000 {
-		compatible = "soc-nv-flash";
-		reg = <0x2000000 DT_SIZE_K(1024)>;
-	};
-};
-
 &sciclk {
 	status = "okay";
 };

dts/arm/renesas/ra/ra8/r7ka8p1kflcac.dtsi

@@ -9,9 +9,32 @@
 
 / {
 	soc {
-		sram: memory@22000000 {
+		mram-controller@4013c000 {
+			code_mram_cm85: mram@2000000 {
+				compatible = "renesas,ra-nv-mram";
+				reg = <0x2000000 DT_SIZE_K(768)>;
+				write-block-size = <1>;
+				erase-block-size = <32>;
+			};
+
+			code_mram_cm33: mram@20c0000 {
+				compatible = "renesas,ra-nv-mram";
+				reg = <0x20c0000 DT_SIZE_K(256)>;
+				write-block-size = <1>;
+				erase-block-size = <32>;
+			};
+		};
+
+		sram0: memory@22000000 {
+			compatible = "mmio-sram";
+			reg = <0x22000000 DT_SIZE_K(1404)>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
+		sram1: memory@2215f000 {
 			compatible = "mmio-sram";
-			reg = <0x22000000 0x1d4000>;
+			reg = <0x2215f000 DT_SIZE_K(468)>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 		};

dts/arm/renesas/ra/ra8/r7ka8t2lfecac.dtsi

@@ -8,9 +8,20 @@
 
 / {
 	soc {
+		mram-controller@4013c000 {
+			code_mram_cm85: mram@2000000 {
+				compatible = "renesas,ra-nv-mram";
+				reg = <0x2000000 DT_SIZE_M(1)>;
+				write-block-size = <1>;
+				erase-block-size = <32>;
+			};
+		};
+
 		sram0: memory@22000000 {
 			compatible = "mmio-sram";
 			reg = <0x22000000 DT_SIZE_K(1664)>;
+			#address-cells = <1>;
+			#size-cells = <1>;
 		};
 	};
 };

dts/arm/renesas/ra/ra8/ra8x2.dtsi

@@ -73,10 +73,12 @@
 			status = "okay";
 		};
 
-		flash: flash-controller@4013c000 {
+		mram: mram-controller@4013c000 {
+			compatible = "renesas,ra-mram-controller";
 			reg = <0x4013c000 0x4000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+			status = "okay";
 		};
 
 		ioport0: gpio@40400000 {