drivers: spi: siwx91x: Add support for higher burst rates using GPDMA

Enable higher SPI burst sizes when using GPDMA to improve throughput.
Bursts are only enabled when both TX and RX channels use GPDMA and
the SPI clock frequency is at least 10 MHz, as DMA flow control is
unreliable at lower SPI rates.

Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>

Author: smalae

drivers/spi/spi_silabs_siwx91x_gspi.c

@@ -27,6 +27,7 @@ LOG_MODULE_REGISTER(spi_siwx91x_gspi, CONFIG_SPI_LOG_LEVEL);
 #define GSPI_MAX_BAUDRATE_FOR_DYNAMIC_CLOCK   110000000
 #define GSPI_MAX_BAUDRATE_FOR_POS_EDGE_SAMPLE 40000000
 #define GSPI_DMA_MAX_DESCRIPTOR_TRANSFER_SIZE 4096
+#define SPI_HIGH_BURST_FREQ_THRESHOLD_HZ      10000000
 
 /* Warning for unsupported configurations */
 #if defined(CONFIG_SPI_ASYNC) && !defined(CONFIG_SPI_SILABS_SIWX91X_GSPI_DMA)
@@ -247,16 +248,16 @@ static void gspi_siwx91x_dma_tx_callback(const struct device *dev, void *user_da
 
 static int gspi_siwx91x_dma_config(const struct device *dev,
 				   struct gspi_siwx91x_dma_channel *channel, uint32_t block_count,
-				   bool is_tx, uint8_t dfs)
+				   bool is_tx, uint8_t dfs, uint8_t burst_size)
 {
 	struct dma_config cfg = {
 		.channel_direction = is_tx ? MEMORY_TO_PERIPHERAL : PERIPHERAL_TO_MEMORY,
 		.channel_priority = 1,
 		.complete_callback_en = 0,
 		.source_data_size = dfs,
 		.dest_data_size = dfs,
-		.source_burst_length = 1,
-		.dest_burst_length = 1,
+		.source_burst_length = burst_size,
+		.dest_burst_length = burst_size,
 		.block_count = block_count,
 		.head_block = channel->dma_descriptors,
 		.dma_slot = channel->dma_slot,
@@ -374,7 +375,8 @@ static void gspi_siwx91x_reset_desc(struct gspi_siwx91x_dma_channel *channel)
 static int gspi_siwx91x_prepare_dma_channel(const struct device *spi_dev,
 					    const struct spi_buf *buffer, size_t buffer_count,
 					    struct gspi_siwx91x_dma_channel *channel,
-					    size_t padded_transaction_size, bool is_tx)
+					    size_t padded_transaction_size, bool is_tx,
+					    uint8_t burst_size)
 {
 	const struct gspi_siwx91x_config *cfg = spi_dev->config;
 	struct gspi_siwx91x_data *data = spi_dev->data;
@@ -391,12 +393,13 @@ static int gspi_siwx91x_prepare_dma_channel(const struct device *spi_dev,
 	}
 
 	ret = gspi_siwx91x_dma_config(spi_dev, channel,
-				      ARRAY_INDEX(channel->dma_descriptors, desc) + 1, is_tx, dfs);
+				      ARRAY_INDEX(channel->dma_descriptors, desc) + 1, is_tx, dfs,
+				      burst_size);
 	return ret;
 }
 
 static int gspi_siwx91x_prepare_dma_transaction(const struct device *dev,
-						size_t padded_transaction_size)
+						size_t padded_transaction_size, uint8_t burst_size)
 {
 	int ret;
 	struct gspi_siwx91x_data *data = dev->data;
@@ -406,13 +409,15 @@ static int gspi_siwx91x_prepare_dma_transaction(const struct device *dev,
 	}
 
 	ret = gspi_siwx91x_prepare_dma_channel(dev, data->ctx.current_tx, data->ctx.tx_count,
-					       &data->dma_tx, padded_transaction_size, true);
+					       &data->dma_tx, padded_transaction_size, true,
+					       burst_size);
 	if (ret) {
 		return ret;
 	}
 
 	ret = gspi_siwx91x_prepare_dma_channel(dev, data->ctx.current_rx, data->ctx.rx_count,
-					       &data->dma_rx, padded_transaction_size, false);
+					       &data->dma_rx, padded_transaction_size, false,
+					       burst_size);
 
 	return ret;
 }
@@ -425,6 +430,34 @@ static size_t gspi_siwx91x_longest_transfer_size(struct spi_context *instance_ct
 	return MAX(tx_transfer_size, rx_transfer_size);
 }
 
+static int gspi_siwx91x_burst_size_buf(const struct spi_buf *dma_spi_buf)
+{
+	int burst_len = 4;
+
+	if (!dma_spi_buf->buf || !dma_spi_buf->len) {
+		return burst_len;
+	}
+
+	burst_len = MIN(burst_len, BIT(find_lsb_set((uint32_t)dma_spi_buf->buf) - 1));
+	burst_len = MIN(burst_len, BIT(find_lsb_set(dma_spi_buf->len) - 1));
+
+	return burst_len;
+}
+
+static int gspi_siwx91x_burst_size(struct spi_context *ctx)
+{
+	int burst_len = 4;
+
+	for (int i = 0; i < ctx->tx_count; i++) {
+		burst_len = MIN(burst_len, gspi_siwx91x_burst_size_buf(ctx->current_tx + i));
+	}
+
+	for (int i = 0; i < ctx->rx_count; i++) {
+		burst_len = MIN(burst_len, gspi_siwx91x_burst_size_buf(ctx->current_rx + i));
+	}
+
+	return burst_len;
+}
 #endif /* CONFIG_SPI_SILABS_SIWX91X_GSPI_DMA */
 
 static int gspi_siwx91x_transceive_dma(const struct device *dev, const struct spi_config *config)
@@ -435,17 +468,42 @@ static int gspi_siwx91x_transceive_dma(const struct device *dev, const struct sp
 	const struct device *dma_dev = data->dma_rx.dma_dev;
 	struct spi_context *ctx = &data->ctx;
 	size_t padded_transaction_size = gspi_siwx91x_longest_transfer_size(ctx);
+	uint8_t burst_size = 1;
 	int ret = 0;
 
 	if (padded_transaction_size == 0) {
 		return -EINVAL;
 	}
 
+	if (config->frequency >= SPI_HIGH_BURST_FREQ_THRESHOLD_HZ &&
+	    data->dma_rx.dma_slot != 0xFF && data->dma_tx.dma_slot != 0xFF) {
+		/* NOTE: This condition ensures that high burst rates are only used with GPDMA.
+		 *
+		 * GPDMA (General-Purpose DMA) supports higher burst rates and operates at higher
+		 * frequencies, unlike UDMA, which does not handle such speeds reliably.
+		 * Therefore, the DMA slots are validated to ensure that the active DMA channels
+		 * belong to GPDMA before enabling higher burst rates.
+		 *
+		 * Currently, DMA flow control (DMA_FLOW_CTRL) is not functioning correctly for
+		 * memory-to-peripheral and peripheral-to-memory transfers. As a result, at lower
+		 * SPI clock frequencies, GPDMA may read/write FIFOs at a much higher rate than the
+		 * SPI peripheral, causing synchronization issues. However, at higher SPI clock
+		 * frequencies (≥ 10 MHz), this timing mismatch is negligible, and higher burst
+		 * rates operate as expected.
+		 *
+		 * In summary, high burst rates are safely enabled only for SPI transfers running
+		 * at or above 10 MHz when using GPDMA.
+		 */
+		burst_size = gspi_siwx91x_burst_size(ctx);
+	}
+
 	cfg->reg->GSPI_FIFO_THRLD_b.RFIFO_RESET = 1;
 	cfg->reg->GSPI_FIFO_THRLD_b.WFIFO_RESET = 1;
 	cfg->reg->GSPI_FIFO_THRLD = 0;
+	cfg->reg->GSPI_FIFO_THRLD_b.FIFO_AEMPTY_THRLD = burst_size - 1;
+	cfg->reg->GSPI_FIFO_THRLD_b.FIFO_AFULL_THRLD = burst_size - 1;
 
-	ret = gspi_siwx91x_prepare_dma_transaction(dev, padded_transaction_size);
+	ret = gspi_siwx91x_prepare_dma_transaction(dev, padded_transaction_size, burst_size);
 	if (ret) {
 		return ret;
 	}