xtensa: save EXCCAUSE/EXCVADDR in BSA during exception

This saves the EXCCAUSE and EXCVADDR into BSA during exception.
These will then be used during exception handling. The reason
for doing this instead of reading from both registers during
exception handing is that another exception will override
the value in these register (e.g. DTLB miss). When returning to
the previous exception handler, these register no longer
contains the original exception cause and address. We need to
save it so that we are actually handling the orignal exception.

Coredump also now uses the EXCCAUSE and EXCVADDR from BSA
instead of reading the registers.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>

Author: dcpleung

arch/xtensa/core/coredump.c

@@ -135,8 +135,6 @@ void arch_coredump_info_dump(const struct arch_esf *esf)
 	xtensa_coredump_fault_sp = (uint32_t)esf;
 #endif
 
-	__asm__ volatile("rsr.exccause %0" : "=r"(arch_blk.r.exccause));
-
 	_xtensa_irq_stack_frame_raw_t *frame = (void *)esf;
 	_xtensa_irq_bsa_t *bsa = frame->ptr_to_bsa;
 	uintptr_t num_high_regs;
@@ -150,7 +148,7 @@ void arch_coredump_info_dump(const struct arch_esf *esf)
 	regs_blk_remaining = (int)num_high_regs / 4;
 
 	arch_blk.r.pc = bsa->pc;
-	__asm__ volatile("rsr.excvaddr %0" : "=r"(arch_blk.r.excvaddr));
+	arch_blk.r.excvaddr = bsa->excvaddr;
 	arch_blk.r.ps = bsa->ps;
 #if XCHAL_HAVE_S32C1I
 	arch_blk.r.scompare1 = bsa->scompare1;
@@ -160,6 +158,7 @@ void arch_coredump_info_dump(const struct arch_esf *esf)
 	arch_blk.r.a1 = (uint32_t)((char *)bsa) + sizeof(*bsa);
 	arch_blk.r.a2 = bsa->a2;
 	arch_blk.r.a3 = bsa->a3;
+	arch_blk.r.exccause = bsa->exccause;
 	if (regs_blk_remaining > 0) {
 		regs_blk_remaining--;
 

arch/xtensa/core/gen_zsr.py

@@ -31,7 +31,7 @@ def parse_args():
 
 NEEDED = ["A0SAVE", "CPU"]
 if args.mmu:
-    NEEDED += ["DBLEXC", "DEPC_SAVE", "EXCCAUSE_SAVE"]
+    NEEDED += ["DBLEXC", "DEPC_SAVE"]
 if args.flush_reg:
     NEEDED += ["FLUSH"]
 

arch/xtensa/core/offsets/offsets.c

@@ -22,6 +22,7 @@ GEN_OFFSET_SYM(_xtensa_irq_bsa_t, a2);
 GEN_OFFSET_SYM(_xtensa_irq_bsa_t, a3);
 
 GEN_OFFSET_SYM(_xtensa_irq_bsa_t, exccause);
+GEN_OFFSET_SYM(_xtensa_irq_bsa_t, excvaddr);
 GEN_OFFSET_SYM(_xtensa_irq_bsa_t, pc);
 GEN_OFFSET_SYM(_xtensa_irq_bsa_t, ps);
 GEN_OFFSET_SYM(_xtensa_irq_bsa_t, sar);

arch/xtensa/core/vector_handlers.c

@@ -220,38 +220,35 @@ static inline unsigned int get_bits(int offset, int num_bits, unsigned int val)
 	return val & mask;
 }
 
-static void print_fatal_exception(void *print_stack, int cause,
-				  bool is_dblexc, uint32_t depc)
+static void print_fatal_exception(void *print_stack, bool is_dblexc, uint32_t depc)
 {
 	void *pc;
-	uint32_t ps, vaddr;
+	uint32_t ps;
 	_xtensa_irq_bsa_t *bsa = (void *)*(int **)print_stack;
 
-	__asm__ volatile("rsr.excvaddr %0" : "=r"(vaddr));
-
 	if (is_dblexc) {
 		EXCEPTION_DUMP(" ** FATAL EXCEPTION (DOUBLE)");
 	} else {
 		EXCEPTION_DUMP(" ** FATAL EXCEPTION");
 	}
 
-	EXCEPTION_DUMP(" ** CPU %d EXCCAUSE %d (%s)",
-		arch_curr_cpu()->id, cause,
-		xtensa_exccause(cause));
+	EXCEPTION_DUMP(" ** CPU %d EXCCAUSE %u (%s)",
+		arch_curr_cpu()->id, (uint32_t)bsa->exccause,
+		xtensa_exccause(bsa->exccause));
 
 	/* Don't print information if the BSA area is invalid as any elements
 	 * obtained via de-referencing the pointer are probably also invalid.
 	 * Or worse, cause another access violation.
 	 */
 	if (xtensa_is_outside_stack_bounds((uintptr_t)bsa, sizeof(*bsa), UINT32_MAX)) {
-		EXCEPTION_DUMP(" ** VADDR %p Invalid SP %p", (void *)vaddr, print_stack);
+		EXCEPTION_DUMP(" ** VADDR %p Invalid SP %p", (void *)bsa->excvaddr, print_stack);
 		return;
 	}
 
 	ps = bsa->ps;
 	pc = (void *)bsa->pc;
 
-	EXCEPTION_DUMP(" **  PC %p VADDR %p", pc, (void *)vaddr);
+	EXCEPTION_DUMP(" **  PC %p VADDR %p", pc, (void *)bsa->excvaddr);
 
 	if (is_dblexc) {
 		EXCEPTION_DUMP(" **  DEPC %p", (void *)depc);
@@ -547,13 +544,12 @@ void *xtensa_excint1_c(void *esf)
 
 #ifdef CONFIG_XTENSA_MMU
 	depc = XTENSA_RSR(ZSR_DEPC_SAVE_STR);
-	cause = XTENSA_RSR(ZSR_EXCCAUSE_SAVE_STR);
 
 	is_dblexc = (depc != 0U);
-#else /* CONFIG_XTENSA_MMU */
-	__asm__ volatile("rsr.exccause %0" : "=r"(cause));
 #endif /* CONFIG_XTENSA_MMU */
 
+	cause = bsa->exccause;
+
 	switch (cause) {
 	case EXCCAUSE_LEVEL1_INTERRUPT:
 #ifdef CONFIG_XTENSA_MMU
@@ -664,7 +660,6 @@ void *xtensa_excint1_c(void *esf)
 		if (cause == EXCCAUSE_ILLEGAL) {
 			if (pc == (void *)&xtensa_arch_except_epc) {
 				cause = 63;
-				__asm__ volatile("wsr.exccause %0" : : "r"(cause));
 				reason = bsa->a2;
 			} else if (pc == (void *)&xtensa_arch_kernel_oops_epc) {
 				cause = 64; /* kernel oops */
@@ -677,11 +672,13 @@ void *xtensa_excint1_c(void *esf)
 				 */
 				print_stack = (void *)bsa->a3;
 			}
+
+			bsa->exccause = cause;
 		}
 
 skip_checks:
 		if (reason != K_ERR_KERNEL_OOPS) {
-			print_fatal_exception(print_stack, cause, is_dblexc, depc);
+			print_fatal_exception(print_stack, is_dblexc, depc);
 		}
 #ifdef CONFIG_XTENSA_EXCEPTION_ENTER_GDB
 		extern void z_gdb_isr(struct arch_esf *esf);

arch/xtensa/include/xtensa_asm2_context.h

@@ -116,7 +116,7 @@
 #endif
 
 /* Must have fields regardless of features. */
-#define _BSA_PADDING_COMMON		(sizeof(uintptr_t) * 12U)
+#define _BSA_PADDING_COMMON		(sizeof(uintptr_t) * 13U)
 
 /* Raw size by adding up all the above. */
 #define _BSA_PADDING_BASE_SIZE		\
@@ -194,6 +194,7 @@ struct xtensa_irq_base_save_area {
 #endif
 
 	uintptr_t exccause;
+	uintptr_t excvaddr;
 
 #if XCHAL_HAVE_LOOPS
 	uintptr_t lcount;

arch/xtensa/include/xtensa_asm2_s.h

@@ -663,7 +663,7 @@ _Level\LVL\()Vector:
 	 * For double exception, DEPC in saved in earlier vector
 	 * code.
 	 */
-	wsr a0, ZSR_EXCCAUSE_SAVE
+	wsr a0, ZSR_A0SAVE
 
 	esync
 
@@ -690,15 +690,11 @@ _Level\LVL\()Vector:
 	 * jump to an infinite loop, or quit the simulator, or invoke
 	 * debugger.
 	 */
-	rsr a0, ZSR_EXCCAUSE_SAVE
+	rsr a0, ZSR_A0SAVE
 	j _TripleFault
 
 _not_triple_fault:
-	rsr.exccause a0
-
-	xsr a0, ZSR_EXCCAUSE_SAVE
-
-	esync
+	rsr a0, ZSR_A0SAVE
 .endif
 #endif
 
@@ -707,6 +703,16 @@ _Level\LVL\()Vector:
 	s32i a2, a1, ___xtensa_irq_bsa_t_a2_OFFSET
 	s32i a3, a1, ___xtensa_irq_bsa_t_a3_OFFSET
 
+	/* Save registers needed for handling the exception as
+	 * these registers can be overwritten during nested
+	 * exceptions.
+	 */
+	rsr.exccause a0
+	s32i a0, a1, ___xtensa_irq_bsa_t_exccause_OFFSET
+
+	rsr.excvaddr a0
+	s32i a0, a1, ___xtensa_irq_bsa_t_excvaddr_OFFSET
+
 	/* Level "1" is the exception handler, which uses a different
 	 * calling convention.  No special register holds the
 	 * interrupted PS, instead we just assume that the CPU has