zephyrproject-rtos · Vge0rge · Nov 12, 2025 · Nov 11, 2025 · Nov 11, 2025 · Nov 11, 2025
diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_ns.dts b/boards/actinius/icarus/actinius_icarus_nrf9160_ns.dts
@@ -5,7 +5,7 @@
  */
 
 /dts-v1/;
-#include <nordic/nrf9160ns_sica.dtsi>
+#include <nordic/nrf9160_ns_sica.dtsi>
 #include "actinius_icarus_common.dtsi"
 
 / {

diff --git a/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.dts b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.dts
@@ -5,7 +5,7 @@
  */
 
 /dts-v1/;
-#include <nordic/nrf9160ns_sica.dtsi>
+#include <nordic/nrf9160_ns_sica.dtsi>
 #include "actinius_icarus_bee_common.dtsi"
 
 / {

diff --git a/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.dts b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.dts
@@ -5,7 +5,7 @@
  */
 
 /dts-v1/;
-#include <nordic/nrf9160ns_sica.dtsi>
+#include <nordic/nrf9160_ns_sica.dtsi>
 #include "actinius_icarus_som_common.dtsi"
 
 / {

diff --git a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.dts b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.dts
@@ -5,7 +5,7 @@
  */
 
 /dts-v1/;
-#include <nordic/nrf9160ns_sica.dtsi>
+#include <nordic/nrf9160_ns_sica.dtsi>
 #include "actinius_icarus_som_dk_common.dtsi"
 
 / {

diff --git a/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_ns.dts b/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_ns.dts
@@ -6,7 +6,7 @@
  */
 
 /dts-v1/;
-#include <nordic/nrf9160ns_sica.dtsi>
+#include <nordic/nrf9160_ns_sica.dtsi>
 #include "circuitdojo_feather_nrf9160_common.dtsi"
 
 / {

diff --git a/boards/ct/ctcc/ctcc_nrf9161_ns.dts b/boards/ct/ctcc/ctcc_nrf9161_ns.dts
@@ -5,7 +5,7 @@
  */
 
 /dts-v1/;
-#include <nordic/nrf9161ns_laca.dtsi>
+#include <nordic/nrf9161_ns_laca.dtsi>
 #include "ctcc_nrf9161_common.dtsi"
 
 / {

diff --git a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts
@@ -6,7 +6,7 @@
  */
 
 /dts-v1/;
-#include <nordic/nrf5340_cpuappns_qkaa.dtsi>
+#include <nordic/nrf5340_cpuapp_ns_qkaa.dtsi>
 #include "bl5340_dvk_nrf5340_cpuapp_common.dtsi"
 
 / {

diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.dts b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.dts
@@ -9,7 +9,7 @@
 
 #define USE_NON_SECURE_ADDRESS_MAP 1
 
-#include <nordic/nrf54l10_cpuapp.dtsi>
+#include <nordic/nrf54l10_cpuapp_ns.dtsi>
 #include "nrf54l_10_15_cpuapp_common.dtsi"
 
 / {
@@ -29,81 +29,10 @@
 	};
 };
 
-/ {
-	/*
-	 * Default SRAM planning when building for nRF54L10 with ARM TrustZone-M support.
-	 * - Lowest 72 kB SRAM allocated to Secure image (sram0_s).
-	 * - Upper 72 kB SRAM allocated to Non-Secure image (sram0_ns).
-	 *
-	 * nRF54L10 has 192 kB of volatile memory (SRAM) but the last 42kB are reserved for
-	 * the FLPR MCU.
-	 * This static layout needs to be the same with the upstream TF-M layout in the
-	 * header flash_layout.h of the relevant platform. Any updates in the layout
-	 * needs to happen both in the flash_layout.h and in this file at the same time.
-	 */
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		sram0_s: image_s@20000000 {
-			/* Secure image memory */
-			reg = <0x20000000 DT_SIZE_K(72)>;
-		};
-
-		sram0_ns: image_ns@20012000 {
-			/* Non-Secure image memory */
-			reg = <0x20012000 DT_SIZE_K(72)>;
-		};
-	};
-};
-
-&cpuapp_rram {
-	partitions {
-		compatible = "fixed-partitions";
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		/* nRF54L10 has 1012 kB of non volatile memory (RRAM) but the
-		 * last 62kB are reserved for the FLPR MCU.
-		 *
-		 * This static layout needs to be the same with the upstream TF-M layout in the
-		 * header flash_layout.h of the relevant platform. Any updates in the layout
-		 * needs to happen both in the flash_layout.h and in this file at the same time.
-		 */
-		slot0_partition: partition@0 {
-			label = "image-0";
-			reg = <0x0000000 DT_SIZE_K(384)>;
-		};
-
-		tfm_ps_partition: partition@60000 {
-			label = "tfm-ps";
-			reg = <0x00060000 DT_SIZE_K(16)>;
-		};
-
-		tfm_its_partition: partition@64000 {
-			label = "tfm-its";
-			reg = <0x00064000 DT_SIZE_K(16)>;
-		};
-
-		tfm_otp_partition: partition@68000 {
-			label = "tfm-otp";
-			reg = <0x00068000 DT_SIZE_K(8)>;
-		};
-
-		slot0_ns_partition: partition@6A000 {
-			label = "image-0-nonsecure";
-			reg = <0x0006A000 DT_SIZE_K(494)>;
-		};
-
-		storage_partition: partition@E5800 {
-			label = "storage";
-			reg = <0x000E5800 DT_SIZE_K(32)>;
-		};
-	};
-};
-
 &uart30 {
 	/* Disable so that TF-M can use this UART */
 	status = "disabled";
 };
+
+/* Include default memory partition configuration file */
+#include <nordic/nrf54l10_ns_partition.dtsi>
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns.dts b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns.dts
@@ -9,7 +9,7 @@
 
 #define USE_NON_SECURE_ADDRESS_MAP 1
 
-#include <nordic/nrf54l15_cpuapp.dtsi>
+#include <nordic/nrf54l15_cpuapp_ns.dtsi>
 #include "nrf54l_10_15_cpuapp_common.dtsi"
 
 / {
@@ -29,35 +29,6 @@
 	};
 };
 
-/ {
-	/*
-	 * Default SRAM planning when building for nRF54L15 with ARM TrustZone-M support
-	 * - Lowest 80 kB SRAM allocated to Secure image (sram0_s).
-	 * - Upper 80 kB SRAM allocated to Non-Secure image (sram0_ns).
-	 *
-	 * nRF54L15 has 256 kB of volatile memory (SRAM) but the last 96kB are reserved for
-	 * the FLPR MCU.
-	 * This static layout needs to be the same with the upstream TF-M layout in the
-	 * header flash_layout.h of the relevant platform. Any updates in the layout
-	 * needs to happen both in the flash_layout.h and in this file at the same time.
-	 */
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		sram0_s: image_s@20000000 {
-			/* Secure image memory */
-			reg = <0x20000000 DT_SIZE_K(80)>;
-		};
-
-		sram0_ns: image_ns@20014000 {
-			/* Non-Secure image memory */
-			reg = <0x20014000 DT_SIZE_K(80)>;
-		};
-	};
-};
-
 &uart30 {
 	/* Disable so that TF-M can use this UART */
 	status = "disabled";

diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.dts b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.dts
@@ -9,7 +9,7 @@
 
 #define USE_NON_SECURE_ADDRESS_MAP 1
 
-#include <nordic/nrf54l15_cpuapp.dtsi>
+#include <nordic/nrf54l15_cpuapp_ns.dtsi>
 #include "nrf54l15_cpuapp_common.dtsi"
 
 / {
@@ -29,35 +29,6 @@
 	};
 };
 
-/ {
-	/*
-	 * Default SRAM planning when building for nRF54L15 with ARM TrustZone-M support
-	 * - Lowest 80 kB SRAM allocated to Secure image (sram0_s).
-	 * - Upper 80 kB SRAM allocated to Non-Secure image (sram0_ns).
-	 *
-	 * nRF54L15 has 256 kB of volatile memory (SRAM) but the last 96kB are reserved for
-	 * the FLPR MCU.
-	 * This static layout needs to be the same with the upstream TF-M layout in the
-	 * header flash_layout.h of the relevant platform. Any updates in the layout
-	 * needs to happen both in the flash_layout.h and in this file at the same time.
-	 */
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		sram0_s: image_s@20000000 {
-			/* Secure image memory */
-			reg = <0x20000000 DT_SIZE_K(80)>;
-		};
-
-		sram0_ns: image_ns@20014000 {
-			/* Non-Secure image memory */
-			reg = <0x20014000 DT_SIZE_K(80)>;
-		};
-	};
-};
-
 &uart30 {
 	/* Disable so that TF-M can use this UART */
 	status = "disabled";

diff --git a/boards/innblue/innblue21/innblue21_nrf9160_ns.dts b/boards/innblue/innblue21/innblue21_nrf9160_ns.dts
@@ -5,7 +5,7 @@
  */
 
 /dts-v1/;
-#include <nordic/nrf9160ns_sica.dtsi>
+#include <nordic/nrf9160_ns_sica.dtsi>
 #include "innblue21_common.dtsi"
 
 / {

diff --git a/boards/innblue/innblue22/innblue22_nrf9160_ns.dts b/boards/innblue/innblue22/innblue22_nrf9160_ns.dts
@@ -5,7 +5,7 @@
  */
 
 /dts-v1/;
-#include <nordic/nrf9160ns_sica.dtsi>
+#include <nordic/nrf9160_ns_sica.dtsi>
 #include "innblue22_common.dtsi"
 
 / {

diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts
@@ -5,7 +5,7 @@
  */
 
 /dts-v1/;
-#include <nordic/nrf5340_cpuappns_qkaa.dtsi>
+#include <nordic/nrf5340_cpuapp_ns_qkaa.dtsi>
 #include "nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi"
 
 / {

diff --git a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.dts b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.dts
@@ -5,7 +5,7 @@
  */
 
 /dts-v1/;
-#include <nordic/nrf5340_cpuappns_qkaa.dtsi>
+#include <nordic/nrf5340_cpuapp_ns_qkaa.dtsi>
 #include "nrf5340_cpuapp_common.dtsi"
 
 / {

diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.dts b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.dts
@@ -8,7 +8,7 @@
 
 #define USE_NON_SECURE_ADDRESS_MAP 1
 
-#include <nordic/nrf54l10_cpuapp.dtsi>
+#include <nordic/nrf54l10_cpuapp_ns.dtsi>
 #include "nrf54l_05_10_15_cpuapp_common.dtsi"
 
 / {
@@ -28,81 +28,10 @@
 	};
 };
 
-/ {
-	/*
-	 * Default SRAM planning when building for nRF54L10 with ARM TrustZone-M support.
-	 * - Lowest 72 kB SRAM allocated to Secure image (sram0_s).
-	 * - Upper 72 kB SRAM allocated to Non-Secure image (sram0_ns).
-	 *
-	 * nRF54L10 has 192 kB of volatile memory (SRAM) but the last 42kB are reserved for
-	 * the FLPR MCU.
-	 * This static layout needs to be the same with the upstream TF-M layout in the
-	 * header flash_layout.h of the relevant platform. Any updates in the layout
-	 * needs to happen both in the flash_layout.h and in this file at the same time.
-	 */
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		sram0_s: image_s@20000000 {
-			/* Secure image memory */
-			reg = <0x20000000 DT_SIZE_K(72)>;
-		};
-
-		sram0_ns: image_ns@20012000 {
-			/* Non-Secure image memory */
-			reg = <0x20012000 DT_SIZE_K(72)>;
-		};
-	};
-};
-
-&cpuapp_rram {
-	partitions {
-		compatible = "fixed-partitions";
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		/* nRF54L10 has 1012 kB of non volatile memory (RRAM) but the
-		 * last 62kB are reserved for the FLPR MCU.
-		 *
-		 * This static layout needs to be the same with the upstream TF-M layout in the
-		 * header flash_layout.h of the relevant platform. Any updates in the layout
-		 * needs to happen both in the flash_layout.h and in this file at the same time.
-		 */
-		slot0_partition: partition@0 {
-			label = "image-0";
-			reg = <0x0000000 DT_SIZE_K(384)>;
-		};
-
-		tfm_ps_partition: partition@60000 {
-			label = "tfm-ps";
-			reg = <0x00060000 DT_SIZE_K(16)>;
-		};
-
-		tfm_its_partition: partition@64000 {
-			label = "tfm-its";
-			reg = <0x00064000 DT_SIZE_K(16)>;
-		};
-
-		tfm_otp_partition: partition@68000 {
-			label = "tfm-otp";
-			reg = <0x00068000 DT_SIZE_K(8)>;
-		};
-
-		slot0_ns_partition: partition@6A000 {
-			label = "image-0-nonsecure";
-			reg = <0x0006A000 DT_SIZE_K(494)>;
-		};
-
-		storage_partition: partition@E5800 {
-			label = "storage";
-			reg = <0x000E5800 DT_SIZE_K(32)>;
-		};
-	};
-};
-
 &uart30 {
 	/* Disable so that TF-M can use this UART */
 	status = "disabled";
 };
+
+/* Include default memory partition configuration file */
+#include <nordic/nrf54l10_ns_partition.dtsi>