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[libcpu][cortex-m4]Added HardFault_Handler to save floating point registers #10618

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Merged
Rbb666 merged 1 commit into from
Aug 19, 2025
Merged

[libcpu][cortex-m4]Added HardFault_Handler to save floating point registers #10618

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15 changes: 14 additions & 1 deletion libcpu/arm/cortex-m4/context_gcc.S
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Original file line number Diff line number Diff line change
Expand Up @@ -238,10 +238,23 @@ HardFault_Handler:
MRS r0, psp /* get fault context from thread. */
_get_sp_done:

#if defined (__VFP_FP__) && !defined(__SOFTFP__)
TST lr, #0x10 /* if(!EXC_RETURN[4]) */
IT EQ
VSTMDBEQ r0!, {d8 - d15} /* push FPU register s16~s31 */
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The comment incorrectly states 's16~s31' but the instruction saves double precision registers d8-d15. The comment should be corrected to 'd8-d15' or explain that these correspond to s16-s31 in single precision mode.

Suggested change
VSTMDBEQ r0!, {d8 - d15} /* push FPU register s16~s31 */
VSTMDBEQ r0!, {d8 - d15} /* push FPU registers d8-d15 (corresponds to s16~s31 in single precision mode) */

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#endif

STMFD r0!, {r4 - r11} /* push r4 - r11 register */

#if defined (__VFP_FP__) && !defined(__SOFTFP__)
STMFD r0!, {lr} /* push dummy for flag */
MOV r4, #0x00 /* flag = 0 */

TST lr, #0x10 /* if(!EXC_RETURN[4]) */
IT EQ
MOVEQ r4, #0x01 /* flag = 1 */
STMFD r0!, {r4} /* push flag */
#endif

STMFD r0!, {lr} /* push exec_return register */

TST lr, #0x04 /* if(!EXC_RETURN[2]) */
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22 changes: 18 additions & 4 deletions libcpu/arm/cortex-m4/context_iar.S
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Expand Up @@ -237,14 +237,28 @@ HardFault_Handler:
MRS r0, psp ; get fault context from thread.
_get_sp_done

#if defined ( __ARMVFP__ )
TST lr, #0x10 ; if(!EXC_RETURN[4])
BNE skip_push_fpu
VSTMDB r0!, {d8 - d15} ; push FPU register s16~s31
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The comment incorrectly states 's16~s31' but the instruction saves double precision registers d8-d15. The comment should be corrected to 'd8-d15' or explain that these correspond to s16-s31 in single precision mode.

Suggested change
VSTMDB r0!, {d8 - d15} ; push FPU register s16~s31
VSTMDB r0!, {d8 - d15} ; push FPU registers d8-d15 (corresponds to s16~s31 in single precision mode)

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skip_push_fpu
#endif

STMFD r0!, {r4 - r11} ; push r4 - r11 register
;STMFD r0!, {lr} ; push exec_return register

#if defined ( __ARMVFP__ )
SUB r0, r0, #0x04 ; push dummy for flag
STR lr, [r0]
MOV r4, #0x00 ; flag = 0

TST lr, #0x10 ; if(!EXC_RETURN[4])
BNE push_flag
MOV r4, #0x01 ; flag = 1
push_flag
SUB r0, r0, #0x04
STR r4, [r0] ; push flag
#endif

SUB r0, r0, #0x04
STR lr, [r0]
STR lr, [r0] ; push exec_return register

TST lr, #0x04 ; if(!EXC_RETURN[2])
BEQ _update_msp
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13 changes: 12 additions & 1 deletion libcpu/arm/cortex-m4/context_rvds.S
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Expand Up @@ -236,10 +236,21 @@ HardFault_Handler PROC
MRSEQ r0, msp ; [2]=0 ==> Z=1, get fault context from handler.
MRSNE r0, psp ; [2]=1 ==> Z=0, get fault context from thread.

IF {FPU} != "SoftVFP"
TST lr, #0x10 ; if(!EXC_RETURN[4])
VSTMFDEQ r0!, {d8 - d15} ; push FPU register s16~s31
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The comment incorrectly states 's16~s31' but the instruction saves double precision registers d8-d15. The comment should be corrected to 'd8-d15' or explain that these correspond to s16-s31 in single precision mode.

Suggested change
VSTMFDEQ r0!, {d8 - d15} ; push FPU register s16~s31
VSTMFDEQ r0!, {d8 - d15} ; push FPU register d8~d15 (corresponds to s16~s31 in single precision mode)

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The VSTMFDEQ instruction uses full descending stack mode, but this is inconsistent with the STMFD instructions used elsewhere. Consider using VSTMDBEQ for consistency with decrement before operation mode.

Suggested change
VSTMFDEQ r0!, {d8 - d15} ; push FPU register s16~s31
VSTMDBEQ r0!, {d8 - d15} ; push FPU register s16~s31

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ENDIF

STMFD r0!, {r4 - r11} ; push r4 - r11 register

IF {FPU} != "SoftVFP"
STMFD r0!, {lr} ; push dummy for flag
MOV r4, #0x00 ; flag = 0

TST lr, #0x10 ; if(!EXC_RETURN[4])
MOVEQ r4, #0x01 ; flag = 1
STMFD r0!, {r4} ; push flag
ENDIF

STMFD r0!, {lr} ; push exec_return register

TST lr, #0x04 ; if(!EXC_RETURN[2])
Expand Down