[bsp][renesas] add device drivers (i2c/spi/adc/pwm/flash/gpio interrupt) support

.github/workflows/utest_auto_run.yml

@@ -281,4 +281,4 @@ jobs:
               echo "=========================================================================================="
               break
             fi
-          done
+          done

bsp/k230/drivers/interdrv/uart/drv_uart.c

@@ -625,4 +625,4 @@ int rt_hw_uart_init(void)
         }
     }
     return RT_EOK;
-}
+}

bsp/k230/drivers/utest/SConscript

@@ -29,4 +29,4 @@ if GetDepend('RT_UTEST_USING_ALL_CASES') or GetDepend('BSP_UTEST_DRIVERS'):
 
 group = DefineGroup('utestcases', src, depend = [''])
 
-Return('group')
+Return('group')

bsp/renesas/libraries/HAL_Drivers/drivers/config/drv_config.h

@@ -87,6 +87,15 @@ extern "C"
 
 #ifdef SOC_SERIES_R7FA2E2
 #include "ra2e2/uart_config.h"
+
+#ifdef BSP_USING_PWM
+#include "ra2e2/pwm_config.h"
+#endif
+
+#ifdef BSP_USING_ADC
+#include "ra2e2/adc_config.h"
+#endif
+
 #endif /* SOC_SERIES_R7FA2E2 */
 
 #ifdef SOC_SERIES_R7FA2L1

bsp/renesas/libraries/HAL_Drivers/drivers/config/ra2e2/adc_config.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-17     CYFS         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "hal_data.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_ADC0)
+
+struct rt_adc_dev
+{
+    struct rt_adc_ops ops;
+    struct rt_adc_device adc_device;
+};
+
+struct ra_adc_map
+{
+    const char *device_name;
+    const adc_cfg_t *g_cfg;
+    const adc_ctrl_t *g_ctrl;
+    const adc_channel_cfg_t   *g_channel_cfg;
+};
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+

bsp/renesas/libraries/HAL_Drivers/drivers/config/ra2e2/pwm_config.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2025-08-17     CYFS              first version
+ */
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+#include <drv_config.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum
+{
+#ifdef BSP_USING_PWM4
+    BSP_PWM4_INDEX,
+#endif
+#ifdef BSP_USING_PWM5
+    BSP_PWM5_INDEX,
+#endif
+#ifdef BSP_USING_PWM6
+    BSP_PWM6_INDEX,
+#endif
+#ifdef BSP_USING_PWM7
+    BSP_PWM7_INDEX,
+#endif
+#ifdef BSP_USING_PWM8
+    BSP_PWM8_INDEX,
+#endif
+#ifdef BSP_USING_PWM9
+    BSP_PWM9_INDEX,
+#endif
+    BSP_PWMS_NUM
+};
+
+#define PWM_DRV_INITIALIZER(num)        \
+    {                                   \
+        .name = "pwm"#num ,             \
+        .g_cfg = &g_timer##num##_cfg,   \
+        .g_ctrl = &g_timer##num##_ctrl, \
+        .g_timer = &g_timer##num,       \
+    }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/renesas/libraries/HAL_Drivers/drivers/drv_flash.c

@@ -228,7 +228,11 @@ bool calculate_block_num(int no, size_t addr, size_t size, void *erase_addr, voi
     level = rt_hw_interrupt_disable();
     R_FLASH_Reset(&g_flash_ctrl);
 
+#if BSP_FEATURE_FLASH_HP_VERSION
     fal_block_iter(&_onchip_flash_hp0, &calculate_block_num, (void *)addr, (void *)size, &block_num);
+#else
+    fal_block_iter(&_onchip_flash_lp, &calculate_block_num, (void *)addr, (void *)size, &block_num);
+#endif
 
     /* Erase Block */
 #if BSP_FEATURE_FLASH_HP_VERSION
@@ -337,6 +341,11 @@ static int fal_flash_lp_erase(long offset, size_t size)
     return _flash_lp_erase(_onchip_flash_lp.addr + offset, size);
 }
 
+void flash_callback(flash_callback_args_t * p_args)
+{
+
+}
+
 #endif
 
 #endif

bsp/renesas/libraries/HAL_Drivers/drivers/drv_gpio.c

@@ -26,7 +26,7 @@
 
 static rt_base_t ra_pin_get_irqx(rt_uint32_t pin)
 {
-    PIN2IRQX_TABLE(pin)
+    PIN2IRQX_TABLE(pin);
 }
 
 static struct rt_pin_irq_hdr pin_irq_hdr_tab[RA_IRQ_MAX] = {0};

bsp/renesas/libraries/HAL_Drivers/drivers/drv_i2c.c

@@ -36,6 +36,14 @@
 #define RA_SCI_EVENT_ERROR          BIT(3)
 #define RA_SCI_EVENT_ALL            BITS(0,3)
 
+#ifdef SOC_SERIES_R7FA2E2
+#define R_IIC_MASTER_Open               R_IIC_B_MASTER_Open
+#define R_IIC_MASTER_Write              R_IIC_B_MASTER_Write
+#define R_IIC_MASTER_Read               R_IIC_B_MASTER_Read
+#define R_IIC_MASTER_SlaveAddressSet    R_IIC_B_MASTER_SlaveAddressSet
+#define R_IIC_MASTER_CallbackSet        R_IIC_B_MASTER_CallbackSet
+#endif
+
 struct ra_i2c_handle
 {
     struct rt_i2c_bus_device bus;

bsp/renesas/ra2e2-ek/.config

@@ -107,7 +107,7 @@ CONFIG_SOC_R7FA2E2A7=y
 # end of rt_strnlen options
 # end of klibc options
 
-CONFIG_RT_NAME_MAX=8
+CONFIG_RT_NAME_MAX=16
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
 # CONFIG_RT_USING_NANO is not set
 # CONFIG_RT_USING_SMART is not set
@@ -146,7 +146,7 @@ CONFIG_RT_DEBUGING_CONTEXT=y
 #
 CONFIG_RT_USING_SEMAPHORE=y
 CONFIG_RT_USING_MUTEX=y
-# CONFIG_RT_USING_EVENT is not set
+CONFIG_RT_USING_EVENT=y
 # CONFIG_RT_USING_MAILBOX is not set
 # CONFIG_RT_USING_MESSAGEQUEUE is not set
 # CONFIG_RT_USING_SIGNALS is not set
@@ -1286,6 +1286,10 @@ CONFIG_BSP_USING_UART9=y
 # CONFIG_BSP_UART9_TX_USING_DMA is not set
 CONFIG_BSP_UART9_RX_BUFSIZE=256
 CONFIG_BSP_UART9_TX_BUFSIZE=0
+# CONFIG_BSP_USING_HW_I2C is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_PWM is not set
+# CONFIG_BSP_USING_ADC is not set
 # end of On-chip Peripheral Drivers
 
 #

bsp/renesas/ra2e2-ek/.secure_azone

@@ -18,10 +18,6 @@
         <peripheral name="PORT3.CM23" group="PORT">
             <slot name="P300.CM23" secure="false"/>
         </peripheral>
-        <peripheral name="PORT4.CM23" group="PORT">
-            <slot name="P400.CM23" secure="false"/>
-            <slot name="P401.CM23" secure="false"/>
-        </peripheral>
         <peripheral name="PORT9.CM23" group="PORT">
             <slot name="P914.CM23" secure="false"/>
         </peripheral>

bsp/renesas/ra2e2-ek/.secure_xml

@@ -31,8 +31,6 @@
   </raClockConfiguration>
   <raPinConfiguration>
     <pincfg active="true" name="" symbol="">
-      <configSetting altId="i3c0.scl0.p400" configurationId="i3c0.scl0" peripheral="I3C0"/>
-      <configSetting altId="i3c0.sda0.p401" configurationId="i3c0.sda0" peripheral="I3C0"/>
       <configSetting altId="jtag_fslash_swd.swclk.p300" configurationId="jtag_fslash_swd.swclk" peripheral="JTAG/SWD"/>
       <configSetting altId="jtag_fslash_swd.swdio.p108" configurationId="jtag_fslash_swd.swdio" peripheral="JTAG/SWD"/>
       <configSetting altId="p015.output.low" configurationId="p015"/>

bsp/renesas/ra2e2-ek/.settings/standalone.prefs

@@ -1,4 +1,4 @@
-#Thu Aug 21 14:44:11 CST 2025
+#Wed Sep 10 17:06:33 CST 2025
 com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
 com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths=ra/arm
 com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#Main\#\#CoreM\#\#\#\#6.1.0+fsp.6.0.0/all=1441545198,ra/arm/CMSIS_6/LICENSE|409404162,ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_armclang.h|3070162158,ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_clang.h|2642675438,ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_compiler.h|432601292,ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_gcc.h|1219721305,ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_version.h|1716662092,ra/arm/CMSIS_6/CMSIS/Core/Include/core_ca.h|3033126542,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0.h|3716711724,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0plus.h|1573341164,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm1.h|1528066797,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm23.h|956077447,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm3.h|3181146757,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm33.h|3422691989,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm35p.h|3011809468,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm4.h|862174236,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm52.h|3557548549,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm55.h|2145813412,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm7.h|215226313,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm85.h|3759822293,ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc000.h|3285488134,ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc300.h|3342995321,ra/arm/CMSIS_6/CMSIS/Core/Include/core_starmc1.h|440777068,ra/arm/CMSIS_6/CMSIS/Core/Include/tz_context.h|987654843,ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h|1790528804,ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_clang_a.h|117658130,ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_cp15.h|3644000269,ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h|947683335,ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h|3200474466,ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/irq_ctrl.h|2703360002,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_cachel1.h|271089146,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_mpu.h|3180041419,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv81m_pac.h|1572899130,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_mpu.h|1964429271,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_pmu.h|2095512231,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h|2951442685,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_clang_m.h|1179088122,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h|1753083115,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h|163659099,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h|718227869,ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_armclang_r.h|681720804,ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_clang_r.h|154254372,ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_gcc_r.h
@@ -22,5 +22,8 @@ com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_io
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#6.0.0/all=429738396,ra/fsp/inc/api/r_transfer_api.h|2894177435,ra/fsp/inc/api/r_uart_api.h|3371921742,ra/fsp/inc/instances/r_sci_uart.h|4212520575,ra/fsp/src/r_sci_uart/r_sci_uart.c
 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#6.0.0/libraries=
 com.renesas.cdt.ddsc.project.standalone.projectgenerationoptions/isCpp=false
-com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
+com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=PinConfiguration
+com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.i2c_on_iic_b_master.1621234958=true
+com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.i2c_on_iic_b_master.1927481972=false
+com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.spi_on_spi.880747616=false
 com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.1832981131=false

bsp/renesas/ra2e2-ek/SConstruct

@@ -44,6 +44,18 @@ Export('SDK_LIB')
 
 rtconfig.BSP_LIBRARY_TYPE = None
 
+def startup_check():
+    import subprocess
+    startup_check_path = os.getcwd() + "/../tools/startup_check.py"
+
+    if os.path.exists(startup_check_path):
+        try:
+            subprocess.call(["python", startup_check_path])
+        except:
+            subprocess.call(["python3", startup_check_path])
+
+RegisterPreBuildingAction(startup_check)
+
 # prepare building environment
 objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
 

bsp/renesas/ra2e2-ek/board/Kconfig

@@ -43,6 +43,67 @@ menu "Hardware Drivers Config"
                     endif
             endif
 
+        menuconfig BSP_USING_HW_I2C
+            bool "Enable hardware I2C BUS"
+            default n
+            select RT_USING_I2C
+            if BSP_USING_HW_I2C
+                config BSP_USING_HW_I2C0
+                    bool "Enable Hardware I2C0 BUS"
+                    default n
+            endif
+
+        menuconfig BSP_USING_SPI
+            bool "Enable hardware SPI BUS"
+            default n
+            select RT_USING_SPI
+            if BSP_USING_SPI
+                config BSP_USING_SPI0
+                    bool "Enable Hardware SPI0 BUS"
+                    default n
+            endif
+
+        menuconfig BSP_USING_PWM
+            bool "Enable PWM"
+            default n
+            select RT_USING_PWM
+            if BSP_USING_PWM
+                config BSP_USING_PWM4
+                    bool "Enable GPT4 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM5
+                    bool "Enable GPT5 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM6
+                    bool "Enable GPT6 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM7
+                    bool "Enable GPT7 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM8
+                    bool "Enable GPT8 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM9
+                    bool "Enable GPT9 (16-Bits) output PWM"
+                    default n
+
+            endif
+
+        menuconfig BSP_USING_ADC
+            bool "Enable ADC"
+            default n
+            select RT_USING_ADC
+            if BSP_USING_ADC
+                config BSP_USING_ADC0
+                    bool "Enable ADC0"
+                    default n
+            endif
+
     endmenu
 
     menu "Board extended module Drivers"

bsp/renesas/ra2e2-ek/board/ports/fal_cfg.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-20     Sherman      the first version
+ */
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include "hal_data.h"
+#include "rtconfig.h"
+
+extern const struct fal_flash_dev _onchip_flash_lp;
+
+#define FLASH_START_ADDRESS 0x00000000
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE             \
+{                                       \
+    &_onchip_flash_lp,                  \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/** partition table, The chip flash partition is defined in "\script\memory_regions.ld".
+ * The partition start at 0x440 instead of 0 because OFS0, OFS1 and security MPU registers exist.
+ * More details can be found in the RA2E2 Group User Manual: Hardware Figure 6.1.
+ *
+ * The table is used to define flash partition by struct fal_partition in fal_def.h */
+#define FAL_PART_TABLE                                                              \
+{                                                                                   \
+    {FAL_PART_MAGIC_WROD, "app", "onchip_flash_lp", 0x440, 0x0000fbc0, 0},          \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* _FAL_CFG_H_ */
+