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Merged
kurisaW merged 1 commit into from
Sep 25, 2025
Merged

[bsp][gd32]: can add support for GD32F5xx #10737

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43 changes: 43 additions & 0 deletions bsp/gd32/arm/gd32527I-eval/board/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -371,6 +371,49 @@ menu "On-chip Peripheral Drivers"
bool "Enable SDRAM"
select RT_USING_SDRAM
default n

menuconfig BSP_USING_CAN
bool "Enable CAN BUS"
default n
select RT_USING_CAN
select RT_USING_DEVICE_IPC
select BSP_USING_GD_DBG
if BSP_USING_CAN
config BSP_USING_CAN0
bool "Enable CAN0"
default n

if BSP_USING_CAN0
choice
prompt "Select CAN0 TX source"
default BSP_CAN0_TX_PH13

config BSP_CAN0_TX_PA12
bool "GPIOA pin 12"
config BSP_CAN0_TX_PB9
bool "GPIOB pin 9"
config BSP_CAN0_TX_PD1
bool "GPIOD pin 1"
config BSP_CAN0_TX_PH13
bool "GPIOH pin 13"
endchoice

choice
prompt "Select CAN0 RX source"
default BSP_CAN0_RX_PI9

config BSP_CAN0_RX_PA11
bool "GPIOA pin 11"
config BSP_CAN0_RX_PB8
bool "GPIOB pin 8"
config BSP_CAN0_RX_PD0
bool "GPIOD pin 0"
config BSP_CAN0_RX_PI9
bool "GPIOI pin 9"
endchoice
endif

endif

source "$(BSP_DIR)/../libraries/gd32_drivers/Kconfig"

Expand Down
4 changes: 4 additions & 0 deletions bsp/gd32/arm/libraries/gd32_drivers/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -24,3 +24,7 @@ if BSP_USING_USBD
# "ULPI: UTMI+ Low Pin Interface"
endif

config BSP_USING_GD_DBG
bool
default y
# "Using GD32 debug module"
27 changes: 16 additions & 11 deletions bsp/gd32/arm/libraries/gd32_drivers/drv_can.c
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Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@
* Change Logs:
* Date Author Notes
* 2025-18-03 Dmitriy Chernov first implementation for GD32F4xx
* 2025-09-24 CYFS add support for GD32F5xx
*/

#include "drv_can.h"
Expand All @@ -31,7 +32,7 @@ static const struct gd32_baudrate_tbl can_baudrate_tbl[] =
{CAN20kBaud, CAN_BT_SJW_1TQ, CAN_BT_BS1_11TQ, CAN_BT_BS2_2TQ, 150},
{CAN10kBaud, CAN_BT_SJW_1TQ, CAN_BT_BS1_11TQ, CAN_BT_BS2_2TQ, 300},
};
#elif defined(GD32F425) || defined(GD32F427) || defined(GD32F450) /* 50MHz(max) */
#elif defined(GD32F425) || defined(GD32F427) || defined(GD32F450) || defined(GD32F527)/* 50MHz(max) */
static const struct gd32_baudrate_tbl can_baudrate_tbl[] =
{
{CAN1MBaud, CAN_BT_SJW_1TQ, CAN_BT_BS1_8TQ, CAN_BT_BS2_1TQ, 5},
Expand Down Expand Up @@ -82,7 +83,9 @@ static const struct gd32_can gd32_can_gpio[] =
#ifdef BSP_USING_CAN0
{
.can_clk = RCU_CAN0,
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
.alt_func_num = GPIO_AF_9,
#endif
#if defined BSP_CAN0_TX_PA12
.tx_clk = RCU_GPIOA,
.tx_pin = GET_PIN(A, 12),
Expand Down Expand Up @@ -119,7 +122,10 @@ static const struct gd32_can gd32_can_gpio[] =
#ifdef BSP_USING_CAN1
{
.can_clk = RCU_CAN1,
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
.alt_func_num = GPIO_AF_9,
#endif

#if defined BSP_CAN1_TX_PB6
.tx_clk = RCU_GPIOB,
.tx_pin = GET_PIN(B, 6),
Expand Down Expand Up @@ -150,7 +156,7 @@ static void gd32_can_gpio_init(void)
rcu_periph_clock_enable(gd32_can_gpio[i].tx_clk);
rcu_periph_clock_enable(gd32_can_gpio[i].rx_clk);

#if defined SOC_SERIES_GD32F4xx
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
gpio_af_set(PIN_GDPORT(gd32_can_gpio[i].tx_pin), gd32_can_gpio[i].alt_func_num, PIN_GDPIN(gd32_can_gpio[i].tx_pin));
gpio_af_set(PIN_GDPORT(gd32_can_gpio[i].rx_pin), gd32_can_gpio[i].alt_func_num, PIN_GDPIN(gd32_can_gpio[i].rx_pin));

Expand Down Expand Up @@ -515,7 +521,7 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
return RT_EOK;
}

static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
static rt_ssize_t _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
{
RT_ASSERT(can);

Expand Down Expand Up @@ -605,7 +611,7 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t
return RT_EOK;
}

static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
static rt_ssize_t _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
{
RT_ASSERT(can);

Expand Down Expand Up @@ -656,7 +662,6 @@ static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
return RT_EOK;
}


static const struct rt_can_ops _can_ops =
{
_can_config,
Expand Down Expand Up @@ -735,23 +740,23 @@ static void _can_ewmc_isr(struct rt_can_device *can)
can->status.ackerrcnt++;
if (can_interrupt_flag_get(can_x, CAN_INT_FLAG_MTF0))
{
if (!can_interrupt_flag_get(can_x, CAN_FLAG_MTFNERR0))
if (!can_flag_get(can_x, CAN_FLAG_MTFNERR0))
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@kurisaW kurisaW Sep 24, 2025

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我看GD这块针对中断留出的接口应该是can_interrupt_flag_get吧，为什么要改成can_flag_get呢

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@CYFS3 CYFS3 Sep 24, 2025

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PixPin_2025-09-24_21-38-24 zhe这边应该要获取的是CAN_TSTAT发送状态寄存器，而且这个interrupt_flag应该指的是CAN_INTEN这个寄存器吧，并非说中断的接口。如果使用原本的函数，应用层这边应该会一直认定他发送没有完成

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@kurisaW kurisaW Sep 24, 2025

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嗯呢，是这么个逻辑，可以这么修改

{
rt_hw_can_isr(can, RT_CAN_EVENT_TX_FAIL | 0 << 8);
}
can_interrupt_flag_clear(can_x, CAN_INT_FLAG_MTF0);
}
else if (can_interrupt_flag_get(can_x, CAN_INT_FLAG_MTF1))
{
if (!can_interrupt_flag_get(can_x, CAN_FLAG_MTFNERR1))
if (!can_flag_get(can_x, CAN_FLAG_MTFNERR1))
{
rt_hw_can_isr(can, RT_CAN_EVENT_TX_FAIL | 1 << 8);
}
can_interrupt_flag_clear(can_x, CAN_INT_FLAG_MTF1);
}
else if (can_interrupt_flag_get(can_x, CAN_INT_FLAG_MTF2))
{
if (!can_interrupt_flag_get(can_x, CAN_FLAG_MTFNERR2))
if (!can_flag_get(can_x, CAN_FLAG_MTFNERR2))
{
rt_hw_can_isr(can, RT_CAN_EVENT_TX_FAIL | 2 << 8);
}
Expand Down Expand Up @@ -796,7 +801,7 @@ static void _can_tx_isr(struct rt_can_device *can)

if (can_interrupt_flag_get(can_x, CAN_INT_FLAG_MTF0))
{
if (can_interrupt_flag_get(can_x, CAN_FLAG_MTFNERR0))
if (can_flag_get(can_x, CAN_FLAG_MTFNERR0))
{
rt_hw_can_isr(can, RT_CAN_EVENT_TX_DONE | 0 << 8);
}
Expand All @@ -809,7 +814,7 @@ static void _can_tx_isr(struct rt_can_device *can)
}
else if (can_interrupt_flag_get(can_x, CAN_INT_FLAG_MTF1))
{
if (can_interrupt_flag_get(can_x, CAN_FLAG_MTFNERR1))
if (can_flag_get(can_x, CAN_FLAG_MTFNERR1))
{
rt_hw_can_isr(can, RT_CAN_EVENT_TX_DONE | 1 << 8);
}
Expand All @@ -822,7 +827,7 @@ static void _can_tx_isr(struct rt_can_device *can)
}
else if (can_interrupt_flag_get(can_x, CAN_INT_FLAG_MTF2))
{
if (can_interrupt_flag_get(can_x, CAN_FLAG_MTFNERR2))
if (can_flag_get(can_x, CAN_FLAG_MTFNERR2))
{
rt_hw_can_isr(can, RT_CAN_EVENT_TX_DONE | 2 << 8);
}
Expand Down
3 changes: 2 additions & 1 deletion bsp/gd32/arm/libraries/gd32_drivers/drv_can.h
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Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@
* Change Logs:
* Date Author Notes
* 2025-18-03 Dmitriy Chernov first implementation
* 2025-09-24 CYFS add support for GD32F5xx
*/

#ifndef __DRV_CAN_H__
Expand All @@ -34,7 +35,7 @@ struct gd32_can
rcu_periph_enum can_clk;
rcu_periph_enum tx_clk;
rcu_periph_enum rx_clk;
#if defined SOC_SERIES_GD32F4xx
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
uint32_t alt_func_num;
#endif
rt_base_t tx_pin;
Expand Down