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[AArch64] Treat NOP as a separate instruction. #170968

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[AArch64] Treat NOP as a separate instruction. #170968

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6 changes: 2 additions & 4 deletions bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1862,14 +1862,12 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
}

bool isNoop(const MCInst &Inst) const override {
return Inst.getOpcode() == AArch64::HINT &&
Inst.getOperand(0).getImm() == 0;
return Inst.getOpcode() == AArch64::NOP;
}

void createNoop(MCInst &Inst) const override {
Inst.setOpcode(AArch64::HINT);
Inst.setOpcode(AArch64::NOP);
Inst.clear();
Inst.addOperand(MCOperand::createImm(0));
}

bool isTrap(const MCInst &Inst) const override {
Expand Down
7 changes: 3 additions & 4 deletions llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp
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Expand Up @@ -178,11 +178,10 @@ static void insertNopBeforeInstruction(MachineBasicBlock &MBB, MachineInstr* MI,
MachineInstr *I = getLastNonPseudo(MBB, TII);
assert(I && "Expected instruction");
DebugLoc DL = I->getDebugLoc();
BuildMI(I->getParent(), DL, TII->get(AArch64::HINT)).addImm(0);
}
else {
BuildMI(I->getParent(), DL, TII->get(AArch64::NOP));
} else {
DebugLoc DL = MI->getDebugLoc();
BuildMI(MBB, MI, DL, TII->get(AArch64::HINT)).addImm(0);
BuildMI(MBB, MI, DL, TII->get(AArch64::NOP));
}

++NumNopsAdded;
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10 changes: 5 additions & 5 deletions llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
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Expand Up @@ -472,7 +472,7 @@ void AArch64AsmPrinter::emitSled(const MachineInstr &MI, SledKind Kind) {
EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::B).addImm(8));

for (int8_t I = 0; I < NoopsInSledCount; I++)
EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::NOP));

OutStreamer->emitLabel(Target);
recordSled(CurSled, MI, Kind, 2);
Expand Down Expand Up @@ -1697,7 +1697,7 @@ void AArch64AsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,

// Emit nops.
for (unsigned i = 0; i < NumNOPBytes; i += 4)
EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::NOP));
}

// Lower a patchpoint of the form:
Expand Down Expand Up @@ -1731,7 +1731,7 @@ void AArch64AsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
assert((NumBytes - EncodedBytes) % 4 == 0 &&
"Invalid number of NOP bytes requested!");
for (unsigned i = EncodedBytes; i < NumBytes; i += 4)
EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::NOP));
}

void AArch64AsmPrinter::LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
Expand All @@ -1740,7 +1740,7 @@ void AArch64AsmPrinter::LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
assert(PatchBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
for (unsigned i = 0; i < PatchBytes; i += 4)
EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::NOP));
} else {
// Lower call target and choose correct opcode
const MachineOperand &CallTarget = SOpers.getCallTarget();
Expand Down Expand Up @@ -2122,7 +2122,7 @@ bool AArch64AsmPrinter::emitDeactivationSymbolRelocation(Value *DS) {

if (isa<GlobalAlias>(DS)) {
// Just emit the nop directly.
EmitToStreamer(MCInstBuilder(AArch64::HINT).addImm(0));
EmitToStreamer(MCInstBuilder(AArch64::NOP));
return true;
}
MCSymbol *Dot = OutContext.createTempSymbol();
Expand Down
6 changes: 2 additions & 4 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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Expand Up @@ -6901,12 +6901,10 @@ bool llvm::rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
void AArch64InstrInfo::insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
DebugLoc DL;
BuildMI(MBB, MI, DL, get(AArch64::HINT)).addImm(0);
BuildMI(MBB, MI, DL, get(AArch64::NOP));
}

MCInst AArch64InstrInfo::getNop() const {
return MCInstBuilder(AArch64::HINT).addImm(0);
}
MCInst AArch64InstrInfo::getNop() const { return MCInstBuilder(AArch64::NOP); }

// AArch64 supports MachineCombiner.
bool AArch64InstrInfo::useMachineCombiner() const { return true; }
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6 changes: 5 additions & 1 deletion llvm/lib/Target/AArch64/AArch64InstrInfo.td
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Expand Up @@ -1544,7 +1544,6 @@ let hasSideEffects = 1, isCodeGenOnly = 1, isTerminator = 1, isBarrier = 1 in {
//===----------------------------------------------------------------------===//

def HINT : HintI<"hint">;
def : InstAlias<"nop", (HINT 0b000)>;
def : InstAlias<"yield",(HINT 0b001)>;
def : InstAlias<"wfe", (HINT 0b010)>;
def : InstAlias<"wfi", (HINT 0b011)>;
Expand All @@ -1554,6 +1553,11 @@ def : InstAlias<"dgh", (HINT 0b110)>;
def : InstAlias<"esb", (HINT 0b10000)>, Requires<[HasRAS]>;
def : InstAlias<"csdb", (HINT 20)>;

let CRm = 0b0000, hasSideEffects = 0 in
def NOP : SystemNoOperands<0b000, "hint\t#0">;

def : InstAlias<"nop", (NOP)>;

let Predicates = [HasPCDPHINT] in {
def STSHH: STSHHI;
}
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48 changes: 24 additions & 24 deletions llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-store-alias.s
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Expand Up @@ -12,12 +12,12 @@ ldr x3, [x10]

# CHECK: Iterations: 3
# CHECK-NEXT: Instructions: 18
# CHECK-NEXT: Total Cycles: 31
# CHECK-NEXT: Total Cycles: 25
# CHECK-NEXT: Total uOps: 18

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.58
# CHECK-NEXT: IPC: 0.58
# CHECK-NEXT: uOps Per Cycle: 0.72
# CHECK-NEXT: IPC: 0.72
# CHECK-NEXT: Block RThroughput: 3.0

# CHECK: Instruction Info:
Expand All @@ -32,7 +32,7 @@ ldr x3, [x10]
# CHECK-NEXT: 1 1 1.00 * str x1, [x10]
# CHECK-NEXT: 1 1 1.00 * str x1, [x10]
# CHECK-NEXT: 1 3 1.00 * ldr x2, [x10]
# CHECK-NEXT: 1 1 1.00 * * U nop
# CHECK-NEXT: 1 1 1.00 nop
# CHECK-NEXT: 1 3 1.00 * ldr x2, [x10]
# CHECK-NEXT: 1 3 1.00 * ldr x3, [x10]

Expand Down Expand Up @@ -64,27 +64,27 @@ ldr x3, [x10]
# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr x3, [x10]

# CHECK: Timeline view:
# CHECK-NEXT: 0123456789 0
# CHECK-NEXT: Index 0123456789 0123456789
# CHECK-NEXT: 0123456789
# CHECK-NEXT: Index 0123456789 01234

# CHECK: [0,0] DE . . . . . . str x1, [x10]
# CHECK-NEXT: [0,1] .DE . . . . . . str x1, [x10]
# CHECK-NEXT: [0,2] . DeeE . . . . . ldr x2, [x10]
# CHECK-NEXT: [0,3] . DE . . . . . nop
# CHECK-NEXT: [0,4] . .DeeE. . . . . ldr x2, [x10]
# CHECK-NEXT: [0,5] . . DeeE . . . . ldr x3, [x10]
# CHECK-NEXT: [1,0] . . DE . . . . str x1, [x10]
# CHECK-NEXT: [1,1] . . .DE . . . . str x1, [x10]
# CHECK-NEXT: [1,2] . . . DeeE . . . ldr x2, [x10]
# CHECK-NEXT: [1,3] . . . DE . . . nop
# CHECK-NEXT: [1,4] . . . .DeeE. . . ldr x2, [x10]
# CHECK-NEXT: [1,5] . . . . DeeE . . ldr x3, [x10]
# CHECK-NEXT: [2,0] . . . . DE . . str x1, [x10]
# CHECK-NEXT: [2,1] . . . . .DE . . str x1, [x10]
# CHECK-NEXT: [2,2] . . . . . DeeE . ldr x2, [x10]
# CHECK-NEXT: [2,3] . . . . . DE . nop
# CHECK-NEXT: [2,4] . . . . . .DeeE. ldr x2, [x10]
# CHECK-NEXT: [2,5] . . . . . . DeeE ldr x3, [x10]
# CHECK: [0,0] DE . . . . . str x1, [x10]
# CHECK-NEXT: [0,1] .DE . . . . . str x1, [x10]
# CHECK-NEXT: [0,2] . DeeE . . . . ldr x2, [x10]
# CHECK-NEXT: [0,3] . DE . . . . nop
# CHECK-NEXT: [0,4] . DeeE . . . . ldr x2, [x10]
# CHECK-NEXT: [0,5] . DeeE . . . . ldr x3, [x10]
# CHECK-NEXT: [1,0] . . DE. . . . str x1, [x10]
# CHECK-NEXT: [1,1] . . DE . . . str x1, [x10]
# CHECK-NEXT: [1,2] . . DeeE . . . ldr x2, [x10]
# CHECK-NEXT: [1,3] . . . DE . . . nop
# CHECK-NEXT: [1,4] . . . DeeE . . ldr x2, [x10]
# CHECK-NEXT: [1,5] . . . DeeE . . ldr x3, [x10]
# CHECK-NEXT: [2,0] . . . .DE . . str x1, [x10]
# CHECK-NEXT: [2,1] . . . . DE . . str x1, [x10]
# CHECK-NEXT: [2,2] . . . . DeeE . ldr x2, [x10]
# CHECK-NEXT: [2,3] . . . . DE . nop
# CHECK-NEXT: [2,4] . . . . DeeE. ldr x2, [x10]
# CHECK-NEXT: [2,5] . . . . .DeeE ldr x3, [x10]

# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
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2 changes: 1 addition & 1 deletion llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-store-noalias.s
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Expand Up @@ -30,7 +30,7 @@ ldr x3, [x10]
# CHECK-NEXT: 1 1 1.00 * str x1, [x10]
# CHECK-NEXT: 1 1 1.00 * str x1, [x10]
# CHECK-NEXT: 1 3 1.00 * ldr x2, [x10]
# CHECK-NEXT: 1 1 1.00 * * U nop
# CHECK-NEXT: 1 1 1.00 nop
# CHECK-NEXT: 1 3 1.00 * ldr x2, [x10]
# CHECK-NEXT: 1 3 1.00 * ldr x3, [x10]

Expand Down
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