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hailong-fankv2019i
hailong-fan
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kv2019i
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drivers: mediatek: Add drivers for mt8196
Add interrupt, timer and ipc driver for mt8196. Signed-off-by: hailong.fan <hailong.fan@mediatek.com>
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‎src/drivers/mediatek/mt8196/CMakeLists.txt‎

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# SPDX-License-Identifier: BSD-3-Clause
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add_local_sources(sof interrupt.c intc.c intc_map.c ipc.c timer.c)
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‎src/drivers/mediatek/mt8196/intc.c‎

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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright(c) 2024 MediaTek. All rights reserved.
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*
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* Author: Hailong Fan <hailong.fan@mediatek.com>
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*/
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#include <rtos/interrupt.h>
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#include <sof/lib/memory.h>
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#include <sof/platform.h>
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#include <sof/lib/uuid.h>
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#include <platform/drivers/interrupt.h>
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#include <platform/drivers/intc.h>
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#include <errno.h>
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#include <stdint.h>
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SOF_DEFINE_REG_UUID(intc_mt8196);
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DECLARE_TR_CTX(intc_tr, SOF_UUID(intc_mt8196_uuid), LOG_LEVEL_INFO);
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static struct intc_desc_t intc_desc;
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void intc_init(void)
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{
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uint32_t word, group, irq;
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for (group = 0; group < INTC_GRP_NUM; group++) {
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for (word = 0; word < INTC_GRP_LEN; word++)
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intc_desc.grp_irqs[group][word] = 0x0;
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}
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for (word = 0; word < INTC_GRP_LEN; word++)
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intc_desc.int_en[word] = 0x0;
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for (irq = 0; irq < IRQ_MAX_CHANNEL; irq++) {
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intc_desc.irqs[irq].id = irq;
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intc_desc.irqs[irq].group = irq2grp_map[irq];
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intc_desc.irqs[irq].pol = INTC_POL_LOW;
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}
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for (word = 0; word < INTC_GRP_LEN; word++) {
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io_reg_write(INTC_IRQ_EN(word), 0x0);
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io_reg_write(INTC_IRQ_WAKE_EN(word), 0x0);
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io_reg_write(INTC_IRQ_STAGE1_EN(word), 0x0);
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io_reg_write(INTC_IRQ_POL(word), 0xFFFFFFFF);
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}
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for (group = 0; group < INTC_GRP_NUM; group++) {
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for (word = 0; word < INTC_GRP_LEN; word++)
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io_reg_write(INTC_IRQ_GRP(group, word), 0x0);
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}
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}
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void intc_irq_unmask(enum IRQn_Type irq)
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{
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uint32_t word, group;
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if (irq < IRQ_MAX_CHANNEL && intc_desc.irqs[irq].group < INTC_GRP_NUM) {
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word = INTC_WORD(irq);
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group = intc_desc.irqs[irq].group;
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io_reg_update_bits(INTC_IRQ_EN(word), INTC_BIT(irq), INTC_BIT(irq));
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} else {
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tr_err(&intc_tr, "Invalid INTC interrupt %d", irq);
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}
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}
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void intc_irq_mask(enum IRQn_Type irq)
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{
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uint32_t word;
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if (irq < IRQ_MAX_CHANNEL) {
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word = INTC_WORD(irq);
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io_reg_update_bits(INTC_IRQ_EN(word), INTC_BIT(irq), 0);
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} else {
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tr_err(&intc_tr, "Invalid INTC interrupt %d", irq);
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}
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}
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int intc_irq_enable(enum IRQn_Type irq)
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{
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uint32_t word, irq_b, group, pol;
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int ret;
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if (irq < IRQ_MAX_CHANNEL && intc_desc.irqs[irq].group < INTC_GRP_NUM &&
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intc_desc.irqs[irq].pol < INTC_POL_NUM) {
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word = INTC_WORD(irq);
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irq_b = INTC_BIT(irq);
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group = intc_desc.irqs[irq].group;
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pol = intc_desc.irqs[irq].pol;
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intc_desc.int_en[word] |= irq_b;
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intc_desc.grp_irqs[group][word] |= irq_b;
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io_reg_update_bits(INTC_IRQ_EN(word), irq_b, 0);
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if (pol == INTC_POL_HIGH)
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io_reg_update_bits(INTC_IRQ_POL(word), irq_b, 0);
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else
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io_reg_update_bits(INTC_IRQ_POL(word), irq_b, irq_b);
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io_reg_update_bits(INTC_IRQ_GRP(group, word), irq_b, irq_b);
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io_reg_update_bits(INTC_IRQ_EN(word), irq_b, irq_b);
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ret = 1;
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} else {
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tr_err(&intc_tr, "Invalid INTC interrupt %d", irq);
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ret = 0;
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}
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return ret;
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}
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int intc_irq_disable(enum IRQn_Type irq)
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{
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uint32_t word, irq_b, group;
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int ret;
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if (irq < IRQ_MAX_CHANNEL && intc_desc.irqs[irq].group < INTC_GRP_NUM) {
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word = INTC_WORD(irq);
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irq_b = INTC_BIT(irq);
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group = intc_desc.irqs[irq].group;
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intc_desc.int_en[word] &= ~irq_b;
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intc_desc.grp_irqs[group][word] &= ~irq_b;
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io_reg_update_bits(INTC_IRQ_EN(word), irq_b, 0);
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io_reg_update_bits(INTC_IRQ_GRP(group, word), irq_b, 0);
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ret = 1;
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} else {
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tr_err(&intc_tr, "INTC fail to disable irq %u\n", irq);
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ret = 0;
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}
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return ret;
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}
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‎src/drivers/mediatek/mt8196/intc_map.c‎

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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright(c) 2024 MediaTek. All rights reserved.
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*
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* Author: Hailong Fan <hailong.fan@mediatek.com>
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*/
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#include <sof/audio/component_ext.h>
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#include <rtos/interrupt.h>
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#include <sof/lib/memory.h>
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#include <sof/platform.h>
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#include <platform/drivers/timer.h>
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#include <platform/drivers/interrupt.h>
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#include <ipc/stream.h>
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#include <errno.h>
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#include <stdint.h>
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const unsigned char grp_pri[INTC_GRP_NUM] = {
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INTC_GRP0_LEVEL, INTC_GRP1_LEVEL, INTC_GRP2_LEVEL, INTC_GRP3_LEVEL,
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INTC_GRP4_LEVEL, INTC_GRP5_LEVEL, INTC_GRP6_LEVEL, INTC_GRP7_LEVEL,
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INTC_GRP8_LEVEL, INTC_GRP9_LEVEL, INTC_GRP10_LEVEL, INTC_GRP11_LEVEL,
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INTC_GRP12_LEVEL, INTC_GRP13_LEVEL, INTC_GRP14_LEVEL, INTC_GRP15_LEVEL,
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};
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const uint8_t irq2grp_map[IRQ_MAX_CHANNEL] = {
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[CCU_IRQn] = INTC_GRP1,
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[SCP_IRQn] = INTC_GRP1,
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[SPM_IRQn] = INTC_GRP1,
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[PCIE_IRQn] = INTC_GRP1,
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[INFRA_HANG_IRQn] = INTC_GRP1,
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[PERI_TIMEOUT_IRQn] = INTC_GRP1,
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[MBOX_C0_IRQn] = INTC_GRP2,
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[MBOX_C1_IRQn] = INTC_GRP2,
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[TIMER0_IRQn] = INTC_GRP1,
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[TIMER1_IRQn] = INTC_GRP1,
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[IPC_C0_IRQn] = INTC_GRP1,
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[IPC_C1_IRQn] = INTC_GRP1,
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[IPC1_RSV_IRQn] = INTC_GRP1,
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[C2C_SW_C0_IRQn] = INTC_GRP1,
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[C2C_SW_C1_IRQn] = INTC_GRP1,
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[UART_IRQn] = INTC_GRP12,
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[UART_BT_IRQn] = INTC_GRP12,
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[LATENCY_MON_IRQn] = INTC_GRP11,
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[BUS_TRACKER_IRQn] = INTC_GRP13,
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[USB0_IRQn] = INTC_GRP8,
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[USB1_IRQn] = INTC_GRP8,
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[SCPVOW_IRQn] = NO_GRP,
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[CCIF3_C0_IRQn] = INTC_GRP8,
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[CCIF3_C1_IRQn] = INTC_GRP8,
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[PWR_CTRL_IRQn] = NO_GRP,
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[DMA_C0_IRQn] = INTC_GRP10,
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[DMA_C1_IRQn] = NO_GRP,
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[AXI_DMA0_IRQn] = INTC_GRP9,
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[AXI_DMA1_IRQn] = NO_GRP,
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[AUDIO_C0_IRQn] = INTC_GRP10,
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[AUDIO_C1_IRQn] = INTC_GRP10,
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[HIFI5_WDT_C0_IRQn] = INTC_GRP13,
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[HIFI5_WDT_C1_IRQn] = INTC_GRP13,
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[APU_MBOX_C0_IRQn] = INTC_GRP0,
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[APU_MBOX_C1_IRQn] = INTC_GRP0,
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[TIMER2_IRQn] = INTC_GRP13,
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[PWR_ON_C0_IRQ] = INTC_GRP13,
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[PWR_ON_C1_IRQ] = INTC_GRP13,
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[WAKEUP_SRC_C0_IRQn] = INTC_GRP13,
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[WAKEUP_SRC_C1_IRQn] = INTC_GRP13,
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[WDT_IRQn] = NO_GRP,
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[CONNSYS1_IRQn] = INTC_GRP3,
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[CONNSYS3_IRQn] = INTC_GRP3,
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[CONNSYS4_IRQn] = INTC_GRP3,
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[CONNSYS2_IRQn] = INTC_GRP3,
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[IPIC_IRQn] = INTC_GRP1,
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[AXI_DMA2_IRQn] = INTC_GRP9,
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[AXI_DMA3_IRQn] = NO_GRP,
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[APSRC_DDREN_IRQn] = INTC_GRP4,
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[LAT_MON_EMI_IRQn] = INTC_GRP11,
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[LAT_MON_INFRA_IRQn] = INTC_GRP11,
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[DEVAPC_VIO_IRQn] = INTC_GRP11,
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[AO_INFRA_HANG_IRQn] = NO_GRP,
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[BUS_TRA_EMI_IRQn] = INTC_GRP13,
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[BUS_TRA_INFRA_IRQn] = INTC_GRP13,
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[L2SRAM_VIO_IRQn] = INTC_GRP11,
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[L2SRAM_SETERR_IRQn] = INTC_GRP11,
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[PCIERC_GRP2_IRQn] = INTC_GRP8,
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[PCIERC_GRP3_IRQn] = INTC_GRP8,
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};
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const uint8_t grp2hifi_irq_map[INTC_GRP_NUM] = {
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[INTC_GRP0] = 0,
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[INTC_GRP1] = 1,
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[INTC_GRP2] = 2,
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[INTC_GRP3] = 3,
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[INTC_GRP4] = 4,
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[INTC_GRP5] = 5,
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[INTC_GRP6] = 7,
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[INTC_GRP7] = 8,
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[INTC_GRP8] = 9,
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[INTC_GRP9] = 10,
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[INTC_GRP10] = 11,
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[INTC_GRP11] = 16,
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[INTC_GRP12] = 17,
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[INTC_GRP13] = 18,
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[INTC_GRP14] = 20,
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[INTC_GRP15] = 21,
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};

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