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[bsp][Infineon]修复psoc6-evaluationkit-062S2调用rt_adc_disable()时报错的问题 #10329

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Merged
Rbb666 merged 1 commit into from
May 29, 2025
Merged

[bsp][Infineon]修复psoc6-evaluationkit-062S2调用rt_adc_disable()时报错的问题 #10329

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62 changes: 62 additions & 0 deletions bsp/Infineon/libraries/HAL_Drivers/config/cy8c62/adc_config.h
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@@ -0,0 +1,62 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-05-28 RTT the first version
*/
#ifndef __ADC_CONFIG_H__
#define __ADC_CONFIG_H__

#include <rtthread.h>
#include <rtdevice.h>
#include "drv_common.h"
#include "cyhal.h"
#include "cybsp.h"

#ifdef __cplusplus
extern "C"
{
#endif

#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2)

cyhal_adc_t adc_obj;
cyhal_adc_channel_t adc_chan_obj;

const cyhal_adc_config_t adc_config = {
.continuous_scanning = false, // Continuous Scanning is disabled
.average_count = 1, // Average count disabled
.vref = CYHAL_ADC_REF_VDDA, // VREF for Single ended channel set to VDDA
.vneg = CYHAL_ADC_VNEG_VSSA, // VNEG for Single ended channel set to VSSA
.resolution = 12u, // 12-bit resolution
.ext_vref = NC, // No connection
.bypass_pin = NC // No connection
};

struct ifx_adc
{
struct rt_adc_device ifx_adc_device;
cyhal_adc_channel_t *adc_ch;
char *name;
};

const cyhal_gpio_t adc_gpio[6] = {P10_0, P10_1, P10_2, P10_3, P10_4, P10_5};

#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
{ \
.adc_ch = &adc_chan_obj, \
.name = "adc1", \
}
#endif

#endif /* defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) */

#ifdef __cplusplus
}
#endif

#endif /* __ADC_CONFIG_H__ */
49 changes: 49 additions & 0 deletions bsp/Infineon/libraries/HAL_Drivers/config/drv_config.h
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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-05-28 RTT the first version
*/
#ifndef __DRV_CONFIG_H__
#define __DRV_CONFIG_H__

#include "board.h"
#include <rtthread.h>

#ifdef __cplusplus
extern "C"
{
#endif

#if defined(SOC_CY8C624ALQI_S2D42) || defined(SOC_CY8C6347BZI_BLD53) || defined(SOC_CY8C6247BZI_D54) || defined(SOC_CY8C6244LQI_S4D92)

#ifdef BSP_USING_ADC
#include "cy8c62/adc_config.h"
#endif

#endif /* SOC_CY8C624ALQI_S2D42 */

#if defined(SOC_XMC7100D_F144K4160AA)

#ifdef BSP_USING_ADC
#include "xmc7100/adc_config.h"
#endif

#endif /* SOC_XMC7100D_F144K4160AA */

#if defined(SOC_XMC7200D_E272K8384AA)

#ifdef BSP_USING_ADC
#include "xmc7200/adc_config.h"
#endif

#endif /* SOC_XMC7200D_E272K8384AA */

#ifdef __cplusplus
}
#endif

#endif /* __DRV_CONFIG_H__ */
62 changes: 62 additions & 0 deletions bsp/Infineon/libraries/HAL_Drivers/config/xmc7100/adc_config.h
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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-05-28 RTT the first version
*/
#ifndef __ADC_CONFIG_H__
#define __ADC_CONFIG_H__

#include <rtthread.h>
#include <rtdevice.h>
#include "drv_common.h"
#include "cyhal.h"
#include "cybsp.h"

#ifdef __cplusplus
extern "C"
{
#endif

#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2)

cyhal_adc_t adc_obj;
cyhal_adc_channel_t adc_chan_obj;

const cyhal_adc_config_t adc_config = {
.continuous_scanning = false, // Continuous Scanning is disabled
.average_count = 1, // Average count disabled
.vref = CYHAL_ADC_REF_VDDA, // VREF for Single ended channel set to VDDA
.vneg = CYHAL_ADC_VNEG_VSSA, // VNEG for Single ended channel set to VSSA
.resolution = 12u, // 12-bit resolution
.ext_vref = NC, // No connection
.bypass_pin = NC // No connection
};

struct ifx_adc
{
struct rt_adc_device ifx_adc_device;
cyhal_adc_channel_t *adc_ch;
char *name;
};

const cyhal_gpio_t adc_gpio[8] = {P6_0, P11_0, P11_1, P11_2, P12_4, P13_7, P14_2, P14_3};

#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
{ \
.adc_ch = &adc_chan_obj, \
.name = "adc1", \
}
#endif

#endif /* defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) */

#ifdef __cplusplus
}
#endif

#endif /* __ADC_CONFIG_H__ */
62 changes: 62 additions & 0 deletions bsp/Infineon/libraries/HAL_Drivers/config/xmc7200/adc_config.h
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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-05-28 RTT the first version
*/
#ifndef __ADC_CONFIG_H__
#define __ADC_CONFIG_H__

#include <rtthread.h>
#include <rtdevice.h>
#include "drv_common.h"
#include "cyhal.h"
#include "cybsp.h"

#ifdef __cplusplus
extern "C"
{
#endif

#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2)

cyhal_adc_t adc_obj;
cyhal_adc_channel_t adc_chan_obj;

const cyhal_adc_config_t adc_config = {
.continuous_scanning = false, // Continuous Scanning is disabled
.average_count = 1, // Average count disabled
.vref = CYHAL_ADC_REF_VDDA, // VREF for Single ended channel set to VDDA
.vneg = CYHAL_ADC_VNEG_VSSA, // VNEG for Single ended channel set to VSSA
.resolution = 12u, // 12-bit resolution
.ext_vref = NC, // No connection
.bypass_pin = NC // No connection
};

struct ifx_adc
{
struct rt_adc_device ifx_adc_device;
cyhal_adc_channel_t *adc_ch;
char *name;
};

const cyhal_gpio_t adc_gpio[8] = {P14_0, P14_1, P14_2, P14_3, P14_4, P14_5, P14_6, P14_7};
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@Rbb666 Rbb666 May 28, 2025

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这几个IO在psoc6平台上都是通用的吗？

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@yans6666 yans6666 May 28, 2025

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SOC_CY8C624ALQI_S2D42, SOC_CY8C6347BZI_BLD53, SOC_CY8C6247BZI_D54, SOC_CY8C6244LQI_S4D92这几个芯片的ADC引脚是一样的


#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
{ \
.adc_ch = &adc_chan_obj, \
.name = "adc1", \
}
#endif

#endif /* defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) */

#ifdef __cplusplus
}
#endif

#endif /* __ADC_CONFIG_H__ */
27 changes: 6 additions & 21 deletions bsp/Infineon/libraries/HAL_Drivers/drv_adc.c
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Expand Up @@ -7,27 +7,14 @@
* Date Author Notes
* 2022-07-04 Rbb666 first version
*/
#include "drv_common.h"
#include "drv_adc.h"

#include "cyhal.h"
#include "cybsp.h"
#include "drv_config.h"

#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2)

/*#define DRV_DEBUG*/
#define LOG_TAG "drv.adc"
#include <drv_log.h>

#define VPLUS_CHANNEL_0 (P10_0)

struct ifx_adc
{
struct rt_adc_device ifx_adc_device;
cyhal_adc_channel_t *adc_ch;
char *name;
};

static struct ifx_adc ifx_adc_obj[] =
{
#ifdef BSP_USING_ADC1
Expand All @@ -52,17 +39,15 @@ static rt_err_t ifx_adc_enabled(struct rt_adc_device *device, rt_uint32_t channe

if (enabled)
{
/* Initialize ADC. The ADC block which can connect to pin 10[0] is selected */
result = cyhal_adc_init(&adc_obj, VPLUS_CHANNEL_0, NULL);
result = cyhal_adc_init(&adc_obj, adc_gpio[channel], NULL);

if (result != RT_EOK)
{
LOG_E("ADC initialization failed. Error: %u\n", result);
return -RT_ENOSYS;
}

/* Initialize a channel 0 and configure it to scan P10_0 in single ended mode. */
result = cyhal_adc_channel_init_diff(adc_ch, &adc_obj, VPLUS_CHANNEL_0,
result = cyhal_adc_channel_init_diff(adc_ch, &adc_obj, adc_gpio[channel],
CYHAL_ADC_VNEG, &channel_config);

if (result != RT_EOK)
Expand All @@ -76,14 +61,14 @@ static rt_err_t ifx_adc_enabled(struct rt_adc_device *device, rt_uint32_t channe

if (result != RT_EOK)
{
printf("ADC configuration update failed. Error: %u\n", result);
rt_kprintf("ADC configuration update failed. Error: %u\n", result);
return -RT_ENOSYS;
}
}
else
{
cyhal_adc_free(&adc_obj);
cyhal_adc_channel_free(adc_ch);
cyhal_adc_free(&adc_obj);
}

return RT_EOK;
Expand Down Expand Up @@ -119,7 +104,7 @@ static int rt_hw_adc_init(void)
/* register ADC device */
if (rt_hw_adc_register(&ifx_adc_obj[i].ifx_adc_device, ifx_adc_obj[i].name, &at_adc_ops, ifx_adc_obj[i].adc_ch) == RT_EOK)
{
LOG_D("%s register success", at32_adc_obj[i].name);
LOG_D("%s register success", ifx_adc_obj[i].name);
}
else
{
Expand Down